CN110289265A - The forming method of 3D nand memory - Google Patents

The forming method of 3D nand memory Download PDF

Info

Publication number
CN110289265A
CN110289265A CN201910575102.9A CN201910575102A CN110289265A CN 110289265 A CN110289265 A CN 110289265A CN 201910575102 A CN201910575102 A CN 201910575102A CN 110289265 A CN110289265 A CN 110289265A
Authority
CN
China
Prior art keywords
channel
hole
layer
pseudo
separate slot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910575102.9A
Other languages
Chinese (zh)
Other versions
CN110289265B (en
Inventor
王香凝
耿静静
王攀
张慧
刘新鑫
吴佳佳
肖梦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to CN201910575102.9A priority Critical patent/CN110289265B/en
Publication of CN110289265A publication Critical patent/CN110289265A/en
Application granted granted Critical
Publication of CN110289265B publication Critical patent/CN110289265B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Abstract

A kind of forming method of 3D nand memory is etching the stacked structure, is being formed after several grid separate slots of stacked structure, and filled layer is formed in the grid separate slot, and the filled layer fills the full grid separate slot；After forming the filled layer, the stacked structure of grid separate slot two sides is etched, forms several channel through-holes for running through stacked structure；Storage organization is formed in the channel through-hole；After forming the storage organization, the filled layer is removed, exposes grid separate slot；The sacrificial layer is removed, is correspondingly formed control gate in the position of removal sacrificial layer；Array common source is formed in the grid separate slot.In the present invention, since grid separate slot forming step is formed before the step of forming channel through-hole and storage organization in channel through-hole, so that grid separate slot will not generate inclination, to prevent grid separate slot and channel through-hole short-circuit.

Description

The forming method of 3D nand memory
Technical field
The present invention relates to field of semiconductor fabrication more particularly to a kind of methods for reducing 3D nand memory.
Background technique
Nand flash memory is the non-volatile memory product of a kind of low in energy consumption, light weight and excellent performance, is obtained in electronic product It is widely applied.Currently, the limit of the nand flash memory of planar structure nearly true extension, holds to further improve storage Amount, reduces the carrying cost of every bit, proposes the 3D nand memory of 3D structure.
The forming process of existing 3D nand memory generally comprises: separation layer and sacrificial layer alternating layer is formed on the substrate Folded stacked structure；The stacked structure is etched, forms channel through-hole in stacked structure, after forming channel through-hole, etching The substrate of channel via bottoms, forms groove in the substrate；In the groove of channel via bottoms, pass through selective epitaxial growth (Selective Epitaxial Growth) forms silicon epitaxial layers, and the usual silicon epitaxial layers are also referred to as SEG；It is logical in the channel Charge storage layer is formed in hole and channel layer, the channel layer are connect with silicon epitaxial layers；Sacrificial layer is removed, in removal sacrificial layer Position forms control gate or wordline.
Existing memory generally comprises several memory blocks (Block), generally by along vertical between memory block and memory block Histogram is separated to the grid separate slot (Gate Line Slit, GLS) through stacked structure, but existing 3D nand memory system During work, partial region grid separate slot is easy inclination, causes short-circuit between grid separate slot and channel through-hole.
Summary of the invention
The technical problem to be solved by the present invention is to how to prevent grid separate slot from tilting, to prevent grid separate slot and ditch It is short-circuit between road through-hole.
The present invention provides a kind of forming methods of 3D nand memory, comprising:
Semiconductor substrate is provided, sacrificial layer and the alternately stacked stacking knot of separation layer are formed in the semiconductor substrate Structure；
The stacked structure is etched, several grid separate slots for running through stacked structure are formed；
Filled layer is formed in the grid separate slot, the filled layer fills the full grid separate slot；
After forming the filled layer, the stacked structure of grid separate slot two sides is etched, is formed and runs through stacked structure Several channel through-holes；
Storage organization is formed in the channel through-hole；
After forming the storage organization, the filled layer is removed, exposes grid separate slot；
The sacrificial layer is removed, is correspondingly formed control gate in the position of removal sacrificial layer；
Array common source is formed in the grid separate slot.
Optionally, the stacked structure includes core space and positioned at the stepped region of core space side, and the grid separate slot is horizontal The core space and stepped region are worn, the channel through-hole is located at stepped region.
Optionally, pseudo- channel through-hole, the puppet are formed after forming the grid separate slot and filled layer, in the stepped region Channel through-hole is located in the stepped region of grid separate slot two sides；Pseudo- channel structure is formed in the pseudo- channel through-hole.
Optionally, the pseudo- channel structure and puppet in the intersection of stepped region and core space, in the stepped region The density of channel through-hole is less than the density of the channel through-hole and storage organization that are located in core space.
Optionally, the material of the filled layer and the material of sacrificial layer are identical.
Optionally, the material of the filled layer and the material of separation layer be not identical.
Optionally, after forming the storage organization, coating is formed on stacked structure；It is formed in the coating sudden and violent Expose the opening of filling layer surface；The filled layer is removed along opening.
Optionally, the opening has the side wall being inclined outwardly, and the size of the open bottom is equal to or more than grid The size of separate slot.
Optionally, the storage organization includes the charge storage layer on channel through-hole side wall surface and deposits positioned at charge The channel layer of reservoir sidewall surfaces.
Optionally, the charge storage layer includes the barrier layer being located on channel through-hole side wall surface, is located at barrier layer side Electric charge capture layer on wall surface and the tunnel layer in electric charge capture layer sidewall surfaces.
Optionally, after removing filled layer, the sacrificial layer along grid separate slot removal stacked structure.
Optionally, after forming the control gate, array common source is formed in the grid separate slot.
Compared with prior art, technical solution of the present invention has the advantage that
The forming method of 3D nand memory of the invention is etching the stacked structure, is being formed through stacked structure After several grid separate slots, filled layer is formed in the grid separate slot, the filled layer fills the full grid separate slot；In shape After the filled layer, the stacked structure of grid separate slot two sides is etched, forms several channel through-holes for running through stacked structure； Storage organization is formed in the channel through-hole；After forming the storage organization, remove the filled layer, expose grid every Slot；The sacrificial layer is removed, is correspondingly formed control gate in the position of removal sacrificial layer；It is total that array is formed in the grid separate slot Source electrode.In the present invention, since grid separate slot forming step is forming channel through-hole and the storage organization in channel through-hole Formed before step, thus when forming grid separate slot, the stress in stacked structure everywhere in film layer is consistent, i.e., grid every Slot not will receive the influence of the difference of the pattern density difference bring stress in thin film of different location in stacked structure, thus a certain Part of grid pole separate slot will not generate inclination, to prevent grid separate slot and the short circuit of channel through-hole.
Further, the stacked structure includes core space and positioned at the stepped region of core space side, and the grid separate slot is horizontal The core space and stepped region are worn, the channel through-hole is located at stepped region, the channel through-hole and storage organization and is forming grid It is formed after separate slot and filled layer, forms pseudo- channel through-hole after forming the grid separate slot and filled layer, in the stepped region, The puppet channel through-hole is located in the stepped region of grid separate slot two sides；Pseudo- channel structure is formed in the pseudo- channel through-hole. Since grid separate slot forming step in core space the step of forming channel through-hole and storage organization in channel through-hole And formed before the step of forming pseudo- channel through-hole and pseudo- channel structure in pseudo- channel through-hole in stepped region, because And when forming grid separate slot, in the intersection two sides of core space and stepped region or neighbouring film layer, stress is consistent, i.e. grid Pole separate slot not will receive the pattern density of the intersection two sides of core space and stepped region (in interface two sides or neighbouring core space Pseudo- channel is logical in the density of channel through-hole and the storage organization in channel through-hole and interface two sides or neighbouring stepped region Hole and the pseudo- channel structure in pseudo- channel through-hole) difference bring stress in thin film difference influence so that core That a part of grid separate slot that the intersection of heart district and stepped region is formed will not generate inclination, to prevent near the intersection Grid separate slot and channel through-hole short circuit.
Further, the material of the filled layer and the material of sacrificial layer are identical, thus the filled layer and sacrificial layer can be with It is removed in same step by wet-etching technology, saves processing step.
Further, the opening formed in the coating has the side wall being inclined outwardly, and the size of the open bottom Equal to or more than the size of grid separate slot, on the one hand, guarantee that the filled layer on grid separate slot top can completely remove；On the other hand, When forming array common source when the subsequent position for removing sacrificial layer again forms control gate and in grid separate slot, material layer is prevented The opening for closing grid separate slot in advance, avoids control gate and array common source that from cannot tamping.
Detailed description of the invention
Fig. 1-Figure 14 is the structural schematic diagram of first embodiment of the invention 3D NAND forming process；
Figure 15-Figure 33 is the structural schematic diagram of second embodiment of the invention 3D NAND forming process；
Figure 34-Figure 36 is the structural schematic diagram of third embodiment of the invention 3D NAND forming process.
Specific embodiment
As described in the background art, in existing 3D nand memory manufacturing process, partial region grid separate slot is easy inclination, Cause short-circuit between grid separate slot and channel through-hole.
The study found that the region of existing grid separate slot run-off the straight is the place of the boundary of core space and stepped region, core Area is the region to form channel through-hole, and stepped region is region and the pseudo- channel through-hole of formation to form the plug connecting with control gate Region.
Further study show that needing first to provide sacrificial layer and separation layer alternating in 3D nand memory manufacturing process The stacked structure of stacking, the stacked structure include core space and stepped region；Several channel through-holes are formed in core space；In platform Rank area forms several pseudo- channel through-holes；Storage organization is formed in the channel through-hole；It is formed in the pseudo- channel through-hole pseudo- Channel structure；After forming pseudo- channel structure and storage organization, the stacked structure is etched, forms the grid for running through stacked structure Separate slot, and the grid separate slot crosses core space and stepped region；After forming grid separate slot, the sacrificial layer is removed, it is sacrificial removing The position of domestic animal layer forms control gate；Array common source is formed in grid separate slot.When forming grid separate slot, due to stepped region and The density and channel through-hole of the pseudo- channel through-hole of the intersection of core space and pseudo- channel structure and the density of storage organization exist compared with (density of pseudo- channel through-hole and pseudo- channel structure in the stepped region near the intersection of stepped region and core space is small for big difference In or much smaller than in core space near intersection channel through-hole and storage organization density), so that stepped region and core space The stress of film can have biggish difference in intersection two sides or neighbouring stacked structure, thus etch stepped region and core space Intersection stacked structure formed grid separate slot when so that etching stepped region and core space intersection grid separate slot side wall It is influenced to be easy inclination by intersection both sides stress difference, when than more serious, inclined grid separate slot exposes intersection Neighbouring channel through-hole, so that grid separate slot and channel through-hole short circuit.
For this purpose, the present invention provides a kind of forming method of 3D nand memory, 3D nand memory of the invention Forming method is etching the stacked structure, is being formed after several grid separate slots of stacked structure, in the grid separate slot Filled layer is formed, the filled layer fills the full grid separate slot；After forming the filled layer, the grid separate slot is etched The stacked structure of two sides forms several channel through-holes for running through stacked structure；Storage organization is formed in the channel through-hole；Shape After the storage organization, the filled layer is removed, exposes grid separate slot；The sacrificial layer is removed, in removal sacrificial layer Position is correspondingly formed control gate；Array common source is formed in the grid separate slot.In the present invention, walked since grid separate slot is formed Suddenly it is formed before the step of forming channel through-hole and storage organization in channel through-hole, thus is forming grid separate slot When, the stress in stacked structure everywhere in film layer is consistent, i.e., grid separate slot not will receive different location in stacked structure The influence of the difference of pattern density difference bring stress in thin film, thus a certain part of grid pole separate slot will not generate inclination, thus Prevent grid separate slot and the short circuit of channel through-hole.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general ratio Example makees partial enlargement, and the schematic diagram is example, should not be limited the scope of the invention herein.In addition, in reality It should include the three-dimensional space of length, width and depth in the production of border.
Fig. 1-Figure 14 is the structural schematic diagram of first embodiment of the invention 3D NAND forming process.
It is Fig. 1 along the schematic diagram of the section structure in the direction cutting line CD with reference to Fig. 1 and Fig. 2, Fig. 2, semiconductor substrate is provided 100, sacrificial layer 103 and the alternately stacked stacked structure 111 of separation layer 104 are formed in the semiconductor substrate 100.
The material of the semiconductor substrate 100 can be monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe (GeSi), carbonization Silicon (SiC)；It is also possible to silicon-on-insulator (SOI), germanium on insulator (GOI)；It or can also be other materials, such as arsenic Change III-V compounds of group such as gallium.In the present embodiment, the material of the semiconductor substrate 100 is monocrystalline silicon (Si).
The stacked structure 111 includes several alternately stacked sacrificial layers 103 and separation layer 104, after the sacrificial layer 103 It is continuous to go divided by cavity is formed, then control gate or wordline are being formed in the position of removal sacrificial layer 103.The separation layer 104 is used Electricity between the control gate of different layers and between control gate and other devices (electrically conducting contact, channel through-hole etc.) every From.
The sacrificial layer 103 and separation layer 104 is alternately laminated refers to: after forming one layer of sacrificial layer 103, in the sacrificial layer 103 surface forms one layer of separation layer 104, then circuit sequentially to be formed sacrificial layer 103 and on sacrificial layer 103 every The step of absciss layer 104.In the present embodiment, the bottom of the stacked structure 111 is one layer of sacrificial layer 103, and top is one layer Separation layer 104.
The number of plies (the double stacked knot of sacrificial layer 103 and separation layer 104 in stacked structure 111 of the stacked structure 111 The number of plies of structure), it is determined according to the number of the storage unit of formation needed for vertical direction, the number of plies of the stacked structure 111 can Think 8 layers, 32 layers, 64 layers etc., the number of plies of stacked structure 111 is more, can more improve integrated level.
The sacrificial layer 103 is not identical as the material of separation layer 104, when subsequent removal sacrificial layer 103, makes sacrificial layer 103 There is high etching selection ratio relative to separation layer 104, thus when removing sacrificial layer 103, to the etch amount of separation layer 104 compared with It is small or ignore, guarantee the integrality of separation layer 104.
The material of the separation layer 104 can be one of silica, silicon nitride, silicon oxynitride, fire sand, it is described The material of sacrificial layer 103 can be silica, silicon nitride, silicon oxynitride, fire sand, unformed silicon, amorphous carbon, polysilicon One of.In the present embodiment, the material of the separation layer 104 is silica, and the material of sacrificial layer 103 is silicon nitride, described Separation layer 104 and sacrificial layer 103 are formed using chemical vapor deposition process.
In the present embodiment, using one layer of sacrificial layer of top in the stacked structure 111 as top layer selection grid sacrificial layer 106, subsequent removal top layer selection grid sacrificial layer 106 forms top layer selection grid in the position of removal top layer selection grid sacrificial layer 106 (TSG).Using one layer of sacrificial layer of the bottom in the stacked structure 111 as bottom selection grid sacrificial layer 105, subsequent removal bottom Layer selection grid sacrificial layer 105 forms bottom selection grid (BSG) in the position of removal bottom selection grid sacrificial layer 105.
In one embodiment, Fig. 1 and Fig. 3 are please referred to, Fig. 3 is the schematic diagram of the section structure of the Fig. 1 along the direction cutting line AB, institute Stacked structure 111 is stated including core space 11 and positioned at the stepped region 12 of 11 side of core space, the core space 11 is used to form 3D The storage array (storage organization including channel through-hole and in channel through-hole) of nand memory, the stepped region 12 is used for It forms step and the metal plug that connect with each step and pseudo- channel through-hole in stepped region and is located at puppet ditch Pseudo- channel structure in road through-hole, referring to FIG. 3, forming several steps 107 in the stepped region 31 of the stacked structure 111, often One layer of step 107 includes one layer of sacrificial layer 103 and the separation layer 104 on sacrificial layer 103, subsequent after removing sacrificial layer, Control gate is formed in the position of removal sacrificial layer, the stepped region of the corresponding composition in several control grid layers in stepped region 12 is (each Layer stepped region includes one layer of control gate and the separation layer on the control gate accordingly).
The stacked structure can also include several grid separate slots region 22, each grid separate slot region 22 is across described Core space 11 and stepped region 12.
It is Fig. 4 along the schematic diagram of the section structure in the direction cutting line CD with reference to Fig. 4 and Fig. 5, Fig. 5, etches the stacked structure 111, form several grid separate slots 107 for running through stacked structure 111.
In the present embodiment, the formation grid separate slot 107 is located at grid separate slot area 22 (with reference to Fig. 4), the grid separate slot 107 cross the core space 11 and stepped region 12.
The dry etch process of anisotropic, such as plasma etching work can be used by etching the stacked structure 111 Skill.
In the application, since 107 forming step of grid separate slot is forming channel through-hole in core space 11 and is being located at channel The step of storage organization in through-hole and pseudo- channel through-hole and the puppet in pseudo- channel through-hole are formed in stepped region 12 It is formed before the step of channel structure, thus when forming grid separate slot 107, the intersection two sides of core space 11 and stepped region 12 Or stress is consistent in neighbouring film layer, i.e. the intersection two that not will receive core space 11 and stepped region 12 of grid separate slot 107 Pattern density (channel through-hole and the storage organization in channel through-hole in interface two sides or neighbouring core space 11 of side Pseudo- channel through-hole and the pseudo- channel structure in pseudo- channel through-hole in density and interface two sides or neighbouring stepped region 12) The influence of the difference of difference bring stress in thin film, so that of core space 11 and the formation of the intersection of stepped region 12 Grid separate slot 107 is divided not generate inclination, to prevent the grid separate slot 107 and the short circuit of channel through-hole near the intersection.
It is carried out on the basis of Fig. 5 with reference to Fig. 6, Fig. 6, forms filled layer 108, the filled layer in the grid separate slot 108 fill the full grid separate slot.
The filled layer 108 is used as sacrificial layer, in order to the progress of subsequent technique.
In the present embodiment, the material of the filled layer 108 is identical as the material of sacrificial layer 103, the specific filled layer 108 material is silicon nitride.Thus subsequent filled layer 108 and sacrificial layer 103 can pass through wet etching work in same step Skill removal, saves processing step.
In other embodiments, the filled layer 108 can be other materials, need to only meet the material of the filled layer 108 Expect it is not identical with the material of separation layer 104 so that when remove filled layer 108, separation layer 104 will not be caused mistake etching or The amount that separation layer 104 is etched is seldom or can be ignored.The material of the specific filled layer 107 can be polysilicon Or amorphous carbon.
In one embodiment, the forming process of the filled layer 108 includes: in the grid separate slot 107 (with reference to Fig. 5) And the surface of the separation layer 104 of top layer forms encapsulant layer, chemical vapor deposition can be used by forming the encapsulant layer Product (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition method (Thermal CVD), high density Plasma activated chemical vapour deposition (HDPCVD).The encapsulant layer higher than 104 surface of top layer separation layer, in the present embodiment In without removal, just as hard mask material needed for subsequent channel hole storage organization forming process, be higher than top layer and be isolated The encapsulant layer on 104 surface of layer can be depleted in the storage organization forming process of channel hole.
It is the schematic diagram of the section structure in Fig. 7 along the direction cutting line CD with reference to Fig. 7 and Fig. 8, Fig. 8, is forming filled layer 108 Afterwards, the stacked structure 111 of etching grid separate slot two sides forms several channel through-holes for running through stacked structure 111；In the channel Storage organization 119 is formed in through-hole.
In the present embodiment, the channel through-hole and storage organization 119 are formed in the stacked structure 111 of core space 11.
The storage organization 119 includes the charge storage layer 118 on channel through-hole side wall surface and deposits positioned at charge The channel layer 117 of 118 sidewall surfaces of reservoir.
In one embodiment, the charge storage layer 118 includes the barrier layer being located on channel through-hole side wall surface, is located at Electric charge capture layer in the sidewall surfaces of barrier layer and the tunnel layer in electric charge capture layer sidewall surfaces；The channel layer 117 fill full remaining channel through-hole.The tunnel layer may include silica, silicon oxynitride or any combination thereof.The electricity Lotus trapping layer may include silicon nitride, silicon oxynitride, silicon or any combination thereof.The barrier layer may include silica, nitrogen oxygen SiClx, high dielectric constant (high k) dielectric or any combination thereof, 117 material of channel layer can be doped N-type foreign ion The polysilicon of (such as phosphonium ion).In a specific embodiment, the charge storage layer 118 can be silica/nitrogen oxygen SiClx (or silicon nitride)/silica (ONO) composite layer.
In one embodiment, the forming process of the storage organization 119 includes: to form electricity in the side wall in channel hole and bottom Lotus accumulation layer, charge storage layer 118 include the barrier layer being located on the side wall and bottom surface of channel through-hole, are located at barrier layer side Electric charge capture layer on wall surface and the tunnel layer in electric charge capture layer sidewall surfaces；Is formed on charge storage layer One channel layer；The first channel layer and charge storage layer on etching removal channel hole bottom, formation expose epitaxial semiconductor layer The opening on 116 surfaces；In said opening and the first channel layer surface forms the second channel layer, second channel layer and the One channel layer constituting channel layer 117.
In one embodiment, it is formed before storage organization 119 in the channel through-hole, etching channel via bottoms exposure Semiconductor substrate 100, form groove in semiconductor substrate 100；First is formed in the groove and part channel through-hole Semiconductor epitaxial layers 116, the top surface of first semiconductor epitaxial layers 116 are higher than the top of bottom selection grid sacrificial layer 105 Portion surface, the material of first semiconductor epitaxial layers 116 can be silicon, germanium or SiGe；On the first semiconductor epitaxial layers 116 Channel through-hole in formed storage organization 119；It is etched back to the storage organization 119 of removal segment thickness, so that remaining storage is tied The top surface that 119 top surface of structure is higher than top layer selection grid sacrificial layer 106 is lower than the top table of the separation layer 104 of top Face；The second semiconductor layer 120 is formed in the channel through-hole on remaining storage organization 119, second semiconductor layer 120 Material can be silicon, germanium or SiGe.
In one embodiment, it is Fig. 7 along the schematic diagram of the section structure in the direction cutting line AB with reference to Fig. 7 and Fig. 9, Fig. 9, also wraps It includes: forming several pseudo- channel through-holes for extending vertically through stacked structure 111 in the stepped region 12；It is formed in pseudo- channel through-hole Pseudo- channel structure 122, the puppet channel structure 122 are used to support the stacked structure in subsequent removal sacrificial layer 103.
The forming step of the storage organization 119 and the forming step of pseudo- channel structure 122 can carry out simultaneously, the puppet The structure filled in channel through-hole 122 and the structure filled in channel through-hole are identical.
In other embodiments, the forming step of the storage organization 119 and the forming step of pseudo- channel structure 122 can be with Be it is separated, storage organization can be initially formed, fill pseudo- channel through-hole by through-hole sacrificial layer when forming storage organization, After forming the storage organization, through-hole sacrificial layer is removed, then forms pseudo- channel structure in pseudo- channel through-hole, thus deposited in formation After storage structure 119, without being removed each film layer structure of formation storage organization 119 of pseudo- channel through-hole filling, then again in puppet Channel through-hole forms pseudo- channel structure, simplifies processing step.In other embodiments, pseudo- channel structure can also be initially formed Storage organization 119 is formed after 122.
In one embodiment, the puppet in the intersection of stepped region 12 and core space 11, in the stepped region 12 The density of channel structure 122 and pseudo- channel through-hole is less than the channel through-hole and storage organization 119 being located in core space 12 Density.It should be noted that density described in the present embodiment is area shared by figure in how area, such as pseudo- channel junction The density of structure 122 (either pseudo- channel through-hole) refers to pseudo- channel structure 122 in the stacked structure of certain area, and (or pseudo- channel is logical Hole) shared by area, the density of the storage organization 119 (or channel through-hole) refers to be stored in the stacked structure of certain area Structure 119 (or channel through-hole)) shared by area.
In one embodiment, Figure 10 and Figure 11 are please referred to, Figure 10 is carried out on the basis of Fig. 8, forms storage organization 119 After (and pseudo- channel structure 122), coating 109 (referring to Figure 10) is formed on stacked structure 111；In the coating 109 Form the opening 110 for exposing 108 surface of filled layer (with reference to Figure 11).
The coating 109 is main as the storage organization 119 formed in channel through-hole and the isolating layer on top of grid separate slot It is used to protect and has formed storage organization 119, the techniques such as planarization or ion etching when subsequent gate separate slot being avoided to form Storage organization 119 is damaged；Coating 109 can also be used as the exposure mask of subsequent removal filled layer 108 simultaneously.
In one embodiment, the material of the coating 109 can be silica or other suitably are different from filling The mask material of layer and sacrificial layer.
In another embodiment, the coating 109 can be the stacked structure of single-layer or multi-layer.
In one embodiment, the opening 110 formed in the coating 109 has the side wall that is inclined outwardly, and described opens The size of 110 bottoms of mouth is equal to or more than the size of grid separate slot, on the one hand, guarantees that the filled layer on grid separate slot top can be completely Removal；On the other hand, array common source is formed when the subsequent position for removing sacrificial layer again forms control gate and in grid separate slot It when pole, prevents material layer from closing the opening of grid separate slot in advance, avoids control gate and array common source that from cannot tamping.
With reference to Figure 12 and Figure 13, Figure 12 is carried out on the basis of Figure 11, after forming storage organization 119, removes the filling Layer, exposes grid separate slot 107；Remove the sacrificial layer 103.
In the present embodiment, along 110 removal of the opening filled layer 108 (referring to Figure 11), removes the filled layer 108 and go Except the sacrificial layer 103 can carry out in same wet-etching technology, the etching solution that wet-etching technology uses is hot phosphorus Acid.
The bottom selection grid sacrificial layer 105 and top layer selection grid sacrificial layer 106 are removed when removing sacrificial layer 103 simultaneously (referring to Figure 12).
In other embodiments, it when the material of the material of the filled layer 108 and sacrificial layer 103 is not identical, first removes The filled layer 108, after along exposed grid separate slot remove the sacrificial layer 103, remove filled layer 108 and sacrificial layer 103 adopted With different etching solutions.
With reference to Figure 14, control gate 133 is correspondingly formed in the position of removal sacrificial layer 103 (referring to Figure 13)；In the grid Array common source 123 is formed in separate slot 107 (referring to Figure 13).
In the present embodiment, it is correspondingly formed control gate 127 in the position that removal sacrificial layer 103 removes, while in removal top layer The position of selection grid sacrificial layer 106 (referring to Figure 12) is correspondingly formed top layer selection grid 129, in removal bottom selection grid sacrificial layer The position of 105 (referring to Figure 12) is correspondingly formed bottom selection grid 132.
The control gate 127 and top layer selection grid 133 and bottom selection grid 132 include gate dielectric layer and are situated between positioned at grid Gate electrode on matter layer, in the present embodiment, the material of the gate dielectric layer is high K dielectric material, and the material of the gate electrode is Metal.The K dielectric material is HfO2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3Or BaSrTiO.The metal is W, Al, Cu, Ti, Ag, Au, Pt, Ni one of or several.
After forming the control gate 133, array common source 123 is formed in the grid separate slot.
141 material of array common source is polysilicon or metal.In one embodiment, the array common source 141 can To include being located at polysilicon layer and the metal layer on polysilicon layer.
In one embodiment, before forming array common source 123, be also formed on the side wall of the grid separate slot every From side wall 124, the material of the isolation side walls 124 can be the one or two of silicon oxide or silicon nitride.
In one embodiment, the detailed process of the formation of the control gate 133 and array common source 123 includes: removal heap Several cavitys are formed after several sacrificial layers in stack structure；Gate dielectric material is formed in the side wall of the grid separate slot and cavity Layer；Layer of gate electrode material is formed on gate dielectric layer；The gate electrode material being etched back in removal grid separate slot side wall and bottom surface The bed of material and gate dielectric material layer form control gate 133 in the cavity；In the side wall and opening 110 of grid separate slot 107 The side wall of (referring to Figure 13) forms isolation side walls 124；Array common source is formed in grid separate slot between isolation side walls 124 123, the array common source 123 fills the full grid separate slot 107 and opening 110.
Figure 15-Figure 33 is the structural schematic diagram of second embodiment of the invention 3D NAND forming process, need to illustrate second It has carried out part with structure similar or identical in first embodiment in embodiment to limit, in second embodiment and in first embodiment Other of similar or identical structure are limited or are described, and are repeated no more, are specifically please referred in first embodiment in a second embodiment The restriction or description of corresponding portion.
It is the schematic diagram of the section structure of the Figure 15 along the direction cutting line CD with reference to Figure 15-Figure 19, Figure 16, Figure 17 is that the edge Figure 15 is cut The schematic diagram of the section structure in the direction secant GH, Figure 18 are the schematic diagram of the section structure of the Figure 15 along the direction cutting line EF, and Figure 19 is figure 15 along the direction cutting line AB the schematic diagram of the section structure, semiconductor substrate 100 is provided, is formed in the semiconductor substrate 100 Sacrificial layer 103 and the alternately stacked stacked structure 111 of separation layer 104, the stacked structure 111 is including core space 11 and is located at core The stepped region 12 of 11 side of heart district, the stacked structure 111 further include several grid separate slots area 22, and grid separate slot area 22 is horizontal Across the core space 11 and stepped region 12, there is channel through-hole regulatory region in the core space 11 of 22 two sides of grid separate slot area 14, also there is in the stepped region 12 of 22 two sides of grid separate slot area pseudo- channel through-hole regulatory region 13, and the channel through-hole tune Section area 14 and pseudo- channel through-hole regulatory region 13 are in contact and are located at the interface two sides of the core space 11 and stepped region 12.
The channel through-hole regulatory region 14 is a part of region in core space 11, and the puppet channel through-hole regulatory region 13 is A part of region in stepped region 12, the channel through-hole regulatory region 14 and pseudo- channel through-hole regulatory region 13 are in contact, contact Two channel through-hole regulatory regions 14 and pseudo- channel through-hole regulatory region 13 are located at the interface two of core space 11 and stepped region 12 Side.In one embodiment, the quantity of the channel through-hole regulatory region 14 and pseudo- channel through-hole regulatory region 13 can be multiple, close on On core space 11 and the interface of stepped region 12, a ditch is distributed in the core space 11 of each 22 two sides of grid separate slot area Road through-hole regulatory region 14, closes on core space 11 and the interface of stepped region 12, the step of each 22 two sides of grid separate slot area A pseudo- channel through-hole regulatory region 13 is distributed in area 12.
It is the schematic diagram of the section structure of the Figure 20 along the direction cutting line CD with reference to Figure 20-Figure 24, Figure 21, Figure 22 is that the edge Figure 20 is cut The schematic diagram of the section structure in the direction secant GH, Figure 23 are the schematic diagram of the section structure of the Figure 20 along the direction cutting line EF, and Figure 24 is figure 20 along the direction cutting line AB the schematic diagram of the section structure, in the pseudo- channel through-hole regulatory region 13 and pseudo- channel through-hole regulatory region 13 Several pseudo- channel through-holes 113 are formed in outer stepped region 12；In the channel through-hole regulatory region 14 and channel through-hole regulatory region Several channel through-holes 112 are formed in core space 11 outside 14, the density of channel through-hole 112 is small in the channel through-hole regulatory region 14 112 density of channel through-hole in the core space 11 outside channel through-hole regulatory region 14, so that the puppet channel through-hole regulatory region 13 Difference in the density of middle puppet channel through-hole 113 and the channel through-hole regulatory region 14 between the density of channel through-hole 112 reduces.
The study found that the density and channel of the pseudo- channel through-hole of the intersection of stepped region and core space and pseudo- channel structure are logical There are biggish difference (the pseudo- channels in stepped region near the intersection of stepped region and core space for the density of hole and storage organization Density of the density of through-hole and pseudo- channel structure much smaller than channel through-hole and storage organization in intersection nearby core space) so that The stress of film can have biggish difference in the intersection two sides or neighbouring stacked structure of stepped region and core space, thus carve When the intersection stacked structure of erosion stepped region and core space forms grid separate slot, so that the intersection of etching stepped region and core space Grid separate slot side wall by intersection both sides stress difference influenced be easy inclination.Thus in the present embodiment, by making The density for stating the channel through-hole 112 formed in channel through-hole regulatory region 14 is less than in the core space 11 outside channel through-hole regulatory region 14 112 density of channel through-hole of formation, so that forming the density of pseudo- channel through-hole 113 in the puppet channel through-hole regulatory region 13 Reduce with the difference in the channel through-hole regulatory region 14 between the density of formation channel through-hole 112, corresponding subsequent ditch pseudo- again Pseudo- channel structure is formed in road through-hole 113, when forming storage organization in channel through-hole 112, so that the channel through-hole is adjusted The density of storage organization is less than the channel through-hole in the core space 11 outside channel through-hole regulatory region 14 in channel through-hole 112 in area 14 The density of storage organization in 112 so that in the puppet channel through-hole regulatory region 13 in pseudo- channel through-hole 113 pseudo- channel structure it is close Difference between the density of storage organization in degree and the channel through-hole regulatory region 14 in channel through-hole 112 reduces, to make The difference for obtaining the stress of film in the intersection two sides or neighbouring stacked structure 111 of stepped region 12 and core space 11 can reduce, Thus when etching the stacked structure of intersection of stepped region and core space formation grid separate slot, so that etching stepped region and core The side wall of the grid separate slot of the intersection in area will not generate inclination or gradient substantially reduces, to prevent grid separate slot and ditch Road through-hole short circuit.Also, due to the density for only changing channel through-hole 112 in the channel through-hole regulatory region 14, core space other The density of the channel through-hole 112 in place and it is existing remain unchanged, because without being designed and the influence of manufacture craft can to existing To ignore.
In one embodiment, the density of the channel through-hole 14 of different location keeps one in the channel through-hole regulatory region 14 It causes.Specifically, the density of storage organization is less than channel through-hole regulatory region in channel through-hole 112 in the channel through-hole regulatory region 14 The density of storage organization in the channel through-hole 112 in core space 11 outside 14, and channel is logical in the channel through-hole regulatory region 14 The equal density of pseudo- channel through-hole 113 in the density in hole 112 and the pseudo- channel through-hole regulatory region 13.
In another embodiment, the density of storage organization is less than in channel through-hole 112 in the channel through-hole regulatory region 14 The density of storage organization in the channel through-hole 112 in core space 11 outside channel through-hole regulatory region 14, and the channel through-hole tune Save in area 14 difference of the density of puppet channel through-hole 113 in the density of channel through-hole 112 and the pseudo- channel through-hole regulatory region 13 Absolute value is less than density threshold.The density threshold is the friendship of the core space 11 and stepped region 12 when forming grid separate slot The density of channel through-hole 112 in the channel through-hole regulatory region 14 when grid separate slot side wall at boundary not will form inclination defect With the maximum value of the difference of the density of pseudo- channel through-hole 113 in the pseudo- channel through-hole regulatory region 13.Specifically, the density threshold Value can be obtained by experiment, or be arranged by experience.
In one embodiment, the density of storage organization is less than ditch in channel through-hole 112 in the channel through-hole regulatory region 14 The density of storage organization in the channel through-hole 112 in core space 11 outside road through-hole regulatory region 14, and the channel through-hole is adjusted The density of channel through-hole 14 is gradually reduced from the direction that core space 11 is directed toward stepped region 12 in area 14.Specifically, the channel The size of the density value of channel through-hole 14 is logical from channel from the direction that core space 11 is directed toward stepped region 12 in through-hole regulatory region 14 The density sizes values of channel through-hole 14 are reduced to pseudo- in the pseudo- channel through-hole regulatory region 13 in core space outside hole regulatory region 14 The density sizes values of channel through-hole 113, so that the stress in film layer near 12 interface of core space 11 and stepped region increases Big or reduction is not in mutation, the grid separate slot for further preventing core space 11 and 12 interface of stepped region to be formed about Side wall will not tilt.
It should be noted that when forming storage organization in the subsequent channel through-hole 112 in channel through-hole regulatory region 14, institute It is close with the channel through-hole in channel through-hole regulatory region 14 to state the Density Distribution of storage organization and setting in channel through-hole regulatory region 14 Degree is distributed and is arranged identical.It is subsequent to form pseudo- channel structure in pseudo- channel through-hole 113 in the pseudo- channel through-hole regulatory region 13 When, pseudo- channel structure Density Distribution and setting and puppet ditch in pseudo- channel through-hole regulatory region 13 in the puppet channel through-hole regulatory region 13 The Density Distribution of road through-hole 113 is identical with setting.
It should be noted that being channel in the puppet channel through-hole regulatory region in the present embodiment and in subsequent embodiment The density (or pseudo- channel structure density) of through-hole refers to channel through-hole all in the pseudo- channel through-hole regulatory region of certain area Area shared by density (or pseudo- channel structure), density (or the storage knot of the channel through-hole in the channel through-hole regulatory region The density of structure) refer to area shared by channel through-hole (or storage organization) all in the channel through-hole regulatory region of certain area.
It is the schematic diagram of the section structure of the Figure 25 along the direction cutting line CD with reference to Figure 25-Figure 29, Figure 26, Figure 27 is that the edge Figure 25 is cut The schematic diagram of the section structure in the direction secant GH, Figure 28 are the schematic diagram of the section structure of the Figure 25 along the direction cutting line EF, and Figure 29 is figure 25 along the direction cutting line AB the schematic diagram of the section structure, form pseudo- channel structure 122 in the pseudo- channel through-hole；In the ditch Storage organization 119 is formed in road through-hole.
Pseudo- channel structure 122 is formed in the pseudo- channel through-hole, forms storage organization 119 in the channel through-hole Afterwards, the density of storage organization 119 is less than channel through-hole regulatory region in channel through-hole in the corresponding channel through-hole regulatory region 14 The density of storage organization 119 in the channel through-hole in core space 11 outside 14, so that pseudo- in the puppet channel through-hole regulatory region 13 The density of pseudo- channel structure 122 and the storage organization 119 in channel through-hole in the channel through-hole regulatory region 14 in channel through-hole Density between difference reduce.
In the present embodiment, the puppet channel structure 122 is identical as the structure of the storage organization 119, the puppet channel junction Structure 122 is formed in same processing step with the storage organization 119.
In other embodiments, the pseudo- channel structure 122 is different from the structure of the storage organization 119, and the puppet The material hardness of channel structure 122 is greater than the material hardness of the storage organization 119, and due to the channel through-hole regulatory region The density of channel through-hole 112 is less than 112 density of channel through-hole in the core space 11 outside channel through-hole regulatory region 14 in 14, so that The density of pseudo- channel through-hole 113 and channel through-hole in the channel through-hole regulatory region 14 in the puppet channel through-hole regulatory region 13 Difference between 112 density reduces so that so that the intersection two sides of stepped region 12 and core space 11 or near Stacked structure 111 in the difference of stress of film be easier and be further reduced, thus etching stepped region and core When the stacked structure of the intersection of heart district forms grid separate slot, so that the grid separate slot of the intersection of etching stepped region and core space Side wall will not generate inclination or effect that gradient substantially reduces can be more preferable.
The storage organization 119 includes the charge storage layer 118 on channel through-hole side wall surface and deposits positioned at charge The channel layer 117 of 118 sidewall surfaces of reservoir.
In one embodiment, the charge storage layer 118 includes the barrier layer being located on channel through-hole side wall surface, is located at Electric charge capture layer in the sidewall surfaces of barrier layer and the tunnel layer in electric charge capture layer sidewall surfaces；The channel layer 117 fill full remaining channel through-hole.The tunnel layer may include silica, silicon oxynitride or any combination thereof.The electricity Lotus trapping layer may include silicon nitride, silicon oxynitride, silicon or any combination thereof.The barrier layer may include silica, nitrogen oxygen SiClx, high dielectric constant (high k) dielectric or any combination thereof, 117 material of channel layer can be doped N-type foreign ion The polysilicon of (such as phosphonium ion).In a specific embodiment, the charge storage layer 118 can be silica/nitrogen oxygen SiClx (or silicon nitride)/silica (ONO) composite layer.
In one embodiment, it is formed before storage organization 119 in the channel through-hole, etching channel via bottoms exposure Semiconductor substrate 100, form groove in semiconductor substrate 100；First is formed in the groove and part channel through-hole Semiconductor epitaxial layers 116, the top surface of first semiconductor epitaxial layers 116 are higher than the top of bottom selection grid sacrificial layer 105 Portion surface, the material of first semiconductor epitaxial layers 116 can be silicon, germanium or SiGe；On the first semiconductor epitaxial layers 116 Channel through-hole in formed storage organization 119；It is etched back to the storage organization 119 of removal segment thickness, so that remaining storage is tied The top surface that 119 top surface of structure is higher than top layer selection grid sacrificial layer 106 is lower than the top table of the separation layer 104 of top Face；The second semiconductor layer 120 is formed in the channel through-hole on remaining storage organization 119, second semiconductor layer 120 Material can be silicon, germanium or SiGe.
It is the schematic diagram of the section structure of the Figure 30 along the direction cutting line CD with reference to Figure 30-Figure 32, Figure 31, forms the pseudo- channel After structure 122 and storage organization 119, formed in grid separate slot area 22 cross the grid of core space 11 and stepped region 12 every Slot 107.
The grid separate slot 107 runs through the stacked structure 111 along the vertical direction.
It is the schematic diagram of the section structure of the Figure 32 along the direction cutting line CD with reference to Figure 32 and Figure 33, Figure 33, forms grid separate slot Afterwards, the sacrificial layer is removed, forms control gate 133 in the position of removal sacrificial layer；After forming control gate 133, in the grid Array common source 123 is formed in separate slot.
The bottom selection grid sacrificial layer 105 and top layer selection grid are removed simultaneously when removal sacrificial layer 103 (referring to Figure 31) Sacrificial layer 106.
It is correspondingly formed control gate 127 in the position that removal sacrificial layer 103 removes, while in removal top layer selection grid sacrificial layer The position of 106 (referring to Figure 31) is correspondingly formed top layer selection grid 129, removal bottom selection grid sacrificial layer 105 (referring to Figure 31) Position be correspondingly formed bottom selection grid 132.
In one embodiment, before forming array common source 123, be also formed on the side wall of the grid separate slot every From side wall 124.
Second embodiment of the invention additionally provides a kind of 3D nand memory, with reference to Figure 32 and Figure 33, comprising:
Semiconductor substrate 100 is formed with control gate 133 in the semiconductor substrate 100 and separation layer 104 is alternately stacked Stacked structure 111, the stacked structure 111 is including core space 11 and positioned at the stepped region 12 of 11 side of core space, the stacking Structure 111 further includes several grid separate slots area 22, and grid separate slot area 22 is described across the core space 11 and stepped region 12 There is channel through-hole regulatory region 14, the stepped region of 22 two sides of grid separate slot area in the core space 11 of 22 two sides of grid separate slot area Also there is pseudo- channel through-hole regulatory region 13, and the channel through-hole regulatory region 14 and pseudo- channel through-hole regulatory region 13 are in contact in 12 And it is located at the interface two sides of the core space 11 and stepped region 12；
Several pseudo- ditches in the stepped region 12 outside the pseudo- channel through-hole regulatory region 13 and pseudo- channel through-hole regulatory region Road through-hole；
Several channels in the core space 11 outside the channel through-hole regulatory region 14 and channel through-hole regulatory region are logical Hole, the density of channel through-hole is less than the channel in the core space 11 outside channel through-hole regulatory region in the channel through-hole regulatory region 14 Via densities, so that in the puppet channel through-hole regulatory region 13 in the density and the channel through-hole regulatory region 14 of pseudo- channel through-hole Difference between the density of channel through-hole reduces；
Pseudo- channel structure 122 in the pseudo- channel through-hole；
Storage organization 119 in the channel through-hole；
The grid separate slot for crossing core space and stepped region in grid separate slot area 22；
Array common source 123 in the grid separate slot.
Correspondingly, the density of storage organization 119 is less than channel through-hole in channel through-hole in the channel through-hole regulatory region 14 The density of storage organization 119 in the channel through-hole in core space 11 outside regulatory region, so that the puppet channel through-hole regulatory region 13 The density of pseudo- channel structure 122 and the storage organization in channel through-hole in the channel through-hole regulatory region 14 in middle puppet channel through-hole Difference between 119 density reduces.
In one embodiment, in the channel through-hole regulatory region channel through-hole density from core space be directed toward stepped region side It is gradually reduced upwards.
In one embodiment, the density of channel through-hole and the pseudo- channel through-hole regulatory region in the channel through-hole regulatory region The density of channel through-hole and the pseudo- channel through-hole in the equal density or the channel through-hole regulatory region of middle puppet channel through-hole The absolute value of the difference of the density of pseudo- channel through-hole is less than density threshold in regulatory region.
The density threshold is the grid separate slot side of the intersection of the core space and stepped region when forming grid separate slot The density of channel through-hole and the pseudo- channel through-hole are adjusted in channel through-hole regulatory region when wall not will form inclination defect The maximum value of the difference of the density of pseudo- channel through-hole in area.
In one embodiment, the pseudo- channel structure is identical with the structure of storage organization.
In one embodiment, the pseudo- channel structure is different with the structure of storage organization, the material of the puppet channel structure Hardness is greater than the material hardness of the storage organization.
The storage organization includes the charge storage layer on the channel through-hole side wall surface and is located at charge storage layer side The channel layer of wall surface.
In one embodiment, the charge storage layer includes the barrier layer being located on channel through-hole side wall surface, is located at resistance Electric charge capture layer in barrier sidewall surfaces and the tunnel layer in electric charge capture layer sidewall surfaces.
Figure 34-Figure 36 is the structural schematic diagram of third embodiment of the invention 3D NAND forming process.3rd embodiment and the The main distinction in two embodiments is: being that the density of channel through-hole in the channel through-hole regulatory region is less than in second embodiment The channel via densities in core space outside channel through-hole regulatory region, so that pseudo- channel through-hole in the puppet channel through-hole regulatory region Density and the channel through-hole regulatory region in channel through-hole density between difference reduce, and be described in 3rd embodiment It is logical to be greater than the pseudo- channel in the stepped region outside pseudo- channel through-hole regulatory region for the density of pseudo- channel through-hole in pseudo- channel through-hole regulatory region Hole density, so that the density of pseudo- channel through-hole and channel in the channel through-hole regulatory region are logical in the puppet channel through-hole regulatory region Difference between the density in hole reduces, the other parts of 3D nand memory and 3D nand memory in 3rd embodiment The other parts of 3D nand memory and the entire formation of 3D nand memory in entire forming process and second embodiment Process is essentially identical, thus subsequent third embodiment is only described the aforementioned main distinction, other portions of 3D nand memory Point and 3D nand memory entire forming process please refer to second embodiment and 3rd embodiment corresponding portion restriction or Description.
With reference to Figure 34-Figure 36, Figure 34 is similar to Figure 20 in second embodiment, Figure 35 and Figure 30 phase in second embodiment Seemingly, Figure 36 is similar to Figure 32 in second embodiment, provides semiconductor substrate, is formed with sacrificial layer in the semiconductor substrate With the alternately stacked stacked structure of separation layer, the stacked structure includes core space 11 and the stepped region positioned at 11 side of core space 12, the stacked structure further includes several grid separate slots area 22, and grid separate slot area 22 is across the core space 11 and step Area 12 has channel through-hole regulatory region 14,22 liang of grid separate slot area in the core space 11 of 22 two sides of grid separate slot area Also there is pseudo- channel through-hole regulatory region 13, and the channel through-hole regulatory region 14 and pseudo- channel through-hole are adjusted in the stepped region 12 of side Area 13 is in contact and is located at the interface two sides of the core space 11 and stepped region 12；
Several channels are formed in the core space 11 outside the channel through-hole regulatory region 14 and channel through-hole regulatory region 14 Through-hole 112；
Several puppets are formed in the stepped region 12 outside the pseudo- channel through-hole regulatory region 13 and pseudo- channel through-hole regulatory region 13 Channel through-hole 113, the density of pseudo- channel through-hole 113 is greater than pseudo- channel through-hole regulatory region 13 in the puppet channel through-hole regulatory region 13 Pseudo- 113 density of channel through-hole in outer stepped region 11, so that pseudo- channel through-hole 113 in the puppet channel through-hole regulatory region 13 Difference in density and the channel through-hole regulatory region 14 between the density of channel through-hole 112 reduces；
Pseudo- channel structure 122 (referring to Figure 36) is formed in the pseudo- channel through-hole；
Storage organization 119 (referring to Figure 36) is formed in the channel through-hole；
After forming the pseudo- channel structure 122 and storage organization 119, is formed in grid separate slot area and cross core space With the grid separate slot 107 (referring to Figure 36) of stepped region.
In the present embodiment, by making the density of pseudo- channel through-hole 113 in the pseudo- channel through-hole regulatory region 13 be greater than pseudo- ditch Pseudo- 113 density of channel through-hole in stepped region 11 outside road through-hole regulatory region 13, so that in the puppet channel through-hole regulatory region 13 Difference in the density of pseudo- channel through-hole 113 and the channel through-hole regulatory region 14 between the density of channel through-hole 112 reduces, phase Pseudo- channel structure is formed in the subsequent channel through-hole 113 pseudo- again answered, when forming storage organization in channel through-hole 112, so that institute The density for stating pseudo- channel structure 122 in pseudo- channel through-hole in pseudo- channel through-hole regulatory region 13 is greater than outside pseudo- channel through-hole regulatory region 13 Stepped region in pseudo- channel through-hole in pseudo- channel structure 122 density so that pseudo- ditch in the puppet channel through-hole regulatory region 13 In road through-hole the density of pseudo- channel structure 122 in channel through-hole in the channel through-hole regulatory region 13 storage organization 119 it is close Difference between degree reduces, so that in the intersection two sides or neighbouring stacked structure 111 of stepped region 12 and core space 11 The difference of the stress of film can reduce, thus form grid separate slot in the stacked structure of etching stepped region and the intersection of core space When, so that the side wall of the grid separate slot of the intersection of etching stepped region and core space will not generate inclination or gradient substantially subtracts It is small, to prevent grid separate slot and the short circuit of channel through-hole.Also, it is logical due to only changing channel in the channel through-hole regulatory region 14 The density in hole 112, the density of the channel through-hole 112 of core space elsewhere and it is existing remain unchanged, because without to existing Design and the influence of manufacture craft can be ignored.
In one embodiment, the density of pseudo- channel through-hole 113 is logical greater than pseudo- channel in the pseudo- channel through-hole regulatory region 13 Pseudo- 113 density of channel through-hole in stepped region 11 outside hole regulatory region 13, and channel through-hole in the channel through-hole regulatory region 14 The equal density or the channel through-hole tune of pseudo- channel through-hole 112 in 113 density and the pseudo- channel through-hole regulatory region 13 Save in area 14 difference of the density of puppet channel through-hole 112 in the density of channel through-hole 113 and the pseudo- channel through-hole regulatory region 13 Absolute value is less than density threshold.
The density threshold is the grid separate slot side of the intersection of the core space and stepped region when forming grid separate slot The density of channel through-hole and the pseudo- channel through-hole are adjusted in channel through-hole regulatory region when wall not will form inclination defect The maximum value of the difference of the density of pseudo- channel through-hole in area.
In one embodiment, the density of pseudo- channel through-hole 113 is logical greater than pseudo- channel in the pseudo- channel through-hole regulatory region 13 Pseudo- 113 density of channel through-hole in stepped region 11 outside hole regulatory region 13, and pseudo- channel in the pseudo- channel through-hole regulatory region 13 The density of through-hole 113 is gradually increased from the direction that core space 11 is directed toward in stepped region 12.
In one embodiment, the density of pseudo- channel through-hole 113 is logical greater than pseudo- channel in the pseudo- channel through-hole regulatory region 13 Pseudo- 113 density of channel through-hole in stepped region 11 outside hole regulatory region 13, and channel through-hole in the channel through-hole regulatory region 14 112 density is less than the density of channel through-hole 14 in the core space outside channel through-hole regulatory region 14.
In one embodiment, the pseudo- channel structure is identical with the structure of storage organization.
In one embodiment, the density of pseudo- channel through-hole is greater than pseudo- channel through-hole adjusting in the pseudo- channel through-hole regulatory region Pseudo- channel via densities in stepped region outside area, so that the density of pseudo- channel through-hole and institute in the puppet channel through-hole regulatory region It states the difference in channel through-hole regulatory region between the density of channel through-hole to reduce, and the knot of the pseudo- channel structure and storage organization Structure is different, and the material hardness of the puppet channel structure is greater than the material hardness of the storage organization.
In one embodiment,
The sacrificial layer is removed after forming grid separate slot with reference to Figure 26, forms control gate in the position of removal sacrificial layer； After forming control gate, array common source 123 is formed in the grid separate slot.
The storage organization includes the charge storage layer on the channel through-hole side wall surface and is located at charge storage layer side The channel layer of wall surface.
In an embodiment, the charge storage layer includes the barrier layer being located on channel through-hole side wall surface, is located at blocking Electric charge capture layer in layer sidewall surfaces and the tunnel layer in electric charge capture layer sidewall surfaces.
Third embodiment of the invention additionally provides a kind of 3D nand memory, comprising:
Semiconductor substrate is formed with control gate and the alternately stacked stacked structure of separation layer, institute in the semiconductor substrate Stating stacked structure includes core space and positioned at the stepped region of core space side, and the stacked structure further includes several grid separate slots Area, grid separate slot area have channel in the core space and stepped region, the core space of grid separate slot area two sides Through-hole regulatory region also has pseudo- channel through-hole regulatory region, and the channel through-hole in the stepped region of grid separate slot area two sides Regulatory region and pseudo- channel through-hole regulatory region are in contact and are located at the interface two sides of the core space and stepped region；
Several channel through-holes in the core space outside the channel through-hole regulatory region and channel through-hole regulatory region；
Several pseudo- channels in the stepped region outside the pseudo- channel through-hole regulatory region and pseudo- channel through-hole regulatory region are logical Hole, the density of pseudo- channel through-hole is greater than the puppet in the stepped region outside pseudo- channel through-hole regulatory region in the puppet channel through-hole regulatory region Channel via densities, so that in the puppet channel through-hole regulatory region in the density and the channel through-hole regulatory region of pseudo- channel through-hole Difference between the density of channel through-hole reduces；
Pseudo- channel structure in the pseudo- channel through-hole；
Storage organization in the channel through-hole；
The grid separate slot for crossing core space and stepped region in grid separate slot area；
Array common source in the grid separate slot.
Correspondingly, the density of pseudo- channel structure is logical greater than pseudo- channel in pseudo- channel through-hole in the puppet channel through-hole regulatory region The density of pseudo- channel structure in pseudo- channel through-hole in stepped region outside the regulatory region of hole, so that in the puppet channel through-hole regulatory region In pseudo- channel through-hole in the density of pseudo- channel structure and the channel through-hole regulatory region in channel through-hole storage organization density it Between difference reduce.
In one embodiment, the density of pseudo- channel through-hole is directed toward core space from stepped region in the pseudo- channel through-hole regulatory region Direction on be gradually increased.
In one embodiment, the density of channel through-hole and the pseudo- channel through-hole regulatory region in the channel through-hole regulatory region The density of channel through-hole and the pseudo- channel through-hole in the equal density or the channel through-hole regulatory region of middle puppet channel through-hole The absolute value of the difference of the density of pseudo- channel through-hole is less than density threshold in regulatory region.
The density threshold is the grid separate slot side of the intersection of the core space and stepped region when forming grid separate slot The density of channel through-hole and the pseudo- channel through-hole are adjusted in channel through-hole regulatory region when wall not will form inclination defect The maximum value of the difference of the density of pseudo- channel through-hole in area.
In one embodiment, the density of channel through-hole is less than outside channel through-hole regulatory region in the channel through-hole regulatory region The density of channel through-hole in core space.
In one embodiment, the pseudo- channel structure is identical with the structure of storage organization.
In one embodiment, the pseudo- channel structure is different with the structure of storage organization, the material of the puppet channel structure Hardness is greater than the material hardness of the storage organization.
The storage organization includes the charge storage layer on the channel through-hole side wall surface and is located at charge storage layer side The channel layer of wall surface.
In one embodiment, the charge storage layer includes the barrier layer being located on channel through-hole side wall surface, is located at resistance Electric charge capture layer in barrier sidewall surfaces and the tunnel layer in electric charge capture layer sidewall surfaces.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as Protection scope of the present invention.

Claims (12)

1. a kind of forming method of 3D nand memory characterized by comprising
Semiconductor substrate is provided, is formed with sacrificial layer and the alternately stacked stacked structure of separation layer in the semiconductor substrate；
The stacked structure is etched, several grid separate slots for running through stacked structure are formed；
Filled layer is formed in the grid separate slot, the filled layer fills the full grid separate slot；
After forming the filled layer, the stacked structure of grid separate slot two sides is etched, if being formed through stacked structure Hondo road through-hole；
Storage organization is formed in the channel through-hole；
After forming the storage organization, the filled layer is removed, exposes grid separate slot；
The sacrificial layer is removed, is correspondingly formed control gate in the position of removal sacrificial layer；
Array common source is formed in the grid separate slot.
2. the forming method of 3D nand memory as described in claim 1, which is characterized in that the stacked structure includes core Heart district and positioned at the stepped region of core space side, the grid separate slot crosses the core space and stepped region, the channel through-hole Positioned at stepped region.
3. the forming method of 3D nand memory as claimed in claim 2, which is characterized in that forming the grid separate slot Pseudo- channel through-hole is formed after filled layer, in the stepped region, the puppet channel through-hole is located at the stepped region of grid separate slot two sides In；Pseudo- channel structure is formed in the pseudo- channel through-hole.
4. the forming method of 3D nand memory as claimed in claim 3, which is characterized in that in stepped region and core space The density of intersection, the pseudo- channel structure and pseudo- channel through-hole in the stepped region is less than the institute being located in core space State the density of channel through-hole and storage organization.
5. the forming method of 3D nand memory as described in claim 1, which is characterized in that the material of the filled layer with The material of sacrificial layer is identical.
6. the forming method of 3D nand memory as described in claim 1, which is characterized in that the material of the filled layer with The material of separation layer is not identical.
7. the forming method of 3D nand memory as described in claim 1, which is characterized in that after forming the storage organization, Coating is formed on stacked structure；The opening for exposing filling layer surface is formed in the coating；Along opening removal institute State filled layer.
8. the forming method of 3D nand memory as claimed in claim 7, which is characterized in that the opening, which has, to lean outward Oblique side wall, and the size of the open bottom is equal to or more than the size of grid separate slot.
9. the forming method of 3D nand memory as described in claim 1, which is characterized in that the storage organization includes position In the charge storage layer on channel through-hole side wall surface and positioned at the channel layer of charge storage layer sidewall surfaces.
10. the forming method of 3D nand memory as claimed in claim 9, which is characterized in that the charge storage layer includes It barrier layer on channel through-hole side wall surface, the electric charge capture layer in the sidewall surfaces of barrier layer and is caught positioned at charge Obtain the tunnel layer in layer sidewall surfaces.
11. the forming method of 3D nand memory as described in claim 1, which is characterized in that after removing filled layer, edge Grid separate slot removes sacrificial layer in stacked structure.
12. the forming method of 3D nand memory as claimed in claim 11, which is characterized in that forming the control gate Afterwards, array common source is formed in the grid separate slot.
CN201910575102.9A 2019-06-28 2019-06-28 Method for forming 3D NAND memory Active CN110289265B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910575102.9A CN110289265B (en) 2019-06-28 2019-06-28 Method for forming 3D NAND memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910575102.9A CN110289265B (en) 2019-06-28 2019-06-28 Method for forming 3D NAND memory

Publications (2)

Publication Number Publication Date
CN110289265A true CN110289265A (en) 2019-09-27
CN110289265B CN110289265B (en) 2020-04-10

Family

ID=68020107

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910575102.9A Active CN110289265B (en) 2019-06-28 2019-06-28 Method for forming 3D NAND memory

Country Status (1)

Country Link
CN (1) CN110289265B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111883426A (en) * 2020-08-03 2020-11-03 长江存储科技有限责任公司 Etching method and three-dimensional memory
CN112614848A (en) * 2020-12-02 2021-04-06 长江存储科技有限责任公司 Three-dimensional memory structure and preparation method thereof
CN112670294A (en) * 2020-12-22 2021-04-16 长江存储科技有限责任公司 Semiconductor device and method for manufacturing the same
CN112670297A (en) * 2020-01-17 2021-04-16 长江存储科技有限责任公司 Dual-stack three-dimensional NAND memory and method for forming the same
CN112838094A (en) * 2021-01-04 2021-05-25 长江存储科技有限责任公司 Three-dimensional memory device
CN113764432A (en) * 2020-01-02 2021-12-07 长江存储科技有限责任公司 3D memory device and method of manufacturing the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3109840B1 (en) * 2020-04-29 2022-05-13 Aveni Method of metallization of a semiconductor substrate, electrolyte and method of manufacturing 3D-NAND

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9230974B1 (en) * 2014-08-26 2016-01-05 Sandisk Technologies Inc. Methods of selective removal of blocking dielectric in NAND memory strings
CN108807405A (en) * 2018-06-12 2018-11-13 长江存储科技有限责任公司 Three-dimensional storage and preparation method thereof
CN109742038A (en) * 2019-01-07 2019-05-10 长江存储科技有限责任公司 3D nand memory and forming method thereof
CN109817623A (en) * 2019-03-27 2019-05-28 长江存储科技有限责任公司 3D nand memory and forming method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9230974B1 (en) * 2014-08-26 2016-01-05 Sandisk Technologies Inc. Methods of selective removal of blocking dielectric in NAND memory strings
CN108807405A (en) * 2018-06-12 2018-11-13 长江存储科技有限责任公司 Three-dimensional storage and preparation method thereof
CN109742038A (en) * 2019-01-07 2019-05-10 长江存储科技有限责任公司 3D nand memory and forming method thereof
CN109817623A (en) * 2019-03-27 2019-05-28 长江存储科技有限责任公司 3D nand memory and forming method thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113764432A (en) * 2020-01-02 2021-12-07 长江存储科技有限责任公司 3D memory device and method of manufacturing the same
CN113764432B (en) * 2020-01-02 2024-02-27 长江存储科技有限责任公司 3D memory device and method of manufacturing the same
CN112670297A (en) * 2020-01-17 2021-04-16 长江存储科技有限责任公司 Dual-stack three-dimensional NAND memory and method for forming the same
CN112670297B (en) * 2020-01-17 2023-09-12 长江存储科技有限责任公司 Dual stack three-dimensional NAND memory and method for forming the same
CN111883426A (en) * 2020-08-03 2020-11-03 长江存储科技有限责任公司 Etching method and three-dimensional memory
CN111883426B (en) * 2020-08-03 2021-10-08 长江存储科技有限责任公司 Etching method and three-dimensional memory
CN112614848A (en) * 2020-12-02 2021-04-06 长江存储科技有限责任公司 Three-dimensional memory structure and preparation method thereof
CN112670294A (en) * 2020-12-22 2021-04-16 长江存储科技有限责任公司 Semiconductor device and method for manufacturing the same
CN112670294B (en) * 2020-12-22 2024-04-09 长江存储科技有限责任公司 Semiconductor device and method for manufacturing the same
CN112838094A (en) * 2021-01-04 2021-05-25 长江存储科技有限责任公司 Three-dimensional memory device

Also Published As

Publication number Publication date
CN110289265B (en) 2020-04-10

Similar Documents

Publication Publication Date Title
CN110289265A (en) The forming method of 3D nand memory
CN110112134B (en) 3D NAND memory and forming method thereof
CN110176461A (en) 3D nand memory and forming method thereof
CN110289263A (en) 3D nand memory and forming method thereof
CN110197830A (en) 3D nand memory and forming method thereof
CN107810552B (en) Use the multi-level store stacked body structure containing the chamber manufacture for sacrificing packing material
TWI693700B (en) Memory device
CN107680972B (en) A kind of 3D nand memory part and its manufacturing method
JP6842386B2 (en) Semiconductor device
US11631691B2 (en) Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same
CN109564922A (en) Three-dimensional storage equipment and its manufacturing method
KR101531800B1 (en) Vertical memory cell
CN103426824B (en) The method for manufacturing nonvolatile semiconductor memory member
US11950418B2 (en) Method and structure for forming stairs in three-dimensional memory devices
CN110211965A (en) 3D nand memory and forming method thereof
CN110462828A (en) Memory devices and forming method thereof
CN109830483B (en) 3D NAND memory and forming method thereof
CN109817623A (en) 3D nand memory and forming method thereof
CN109755252A (en) A kind of memory device and its manufacturing method
CN110211964A (en) 3D nand memory and forming method thereof
CN109860196B (en) Method for forming 3D NAND memory
CN109904169B (en) Method for forming 3D NAND memory
CN107818984A (en) A kind of 3D nand memories part and its manufacture method
CN109887924B (en) Method for forming 3D NAND memory
CN109817635B (en) Method for forming 3D NAND memory

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant