CN107680972B - A kind of 3D nand memory part and its manufacturing method - Google Patents
A kind of 3D nand memory part and its manufacturing method Download PDFInfo
- Publication number
- CN107680972B CN107680972B CN201711059075.7A CN201711059075A CN107680972B CN 107680972 B CN107680972 B CN 107680972B CN 201711059075 A CN201711059075 A CN 201711059075A CN 107680972 B CN107680972 B CN 107680972B
- Authority
- CN
- China
- Prior art keywords
- layer
- hole
- area
- etching
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
The present invention provides a kind of manufacturing method of 3D nand memory part, the stack layer being alternately stacked by the way that sacrificial layer and insulating layer is formed on the substrate, the accumulation layer being formed in the first area of the stack layer in channel hole and channel hole, coating is formed on stack layer, it is wherein formed with the etched hole of different pore size in the coating of second area, is to block with coating, carries out the etching of stack layer, to form contact hole under etched hole, different contact hole stops is in the sacrificial layer of different layers.Due in etching process, etched hole aperture is bigger, under stack layer etch rate it is bigger, enable the contact hole under bigger etched hole that there is deeper hole depth, it is achieved that the etching of the contact hole of different depth, forms the contact hole for corresponding to different sacrificial layers.For the memory device with more layer heap lamination, preparation process complexity and higher cost caused by etching multilayer steps are avoided, area required for device is reduced, improves the yield of wafer.
Description
Technical field
The present invention relates to semiconductor devices and its manufacturing field, in particular to a kind of 3D NAND device and its manufacturing method.
Background technique
Nand flash memory is a kind of storage equipment more better than hard disk drive, with people pursue low in energy consumption, light weight and
The non-volatile memory product of excellent performance, is widely used in electronic product.Currently, the nand flash memory of planar structure is
The limit of nearly true extension reduces the carrying cost of every bit to further improve memory capacity, proposes 3D structure
Nand memory part.
In 3D nand memory part structure, by the way of vertical stacking multilayered memory unit, the vertical of stack is realized
Body memory part.When manufacturing 3D nand memory part, it is initially formed insulating layer and the alternately stacked stack layer of sacrificial layer, and
By multiple photoetching and etching technics, ladder pattern is formed in the side of stack layer, so that stack layer has middle section and rank
Terraced region；Then, channel hole (Channel hole) is formed in middle section, channel hole is used to form accumulation layer；In channel
It is formed after accumulation layer in hole, the silicon nitride layer in stack layer is replaced with into metal layer, each layer of metal layer is that each layer is deposited
The control gate of storage unit, each layer of step of stack layer staircase areas are used to form the contact plug of each layer of control gate.
In this manufacturing process, form contact plug in stepped area, and being continuously increased with stacking number, need through
It crosses more multiple tracks lithography and etching technique and forms ladder pattern, so that manufacturing cost greatly improves, meanwhile, ladder quantity is more, institute
The area for the stack layer that need to be formed is also bigger, is unfavorable for improving the integrated level of memory device, in addition, stacking number is more, wafer
Warpage degree aggravation, when forming contact plug in staircase areas step surface to will definitely be more difficult, influence the performance of device, no
Conducive to the promotion of wafer yield.
Summary of the invention
In view of this, reducing and being etched into the purpose of the present invention is to provide a kind of 3D NAND device and its manufacturing method
This, reduces device area, promotes device integration, improve wafer yield.
To achieve the above object, this application provides a kind of manufacturing methods of 3D nand memory part, this method comprises:
Substrate is provided；
Sacrificial layer and the alternately stacked stack layer of insulating layer are formed over the substrate, and the stack layer has first area
And second area, the accumulation layer being formed in the stack layer of the first area in channel hole and channel hole；
Coating is formed on the stack layer, and the etching of different pore size is formed in the coating of the second area
Hole；
It is to block with the coating except the etched hole, the etching of the stack layer is carried out, under the etched hole
Contact hole is formed, contact hole of the different contact hole stops under the sacrificial layer of different layers, the bigger etched hole in aperture has more
Deep hole depth；
Contact insulation layer is formed on the side wall of the contact hole, and is filled, and contact plug is formed.
Optionally, the bigger etched hole in aperture has deeper hole depth；Then, the step of the etching for carrying out the stack layer
In rapid, further includes: while carrying out the etching of the coating.
Optionally, between the step of forming coating and carrying out the etching of the stack layer, further includes:
Deposition stops control layer, and the blocking control layer in the smaller etched hole in aperture has bigger thickness；Then, it is described into
In the step of etching of the row stack layer, further includes: while carrying out the etching for stopping control layer.
Optionally, the stack layer is rectangle stacking, and the channel hole in the first area is arranged in array, described second
Region is located at the side of the first area.
Optionally, the etched hole in the second area is consistent with the arragement direction in channel hole of its side.
Optionally, after forming contact hole, further includes:
Insulation barrier is formed on the inner wall of the contact hole；
The sacrificial layer is replaced with into metal layer using grid line gap；Then,
Contact insulation layer is formed on the side wall of the contact hole, comprising:
The insulation barrier for removing the contact hole bottom, using the insulation barrier as contact insulation layer.
The embodiment of the present application also provides a kind of 3D nand memory part, which includes:
Substrate；
Metal layer on the substrate and the alternately stacked stack layer of insulating layer, the stack layer have first area and the
Two regions, the accumulation layer being formed in the stack layer of the first area in channel hole and channel hole；
Contact hole in the stack layer of the second area, different contact holes has different apertures and aperture is bigger
Contact hole is set on the metal layer of more lower；
The contact plug in contact insulation layer and contact hole on contact hole side wall.
Optionally, the stack layer is rectangle stacking, and the channel hole in the first area is arranged in array, described second
Region is located at the side of the first area.
Optionally, the contact hole in the second area is consistent with the arragement direction in channel hole of its side.
The manufacturing method of 3D nand memory part provided in an embodiment of the present invention, by be formed on the substrate sacrificial layer with
The stack layer that insulating layer is alternately stacked, the accumulation layer being formed in the first area of the stack layer in channel hole and channel hole,
Coating is formed on stack layer, and the etched hole of different pore size is wherein formed in the coating of second area, is with coating
It blocks, carries out the etching of stack layer, to form contact hole under etched hole, different contact hole stops is in the sacrifice of different layers
Layer.Since in etching process, etched hole aperture is bigger, under stack layer etch rate it is bigger so that bigger etched hole
Under contact hole can have deeper hole depth, realize the etching of the contact hole of different depth, thus, formed correspond to difference
The contact hole of sacrificial layer.For the memory device with more layer heap lamination, avoids and prepare work caused by etching multilayer steps
Skill complexity and higher cost, reduce area required for device, improve the yield of wafer.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 a and 1b show the lateral sectional view and vertical view of the 3D nand memory part of the formation of prior art offer
Figure；
Fig. 2 shows a kind of production method flow charts of 3D nand memory part provided by the embodiments of the present application；
Fig. 3 a-3h shows the device formed during 3D nand memory part according to the manufacturing method of the embodiment of the present application
Part the schematic diagram of the section structure；
Fig. 4 shows the schematic top plan view of the etched hole in the embodiment of the present application；
Fig. 5 shows the production method flow chart of another kind 3D nand memory part provided by the embodiments of the present application；
Fig. 6 a-6j is shown to be formed during 3D nand memory part according to the manufacturing method of another embodiment of the application
Device profile structural schematic diagram.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
Implemented using other than the one described here other way, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by the specific embodiments disclosed below.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
As shown in Figure 1a, staircase areas in the 3D NAND vertical stacks stacked memory cells formed for art methods
Lateral diagrammatic cross-section forms each layer and deposits by the way that the silicon nitride layer (not shown go out) in stack layer is replaced with metal layer 101
The control gate of storage unit, horizontal metal control grid layer 101 are connected by individual vertical metal connecting line 102 with wordline 103, wherein
It is separated between vertical metal line 102 by insulating layer (not shown go out).
As shown in Figure 1 b, the top view of the 3D NAND vertical stacks stacked memory cells formed for art methods, the left side
Part be staircase areas 104, dotted line indicate be in step structure metal gate, horizontal metal grid layer connected by individual vertical metal
Line 102 is connected with wordline 103.Right side is storage region 105, is formed with the array in channel hole 106.Formed above vertical
In the method for stack layer storage unit, Metal gate layer 101 be it is step-like, with being continuously increased for stacking number, cost of manufacture
It greatly improves, the area for forming stack layer also greatly increases.
To solve the above-mentioned problems, this application provides a kind of manufacturing methods of 3D nand memory part, as shown in Figure 2
For a kind of manufacturing method flow chart of 3D nand memory part of the embodiment of the present application, below with reference to flow chart and attached drawing 3a-3h
Specific embodiment is described in detail, in order to preferably embody this programme, attached drawing 3a-3h illustrates only 3D NAND and deposits
The schematic diagram of the section structure of the contact area of memory device, the first area in the description of storage region, that is, the application, contact area
Second area i.e. in the application description.
Step S201 provides substrate 201, with reference to shown in Fig. 3 a.
In the embodiment of the present application, substrate 201 is semiconductor substrate, such as can be Si substrate, Ge substrate, SiGe lining
Bottom, SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium On
Insulator) etc..In other embodiments, the semiconductor substrate can also be include other elements semiconductor or compound
The substrate of semiconductor, such as GaAs, InP or SiC etc. can also be laminated construction, such as Si/SiGe etc. can also be other
Epitaxial structure, such as SGOI (silicon germanium on insulator) etc..In the present embodiment, the substrate 201 is body silicon substrate, is used to support
Device architecture on it.
Step S202 forms sacrificial layer 203 and the alternately stacked stack layer of insulating layer 202, with reference to Fig. 4 on substrate 201
Shown, the stack layer has first area 105 and second area 303, is formed with ditch in the stack layer of the first area 105
Accumulation layer (not shown go out) in road hole 106 and channel hole.
In the step, insulating layer 202 can be silica, and sacrificial layer 203 can be silicon nitride, by silicon nitride layer and oxidation
Silicon layer is alternately laminated to form stack layer, determines the layer of stack layer according to the number of the storage unit of formation needed for vertical direction
Number, the number of plies of stack layer for example can be 8 layers, 32 layers, 64 layers etc., and the number of plies is more, can more improve integrated level.It can be using chemistry
Vapor deposition, atomic layer deposition or other suitable deposition methods, successively alternating deposit silicon nitride and silica, form the stacking
Layer.
Patterned photoresist can be formed by exposure development by the spin coating photoresist layer on stack layer
Layer forms the array of through-hole that is, in the photoresist layer of second area, is masking with the patterned photoresist layer, by heap
The etching of lamination forms the channel hole 106 of exposure substrate, with reference to shown in Fig. 4.
After channel hole 106 is formed, the formation of accumulation layer in the removal and channel hole 106 of photoresist layer is carried out, is stored
Layer includes electric charge capture layer and channel layer, and electric charge capture layer for example can be ONO structure, i.e. oxide, nitride and oxide
Lamination, channel layer for example can be polysilicon layer, in specific application, successively on the side wall of channel hole formed ONO electricity
The channel layer of lotus trapping layer and polysilicon, then forms filled layer in channel hole, and filled layer can be silica.
Step S203 forms coating 204 on the stack layer, is formed in the coating 204 of the second area
The etched hole 207 of different pore size.
Coating 204 is mask layer when subsequent etching forms contact hole, is the protective layer of the exterior domain of contact hole, can be with
According to the specific material and thickness needed to select coating 204.In some embodiments, coating 204 can be to heap
There is lamination the material of high selectivity ratio to be formed, and coating 204 for example can be polysilicon membrane, and etched hole 207 therein can be with
It is the through-hole of exposed stack layer.In the application other embodiments, coating 204 is also possible to other hard mask materials.Due to
Coating 204 has high selectivity ratio to stack layer, therefore will not be etched when carrying out the etching of stack layer later, and due to carving
The pore size of borrosion hole 207 is different, and the etch rate of the more stack layer under large aperture is bigger, so as to form different depth
Contact hole 208 (refers to Fig. 3 d).
In further embodiments, coating 204 can be the material to stack layer with low selection ratio, that is, carve
When losing stack layer, coating 204 can also be etched away a part, coating 204 such as can be for agraphitic carbon or silica,
When performing etching to stack layer, the thickness of coating 204 is also being reduced, therefore the thickness of coating 204 needs to have properly
Thickness, or other barrier layers are set under coating 204, avoid stack layer by over etching.In this embodiment, it etches
Hole 207 can be the through-hole of exposed stack layer, more preferably, be also possible to by certain depth but do not penetrate the hole of the coating 204,
And the bigger etched hole in aperture has a deeper hole depth, that is, the smaller lower coating 204 retained of etched hole 207 in aperture
Thickness is bigger.Since the pore size of etched hole 207 is different, the etch rate of the more stack layer under large aperture is bigger, meanwhile, more
The coating 204 of reservation under small etched hole 207 is thicker, in this way, making the etching of the stack layer under smaller etched hole 207
Time started is more late, is convenient for the control of etch rate, forms the contact hole 208 of different hole depths.
In the particular embodiment, as shown in Figure 3a, it is possible, firstly, to deposit coating on the stack layer of second area
204, and the spin coating photoresist layer 205 on coating 204 then forms patterned photoresist layer 205, patterned photoetching
The through-hole 206 with different apertures is formed in glue-line 205；Then, with reference to shown in Fig. 3 b, using photoresist layer 205 as covering
Film performs etching, and forms the etched hole 207 of different pore size on the cover layer, then removes photoresist 205, as shown in Figure 3c.Covering
The etching mode of layer can be anisotropic dry etching, since the pore size of through-hole 206 in photoresist layer 205 is different,
To, more the coating under the through-hole 206 of large aperture has faster etch rate, thus, form the different etching of depth
The upper diameter in hole 207, the etched hole formed in anisotropic etching is typically larger than base diameter.
In the stack layer that rectangle stacks, the channel hole 106 of usual first area 105 is arranged in array, array arrangement
Mode can be ranks alignment arrangement, as shown in figure 4, be also possible to the arrangement of wrong row, that is, a line channel hole be formed in front of
At position between two channel holes of a line, be conducive to the integration density for improving channel hole.In embodiments of the present invention, the secondth area
Domain 303 can be located at the side of first area 105, such as one side of side, be also possible to the polygon of side, second area 303
In etched hole 304 can be consistent with the arragement direction in channel hole 106 of its side, in this way, contact hole can be effectively reduced
The area in region, to reduce the area of whole memory.
It is illustrated in figure 4 a kind of possible embodiment of the application, the etched hole 106 in second area 105 is in array
Distribution, second area 303 are located at the side of first area, and each etched hole 304 can arragement direction can be with first area 105
In channel hole 106 arragement direction it is consistent.Therefore, in the side of first area, the area of second area need to only accommodate multiple
Rows of etched hole, such as 32 layers of stack layer, the area of the second area in the embodiment of the present application is only needed
Accommodate 32 etched holes, compared with the existing technology in for 32 metal gate steps needing, save the area of stack layer, drop
Low cost.
Step S204 is to block with the coating 204 except etched hole 207, the etching of stack layer is carried out, in etched hole
Contact hole 208 is formed under 207, different contact holes 208 stops at the sacrificial layer 203 of different layers, the bigger etched hole 207 in aperture
Under contact hole 208 have deeper hole depth, with reference to shown in Fig. 3 d.
To the etching of stack layer, anisotropic dry etching can be, such as can be RIE (reactive ion etching),
As shown in Figure 3d, the stack layer under etched hole 207 is etched to form contact hole 208.The etched hole 207 of different pore size, due to it
Influence to etch rate, the depth for forming contact hole 208 is also different, the contact hole under etched hole 207 biggish for aperture
208, because etch rate is larger, the contact hole 208 formed has deeper hole depth.
In the etching process to stack layer, for having the coating 204 of the material formation of high selectivity ratio to stack layer,
Its thickness change very little.For the coating 204 that there is the material of low selection ratio to be formed stack layer, during etching,
The coating 204 is also gradually etched, and thickness is constantly reduced, therefore in the formation of coating 204, should be taken into account that etching causes
Coating 204 be lost, the thickness being initially formed can be greater than the loss thickness that is formed in etching process, or in coating
Lower increase barrier layer.
Since the pore size of the etched hole 207 of formation is different, alternatively, further, the coating under etched hole 207
The thickness of 204 reservation is also different, and aperture is bigger, and in etching process, the etch rate of other layers that are etched will be more
Fastly, the coating 204 of reservation can also postpone the etching to the stack layer being etched, and controlled by these, be can be combined with simultaneously
The control of specific etching technics, after etching, the contact hole 208 bigger etched hole 207 in aperture under with deeper hole depth, and
It stops on different sacrificial layers 203.
In step S205, contact insulation layer 211 is formed on the side wall of contact hole 208, and be filled, form contact plug
212, with reference to Fig. 3 g and 3h.
The contact insulation layer 211 is insulating materials, such as can be silica or silicon oxynitride etc., is contacted as being formed
Separation layer after plug 211 with other metal layers.Removal contact hole can be then performed etching by Deposit contact insulating layer material
The contact insulation layer material of bottom is formed.Then, metal material, such as W are filled in the contact hole, to form contact plug
212。
In the preferred embodiment of the invention, which carries out after the replacement for carrying out sacrificial layer 203, is easy to
It realizes, and is conducive to improve the integrated level of technique.
Specifically, after step s 204, following steps can be carried out:
Step S2051 forms insulation barrier 209 on the inner wall of contact hole 208.
Sacrificial layer 203 is replaced with metal layer 210 using grid line gap by step S2052.
Step S2053 removes the insulation barrier of 208 bottom of contact hole, insulate using the insulation barrier as contact
Layer, and contact plug is formed in the contact hole.
As shown in Figure 3 e, insulation barrier 209 is formed in contact hole side wall.The insulation barrier 209 is by sacrificial layer 203
In the technique for replacing with metal layer 210, the purpose for being kept in contact pattern is played.It should be noted that contact insulation layer 211 is exhausted
Edge material, as the separation layer formed after contact plug 212 with other metal layers.As a preferred embodiment, insulation
Barrier layer 209 is a kind of insulating materials, for example, can for silica or silicon oxynitride etc., can be realized after forming contact plug with its
The purpose of the isolation of his metal layer, therefore the insulation barrier of contact hole bottom can be removed, as contact insulation layer 212,
To simplify preparation process.In the application other embodiments, above two film can also be formed by different materials.
In the particular embodiment, the insulation barrier 209 of silica, ginseng can be formed using the method for atomic layer deposition
As shown in Fig. 3 e, insulation barrier 209 is formed on the inner wall of contact hole.
Then, by the silicon nitride layer 203 in grid line gap (not shown go out) removal stack layer, and substitution nitrogen is formed
The metal layer 210 of SiClx.Normally, it is initially formed grid line gap, then, selects the acid to the high selectivity ratio of silicon nitride and silica
Liquid enters grid line gap by acid solution, silicon nitride layer 203 is removed, and acid solution for example can be phosphoric acid (H3PO4).Remove silicon nitride
After 203, it is packed into metal layer 210, metal layer 210 can be tungsten (W).Vapor deposition can be used in the filling of metal layer 210
Method is realized, then removes extra part metals by carve to metal, metal layer 210 is formed, with reference to Fig. 3 f.
Later, it needs to remove on contact hole bottom insulation barrier layer, forms contact insulation layer 211, connect so as to subsequent
The formation of touching plug 212.As shown in figure 3g, insulation barrier 209 is removed by anisotropic dry etching and is located at contact hole bottom
The part in portion.As illustrated in figure 3h, contact plug 211 is formed in the contact hole, and contact plug 211 can be for connecting 103 He of wordline
The metallic conductor of metal layer 210, such as can be tungsten.
The manufacturing method of 3D nand memory part provided in an embodiment of the present invention, by be formed on the substrate sacrificial layer with
The stack layer that insulating layer is alternately stacked, the accumulation layer being formed in the first area of the stack layer in channel hole and channel hole,
Coating is formed on stack layer, and the etched hole of different pore size is wherein formed in the coating of second area, is with coating
It blocks, carries out the etching of stack layer, to form contact hole under etched hole, different contact hole stops is in the sacrifice of different layers
Layer.Since in etching process, etched hole aperture is bigger, under stack layer etch rate it is bigger so that bigger etched hole
Under contact hole can have deeper hole depth, realize the etching of the contact hole of different depth, thus, formed correspond to difference
The contact hole of sacrificial layer.For the memory device with more layer heap lamination, avoids and prepare work caused by etching multilayer steps
Skill complexity and higher cost, reduce area required for device, improve the yield of wafer.
Based on the above embodiment, this application provides the manufacturing methods of another 3D nand memory part, with above-mentioned implementation
Example unlike, in coating formed different pore size etched hole after, can further deposit blocking control layer, so as into
One step controls the etching speed of stack layer, part unlike the embodiments above described in detail below, and same section will no longer go to live in the household of one's in-laws on getting married
It states.
Refering to what is shown in Fig. 5, step S501, provides substrate 201, with reference to shown in Fig. 6 a.
Identical in substrate step S201 in the embodiment of the present application, details are not described herein.
Step S502 forms sacrificial layer 203 and the alternately stacked stack layer of insulating layer 202, with reference to Fig. 4 on substrate 201
Shown, stack layer has first area 105 and second area 303, is formed with channel hole 106 in the stack layer of first area 105
And the accumulation layer (not shown go out) in channel hole.
Above-mentioned steps are identical as step S202, and details are not described herein.
Step S503 forms coating 202 on stack layer, is formed with different pore size in the coating of second area 303
Etched hole 207, with reference to Fig. 6 b.
Coating 204 is mask layer when subsequent etching forms contact hole, is the protective layer of the exterior domain of contact hole, can be with
According to the specific material and thickness needed to select coating 204.In some embodiments, coating 204 can be to heap
Lamination has the material of high selectivity ratio, and coating 204 for example can be polysilicon membrane, and etched hole 207 therein can be cruelly
Reveal the through-hole of stack layer.In further embodiments, coating 204 can be the material to stack layer with low selection ratio,
Be exactly when etching stack layer, coating 204 can also be etched away a part, coating 204 for example can for agraphitic carbon or
Silica etc., when performing etching to stack layer, the thickness of coating 204 is also being reduced, therefore the thickness of coating 204 needs
With suitable thickness, or other barrier layers are set under coating 204, avoid stack layer by over etching.
The forming process of coating 204 is shown in step S203, and details are not described herein.
In the stack layer that rectangle stacks, the channel hole 106 of usual first area 105 is arranged in array, array arrangement
Mode can be ranks alignment arrangement, as shown in figure 4, be also possible to the arrangement of wrong row, that is, a line channel hole be formed in front of
At position between two channel holes of a line, be conducive to the integration density for improving channel hole.In embodiments of the present invention, the secondth area
Domain 303 can be located at the side of first area 105, such as one side of side, be also possible to the polygon of side, second area 303
In etched hole 304 can be consistent with the arragement direction in channel hole 106 of its side, therefore, the side in first area, second
The area in region need to only accommodate multiple rows of etched holes, in this way, the area of contact bore region can be effectively reduced, from
And the area of whole memory is reduced, it reduces costs.
Step S504, deposition stop control layer 401, and the blocking control layer 401 in the smaller etched hole in aperture has bigger
Thickness.
Stopping control layer 401 can be relative to stack layer there is the material of low selection ratio to be formed, when etching stack layer,
The blocking control layer 401 will be also etched away, as the control layer for etching etch rate when forming contact hole.Due to coating
The aperture of middle etched hole is different, and the uniformity of film will be different when deposition, the more resistance of the etched hole bottom surface of small-bore
The thickness for keeping off control layer can be thicker, stops control layer 401 in this way, being formed by deposition, smaller when performing etching to stack layer
The first etch stopper control layer of meeting in aperture, and then stack layer can be just etched into, by the etching barrier layer of different-thickness, can control
The initial time of system etching stack layer, the etch period of the more stack layer under small-bore is more late, thus, further control stack layer
The depth of middle contact hole.
Deposition stops the method for control layer 401 to can be vapour deposition process, in the coating 204 for being formed with etched hole 207
Surface, which is formed, stops control layer 401, as fig. 6 c, after stopping the deposition of control layer 401, in the etched hole of different pore size
Blocking 401 film of control layer thickness it is different, the aperture of etched hole is smaller, in the blocking control layer 401 that is formed it is thicker, carve
Erosion stops control layer 401 longer to expose the time required for stack layer.As shown in fig 6d, it is carried out to blocking control layer 401
When etching, the blocking control layer 401 in the biggish etched hole 207 in aperture is relatively thin, and etch rate is very fast, more first complete etching with
Expose the stack layer under it；And the blocking control layer 401 in the lesser etched hole 207 in aperture is thicker, and its etch rate is slower,
Etching is completed more afterwards.By stopping control layer 401 to realize to the sequence of the lower stack layer etching of different etching hole 207 and rate
Control, further controls the depth of contact hole 208, with reference to shown in Fig. 6 f.
In the embodiment of the present application, step S504 is the etching in order to control stack layer, is preferred mode, in the application
It, can also be without not influencing the realization of the embodiment of the present application in other embodiments.
Step S505 is to block with the coating 204 except etched hole 207, the etching of stack layer 208 is carried out, to carve
Contact hole 208 is formed under borrosion hole 207, different contact holes 208 stops at the sacrificial layer 203 of different layers, the bigger etching in aperture
Contact hole 208 under hole 207 has deeper hole depth, with reference to shown in Fig. 6 f.
To the etching of stack layer, anisotropic dry etching can be, such as can be RIE (reactive ion etching),
Stack layer under etched hole 207 is etched to form contact hole 208.The etched hole 207 of different pore size, since it is to etch rate
It influences, the depth for forming contact hole 208 is also different, the contact hole 208 under etched hole 207 biggish for aperture, because of etching
Rate is larger and etched hole in blocking control layer it is thinner, therefore the contact hole 208 formed has deeper hole depth.
In the etching process to stack layer, while blocking control layer 401 can be performed etching.Due to the quarter of different pore size
The blocking control layer thickness formed in borrosion hole is different, and the etch rate of the blocking control layer in the etched hole of different pore size is not
Together, therefore, it in such as specific embodiment of Fig. 6 d, in stack layer etching process, needs to perform etching blocking control layer,
Blocking control layer thickness in the biggish etched hole in aperture is smaller, and take the lead in the etching for completing to etch and begin to stack up layer, therefore heap
The etching of lamination is more early, and the blocking control layer thickness in the lesser etched hole in aperture is larger, needs the long period that could complete to carve
The stack layer under it is lost and exposed, therefore the etching of stack layer is later, therefore by stopping control layer 401, may be implemented pair
The control of the sequence and rate of the lower stack layer etching of the etched hole 207 of different pore size.
As shown in fig 6e, the stack layer etch rate under the biggish etched hole 207 in aperture is very fast, the lesser etched hole in aperture
Under stack layer etch rate it is slower, formed interstitial hole 402, interstitial hole 402 is continued to etch, formed contact hole 208, such as
Shown in Fig. 6 f, wherein the contact hole 208 of different pore size stops at different sacrificial layers 203, to be replaced by sacrificial layer 203
After metal, the metal medium 212 in contact hole 208 is connected to (with reference to Fig. 6 j) with metal layer 210.
Step S506 forms insulation barrier 209 (as shown in figure 6g) on the inner wall of the contact hole；It is stitched using grid line
The sacrificial layer 203 is replaced with metal layer 210 (as shown in figure 6h) by gap (not shown go out)；Remove 208 bottom of contact hole
Insulation barrier (as shown in Fig. 6 i), using the insulation barrier as contact insulation layer 211, and be filled, formation connects
212 (as shown in Fig. 6 j) of touching plug.
Above-mentioned steps are similar with step S205, and details are not described herein.
The manufacturing method of 3D nand memory part provided in an embodiment of the present invention, is controlled by the etched hole of different pore size
The etch rate to stack layer is made, by stopping control layer control to be formed to the etch period of stack layer and correspond to different sacrifices
The contact hole of layer.For the memory device with more layer heap lamination, the accuracy of stack layer etching is improved, etching is avoided
The complexity of preparation process caused by multilayer steps and higher cost, reduce area required for device, improve the yield of wafer.
Based on the description of the manufacturing method above to 3D nand memory part, present invention also provides one kind by above-mentioned side
The 3D nand memory part that method is formed, with reference to shown in Fig. 4 and Fig. 6 j, which includes:
Substrate 201；
Metal layer 210 and the alternately stacked stack layer of insulating layer 202 on the substrate, the stack layer have the firstth area
Domain and second area, the accumulation layer being formed in channel hole and channel hole in the stack layer of the first area are (not shown
Out)；
Contact hole 208 in the stack layer of the second area, different contact holes has different apertures and aperture is got over
Big contact hole is set on the metal layer 210 of more lower；
The contact plug 212 in contact insulation layer 211 and contact hole on 208 side wall of contact hole.
In the stack layer that rectangle stacks, the channel hole of usual first area is arranged in array, and can set second area
Side positioned at first area, such as one side of side, are also possible to the polygon of side, and the etched hole in second area can be with
The arragement direction in the channel hole of its side is consistent, and therefore, the side in first area, the area of second area need to only accommodate multiple
Rows of etched hole saves the area of stack layer, reduces costs.
The above is only a preferred embodiment of the present invention, although the present invention has been disclosed in the preferred embodiments as above, so
And it is not intended to limit the invention.Anyone skilled in the art is not departing from technical solution of the present invention ambit
Under, many possible changes and modifications all are made to technical solution of the present invention using the methods and technical content of the disclosure above,
Or equivalent example modified to equivalent change.Therefore, anything that does not depart from the technical scheme of the invention, according to the present invention
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within the technology of the present invention side
In the range of case protection.
Claims (5)
1. a kind of manufacturing method of 3D nand memory part characterized by comprising
Substrate is provided；
Form sacrificial layer and the alternately stacked stack layer of insulating layer over the substrate, the stack layer has first area and the
Two regions, the accumulation layer being formed in the stack layer of the first area in channel hole and channel hole；
Coating is formed on the stack layer, and the etched hole of different pore size is formed in the coating of the second area；
Deposition stops control layer, and the blocking control layer in the smaller etched hole in aperture has bigger thickness；
It is to block, while carrying out the stack layer and the etching for stopping control layer with the coating except the etched hole,
To form contact hole under the etched hole, different contact hole stops is in the sacrificial layer of different layers, the bigger etched hole in aperture
Under contact hole have deeper hole depth；
Contact insulation layer is formed on the side wall of the contact hole, and is filled, and contact plug is formed.
2. the manufacturing method according to claim 1, which is characterized in that the bigger etched hole in aperture has deeper hole depth；
Then,
In the step of etching for carrying out the stack layer, further includes:
The etching of the coating is carried out simultaneously.
3. the manufacturing method according to claim 1, which is characterized in that the stack layer is rectangle stacking, firstth area
Channel hole in domain is arranged in array, and the second area is located at the side of the first area.
4. manufacturing method according to claim 3, which is characterized in that etched hole and its side in the second area
The arragement direction in channel hole is consistent.
5. the manufacturing method according to claim 1, which is characterized in that after forming contact hole, further includes:
Insulation barrier is formed on the inner wall of the contact hole；
The sacrificial layer is replaced with into metal layer using grid line gap；Then,
Contact insulation layer is formed on the side wall of the contact hole, comprising:
The insulation barrier for removing the contact hole bottom, using the insulation barrier as contact insulation layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711059075.7A CN107680972B (en) | 2017-11-01 | 2017-11-01 | A kind of 3D nand memory part and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711059075.7A CN107680972B (en) | 2017-11-01 | 2017-11-01 | A kind of 3D nand memory part and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107680972A CN107680972A (en) | 2018-02-09 |
| CN107680972B true CN107680972B (en) | 2019-01-29 |
Family
ID=61143514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711059075.7A Active CN107680972B (en) | 2017-11-01 | 2017-11-01 | A kind of 3D nand memory part and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107680972B (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI651837B (en) * | 2018-02-21 | 2019-02-21 | Powerchip Technology Corporation | Integrated circuit structure and manufacturing method thereof |
| CN108470737B (en) * | 2018-03-19 | 2021-10-29 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN108649033B (en) * | 2018-03-20 | 2021-07-13 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
| DE112018007788T5 (en) * | 2018-07-27 | 2021-04-15 | Yangtze Memory Technologies Co., Ltd. | THREE-DIMENSIONAL STORAGE DEVICE WITH MULTIPLE STACKS AND METHOD OF MANUFACTURING IT |
| CN109545790B (en) * | 2018-11-02 | 2021-08-31 | 长江存储科技有限责任公司 | Method for forming channel hole of three-dimensional memory |
| CN109524417B (en) * | 2018-11-27 | 2021-03-30 | 长江存储科技有限责任公司 | 3D NAND memory and forming method thereof |
| CN109716521A (en) | 2018-12-12 | 2019-05-03 | 长江存储科技有限责任公司 | Contact structures for three-dimensional storage part |
| CN110112133A (en) * | 2019-03-29 | 2019-08-09 | 长江存储科技有限责任公司 | Three-dimensional storage part and preparation method thereof |
| CN111162081B (en) * | 2020-01-02 | 2022-04-26 | 长江存储科技有限责任公司 | Method for forming step region and method for manufacturing semiconductor device |
| CN111312713B (en) * | 2020-03-03 | 2021-07-20 | 长江存储科技有限责任公司 | Three-dimensional memory, preparation method thereof and electronic equipment |
| CN111430362B (en) * | 2020-04-09 | 2023-07-25 | 长江存储科技有限责任公司 | Manufacturing method of 3D NAND memory device |
| CN114709219A (en) * | 2020-05-18 | 2022-07-05 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN112885839B (en) * | 2020-06-18 | 2021-12-28 | 长江存储科技有限责任公司 | Three-dimensional memory, preparation method and electronic equipment |
| WO2022052049A1 (en) * | 2020-09-11 | 2022-03-17 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory device and fabrication method thereof |
| CN116018060B (en) * | 2023-03-27 | 2023-06-13 | 长鑫存储技术有限公司 | Semiconductor structure, preparation method thereof and packaging structure |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4737953B2 (en) * | 2004-07-14 | 2011-08-03 | 株式会社東芝 | Manufacturing method of semiconductor device |
| JP5305980B2 (en) * | 2009-02-25 | 2013-10-02 | 株式会社東芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
| JP2011060958A (en) * | 2009-09-09 | 2011-03-24 | Toshiba Corp | Semiconductor device, and method of manufacturing the same |
| JP2012174892A (en) * | 2011-02-22 | 2012-09-10 | Toshiba Corp | Semiconductor storage device and manufacturing method of the same |
| KR101721117B1 (en) * | 2011-03-15 | 2017-03-29 | 삼성전자 주식회사 | Method for fabricating of semiconductor device |
| CN106920794B (en) * | 2017-03-08 | 2018-11-30 | 长江存储科技有限责任公司 | A kind of 3D nand memory part and its manufacturing method |
-
2017
- 2017-11-01 CN CN201711059075.7A patent/CN107680972B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN107680972A (en) | 2018-02-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107680972B (en) | A kind of 3D nand memory part and its manufacturing method | |
| CN107564915B (en) | A kind of 3D nand memory part and its manufacturing method | |
| CN109524417B (en) | 3D NAND memory and forming method thereof | |
| CN107863348B (en) | A kind of 3D nand memory part and its manufacturing method | |
| CN110176461A (en) | 3D nand memory and forming method thereof | |
| CN108565266A (en) | Form the method and three-dimensional storage of three-dimensional storage | |
| KR101907069B1 (en) | Nonvolatile memory device and method for fabricating the same | |
| JP7427685B2 (en) | Three-dimensional memory device with support structure in slit structure and method for forming the three-dimensional memory device | |
| CN109564922A (en) | Three-dimensional storage equipment and its manufacturing method | |
| CN110062958A (en) | The method for being used to form three-dimensional storage part | |
| CN110462828A (en) | Memory devices and forming method thereof | |
| TWI565037B (en) | Embedded memory device with silicon-on-insulator substrate, and method of making same | |
| CN108766971A (en) | Three-dimensional storage and its manufacturing method | |
| CN109920792A (en) | A kind of manufacturing method of 3D nand memory part | |
| CN110121778A (en) | Three-dimensional storage part | |
| CN108649033A (en) | Semiconductor devices and its manufacturing method | |
| CN111403397B (en) | 3D NAND memory and manufacturing method thereof | |
| CN107078035B (en) | The method that the in-line memory equipment with silicon-on-insulator substrate is made | |
| CN110289265A (en) | The forming method of 3D nand memory | |
| CN109755252A (en) | A kind of memory device and its manufacturing method | |
| KR102655098B1 (en) | Three-dimensional memory device with source structure and methods for forming the same | |
| CN110289263A (en) | 3D nand memory and forming method thereof | |
| CN110197830A (en) | 3D nand memory and forming method thereof | |
| KR20140025054A (en) | Nonvolatile memory device and method for fabricating the same | |
| CN107818984A (en) | A kind of 3D nand memories part and its manufacture method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |