CN107680972A - A kind of 3D nand memories part and its manufacture method - Google Patents
A kind of 3D nand memories part and its manufacture method Download PDFInfo
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- CN107680972A CN107680972A CN201711059075.7A CN201711059075A CN107680972A CN 107680972 A CN107680972 A CN 107680972A CN 201711059075 A CN201711059075 A CN 201711059075A CN 107680972 A CN107680972 A CN 107680972A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
The present invention provides a kind of manufacture method of 3D nand memories part, the stack layer being alternately stacked by forming sacrifice layer on substrate with insulating barrier, formed with the accumulation layer in raceway groove hole and raceway groove hole in the first area of the stack layer, coating is formed on stack layer, the wherein etched hole formed with different pore size in the coating of second area, using coating to block, carry out the etching of stack layer, to form contact hole under etched hole, different contact hole stops is in the sacrifice layer of different layers.Due in etching process, etched hole aperture is bigger, and the etch rate of the stack layer under it is bigger so that the contact hole under bigger etched hole can have deeper hole depth, it is achieved that the etching of the contact hole of different depth, forms the contact hole corresponding to different sacrifice layers.For the memory device with compared with multilayer stack layer, preparation technology complexity and higher cost, reduce the area required for device, improve the yield of wafer caused by avoiding etching multilayer steps.
Description
Technical field
The present invention relates to semiconductor devices and its manufacturing field, more particularly to a kind of 3D NAND devices and its manufacture method.
Background technology
Nand flash memory is a kind of storage device more more preferable than hard disk drive, with people pursue low in energy consumption, light weight and
The non-volatile memory product of excellent performance, is widely used in electronic product.At present, the nand flash memory of planar structure has been
The limit of nearly true extension, in order to further improve memory capacity, reduce the carrying cost per bit, it is proposed that 3D structures
Nand memory part.
In 3D nand memory part structures, by the way of vertical stacking multilayered memory unit, the vertical of stack is realized
Body memory part.When manufacturing 3D nand memory parts, insulating barrier and the alternately laminated stack layer of sacrifice layer are initially formed, and
By multiple photoetching and etching technics, ladder pattern is formed in the side of stack layer so that stack layer has middle section and rank
Terraced region；Then, raceway groove hole (Channel hole) is formed in middle section, raceway groove hole is used to form accumulation layer；In raceway groove
Formed in hole after accumulation layer, the silicon nitride layer in stack layer is replaced with into metal level, each layer of metal level is deposited for each layer
The control gate of storage unit, each layer of step of stack layer staircase areas are used for the contact plug for forming each layer of control gate.
In this manufacturing process, form contact plug in stepped area, and with stacking number be continuously increased, it is necessary to through
To cross more multiple tracks photoetching and etching technics forms ladder pattern so that manufacturing cost greatly improves, meanwhile, ladder quantity is more, institute
The area for the stack layer that need to be formed is also bigger, is unfavorable for improving the integrated level of memory device, in addition, stacking number is more, wafer
Warpage degree aggravation, when forming contact plug with staircase areas step surface to will definitely be more difficult, influence the performance of device, no
Beneficial to the lifting of wafer yield.
The content of the invention
In view of this, it is an object of the invention to provide a kind of 3D NAND devices and its manufacture method, reduce and be etched into
This, reduces device area, promotes device integration, improve wafer yield.
To achieve the above object, this application provides a kind of manufacture method of 3D nand memories part, this method to include：
Substrate is provided；
Sacrifice layer and the alternately laminated stack layer of insulating barrier are formed over the substrate, and the stack layer has first area
And second area, formed with the accumulation layer in raceway groove hole and raceway groove hole in the stack layer of the first area；
Form coating on the stack layer, the etching formed with different pore size in the coating of the second area
Hole；
Using the coating outside the etched hole to block, the etching of the stack layer is carried out, with the etched hole
Contact hole is formed, contact hole of the different contact hole stops under the sacrifice layer of different layers, the bigger etched hole in aperture has more
Deep hole depth；
Contact insulation layer is formed in the side wall of the contact hole, and is filled, forms contact plug.
Alternatively, the bigger etched hole in aperture has deeper hole depth；Then, the step of the etching for carrying out the stack layer
In rapid, in addition to：The etching of the coating is carried out simultaneously.
Alternatively, between the step of forming coating and carrying out the etching of the stack layer, in addition to：
Deposit and stop key-course, the stop key-course in the smaller etched hole in aperture has bigger thickness；Then, it is described enter
In the step of etching of the row stack layer, in addition to：The etching of the stop key-course is carried out simultaneously.
Alternatively, the stack layer stacks for rectangle, and the raceway groove hole in the first area is arranged in array, and described second
Region is located at the side of the first area.
Alternatively, the etched hole in the second area is consistent with the arragement direction in the raceway groove hole of its side.
Alternatively, after contact hole is formed, in addition to：
Insulation barrier is formed on the inwall of the contact hole；
The sacrifice layer is replaced with into metal level using grid line gap；Then,
Contact insulation layer is formed in the side wall of the contact hole, including：
The insulation barrier of the contact hole bottom is removed, contact insulation layer is used as using the insulation barrier.
The embodiment of the present application additionally provides a kind of 3D nand memories part, and the device includes：
Substrate；
Metal level on the substrate and the alternately laminated stack layer of insulating barrier, the stack layer have first area and the
Two regions, formed with the accumulation layer in raceway groove hole and raceway groove hole in the stack layer of the first area；
Contact hole in the stack layer of the second area, different contact holes has different apertures and aperture is bigger
Contact hole is arranged on the metal level of more lower；
The contact plug in contact insulation layer and contact hole in contact hole side wall.
Alternatively, the stack layer stacks for rectangle, and the raceway groove hole in the first area is arranged in array, and described second
Region is located at the side of the first area.
Alternatively, the contact hole in the second area is consistent with the arragement direction in the raceway groove hole of its side.
The manufacture method of 3D nand memories part provided in an embodiment of the present invention, by substrate formed sacrifice layer with
The stack layer that insulating barrier is alternately stacked, formed with the accumulation layer in raceway groove hole and raceway groove hole in the first area of the stack layer,
Coating, the wherein etched hole formed with different pore size in the coating of second area are formed on stack layer, using coating as
Block, carry out the etching of stack layer, to form contact hole under etched hole, different contact hole stops is in the sacrifice of different layers
Layer.Because in etching process, etched hole aperture is bigger, the etch rate of the stack layer under it is bigger so that bigger etched hole
Under contact hole can have deeper hole depth, realize the etching of the contact hole of different depth, so as to, formed correspond to difference
The contact hole of sacrifice layer.For the memory device with compared with multilayer stack layer, preparation work caused by avoiding etching multilayer steps
Skill complexity and higher cost, reduce the area required for device, improve the yield of wafer.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
These accompanying drawings obtain other accompanying drawings.
Fig. 1 a and 1b show the lateral sectional view and vertical view of the 3D nand memory parts for the formation that prior art provides
Figure；
Fig. 2 shows a kind of preparation method flow chart for 3D nand memories part that the embodiment of the present application provides；
Fig. 3 a-3h show the device formed according to the manufacture method of the embodiment of the present application during 3D nand memory parts
Part cross-sectional view；
Fig. 4 shows the schematic top plan view of the etched hole in the embodiment of the present application；
Fig. 5 shows the preparation method flow chart for another 3D nand memories part that the embodiment of the present application provides；
Fig. 6 a-6j are shown to be formed during 3D nand memory parts according to the manufacture method of another embodiment of the application
Device profile structural representation.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with
It is different from other manner described here using other to implement, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
Secondly, combination schematic diagram of the present invention is described in detail, when the embodiment of the present invention is described in detail, for purposes of illustration only, table
Show that the profile of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, and it should not herein
Limit the scope of protection of the invention.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
As shown in Figure 1a, staircase areas in the 3D NAND vertical stacks stacked memory cells formed for art methods
Lateral diagrammatic cross-section, by the way that the silicon nitride layer (not shown) in stack layer is replaced with into metal level 101, form each layer and deposit
The control gate of storage unit, horizontal metal control grid layer 101 are connected by individual vertical metal connecting line 102 with wordline 103, wherein,
Separated between vertical metal line 102 by insulating barrier (not shown).
As shown in Figure 1 b, the top view of the 3D NAND vertical stacks stacked memory cells formed for art methods, the left side
Part be staircase areas 104, dotted line represents by individual vertical metal to connect in the metal gate of ledge structure, horizontal metal gate layer
Line 102 is connected with wordline 103.Right side is storage region 105, is formed with the array in raceway groove hole 106.Formed above vertical
In the method for stack layer memory cell, Metal gate layer 101 is step-like, with being continuously increased for stacking number, cost of manufacture
Greatly improve, the area for forming stack layer also greatly increases.
In order to solve the above problems, this application provides a kind of manufacture method of 3D nand memories part, as shown in Figure 2
For a kind of manufacture method flow chart of 3D nand memories part of the embodiment of the present application, below with reference to flow chart and accompanying drawing 3a-3h
Specific embodiment is described in detail, in order to preferably embody this programme, accompanying drawing 3a-3h illustrate only 3D NAND and deposit
The cross-sectional view of the contact area of memory device, storage region be the application description in first area, contact area
Second area i.e. in the application description.
Step S201, there is provided substrate 201, with reference to shown in figure 3a.
In the embodiment of the present application, substrate 201 is Semiconductor substrate, such as can be Si substrates, Ge substrates, SiGe linings
Bottom, SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium On
Insulator) etc..In other embodiments, the Semiconductor substrate can also be to include other elements semiconductor or compound
The substrate of semiconductor, such as GaAs, InP or SiC etc., it can also be laminated construction, such as Si/SiGe etc., can also be other
Epitaxial structure, such as SGOI (silicon germanium on insulator) etc..In the present embodiment, the substrate 201 is body silicon substrate, for supporting
In device architecture thereon.
Step S202, sacrifice layer 203 and the alternately laminated stack layer of insulating barrier 202 is formed on the substrate 201, with reference to figure 4
Shown, the stack layer has a first area 105 and second area 303, formed with ditch in the stack layer of the first area 105
Accumulation layer (not shown) in road hole 106 and raceway groove hole.
In the step, insulating barrier 202 can be silica, and sacrifice layer 203 can be silicon nitride, by silicon nitride layer and oxidation
Silicon layer is alternately laminated to form stack layer, and the number of the memory cell formed according to needed for vertical direction determines the layer of stack layer
Number, for the number of plies of stack layer such as can be 8 layers, 32 layers, 64 layers, the number of plies be more, can more improve integrated level.Chemistry can be used
Vapour deposition, ald or other suitable deposition process, alternating deposit silicon nitride and silica, form the stacking successively
Layer.
By the spin coating photoresist layer on stack layer, the photoresist of patterning can be formed by steps such as exposure imagings
Layer, i.e., the array of through hole is formed in the photoresist layer of second area, using the photoresist layer of the patterning as masking, by heap
The etching of lamination forms the raceway groove hole 106 of exposure substrate, with reference to shown in figure 4.
After being formed in raceway groove hole 106, the removal of photoresist layer and the formation of accumulation layer in raceway groove hole 106, storage are carried out
Layer includes electric charge capture layer and channel layer, and electric charge capture layer for example can be ONO structure, i.e. oxide, nitride and oxide
Lamination, channel layer for example can be polysilicon layer, in specific application, form ONO electricity in the side wall of raceway groove hole successively
The channel layer of lotus trapping layer and polysilicon, then forms packed layer in raceway groove hole, and packed layer can be silica.
Step S203, coating 204 is formed on the stack layer, in the coating 204 of the second area formed with
The etched hole 207 of different pore size.
Coating 204 is mask layer when subsequent etching forms contact hole, is the protective layer of the exterior domain of contact hole, can be with
Needed according to specific to select the material of coating 204 and thickness.In certain embodiments, coating 204 can be to heap
The material that lamination has high selectivity is formed, and coating 204 for example can be polysilicon membrane, and etched hole 207 therein can be with
It is the through hole of exposed stack layer.In the application other embodiment, coating 204 can also be other hard mask materials.Due to
Coating 204 has high selectivity to stack layer, therefore will not be etched when carrying out the etching of stack layer afterwards, and due to carving
The pore size of pit 207 is different, and the etch rate of the more stack layer under large aperture is bigger, so as to form different depth
Contact hole 208 (with reference to figure 3d).
In further embodiments, coating 204 can be the material to stack layer with low selection ratio, that is, carve
When losing stack layer, coating 204 can also be etched away a part, coating 204 such as can be agraphitic carbon or silica,
When being performed etching to stack layer, the thickness of coating 204 is also reducing, therefore the thickness of coating 204 needs to have properly
Thickness, or other barrier layers are set in coating 204 times, avoid stack layer by over etching.In this embodiment, etch
Hole 207 can be the through hole of exposed stack layer, not penetrate more preferably or by certain depth but the hole of the coating 204,
And the bigger etched hole in aperture has a deeper hole depth, that is, the coatings 204 of the smaller 207 times reservations of etched hole in aperture
Thickness is bigger.Because the pore size of etched hole 207 is different, the etch rate of the more stack layer under large aperture is bigger, meanwhile, more
The coating 204 of reservation under small etched hole 207 is thicker, so so that the etching of the stack layer under smaller etched hole 207
Time started is more late, is convenient for the control of etch rate, forms the contact hole 208 of different hole depths.
In the particular embodiment, as shown in Figure 3 a, it is possible, firstly, to deposit coating on the stack layer of second area
204, and the spin coating photoresist layer 205 on coating 204, then, form the photoresist layer 205 of patterning, the photoetching of patterning
Formed with the through hole 206 with different apertures in glue-line 205；Then, with reference to shown in figure 3b, using photoresist layer 205 as covering
Film performs etching, and forms the etched hole 207 of different pore size on the cover layer, then removes photoresist 205, as shown in Figure 3 c.Covering
The etching mode of layer can be anisotropic dry etching, because the pore size of through hole 206 in photoresist layer 205 is different,
So as to which more the coating under the through hole 206 of large aperture has faster etch rate, so as to form the different etching of depth
Hole 207, the upper diameter of the etched hole formed in anisotropic etching are typically larger than base diameter.
In the stack layer that rectangle stacks, the raceway groove hole 106 of usual first area 105 is arranged in array, array arrangement
Mode can be that ranks alignment arrangement, as shown in Figure 4 or wrong row arrangement, that is, the raceway groove hole of a line are formed preceding
Opening position between two raceway groove holes of a line, be advantageous to improve the integration density in raceway groove hole.In embodiments of the present invention, the secondth area
Domain 303 can be located at the side of first area 105, such as polygon, the second area 303 of one side of side or side
In etched hole 304 can be consistent with the arragement direction in the raceway groove hole 106 of its side, so, can effectively reduce contact hole
The area in region, so as to reduce the area of whole memory.
A kind of possible embodiment of the application is illustrated in figure 4, the etched hole 106 in second area 105 is in array
Distribution, second area 303 are located at the side of first area, and each etched hole 304 can arragement direction can be with first area 105
In raceway groove hole 106 arragement direction it is consistent.Therefore, in the side of first area, the area of second area need to only accommodate multiple
Rows of etched hole, such as 32 layers of stack layer, the area of the second area in the embodiment of the present application only needs
32 etched holes are accommodated, for the 32 metal gate steps needed in the prior art, save the area of stack layer, are dropped
Low cost.
Step S204, with the coating 204 outside etched hole 207 to block, the etching of stack layer is carried out, with etched hole
Contact hole 208 is formed under 207, different contact holes 208 stops at the sacrifice layer 203 of different layers, the bigger etched hole 207 in aperture
Under contact hole 208 there is deeper hole depth, with reference to shown in figure 3d.
It can be anisotropic dry etching to the etching of stack layer, such as can be RIE (reactive ion etching),
As shown in Figure 3 d, the stack layer under etched hole 207 is etched to form contact hole 208.The etched hole 207 of different pore size, due to it
Influence to etch rate, the depth of formation contact hole 208 is also different, for the contact hole under the larger etched hole 207 in aperture
208, because etch rate is larger, therefore the contact hole 208 formed has deeper hole depth.
In the etching process to stack layer, for having the coating 204 of the material of high selectivity formation to stack layer,
Its thickness change very little.For having the coating 204 of the material of low selection ratio formation to stack layer, during etching,
The coating 204 is also gradually etched, and its thickness is constantly reduced, therefore when coating 204 is formed, should be taken into account that etching causes
Coating 204 be lost, the thickness being initially formed can be more than the loss thickness that is formed in etching process, or in coating
Lower increase barrier layer.
Because the pore size of the etched hole 207 of formation is different, or, further, the coating under etched hole 207
The thickness of 204 reservation is also different, and aperture is bigger, and in etching process, the etch rate of other layers that are etched will be more
It hurry up, the coating 204 of reservation can also postpone the etching of the stack layer to being etched, and by these controls, can be combined with simultaneously
The control of specific etching technics, after etching, the contact hole 208 under the bigger etched hole 207 in aperture has deeper hole depth, and
Stop on different sacrifice layers 203.
In step S205, contact insulation layer 211 is formed in the side wall of contact hole 208, and is filled, forms contact plug
212, with reference to figure 3g and 3h.
The contact insulation layer 211 is insulating materials, such as can be silica or silicon oxynitride etc., and it is contacted as formation
Separation layer after plug 211 with other metal levels.Removal contact hole can then be performed etching by Deposit contact insulating layer material
The contact insulation layer material of bottom is formed.Then, metal material, such as W are filled in the contact hole, so as to form contact plug
212。
In the preferred embodiment of the invention, the contact plug 212 is carried out after the replacing it of sacrifice layer 203 is carried out, and is easy to
Realize, and beneficial to the integrated level for improving technique.
Specifically, after step s 204, following steps can be carried out：
Step S2051, insulation barrier 209 is formed on the inwall of contact hole 208.
Step S2052, sacrifice layer 203 is replaced with into metal level 210 using grid line gap.
Step S2053, the insulation barrier of the bottom of contact hole 208 is removed, insulated using the insulation barrier as contact
Layer, and form contact plug in the contact hole.
As shown in Figure 3 e, insulation barrier 209 is formed in contact hole side wall.The insulation barrier 209 is by sacrifice layer 203
In the technique for replacing with metal level 210, the purpose for keeping contact pattern is played.It should be noted that contact insulation layer 211 is exhausted
Edge material, it is as the separation layer formed after contact plug 212 with other metal levels.As a preferred embodiment, insulation
Barrier layer 209 is a kind of insulating materials, such as can be silica or silicon oxynitride etc., you can realization formed after contact plug with its
The purpose of the isolation of his metal level, therefore the insulation barrier of contact hole bottom can be removed, as contact insulation layer 212,
So as to simplify preparation technology.In the application other embodiment, above two film can also be formed by different materials.
In the particular embodiment, the method for ald can be used to form the insulation barrier 209 of silica, ginseng
As shown in Fig. 3 e, formed with insulation barrier 209 on the inwall of contact hole.
Then, by (not shown) silicon nitride layer 203 removed in the stack layer in grid line gap, and replacement nitrogen is formed
The metal level 210 of SiClx.Normally, grid line gap is initially formed, then, selects the acid of the high selectivity to silicon nitride and silica
Liquid, grid line gap is entered by acid solution, silicon nitride layer 203 is removed, acid solution for example can be phosphoric acid (H3PO4).Remove silicon nitride
After 203, metal level 210 is packed into, metal level 210 can be tungsten (W).The filling of metal level 210 can use vapour deposition
Method is realized, then removes unnecessary part metals by metal carve, and metal level 210 is formed, with reference to figure 3f.
Afterwards, it is necessary to which contact hole bottom insulation barrier layer is removed, contact insulation layer 211 is formed, subsequently to be connect
Touch the formation of plug 212.As shown in figure 3g, insulation barrier 209 is removed by anisotropic dry etching and is located at contact hole bottom
The part in portion.As illustrated in figure 3h, contact plug 211 is formed in the contact hole, and contact plug 211 can be used to connect the He of wordline 103
The metallic conductor of metal level 210, such as can be tungsten.
The manufacture method of 3D nand memories part provided in an embodiment of the present invention, by substrate formed sacrifice layer with
The stack layer that insulating barrier is alternately stacked, formed with the accumulation layer in raceway groove hole and raceway groove hole in the first area of the stack layer,
Coating, the wherein etched hole formed with different pore size in the coating of second area are formed on stack layer, using coating as
Block, carry out the etching of stack layer, to form contact hole under etched hole, different contact hole stops is in the sacrifice of different layers
Layer.Because in etching process, etched hole aperture is bigger, the etch rate of the stack layer under it is bigger so that bigger etched hole
Under contact hole can have deeper hole depth, realize the etching of the contact hole of different depth, so as to, formed correspond to difference
The contact hole of sacrifice layer.For the memory device with compared with multilayer stack layer, preparation work caused by avoiding etching multilayer steps
Skill complexity and higher cost, reduce the area required for device, improve the yield of wafer.
Based on above-described embodiment, this application provides the manufacture method of another 3D nand memories part, with above-mentioned implementation
Unlike example, formed in coating after the etched hole of different pore size, stop key-course can be further deposited, to enter
One step controls the etching speed of stack layer, part unlike the embodiments above described in detail below, and same section will no longer go to live in the household of one's in-laws on getting married
State.
With reference to shown in figure 5, step S501, there is provided substrate 201, with reference to shown in figure 6a.
It is identical in substrate step S201 in the embodiment of the present application, it will not be repeated here.
Step S502, sacrifice layer 203 and the alternately laminated stack layer of insulating barrier 202 is formed on the substrate 201, with reference to figure 4
Shown, stack layer has a first area 105 and second area 303, formed with raceway groove hole 106 in the stack layer of first area 105
And the accumulation layer (not shown) in raceway groove hole.
Above-mentioned steps are identical with step S202, will not be repeated here.
Step S503, coating 202 is formed on stack layer, formed with different pore size in the coating of second area 303
Etched hole 207, with reference to figure 6b.
Coating 204 is mask layer when subsequent etching forms contact hole, is the protective layer of the exterior domain of contact hole, can be with
Needed according to specific to select the material of coating 204 and thickness.In certain embodiments, coating 204 can be to heap
Lamination has the material of high selectivity, and coating 204 for example can be polysilicon membrane, and etched hole 207 therein can be sudden and violent
Reveal the through hole of stack layer.In further embodiments, coating 204 can be the material to stack layer with low selection ratio,
Be exactly when etching stack layer, coating 204 can also be etched away a part, coating 204 for example can be agraphitic carbon or
Silica etc., when being performed etching to stack layer, the thickness of coating 204 is also reducing, therefore the thickness of coating 204 needs
Other barrier layers are set with suitable thickness, or in coating 204 times, avoid stack layer by over etching.
The forming process of coating 204 is shown in step S203, will not be repeated here.
In the stack layer that rectangle stacks, the raceway groove hole 106 of usual first area 105 is arranged in array, array arrangement
Mode can be that ranks alignment arrangement, as shown in Figure 4 or wrong row arrangement, that is, the raceway groove hole of a line are formed preceding
Opening position between two raceway groove holes of a line, be advantageous to improve the integration density in raceway groove hole.In embodiments of the present invention, the secondth area
Domain 303 can be located at the side of first area 105, such as polygon, the second area 303 of one side of side or side
In etched hole 304 can be consistent with the arragement direction in the raceway groove hole 106 of its side, therefore, the side in first area, second
The area in region need to only accommodate multiple rows of etched holes, so, can effectively reduce the area of contact bore region, from
And the area of whole memory is reduced, reduce cost.
Step S504, deposit and stop key-course 401, the stop key-course 401 in the smaller etched hole in aperture has bigger
Thickness.
Stop that key-course 401 can be that the material for having low selection ratio relative to stack layer is formed, when etching stack layer,
The stop key-course 401 will be also etched away, as the key-course for etching etch rate when forming contact hole.Due to coating
The aperture of middle etched hole is different, and the uniformity of film can be different during deposition, the more resistance of the etched hole lower surface of small-bore
The thickness for keeping off key-course can be thicker, so, stops key-course 401 by depositing to be formed, smaller when being performed etching to stack layer
The first etch stopper key-course of meeting in aperture, and then stack layer can be just etched into, by the etching barrier layer of different-thickness, can control
The initial time of system etching stack layer, the etch period of the more stack layer under small-bore is more late, so as to further control stack layer
The depth of middle contact hole.
Deposition stops that the method for key-course 401 can be vapour deposition process, in the coating 204 formed with etched hole 207
Surface, which is formed, stops key-course 401, as fig. 6 c, after stopping the deposition of key-course 401, in the etched hole of different pore size
The stop film of key-course 401 thickness it is different, the aperture of etched hole is smaller, and the stop key-course 401 formed in it is thicker, carves
It is longer to expose time required for stack layer that erosion stops key-course 401.As shown in fig 6d, to stopping that key-course 401 is carried out
During etching, the stop key-course 401 in the larger etched hole 207 in aperture is relatively thin, and etch rate is very fast, more first complete etching with
Expose the stack layer under it；And the stop key-course 401 in the less etched hole 207 in aperture is thicker, and its etch rate is slower,
Etching is completed more afterwards.By stopping that key-course 401 realizes the order etched to the 207 times stack layers in different etching hole and speed
Control, is further controlled to the depth of contact hole 208, with reference to shown in figure 6f.
In the embodiment of the present application, step S504 is to control the etching of stack layer, is preferable mode, in the application
, can also be without not influenceing the realization of the embodiment of the present application in other embodiment.
Step S505, with the coating 204 outside etched hole 207 to block, the etching of stack layer 208 is carried out, to carve
Contact hole 208 is formed under pit 207, different contact holes 208 stops at the sacrifice layer 203 of different layers, the bigger etching in aperture
Contact hole 208 under hole 207 has deeper hole depth, with reference to shown in figure 6f.
It can be anisotropic dry etching to the etching of stack layer, such as can be RIE (reactive ion etching),
Stack layer under etched hole 207 is etched to form contact hole 208.The etched hole 207 of different pore size, because it is to etch rate
Influence, the depth of formation contact hole 208 is also different, for the contact hole 208 under the larger etched hole 207 in aperture, because etching
Speed is larger and etched hole in stop key-course it is thinner, therefore the contact hole 208 formed has deeper hole depth.
In the etching process to stack layer, while can be to stopping that key-course 401 performs etching.Due to the quarter of different pore size
The stop key-course thickness formed in pit is different, and the etch rate of the stop key-course in the etched hole of different pore size is not
Together, therefore, in such as Fig. 6 d specific embodiment, in stack layer etching process, it is necessary to stopping that key-course performs etching,
Stop key-course thickness in the larger etched hole in aperture is smaller, takes the lead in completing to etch and begin to stack up the etching of layer, therefore heap
The etching of lamination is more early, and the stop key-course thickness in the less etched hole in aperture is larger, it is necessary to which the long period could complete to carve
Lose and expose the stack layer under it, therefore the etching of stack layer is later, therefore by stopping key-course 401, it is possible to achieve pair
The control of the order and speed of 207 times stack layer etchings of etched hole of different pore size.
As shown in fig 6e, the stack layer etch rate under the larger etched hole 207 in aperture is very fast, the less etched hole in aperture
Under stack layer etch rate it is slower, formed interstitial hole 402, interstitial hole 402 is continued to etch, formed contact hole 208, such as
Shown in Fig. 6 f, the contact hole 208 of wherein different pore size stops at different sacrifice layers 203, to be replaced by sacrifice layer 203
After metal, the metal medium 212 in contact hole 208 connects (with reference to figure 6j) with metal level 210.
Step S506, insulation barrier 209 (as shown in figure 6g) is formed on the inwall of the contact hole；Stitched using grid line
The sacrifice layer 203 is replaced with metal level 210 (as shown in figure 6h) by gap (not shown)；Remove the bottom of contact hole 208
Insulation barrier (as shown in Fig. 6 i), using the insulation barrier as contact insulation layer 211, and be filled, formation connects
Touch 212 (as shown in Fig. 6 j) of plug.
Above-mentioned steps are similar with step S205, will not be repeated here.
The manufacture method of 3D nand memories part provided in an embodiment of the present invention, is controlled by the etched hole of different pore size
The etch rate to stack layer is made, by stopping etch period of the key-course control to stack layer, formation corresponds to different sacrifices
The contact hole of layer.For the memory device with compared with multilayer stack layer, the accuracy of stack layer etching is improved, avoids etching
Preparation technology complexity and higher cost, reduce the area required for device, improve the yield of wafer caused by multilayer steps.
Description based on the above to the manufacture method of 3D nand memory parts, present invention also provides one kind by above-mentioned side
The 3D nand memory parts that method is formed, with reference to shown in figure 4 and Fig. 6 j, the device includes：
Substrate 201；
Metal level 210 and the alternately laminated stack layer of insulating barrier 202, the stack layer on the substrate have the firstth area
Domain and second area, it is (not shown formed with the accumulation layer in raceway groove hole and raceway groove hole in the stack layer of the first area
Go out)；
Contact hole 208 in the stack layer of the second area, different contact holes has different apertures and aperture is got over
Big contact hole is arranged on the metal level 210 of more lower；
The contact plug 212 in contact insulation layer 211 and contact hole in the side wall of contact hole 208.
In the stack layer that rectangle stacks, the raceway groove hole of usual first area is arranged in array, and can set second area
Side positioned at first area, such as one side of side or side are polygon, and the etched hole in second area can be with
The arragement direction in the raceway groove hole of its side is consistent, and therefore, the side in first area, the area of second area need to only accommodate multiple
Rows of etched hole, the area of stack layer is saved, reduces cost.
Described above is only the preferred embodiment of the present invention, although the present invention is disclosed as above, so with preferred embodiment
And it is not limited to the present invention.Any those skilled in the art, technical solution of the present invention ambit is not being departed from
Under, many possible changes and modifications are all made to technical solution of the present invention using the methods and technical content of the disclosure above,
Or it is revised as the equivalent embodiment of equivalent variations.Therefore, every content without departing from technical solution of the present invention, according to the present invention's
Technical spirit still falls within the technology of the present invention side to any simple modification, equivalent variation and modification made for any of the above embodiments
In the range of case protection.
Claims (9)
- A kind of 1. manufacture method of 3D nand memories part, it is characterised in that including：Substrate is provided；Form sacrifice layer and the alternately laminated stack layer of insulating barrier over the substrate, the stack layer has first area and the Two regions, formed with the accumulation layer in raceway groove hole and raceway groove hole in the stack layer of the first area；Form coating on the stack layer, the etched hole formed with different pore size in the coating of the second area；Using the coating outside the etched hole to block, the etching of the stack layer is carried out, to be formed under the etched hole Contact hole, contact hole of the different contact hole stops under the sacrifice layer of different layers, the bigger etched hole in aperture have deeper Hole depth；Contact insulation layer is formed in the side wall of the contact hole, and is filled, forms contact plug.
- 2. manufacture method according to claim 1, it is characterised in that the bigger etched hole in aperture has deeper hole depth； Then,In the step of etching of the progress stack layer, in addition to：The etching of the coating is carried out simultaneously.
- 3. manufacture method according to claim 1 or 2, it is characterised in that forming coating with carrying out the stack layer Etching the step of between, in addition to：Deposit and stop key-course, the stop key-course in the smaller etched hole in aperture has bigger thickness；Then,In the step of etching of the progress stack layer, in addition to：The etching of the stop key-course is carried out simultaneously.
- 4. manufacture method according to claim 1, it is characterised in that the stack layer stacks for rectangle, firstth area Raceway groove hole in domain is arranged in array, and the second area is located at the side of the first area.
- 5. manufacture method according to claim 4, it is characterised in that etched hole and its side in the second area The arragement direction in raceway groove hole is consistent.
- 6. manufacture method according to claim 1, it is characterised in that after contact hole is formed, in addition to：Insulation barrier is formed on the inwall of the contact hole；The sacrifice layer is replaced with into metal level using grid line gap；Then,Contact insulation layer is formed in the side wall of the contact hole, including：The insulation barrier of the contact hole bottom is removed, contact insulation layer is used as using the insulation barrier.
- A kind of 7. 3D nand memories part, it is characterised in that including：Substrate；Metal level and the alternately laminated stack layer of insulating barrier, the stack layer on the substrate have first area and the secondth area Domain, formed with the accumulation layer in raceway groove hole and raceway groove hole in the stack layer of the first area；Contact hole in the stack layer of the second area, different contact holes have the bigger contact in different apertures and aperture Hole is arranged on the metal level of more lower；The contact plug in contact insulation layer and contact hole in contact hole side wall.
- 8. memory device according to claim 7, it is characterised in that the stack layer stacks for rectangle, the first area In raceway groove hole be arranged in array, the second area is located at the side of the first area.
- 9. memory device according to claim 8, it is characterised in that contact hole and its side in the second area The arragement direction in raceway groove hole is consistent.
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