CN116018060A - Semiconductor structure, preparation method thereof and packaging structure - Google Patents
Semiconductor structure, preparation method thereof and packaging structure Download PDFInfo
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Abstract
The disclosure relates to a semiconductor structure, a preparation method thereof and a packaging structure, wherein the preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a target capacitor structure on a substrate, wherein the target capacitor structure comprises a first electrode and a second electrode which are formed in sequence; the target capacitor structure comprises a trench capacitor structure and a plane capacitor structure; forming first conductive plugs and second conductive plugs which are distributed at intervals in at least the second electrode; the orthographic projection of the first conductive plug on the second surface of the substrate is positioned in the orthographic projection of the second electrode of the groove capacitor structure on the second surface of the substrate, and the second conductive plug is electrically connected with the first electrode of the plane capacitor structure. The preparation method can simplify the process steps, save the process materials, improve the problem of over etching, avoid short circuit, and reduce the resistance so as to improve the conductivity of the semiconductor.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure, a preparation method thereof and a packaging structure.
Background
With the continuous improvement of chip integration, the performance of the capacitor needs to be improved, and the deep trench capacitor (Deep trench capacitor, abbreviated as DTC) is used to replace the traditional chip capacitor to become a trend, and because the deep trench capacitor has high stability and low leakage current under high bias voltage, the deep trench capacitor is widely applied to the fields of antenna matching, radio frequency filtering, IC (Integrated Circuit ) decoupling and related industries.
However, as the number of capacitance layers increases, the fabrication process and related performance of deep trench capacitors need to be further optimized. Therefore, it is desirable to provide a semiconductor structure and a method for fabricating the same to improve the process and the overall performance of the deep trench capacitor.
Disclosure of Invention
Based on the above, the present disclosure provides a semiconductor structure, a method for manufacturing the same, and a package structure, which can optimize the manufacturing process of a deep trench capacitor, simplify the manufacturing process thereof, and improve the electrical performance thereof.
According to various embodiments of the present disclosure, there is provided a method for manufacturing a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite along the thickness direction of the substrate; forming a target capacitor structure on a substrate, wherein the target capacitor structure comprises a first electrode and a second electrode which are formed in sequence; the target capacitor structure comprises a groove capacitor structure extending into the substrate from the first surface towards the second surface and a plane capacitor structure positioned on the first surface; the top surface of the second electrode is higher than the first surface, and the first electrode is positioned between the substrate and the second electrode; forming first conductive plugs and second conductive plugs which are distributed at intervals in at least the second electrode; the orthographic projection of the first conductive plug on the second surface of the substrate is positioned in the orthographic projection of the second electrode of the groove capacitor structure on the second surface of the substrate, and the second conductive plug is electrically connected with the first electrode of the plane capacitor structure.
In the method for manufacturing a semiconductor structure in the above embodiment, the target capacitor structure includes a trench capacitor structure and a planar capacitor structure, and the orthographic projection of the first conductive plug on the second surface of the substrate is located in the orthographic projection of the second electrode of the trench capacitor structure on the second surface of the substrate, so that the contact area between the first conductive plug and the target capacitor structure is increased, and the resistance can be reduced. In addition, since the orthographic projection of the first conductive plug on the second surface of the substrate is positioned in the orthographic projection of the second electrode of the trench capacitor structure on the second surface of the substrate, the phenomenon of over etching of the first conductive plug in the process can be avoided, so that the short circuit phenomenon is avoided, and the conductive effect is further improved. In addition, the second conductive plug is formed in the planar capacitor structure, penetrates through the second electrode of the planar capacitor structure, and the bottom surface of the second conductive plug is in contact with the first electrode, so that the first conductive plug and the second conductive plug can be directly prepared in the target capacitor structure in the preparation process, and in the traditional process, in order to expose the electrode layer, the planar capacitor structure needs to be etched in advance, the process steps are complicated, the number of required photomasks is large, and the preparation method provided by the invention can at least save one layer of photomasks and reduce corresponding process steps, thereby improving the preparation efficiency of the semiconductor structure and saving the material cost.
In some of these embodiments, the area of the orthographic projection of the second conductive plug on the second surface of the substrate is smaller than the area of the orthographic projection of the first conductive plug on the second surface of the substrate.
In some embodiments, the step of forming at least a first conductive plug and a second conductive plug in the second electrode at intervals includes: forming a hard mask layer on the surface of the planar capacitor structure, which is far away from the substrate; forming a patterned photoresist layer on the surface of the hard mask layer far away from the planar capacitor structure; etching the hard mask layer and the planar capacitor structure below the hard mask layer by taking the patterned photoresist layer as a mask, so that first grooves and second grooves which are distributed at intervals are formed in at least the second electrode, the first grooves expose the second electrode of the groove capacitor structure, and the second grooves expose the first electrode of the planar capacitor structure; a first conductive plug is formed in the first trench, and a second conductive plug is formed in the second trench.
In some embodiments, before the step of forming the first conductive plug in the first trench and the second conductive plug in the second trench, the method includes: forming a first isolation layer on the side wall surface of the first groove, and forming a second isolation layer on the side wall surface of the second groove.
In some embodiments, the hard mask layer comprises a protective mask layer and an anti-reflection layer sequentially stacked in a thickness direction away from the substrate; at least after the step of forming the first groove and the second groove which are distributed at intervals in the second electrode, the step of forming the first isolation layer and the step of forming the second isolation layer further comprises the following steps: and removing the patterned photoresist layer and the residual anti-reflection layer, and forming a first protection layer by the residual protection mask layer.
In some of these embodiments, after the steps of forming the first isolation layer and forming the second isolation layer, further comprising: and forming a second protection layer on the side wall surface of the first groove, the side wall surface of the second groove and the surface of the first protection layer.
Another aspect of the present disclosure also provides a semiconductor structure including a substrate, a target capacitance structure, a first conductive plug, and a second conductive plug; the substrate is provided with a first surface and a second surface which are opposite along the thickness direction; the target capacitor structure comprises a first electrode and a second electrode which are formed in sequence; the target capacitor structure comprises a groove capacitor structure extending into the substrate from the first surface towards the second surface and a plane capacitor structure positioned on the first surface; the top surface of the second electrode is higher than the first surface, and the first electrode is positioned between the substrate and the second electrode; the first conductive plug is at least partially positioned in the second electrode; the second conductive plugs are at least partially positioned in the second electrode and are distributed at intervals with the first conductive plugs; the orthographic projection of the first conductive plug on the second surface of the substrate is positioned in the orthographic projection of the second electrode of the groove capacitor structure on the second surface of the substrate, and the second conductive plug is electrically connected with the first electrode of the plane capacitor structure.
In the semiconductor structure in the above embodiment, the orthographic projection of the first conductive plug on the second surface of the substrate is located in the orthographic projection of the second electrode of the trench capacitor structure on the second surface of the substrate, so as to increase the contact area between the target capacitor structure and the first conductive plug, thereby reducing the contact resistance and improving the conductive effect, and the first conductive plug and the second conductive plug are respectively connected with the second electrode and the first electrode, so that the electrode extraction is more uniform while the contact resistance is reduced, and the decoupling effect is improved.
In some of these embodiments, the area of the orthographic projection of the second conductive plug on the second surface of the substrate is smaller than the area of the orthographic projection of the first conductive plug on the second surface of the substrate.
In some embodiments, the semiconductor structure further includes a first isolation layer and a second isolation layer; the first isolation layer surrounds the side wall surface of the first conductive plug and is positioned between the second electrode and the first conductive plug; the second isolation layer surrounds the side wall surface of the second conductive plug and is positioned between the second electrode and the second conductive plug; the semiconductor structure further comprises a first protective layer and a second protective layer; the first protective layer is positioned on the surface of the planar capacitor structure, which is far away from the substrate; the second protection layer comprises a first part positioned between the first conductive plug and the first isolation layer and a second part positioned between the second conductive plug and the second isolation layer; wherein the first portion of the second protection layer surrounds the first conductive plug, and the second portion of the second protection layer surrounds the second conductive plug.
Still another aspect of the present disclosure further provides a package structure, including a circuit board, a package substrate, a semiconductor structure according to any one of the embodiments of the present disclosure, a central processing unit, and a memory; the packaging substrate is positioned on the surface of the circuit board, and the first surface of the packaging substrate is connected with the circuit board through packaging solder balls; the semiconductor structure of any one of the embodiments of the present disclosure is located on a second surface of the package substrate, and the second surface of the semiconductor structure is connected with the second surface of the package substrate through a back-fastening bump; the central processing unit is positioned on the first surface of the semiconductor structure, and the first surface of the central processing unit is connected with the first surface of the semiconductor structure through a first micro-bump; the memory is positioned on the second surface of the central processing unit, and the first surface of the memory is connected with the second surface of the central processing unit through the second micro-convex points.
In the package structure in the foregoing embodiment, the semiconductor structure in any one of the embodiments of the present disclosure is connected to a circuit board, a package substrate, a central processing unit, a memory, and other chip structures, and the semiconductor structure in any one of the embodiments of the present disclosure is used as an interconnection structure for connection between chips, so that contact resistance can be reduced, a connection effect of each portion in the package structure is improved, an effect of supporting the top and bottom is provided, and a manufacturing cost of the package structure is reduced. Therefore, the packaging structure can improve the performance and the yield of the packaging structure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor structure according to a first embodiment of the disclosure;
fig. 2a is a schematic cross-sectional view illustrating a first mask layer formed on a capacitor structure in a method for fabricating a semiconductor structure according to a second embodiment of the present disclosure;
fig. 2b is a schematic cross-sectional structure diagram of a capacitor structure etched through a first mask layer in a method for manufacturing a semiconductor structure according to a third embodiment of the present disclosure;
fig. 2c is a schematic cross-sectional view illustrating a second mask layer formed on a capacitor structure in a method for fabricating a semiconductor structure according to a fourth embodiment of the present disclosure;
fig. 2d is a schematic cross-sectional view illustrating a first plug and a second plug formed through a first mask layer in a method for fabricating a semiconductor structure according to a fifth embodiment of the present disclosure;
Fig. 3 is a schematic cross-sectional view showing a structure obtained in a method for manufacturing a semiconductor structure according to a sixth embodiment of the present disclosure;
fig. 4 is a schematic flow chart of a method for manufacturing a semiconductor structure according to a seventh embodiment of the disclosure;
fig. 5 is a schematic cross-sectional view showing a structure obtained in a method for manufacturing a semiconductor structure according to an eighth embodiment of the present disclosure;
fig. 6 is a schematic cross-sectional view showing a structure obtained in a method for manufacturing a semiconductor structure according to a ninth embodiment of the present disclosure;
fig. 7 is a schematic flow chart of a method for manufacturing a semiconductor structure according to a tenth embodiment of the disclosure;
fig. 8 is a schematic cross-sectional view showing a structure obtained in a method for manufacturing a semiconductor structure according to an eleventh embodiment of the present disclosure;
fig. 9 is a schematic cross-sectional view showing a structure obtained in a method for manufacturing a semiconductor structure according to a twelfth embodiment of the present disclosure;
fig. 10 is a schematic cross-sectional view showing a structure obtained in a method for manufacturing a semiconductor structure according to a thirteenth embodiment of the present disclosure;
fig. 11 is a schematic cross-sectional view of a package structure according to a fourteenth embodiment of the present disclosure.
Reference numerals illustrate:
1000. a package structure; 100/200, semiconductor structure; 10. a substrate; 10a, a first surface of a substrate; 10b, a second surface of the substrate; 11. a target capacitance structure; 11a, trench capacitor structure; 11b, planar capacitive structures; 111. a first dielectric layer; 112. a first electrode; 113. a second dielectric layer; 114. a conductive layer; 115. a second electrode; 12. a hard mask layer; 121. protecting the mask layer; 122. an anti-reflection layer; 13. patterning the photoresist layer; 141. a first trench; 142. a second trench; 15. a first protective layer; 16. a layer of isolation material; 171. a first isolation layer; 172. a second isolation layer; 18. a protective material layer; 191. a first portion of the second protective layer; 192. a second portion of the second protective layer; 20. a first conductive plug; 21. a second conductive plug; 22. a first mask layer; 23. a first electrode; 24. a second mask layer; 25. a second electrode; 26. a first plug; 27. a second plug; 28. a capacitor structure; 300. a circuit board; 400. packaging a substrate; 410. packaging the solder balls; 110. reversely buckling the convex points; 500. a central processing unit; 501. a base module; 502. a computing module; 503. a logic module; 504. a port physical layer; 510. a first micro bump; 600. a memory; 610. and second micro-bumps.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the illustration, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The interposer (Silicon Interposer) is a silicon substrate made of silicon and organic materials, is a pipeline for transmitting electric signals by the multi-chip module in advanced packaging, can realize interconnection between chips and also can realize interconnection with the packaging substrate, and serves as a bridge between a plurality of bare chips and a circuit board. Silicon interposer is a proven technology with high fine pitch routing capability and reliable TSV (Through Silicon Via ) capability, which can achieve high density I/O (input/output) requirements.
In the interposer structure, a deep trench capacitor (deep trench capacitor, abbreviated as DTC) is an important parameter, and the deep trench capacitor can effectively improve impedance and logic voltage drop of the PDN (power delivery network, power distribution network, power transmission network) and can also effectively improve leakage current. The larger the capacitance value of the deep trench capacitor, the better its performance. However, as the number of capacitor layers increases, the number of deep trench capacitor manufacturing processes, particularly the number of masks, increases.
Based on the technical problems, the present disclosure provides a semiconductor structure, a preparation method thereof, and a packaging structure, which can optimize the preparation process of a deep trench capacitor, simplify the manufacturing process thereof, and improve the electrical performance thereof.
As an example, referring to fig. 1, a method for preparing a semiconductor structure is provided, including the following steps:
step S2: providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite along the thickness direction of the substrate;
step S4: forming a target capacitor structure on a substrate, wherein the target capacitor structure comprises a first electrode and a second electrode which are formed in sequence; the target capacitor structure comprises a groove capacitor structure extending into the substrate from the first surface towards the second surface and a plane capacitor structure positioned on the first surface; the top surface of the second electrode is higher than the first surface, and the first electrode is positioned between the substrate and the second electrode;
step S6: forming first conductive plugs and second conductive plugs which are distributed at intervals in at least the second electrode; the orthographic projection of the first conductive plug on the second surface of the substrate is positioned in the orthographic projection of the second electrode of the groove capacitor structure on the second surface of the substrate, and the second conductive plug is electrically connected with the first electrode of the plane capacitor structure.
The substrate may be a silicon interposer, as examples, and may also be formed of semiconductor materials, insulating materials, conductor materials, or any combination thereof. The substrate may have a single-layer structure or a multilayer structure. For example, the substrate may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, the substrate may be a layered substrate comprising, for example, si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Those skilled in the art may select a substrate type according to a type of transistor formed on the substrate, and thus the type of substrate should not limit the scope of protection of the present application.
In the method for manufacturing a semiconductor structure in the above embodiment, the target capacitor structure includes a trench capacitor structure and a planar capacitor structure, the first conductive plug is formed in a trench of the trench capacitor structure, and a bottom surface of the first conductive plug contacts the second electrode and is lower than the first surface of the substrate, so as to increase a contact area between the first conductive plug and the target capacitor structure, and reduce a resistance. In addition, as the orthographic projection of the first conductive plug on the second surface of the substrate is positioned in the orthographic projection of the second electrode of the trench capacitor structure on the second surface of the substrate, the phenomenon of over etching of the first conductive plug in the process is avoided, so that the short circuit phenomenon is avoided, and the conductive effect is further improved. In addition, the second conductive plug is formed in the planar capacitor structure, penetrates through the second electrode of the planar capacitor structure, and the bottom surface of the second conductive plug is in contact with the first electrode, so that the first conductive plug and the second conductive plug can be directly prepared in the target capacitor structure in the preparation process, and in the traditional process, in order to expose the electrode layer, the planar capacitor structure needs to be etched in advance, the process steps are complicated, the number of required photomasks is large, and the preparation method provided by the invention can at least save one layer of photomasks and reduce corresponding process steps, thereby improving the preparation efficiency of the semiconductor structure and saving the material cost.
As an example, referring to fig. 2 a-2 d, in the conventional fabrication process of the deep trench capacitor, in the semiconductor structure 200, the interposer includes a capacitor structure 28, the capacitor structure 28 includes a first electrode 23 and a second electrode 25, and since the first electrode 23 is conformally covered by the second electrode 25, the capacitor structure 28 needs to be etched by using the first mask layer 22 to expose the first electrode 23, and then the capacitor structure 28 needs to be etched by using the second mask layer 24 to obtain a first plug 26 and a second plug 27, the first plug 26 is connected to the second electrode 25, and the second plug 27 is connected to the first electrode 23 to lead out two electrodes of the capacitor structure 28. It can be seen that in the conventional process of manufacturing the conductive plugs, two electrodes are usually exposed to facilitate connection with the plugs, at least one photomask is used for etching to expose the electrode layer, and the dimension of the second plug 27 in the thickness direction is larger than that of the first plug 26 in the thickness direction. The preparation method disclosed by the disclosure can combine the step of etching to expose the electrode layer and the step of forming the plug, so that the two steps can be completed in one step, and one layer of mask is also reduced, so that the process steps are simplified, process materials can be saved, and a large amount of cost is saved in the mass production process. In addition, compared with the traditional process, the first conductive plug is positioned in the groove and can be better contacted with the target capacitor structure, so that the electrical performance of the target capacitor structure is improved.
In step S2, referring to step S2 in fig. 1 and fig. 3, a substrate 10 is provided, and the substrate 10 has a first surface 10a and a second surface 10b opposite to each other along a thickness direction thereof.
In step S4, referring to step S4 in fig. 1 and fig. 3, a target capacitor structure 11 is formed on a substrate 10, and the target capacitor structure 11 includes a first electrode 112 and a second electrode 115 formed in sequence; the target capacitance structure 11 includes a trench capacitance structure 11a extending into the substrate 10 via the first surface 10a toward the second surface 10b, and a planar capacitance structure 11b located at the first surface 10 a; the top surface of the second electrode 115 is higher than the first surface 10a, and the first electrode 112 is located between the substrate 10 and the second electrode 115.
As an example, with continued reference to fig. 3, the target capacitor structure 11 further includes a first dielectric layer 111, a second dielectric layer 113, and a conductive layer 114 that are conformally stacked; the first dielectric layer 111 includes a first portion extending into the substrate 10 from the first surface 10a toward the second surface 10b, and a second portion located on the first surface 10a, and the first dielectric layer 111 conformally covers the first electrode 112.
As an example, referring to fig. 3, the step of forming the target capacitor structure 11 on the substrate 10 (not shown) may include:
Step S41: forming a capacitor trench extending in a thickness direction thereof in the substrate 10;
step S42: forming a first dielectric layer 111 on the inner wall of the capacitor trench and the first surface 10a of the substrate 10;
step S43: forming a first electrode 112 on the surface of the first dielectric layer 111;
step S44: forming a second dielectric layer 113 on the surface of the first electrode 112;
step S45: forming a conductive layer 114 on the surface of the second dielectric layer 113;
step S46: a second electrode 115 is formed on the surface of the conductive layer 114, and the second electrode 115 fills the gap in the capacitor trench.
As an example, the first electrode 112, the second electrode 115, and the conductive layer 114 may be formed by Electroplating (electro plating), electroless plating (Electroless plating), or Sputtering (Sputtering), or the like; the first dielectric layer 111 and the second dielectric layer 113 may be formed by atomic layer deposition (Atomic Layer Deposition, ALD) or chemical vapor deposition (Chemical Vapor Deposition, PECVD).
As an example, referring to fig. 4, in step S6, at least the first conductive plugs and the second conductive plugs are formed in the second electrode at intervals, including:
step S61: forming a hard mask layer on the surface of the planar capacitor structure, which is far away from the substrate;
Step S62: forming a patterned photoresist layer on the surface of the hard mask layer far away from the planar capacitor structure;
step S63: etching the hard mask layer and the planar capacitor structure below the hard mask layer by taking the patterned photoresist layer as a mask, so that first grooves and second grooves which are distributed at intervals are formed in at least the second electrode, the first grooves expose the second electrode of the groove capacitor structure, and the second grooves expose the first electrode of the planar capacitor structure;
step S67: a first conductive plug is formed in the first trench, and a second conductive plug is formed in the second trench.
In step S61, referring to step S61 in fig. 4 and fig. 5, a hard mask layer 12 is formed on a surface of the planar capacitor structure 11b away from the substrate 10, and the hard mask layer 12 is used for protecting the exposed surface of the planar capacitor structure 11 b.
As an example, referring to fig. 5, the hard mask layer 12 includes a protective mask layer 121 and an anti-reflection layer 122 sequentially stacked in a thickness direction away from the substrate 10. The protection mask layer 121 is used for protecting the surface of the planar capacitor structure 11b from being damaged; the anti-reflection layer 122 is used to eliminate the reflection at the interface between the photoresist and the planar capacitive structure 11b, reduce the influence of standing wave effect caused by diffraction on the photoresist performance, and the anti-reflection layer 122 may include BARC (Bottom Anti Reflection Coating, bottom anti-reflection coating).
In step S62, referring to step S62 in fig. 4 and fig. 5, a patterned photoresist layer 13 is formed on the surface of the hard mask layer 12 away from the planar capacitor structure 11b, and the patterned photoresist layer 13 has an opening defining the positions and the aperture sizes of the two conductive plugs.
In step S63, referring to step S63 in fig. 4 and fig. 6, the patterned photoresist layer 13 is used as a mask to etch the hard mask layer 12 and the planar capacitor structure 11b below the hard mask layer to form first trenches 141 and second trenches 142 in at least the second electrode 115, wherein the first trenches 141 expose the second electrode 115 of the trench capacitor structure 11a, and the second trenches 142 expose the first electrode 112 of the planar capacitor structure 11 b. The bottom surface of the first trench 141 is lower than the bottom surface of the second trench 142 and lower than the first surface 10a of the substrate 10, so as to ensure that the first conductive plug 20 (see fig. 10) is located inside the trench, thereby increasing the contact area between the first conductive plug 20 and the trench capacitor structure 11a, reducing the contact resistance, avoiding the phenomenon that the first trench 141 is over etched to cause short circuit, and improving the conductivity of the first conductive plug 20.
As an example, referring to fig. 7, after at least the step of forming the first trenches and the second trenches in the second electrode at intervals in step S63, the method further includes:
Step S64: and removing the patterned photoresist layer and the residual anti-reflection layer, and forming a first protection layer by the residual protection mask layer.
In step S64, referring to step S64 in fig. 7, fig. 5 and fig. 6, the patterned photoresist layer 13 and the remaining anti-reflective layer 122 are removed, and the remaining protective mask layer 121 forms the first protective layer 15, and the first protective layer 15 covers the surface of the planar capacitor structure 11b away from the substrate 10, i.e. covers the surface of the second electrode 115, so as to protect the surface of the second electrode 115 from being damaged.
As an example, referring to fig. 7, before the step of forming the first conductive plug in the first trench and the step of forming the second conductive plug in the second trench in step S67, the method further includes:
step S65: forming a first isolation layer on the side wall surface of the first groove, and forming a second isolation layer on the side wall surface of the second groove.
In step S65, referring to step S65 in fig. 7, fig. 6 and 8, after removing the patterned photoresist layer 13 and the remaining anti-reflective layer 122, an isolation material layer 16 is formed on the surface of the first protection layer 15, the sidewalls and bottom of the first trench 141, and the sidewalls and bottom of the second trench 142; then, the surface of the first protection layer 15, the bottom of the first trench 141 and the isolation material layer 16 at the bottom of the second trench 142 are removed, the isolation material layer 16 remaining in the first trench 141 forms a first isolation layer 171, and the isolation material layer 16 remaining in the second trench 142 forms a second isolation layer 172. The first isolation layer 171 and the second isolation layer 172 can protect two conductive plugs formed later, and isolate the sidewalls of the two conductive plugs from the adjacent conductive structures, so as to avoid shorting between different electrode layers, and improve the conductivity of the semiconductor structure 100.
As an example, with continued reference to fig. 7, after the steps of forming the first isolation layer and forming the second isolation layer in step S65, the method further includes:
step S66: and forming a second protection layer on the side wall surface of the first groove, the side wall surface of the second groove and the surface of the first protection layer.
In step S66, referring to step S66 in fig. 7, fig. 8 and fig. 9, a protective material layer 18 is formed on the surface of the first protective layer 15, the sidewall and bottom of the first trench 141, and the sidewall and bottom of the second trench 142; then, the surface of the first protection layer 15, the bottom of the first trench 141 and the protection material layer 18 at the bottom of the second trench 142 are removed, the remaining protection material layer 18 in the first trench 141 conformally covers the first isolation layer 171 to form a first portion 191 of the second protection layer, the remaining protection material layer 18 in the second trench 142 conformally covers the second isolation layer 172 to form a second portion 192 of the second protection layer, the first portion 191 of the second protection layer and the second portion 192 of the second protection layer together form a second protection layer, and the second protection layer can protect sidewall surfaces of the first conductive plug 20 and the second conductive plug 21 (refer to fig. 10) which are deposited later, and facilitate subsequent deposition of the first conductive plug 20 and the second conductive plug 21.
In step S67, referring to step S67 in fig. 7 and fig. 10, a first conductive plug 20 is formed in the first trench 141, and a second conductive plug 21 is formed in the second trench 142. The sidewalls of the first conductive plugs 20 cover the first portions 191 of the second protective layer and the sidewalls of the second conductive plugs 21 cover the second portions 192 of the second protective layer. The bottom of the first conductive plug 20 is located inside the trench of the trench capacitor structure 11a and is connected to the second electrode 115, and the bottom of the second conductive plug 21 is located inside the planar capacitor structure 11b and is connected to the first electrode 112. Since the aperture of the first conductive plug 20 is smaller than the opening size of the trench, the over-etching phenomenon is avoided when the first conductive plug 20 is prepared, thereby improving the short circuit problem; and the bottom surface of the first conductive plug 20 is connected to the second electrode 115 in the trench, the contact resistance can be reduced, thereby further improving the conductive performance of the semiconductor structure 100.
As an example, with continued reference to fig. 10, the area of the orthographic projection of the second conductive plug 21 on the second surface 10b of the substrate 10 is smaller than the area of the orthographic projection of the first conductive plug 20 on the second surface 10b of the substrate 10, that is, the aperture of the second conductive plug 21 is smaller than the aperture of the first conductive plug 20. The loading effect in the etching process means that the etching depths of patterns with different sizes on the same substrate are different, the etching depths of wide patterns are deep, and the etching depths of narrow patterns are shallow, because the updating of effective reaction components of the etched surface is more and more difficult along with the increase of the etching depth of a structure with high depth-to-width ratio. Because the aperture size of the second conductive plug 21 is smaller, the etching speed is low when the second trench 142 is formed, and the over etching is not easy, so that the bottom of the second trench 142 can be ensured to be accurately connected with the first conductive layer 114 with smaller thickness, thereby avoiding the occurrence of the short circuit phenomenon. In addition, since the first conductive plug 20 is located inside the trench, there is no concern that the over-etching will cause a short circuit, and the aperture size is larger than that of the second conductive plug 21, so that the contact area between the first conductive plug 20 and the target capacitor structure 11 can be increased, and the resistance can be further reduced on the basis of improving the short circuit problem, thereby improving the conductivity thereof.
As an example, with continued reference to fig. 10, the material of the first dielectric layer 111 is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. The first dielectric layer 111 may further include other insulating materials with a low dielectric constant (low-k), for example, a material with a dielectric constant less than or equal to 3.9.
As an example, with continued reference to fig. 10, the material of the first electrode 112 is selected from the group consisting of doped silicon, polysilicon, copper, tungsten, aluminum, copper alloys, titanium nitride, nitride buttons, and combinations thereof.
As an example, with continued reference to fig. 10, the material of the second dielectric layer 113 is selected from the group consisting of aluminum oxide, zirconium oxide, and combinations thereof. The second dielectric layer 113 may also include other insulating materials with a relatively high dielectric constant (high-k), such as materials with a dielectric constant greater than 3.9.
As an example, with continued reference to fig. 10, the material of the conductive layer 114 is selected from the group consisting of doped silicon, polysilicon, copper, tungsten, aluminum, copper alloys, titanium nitride, nitride buttons, and combinations thereof.
As an example, with continued reference to fig. 10, the material of the second electrode 115 is selected from the group consisting of polysilicon, titanium nitride, tantalum nitride, copper, tungsten, aluminum, and combinations thereof.
As an example, with continued reference to fig. 10, the materials of the first conductive plugs 20 and the second conductive plugs 21 are selected from tungsten, titanium, nickel, platinum, gold, aluminum, copper, and combinations thereof.
As an example, with continued reference to fig. 10, the materials of the first protective layer 15 and the second protective layer are selected from silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.
As an example, with continued reference to fig. 10, the materials of the first isolation layer 171 and the second isolation layer 172 are selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, and combinations thereof.
It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, although at least a portion of the steps in the flowchart may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, the order in which the steps or stages are performed is not necessarily sequential, and may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or stages.
As an example, with continued reference to fig. 10, the present disclosure further provides a semiconductor structure 100 including a substrate 10, a target capacitor structure 11, a first conductive plug 20, and a second conductive plug 21; wherein the substrate 10 has a first surface 10a and a second surface 10b opposite to each other in a thickness direction thereof; the target capacitor structure 11 includes a first electrode 112 and a second electrode 115 formed in sequence; the target capacitance structure 11 includes a trench capacitance structure 11a extending into the substrate 10 via the first surface 10a toward the second surface 10b, and a planar capacitance structure 11b located at the first surface 10 a; the top surface of the second electrode 115 is higher than the first surface 10a, and the first electrode 112 is located between the substrate 10 and the second electrode 115; the first conductive plug 20 is at least partially located within the second electrode 115; the second conductive plugs 21 are at least partially located in the second electrode 115 and spaced apart from the first conductive plugs 20; wherein, the orthographic projection of the first conductive plug 20 on the second surface 10b of the substrate 10 is located in the orthographic projection of the second electrode 115 of the trench capacitor structure 11a on the second surface 10b of the substrate 10, and the second conductive plug 21 is electrically connected to the first electrode 112 of the planar capacitor structure 11 b.
With continued reference to fig. 10, in the semiconductor structure 100 of the foregoing embodiment, by disposing the first conductive plug 20 in the second electrode 115 of the trench capacitor structure 11a, and making the bottom surface of the first conductive plug 20 lower than the first surface 10a of the substrate 10, that is, at least part of the first conductive plug 20 is located in the trench of the trench capacitor structure 11a, and the orthographic projection of the first conductive plug 20 on the second surface 10b of the substrate 10 is located in the orthographic projection of the second electrode 115 of the trench capacitor structure 11a on the second surface 10b of the substrate 10, the contact area between the target capacitor structure 11 and the first conductive plug 20 is increased, so as to reduce the contact resistance, improve the conductive effect, and the first conductive plug 20 and the second conductive plug 21 are respectively connected with the second electrode 115 and the first electrode 112, so that the electrode extraction is more uniform by reducing the contact resistance, and the decoupling effect is improved.
As an example, with continued reference to fig. 10, the area of the orthographic projection of the second conductive plug 21 on the second surface 10b of the substrate 10 is smaller than the area of the orthographic projection of the first conductive plug 20 on the second surface 10b of the substrate 10. Since the aperture size of the second conductive plug 21 is small, the etching rate is slow at the time of forming the second trench 142, and overetching is not easy, thereby avoiding the occurrence of a short circuit phenomenon. In addition, since the first conductive plug 20 is located inside the trench, there is no concern that the over-etching will cause a short circuit, the aperture size is large, the contact area between the first conductive plug 20 and the target capacitor structure 11 can be increased, and the resistance can be further reduced on the basis of improving the short circuit problem.
As an example, referring to fig. 10, the semiconductor structure further includes a first isolation layer 171 and a second isolation layer 172; the first isolation layer 171 surrounds the sidewall surface of the first conductive plug 20 and is located between the second electrode 115 and the first conductive plug 20; the second isolation layer 172 surrounds the sidewall surface of the second conductive plug 21 and is located between the second electrode 115 and the second conductive plug 21. The first isolation layer 171 and the second isolation layer 172 can protect the first conductive plug 20 and the second conductive plug 21, and isolate the sidewalls of the first conductive plug 20 and the second conductive plug 21 from the adjacent conductive structures, so as to avoid the phenomenon of short circuit between different electrodes, and improve the conductivity of the semiconductor structure.
As an example, referring to fig. 10, the semiconductor structure further includes a first protection layer 15 and a second protection layer; the first protection layer 15 is located on the surface of the planar capacitor structure 11b away from the substrate 10; the second protective layer includes a first portion 191 located between the first conductive plug 20 and the first isolation layer 171, and a second portion 192 located between the second conductive plug 21 and the second isolation layer 172; wherein a first portion 191 of the second protective layer surrounds the first conductive plug 20 and a second portion 192 of the second protective layer surrounds the second conductive plug 21. The first protection layer 15 covers the surface of the planar capacitor structure 11b away from the substrate 10, i.e., the surface of the second electrode 115, to protect the second electrode 115. The second protection layer can protect the sidewall surfaces of the first conductive plugs 20 and the second conductive plugs 21 and facilitate the subsequent deposition of the first conductive plugs 20 and the second conductive plugs 21.
As an example, with continued reference to fig. 10, the target capacitor structure 11 further includes a first dielectric layer 111, a second dielectric layer 113, and a conductive layer 114 that are conformally stacked; the first dielectric layer 111 includes a first portion extending into the substrate 10 from the first surface 10a toward the second surface 10b, and a second portion located on the first surface 10a, and the first dielectric layer 111 conformally covers the first electrode 112.
As an example, with continued reference to fig. 10, the material of the first dielectric layer 111 is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. The first dielectric layer 111 may further include other insulating materials with a low dielectric constant (low-k), for example, a material with a dielectric constant less than or equal to 3.9.
As an example, with continued reference to fig. 10, the material of the first electrode 112 is selected from the group consisting of doped silicon, polysilicon, copper, tungsten, aluminum, copper alloys, titanium nitride, nitride buttons, and combinations thereof.
As an example, with continued reference to fig. 10, the material of the second dielectric layer 113 is selected from the group consisting of aluminum oxide, zirconium oxide, and combinations thereof. The second dielectric layer 113 may also include other insulating materials with a relatively high dielectric constant (high-k), such as materials with a dielectric constant greater than 3.9.
As an example, with continued reference to fig. 10, the material of the conductive layer 114 is selected from the group consisting of doped silicon, polysilicon, copper, tungsten, aluminum, copper alloys, titanium nitride, nitride buttons, and combinations thereof.
As an example, with continued reference to fig. 10, the material of the second electrode 115 is selected from the group consisting of polysilicon, titanium nitride, tantalum nitride, copper, tungsten, aluminum, and combinations thereof.
As an example, referring to fig. 11, the present disclosure further provides a package structure 1000, including a circuit board 300, a package substrate 400, the semiconductor structure 100 according to any one of the embodiments of the present disclosure, a central processing unit 500 (Central Processing Unit, abbreviated as CPU), and a memory 600; the Package substrate 400 is located on the surface of the circuit board 300, and the first surface of the Package substrate 400 is connected to the circuit board 300 through a Package ball 410 (Package balls); the semiconductor structure 100 of any of the embodiments of the present disclosure is located on the second surface of the package substrate 400, and the second surface of the semiconductor structure is connected to the second surface of the package substrate 400 through the back-off bump 110; the central processor 500 is located on the first surface of the semiconductor structure 100, and the first surface of the central processor 500 is connected with the first surface of the semiconductor structure 100 through a first micro bump 510 (ubumps); the memory 600 is located on the second surface 10b of the cpu 500, and the first surface of the memory 600 is connected to the second surface of the cpu 500 through a second micro bump 610 (ubumps).
As an example, with continued reference to fig. 11, the central processor 500 may include a base module 501, a calculation module 502, and a logic module 503. The base module 501 has a plurality of vias therein to connect with the memory 600.
As an example, referring to fig. 11, the central processor 500 further includes a port Physical layer 504 (PHY for short) for interfacing with external signals.
As an example, with continued reference to fig. 11, memory 600 includes high bandwidth memory, which may be, for example, HBM DRAM (High Bandwidth Memory Dynamic Random Access Memory, high bandwidth dynamic random access memory).
As an example, referring to fig. 11, the flip-chip bump 110 may include a C4 Cu Bumps (C4 copper bump), and the chip may be directly flip-chip soldered (Filp Chip on Board) to complete the assembly interconnection between the chips. However, each corresponding point of the chip needs to be first provided with various round or square micro solder bumps, and if the bumps are arranged on each part of the whole surface of the chip, the flip chip bonding method is specially called as Controlled Collapsed Chip Connection, and is called as C4 for short.
With continued reference to fig. 11, in the package structure 1000 in the above embodiment, the semiconductor structure 100 in any one of the embodiments of the present disclosure is connected to the chip structures such as the circuit board 300, the package substrate 400, the cpu 500, and the memory 600, and the semiconductor structure 100 in any one of the embodiments of the present disclosure is used as an interconnection structure for connection between chips, so that the performance and yield of the package structure 1000 can be improved to improve the overall performance thereof.
In the semiconductor structure, the manufacturing method thereof and the packaging structure in the embodiment, the first conductive plug is arranged in the groove of the deep groove capacitor, so that the contact resistance is reduced, and meanwhile, the problem of short circuit caused by electrode interconnection due to over etching is avoided; and the aperture size of the first conductive plug is larger than that of the second conductive plug, so that the short circuit phenomenon caused by over etching is avoided, the connection effect of each part of structure in the packaging structure is improved, and the manufacturing cost of the packaging structure is reduced and the efficiency is improved by simplifying the process steps. Therefore, the present disclosure can improve performance and yield of semiconductor structures and packaging structures to improve overall performance of memories, such as high bandwidth dynamic random access memories.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples merely represent several embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the disclosure. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
Providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite along the thickness direction of the substrate;
forming a target capacitor structure on the substrate, wherein the target capacitor structure comprises a first electrode and a second electrode which are formed in sequence; the target capacitance structure comprises a trench capacitance structure extending into the substrate towards the second surface via the first surface, and a planar capacitance structure located at the first surface; the top surface of the second electrode is higher than the first surface, and the first electrode is positioned between the substrate and the second electrode;
forming first conductive plugs and second conductive plugs which are distributed at intervals in at least the second electrode; the orthographic projection of the first conductive plug on the second surface of the substrate is positioned in the orthographic projection of the second electrode of the groove capacitor structure on the second surface of the substrate, and the second conductive plug is electrically connected with the first electrode of the plane capacitor structure.
2. The method of claim 1, wherein an area of the orthographic projection of the second conductive plug on the second surface of the substrate is smaller than an area of the orthographic projection of the first conductive plug on the second surface of the substrate.
3. The method of manufacturing a semiconductor structure according to claim 2, wherein the step of forming the first conductive plugs and the second conductive plugs in the at least second electrode in a spaced apart arrangement comprises:
forming a hard mask layer on the surface of the planar capacitor structure far away from the substrate;
forming a patterned photoresist layer on the surface of the hard mask layer far away from the planar capacitor structure;
etching the hard mask layer and the planar capacitor structure below the hard mask layer by taking the patterned photoresist layer as a mask, so that first grooves and second grooves which are distributed at intervals are formed in at least the second electrode, the first grooves expose the second electrode of the groove capacitor structure, and the second grooves expose the first electrode of the planar capacitor structure;
forming a first conductive plug in the first groove and forming a second conductive plug in the second groove.
4. The method of claim 3, wherein the step of forming a first conductive plug in the first trench and forming a second conductive plug in the second trench is preceded by the steps of:
And forming a first isolation layer on the side wall surface of the first groove, and forming a second isolation layer on the side wall surface of the second groove.
5. The method of manufacturing a semiconductor structure according to claim 4, wherein the hard mask layer includes a protective mask layer and an anti-reflection layer sequentially stacked in a thickness direction away from the substrate;
after the step of forming the first trenches and the second trenches which are distributed at intervals in the at least second electrode, before the step of forming the first isolation layer and the step of forming the second isolation layer, the method further comprises:
and removing the patterned photoresist layer and the residual anti-reflection layer, wherein the residual protection mask layer forms a first protection layer.
6. The method of manufacturing a semiconductor structure according to claim 5, further comprising, after the steps of forming the first isolation layer and forming the second isolation layer:
and forming a second protection layer on the side wall surface of the first groove and the side wall surface of the second groove.
7. A semiconductor structure, comprising:
a substrate having a first surface and a second surface opposite to each other in a thickness direction thereof;
The target capacitor structure comprises a first electrode and a second electrode which are formed in sequence; the target capacitance structure comprises a trench capacitance structure extending into the substrate towards the second surface via the first surface, and a planar capacitance structure located at the first surface; the top surface of the second electrode is higher than the first surface, and the first electrode is positioned between the substrate and the second electrode;
a first conductive plug at least partially within the second electrode;
second conductive plugs at least partially located within the second electrode and spaced apart from the first conductive plugs;
the orthographic projection of the first conductive plug on the second surface of the substrate is located in the orthographic projection of the second electrode of the groove capacitor structure on the second surface of the substrate, and the second conductive plug is electrically connected with the first electrode of the plane capacitor structure.
8. The semiconductor structure of claim 7, wherein an area of an orthographic projection of the second conductive plug on the second surface of the substrate is smaller than an area of an orthographic projection of the first conductive plug on the second surface of the substrate.
9. The semiconductor structure of claim 8, further comprising:
A first isolation layer surrounding a sidewall surface of the first conductive plug and located between the second electrode and the first conductive plug;
a second isolation layer surrounding a sidewall surface of the second conductive plug and located between the second electrode and the second conductive plug;
the first protection layer is positioned on the surface of the planar capacitor structure, which is far away from the substrate;
a second protective layer including a first portion between the first conductive plug and the first isolation layer, and a second portion between the second conductive plug and the second isolation layer;
wherein a first portion of the second protective layer surrounds the first conductive plug and a second portion of the second protective layer surrounds the second conductive plug.
10. A package structure, comprising:
a circuit board;
the packaging substrate is positioned on the surface of the circuit board, and the first surface of the packaging substrate is connected with the circuit board through packaging solder balls;
the semiconductor structure of any one of claims 7-9, being located on a second surface of the package substrate, the second surface of the semiconductor structure being connected to the second surface of the package substrate by a reverse bump;
The central processing unit is positioned on the first surface of the semiconductor structure, and the first surface of the central processing unit is connected with the first surface of the semiconductor structure through a first micro bump;
the memory is positioned on the second surface of the central processing unit, and the first surface of the memory is connected with the second surface of the central processing unit through a second micro-bump.
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