CN109716521A - Contact structures for three-dimensional storage part - Google Patents

Contact structures for three-dimensional storage part Download PDF

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Publication number
CN109716521A
CN109716521A CN201880002919.0A CN201880002919A CN109716521A CN 109716521 A CN109716521 A CN 109716521A CN 201880002919 A CN201880002919 A CN 201880002919A CN 109716521 A CN109716521 A CN 109716521A
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China
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layer
dielectric
conductive
dielectric layer
stair
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Chinese (zh)
Inventor
孙中旺
李广济
张坤
胡明
程纪伟
罗世金
鲍琨
夏志良
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Publication of CN109716521A publication Critical patent/CN109716521A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Abstract

Disclose the contact structures of three-dimensional storage part and its embodiment of manufacturing method.The three-dimensional storage organization includes the film lamination of setting on substrate, wherein the film lamination includes multiple conductive layers and dielectric layer pair, each conductive layer and dielectric layer are to conductive layer and the first dielectric layer.The three-dimensional storage organization further includes the hierarchic structure being formed in the film lamination, wherein the hierarchic structure includes multiple steps, each stair-step has two or more conductive layers and dielectric layer pair.The three-dimensional storage organization further comprises multiple axial contact structures in the first insulating layer being formed in above the hierarchic structure, wherein each axial contact structure includes one or more conducting rings and dead ring pair and conductive core, and each conducting ring and dead ring are to conducting ring and dead ring.

Description

Contact structures for three-dimensional storage part
Technical field
The disclosure relates generally to technical field of semiconductors, it is more particularly related to form three-dimensional (3D) memory Method.
Background technique
Planar storage cell is narrowed down to by improving technology, circuit design, algorithm programming and manufacturing process Smaller size.But as the characteristic size of storage unit close to lower limit, plane machining and manufacturing technology becomes more to choose War property and also cost it is higher.Therefore, the storage density of planar storage cell is close to the upper limit.Three-dimensional (3D) storage architecture is able to solve Density limitation in planar storage cell.
Summary of the invention
The embodiment of contact structures for three-dimensional storage part and forming method thereof is described in the disclosure.
In some embodiments, three-dimensional storage organization includes the film lamination of setting on substrate, wherein the film lamination packet Multiple conductive layers and dielectric layer pair are included, each conductive layer and dielectric layer are to conductive layer and the first dielectric layer.It is described Three-dimensional storage organization further includes the hierarchic structure being formed in the film lamination, wherein the hierarchic structure includes multiple steps, Each stair-step has two or more conductive layers and dielectric layer pair.The three-dimensional storage organization further comprises being formed in Multiple axial contact structures in the first insulating layer above the hierarchic structure, wherein each axial contact structure includes one Or multiple conducting rings and dead ring pair and conductive core, wherein each conducting ring and dead ring are to including conducting ring and dead ring.
In some embodiments, the correspondence conductive layer and dielectric layer that each conducting ring contacts the stair-step are to leading Electric layer.
In some embodiments, each axial contact structure includes at least outer conducting ring and interior conducting ring, and described outer Conducting ring is with the upper conductive layer and dielectric layer of the stair-step to corresponding, wherein and the outer conducting ring includes larger diameter, And the upper conductive layer and dielectric layer are to farther from the substrate.
In some embodiments, each axial contact structure includes at least outer conducting ring and interior conducting ring, and described interior Conducting ring is with the lower conductiving layer of the stair-step and dielectric layer to corresponding, wherein and the interior conducting ring includes smaller diameter, And the lower conductiving layer and dielectric layer are to closer from the substrate.
In some embodiments, the conductive core contacts two or more conductive layers and dielectric layer to the ladder platform of composition The conductive layer nearest from substrate in rank.
In some embodiments, the dead ring of the conducting ring and dead ring pair is provided about the side of the conducting ring The side wall of wall and the conductive layer of the hierarchic structure, wherein the dead ring is configured as making the conducting ring and another conduction Ring or the conductive core are electrically isolated.
In some embodiments, the dead ring is set to two or more conductive layers and dielectric layer to the rank of composition On the side wall of first dielectric layer of halfpace rank.
In some embodiments, the three-dimensional storage organization further comprises being arranged in first insulating layer and the rank Barrier layer between terraced structure, and the multiple axial contact structure extends across the barrier layer.
In some embodiments, the three-dimensional storage organization further comprises the gate dielectric layer on the conductive layer, And the conducting ring extends across the gate dielectric layer, to contact the conductive layer of the hierarchic structure.
Another aspect of the present disclosure provides the method that one kind is used to form three-dimensional (3D) memory device.One kind is used to form The method of three-dimensional (3D) storage organization includes that dielectric film stack is arranged on substrate, wherein the dielectric film stack includes more A alternately dielectric layer pair, each alternately dielectric layer is to the first dielectric layer and different from first dielectric layer Second dielectric layer.The method also includes forming dielectric ladder in the dielectric film stack, wherein the dielectric Ladder includes multiple steps, and each dielectric stair-step has two or more alternating dielectric layers pair.The method is into one Step includes that the first insulating layer is arranged on the dielectric ladder, and multiple storage strings are formed in the dielectric film stack, with And second dielectric layer is substituted using conductive layer, to form the hierarchic structure with multiple steps, wherein each ladder platform Rank includes two or more conductive layers and dielectric layer pair, and each conductive layer and dielectric layer are situated between to conductive layer and the first electricity Matter layer.The method also includes multiple axial contact structures are formed in the hierarchic structure.
In some embodiments, forming the axial contact structure includes the ladder platform to be formed in the hierarchic structure Each conductive layer of rank and the conducting ring and dead ring pair of dielectric layer pair.
In some embodiments, forming the conducting ring includes: to form the first contact hole, and first contact hole exposes institute State the stair-step in hierarchic structure two or more conductive layers and dielectric layer to one of in conductive layer；In the contact Conductive film is set on the side wall in hole and on the conductive layer of exposing；And the conductive film is removed from the bottom of first contact hole With the part of the conductive layer, to form conducting ring, wherein the bottom of the conducting ring is formed to contact the hierarchic structure In stair-step two or more conductive layers and dielectric layer to one of in conductive layer.
In some embodiments, forming the conducting ring further comprises the electricity for etching next conductive layer and dielectric layer pair Dielectric layer.
In some embodiments, forming the dead ring includes: that second insulating layer is arranged in the first contact hole；And from The bottom of first contact hole removes the second insulating layer.Form the dead ring further include: formed and surround the conduction Two or more conductive layers and dielectric layer of the side wall of ring and the stair-step in the hierarchic structure to one of conduction The dead ring of the side wall of layer；And form the second contact hole for exposing next conductive layer in the stair-step.
In some embodiments, forming the axial contact structure further comprises: being formed and exposes two or more conductions The contact hole of layer and dielectric layer to the conductive layer nearest from substrate in the stair-step of composition；Conductive material is set, to fill out Fill the contact hole；And formed contact two or more conductive layers and dielectric layer in the stair-step of composition from substrate The conductive core of nearest conductive layer.
In some embodiments, the method further includes executing flatening process, to remove outside the contact hole Conductive material, and form coplanar surface.
In some embodiments, the method further includes before first insulating layer in the dielectric ladder Upper setting barrier layer.
In some embodiments, forming the multiple dielectric stair-step includes: the setting figure on dielectric film stack Case mask；And the exposed portion of the dielectric film stack is etched on the direction of the main surface perpendicular to the substrate, Until eliminating the part of described two or more dielectric layers pair.The multiple dielectric stair-step is formed also to wrap It includes: the pattern mask being carried out on the direction of main surface for being parallel to the substrate laterally trimmed；Repeat the etching And dressing process, until foring closest to the dielectric stair-step of the main surface of substrate；And the removal pattern Change mask.
In some embodiments, substituting second dielectric layer using conductive layer to form the hierarchic structure includes: The one or more gap structures opening extended along the dielectric step horizontal is formed, wherein gap structure opening is vertical Across the dielectric film stack.Substitute second dielectric layer further include: the second electricity for removing the dielectric ladder is situated between Matter layer, to form multiple horizontal tunnels；And it will be in conductive layer setting to the multiple horizontal tunnel.
In some embodiments, the method further includes before the conductive layer is set in the horizontal tunnel Gate dielectric layer is set on side wall, wherein the gate dielectric layer include high-k dielectric material, silica, silicon nitride or Silicon oxynitride.
Those skilled in the art according to specification, the claims and drawing of the disclosure it will be appreciated that the disclosure its In terms of him.
Detailed description of the invention
The attached drawing for being incorporated herein and being formed the part of specification instantiates embodiment of the disclosure and together with specification Further to explain the principle of the disclosure, and those skilled in the relevant art is enable to make and use the disclosure.
Fig. 1 shows the diagrammatic top that tube core is stored according to the exemplary three dimensional (3D) of some embodiments of the present disclosure Figure.
Fig. 2A -2B shows the signal that some regions of tube core are stored according to the exemplary 3D of some embodiments of the present disclosure Property top view.
Fig. 3 shows the perspective view of the part of the exemplary 3D memory array structure according to some embodiments of the present disclosure.
Fig. 4-15 shows the exemplary 3D storage knot in certain fabrication stages according to some embodiments of the present disclosure The schematic sectional view of structure.
Figure 16 A shows the exemplary 3D storage organization in a certain fabrication stage according to some embodiments of the present disclosure Schematic sectional view.
Figure 16 B shows the exemplary 3D storage organization in a certain fabrication stage according to some embodiments of the present disclosure Part perspective view.
Figure 17 A-17D shows the exemplary 3D storage in certain fabrication stages according to some embodiments of the present disclosure The schematic sectional view of structure.
Figure 18 shows the stream of the illustrative methods for being used to form 3D storage organization according to some embodiments of the present disclosure Cheng Tu.
When considered in conjunction with the drawings, by the detailed description being set forth below, the features and advantages of the present invention will become more It is obvious, in the accompanying drawings, it is indicated using like numerals corresponding element always.In the accompanying drawings, similarly appended drawing reference is general Indicate equivalent, similar in functionally similar and/or structure element.Pass through leftmost side position in respective figure label Instruction first appears the attached drawing of the element.
Embodiment of the disclosure will be described with reference to the drawings.
Specific embodiment
Although discussing concrete configuration and arrangement it should be appreciated that the discussion is intended merely to reach the mesh of illustration 's.Those skilled in the art will appreciate that other configurations and arrangement can be used without departing from the spirit and scope of the disclosure.This Field technical staff, which obviously will recognize that, uses the disclosure in various other applications.
It should be pointed out that mentioning " one embodiment ", " embodiment ", " exemplary embodiment ", " some implementations in the description Example " etc. indicates that described embodiment may include specific feature, structure or characteristic, but may not each embodiment include this A particular feature, structure, or characteristic.In addition, such phrase is not necessarily referring to the same embodiment.In addition, special in description in conjunction with the embodiments When determining feature, structure or characteristic, feature, structure or characteristic in conjunction with as other embodiments realization that is clear or being not explicitly described Within knowledge in those skilled in the art.
In general, should understand term based in part on context of use.For example, the word " one used in text It is a or multiple " it can be used to describe any feature, structure or feature in the sense that odd number based in part on context, Or the combination of Expressive Features, structure or feature in the sense that plural number can be used to.Similarly, can also by word " one ", "one" or "the" are interpreted as conveying odd number to use or plural number being conveyed to use, and depend, at least partially, on context.In addition, can To be interpreted as word " being based on " to be intended to convey one group of exclusive factor, can permit on the contrary in the presence of other not necessarily clear The factor of statement, this still depends, at least partially, on context.
It should be appreciated that in the disclosure " ... on ", " in ... top " and " ... on " meaning should be by It is explained according to broadest mode, so that " ... on " do not mean only that on something, it further include on something When there is the meaning of intermediate features or layer therebetween.In addition, " ... on " or " ... on " not only have in something It is upper or on meaning, but also including its be on something or on but therebetween without any intermediate features or the meaning of layer (that is, on something).
In addition, spatially relative term can be used in text for ease of description, for example, " following ", " under ", " lower section ", " on ", " top " etc., to describe the relationship as shown in the figure of an elements or features and other elements or feature.Space is opposite Term is intended to comprising the different orientation in use or the device in processing step other than orientation shown in the drawings.It is described Equipment can have other orientations (being rotated by 90 ° or in other orientations), and the sky used in text is interpreted accordingly in the same old way Between relative descriptors.
As used herein, " substrate " word refers in the material for adding subsequent layers of material above.Substrate includes top table Face and bottom surface.The top surface of substrate is typically formed the place of semiconductor devices, therefore semiconductor devices is formed in substrate Top side, unless otherwise specified.Bottom surface is opposite with top surface, therefore the bottom side of substrate is opposite with the top side of substrate.It can be to lining Copy for the record or for reproduction body is patterned.The material for being added to substrate top can be patterned, or can keep not being patterned.This Outside, substrate may include a series of materials in wide range, for example, silicon, germanium, GaAs, indium phosphide etc..Alternatively, substrate can With by non-conducting material, for example, glass, plastics or sapphire wafer etc. are formed.
As used herein, " layer " word can refer to the material part including having certain thickness region.Layer has Top side and bottom side, wherein the bottom side of layer is relatively close to substrate, and top side is relatively distant from substrate.Layer can entire lower layer or on Cover and extend on structure, or can have than lower layer or on cover the small range of range of structure.In addition, layer can be it is homogeneous or One region of the continuous structure of person's nonuniformity, thickness are less than the thickness of the continuous structure.For example, layer can be located at the company Between any group of horizontal plane between the top surface and bottom surface of continuous structure, or it is located at the top surface and bottom surface. Layer can extend with horizontal extension, vertical extension and/or along conical surface.Substrate can be layer, can in it comprising one or Multiple layers, and/or can have it is disposed thereon, on and/or under one or more layers.Layer may include multiple Layer.For example, interconnection layer may include that one or more conductive layers and contact layer (form contact, interconnection line wherein and/or erect Straight interconnection access (VIA)) and one or more dielectric layers.
As used herein, word " nominal/nominally " refers to is arranged during the design phase of product or technique The expection or target value of the feature or parameter of component or processing step, together be higher than and/or lower than the desired value a certain value Range.Described value range may be attributed to the slightly variation of manufacturing process or tolerance.As used herein, " about " word is Refer to that both quantitative value can be changed based on particular technology node associated with object semiconductor devices.Based on particular technology section Point, " about " word can indicate both quantitative value the (for example) value 10-30% (for example, ± the 10% of the value, ± 20% Or 30%) within change.
In the disclosure, word " horizontal/horizontally/lateral/laterally ", which refers to, is nominally being parallel to substrate Lateral surfaces.In the disclosure, " each " word may not may only refer to " all of each ", but can also refer to " son Each of concentrate ".
As used herein, " 3D memory " word refers to, and there is the memory cell transistor string that is vertically oriented (to claim in text For " storage string ", for example, NAND storage string) three-dimensional (3D) semiconductor devices, the memory cell transistor string that is vertically oriented On the substrate of horizontal orientation, so that the storage string extends along the vertical direction relative to substrate.As used herein , word " vertical/vertically " refer to the nominally lateral surfaces perpendicular to substrate.
In the disclosure, for ease of description, " level (tier) " is used to refer to substantially vertically with identical The element of height.For example, wordline and following gate dielectric layer can be referred to as " level ", wordline and following insulating layer one " level " can be referred to as by rising, and substantially there is mutually level each wordline can be referred to as " wordline level ", and so on.
In some embodiments, the storage string of 3D memory device includes passing vertically through multiple conductive layers and dielectric layer to prolonging The semiconductor column (for example, silicon channel) stretched.The multiple conductive layer and dielectric layer to be otherwise known as in the text " alternating conductive and It is dielectric laminated ".The intersection of the conductive layer and the semiconductor column can form storage unit.The alternating conductive and electricity are situated between The conductive layer of matter lamination can be connected to wordline in later process, wherein the wordline can be electrically connected to one or more controls Grid.For illustrative purposes, the disclosure is described using wordline and control grid in a manner of interchangeable.The semiconductor column Top (for example, transistor drain area) can connect to bit line (be electrically connected one or more semiconductor columns).Wordline and bit line It is usually (for example, respectively by row and by column) for being mutually perpendicular to lay, to form " array " of memory, is otherwise known as and deposits It stores up " block " or " array block ".
Storage " tube core " can have one or more storages " plane ", and each memory plane can have multiple deposit Store up block.Array block can also be divided into multiple storages " page ", wherein each memory page can have multiple storage strings.In flash In nand memory part, erasing operation can be executed to each memory block, and reading/write-in can be executed to each memory page Operation.Array block is the core area of the execution store function in memory device.In order to realize higher storage density, greatly improve The quantity of vertical 3D storage layer stack, to increase the complexity and cost of manufacture.
Storing tube core has another region for being referred to as periphery, provides support function for the core.External zones includes very Multiple digital signal circuit, analogue signal circuit and/or mixed signal circuit, for example, row decoder and column decoder, driver, The circuits such as page buffer, sensing amplifier, timing and control.Peripheral circuit uses active and/or passive semiconductor devices, example Such as, transistor, diode, capacitor, resistor etc., this will be apparent to those skilled in the art.
For ease of description, the other parts of memory device are not discussed.In the disclosure, " memory device " is a common name Vocabulary can be storage chip (encapsulation), storage tube core or any part for storing tube core.
Although using three dimensional NAND device as an example, in various applications and design, can also will be disclosed Structure is applied in similar or different semiconductor devices, to (for example) improve metal connection or wiring.Disclosed knot The concrete application of structure should not be limited by embodiment of the disclosure.
Fig. 1 shows the top view of exemplary three dimensional (3D) memory device 100 according to some embodiments of the present disclosure.3D Memory device 100 can be storage tube core, and may include one or more memory planes 101, in the memory plane 101 Each may include multiple memory blocks 103.Equivalent concurrent operations can occur at each memory plane 101.It can be with The memory block 103 of size with several Mbytes (MB) is to execute the minimum dimension of erasing operation.As shown in Figure 1, exemplary 3D Memory device 100 includes four memory planes 101, and each memory plane 101 includes six memory blocks 103.Each storage Block 103 may include multiple storage units, wherein can be addressed by the interconnection of such as bit line and wordline to each storage unit. Bit line and wordline can be vertical runs, to form the array of metal wire.In Fig. 1, the direction of wordline and bit line is marked It is shown as " BL " and " WL ".In the disclosure, memory block 103 is otherwise known as " storage array ".
3D memory device 100 further includes external zones 105, that is, surrounds the region of memory plane 101.External zones 105 is containing outer Circuit is enclosed to support the function of storage array, for example, page buffer, row decoder and column decoder and sensing amplifier.
It is noted that arrangement and each memory plane of the memory plane 101 in 3D memory device 100 shown in FIG. 1 The arrangement of memory block 103 in 101 is merely used as example, does not limit the scope of the present disclosure.
In some embodiments, the storage array of 3D memory device 100 and peripheral circuit are formed on different substrates, And it can be joined together by wafer bonding, to form 3D memory device 100.In the example present, it is connect through array Touching structure can provide vertical interconnection between storage array and peripheral circuit, thus reduce metal level and reduce tube core ruler It is very little.In entitled " Hybrid Bonding Contact Structure of Three-Dimensional Memory The co-pending U.S.Patent application of Device " (application No. is No.16/046,852 and being filed on July 26th, 2018) is worked as In describe detailed construction and method using hybrid bonded 3D memory, be incorporated by herein by reference.
With reference to Fig. 2A, it illustrates the enlarged plan views in the region 108 in Fig. 1 according to some embodiments of the present disclosure. The region 108 of 3D memory device 100 may include stepped region 210 and channel structure area 211.Channel structure area 211 can wrap The array of storage string 212 is included, each storage string includes the storage unit of multiple stackings.Stepped region 210 may include hierarchic structure With the array for the contact structures 214 being formed in the hierarchic structure.In some embodiments, across 211 He of channel structural area Memory block can be divided into multiple storages along multiple gap structures 216 that the direction WL extends and refer to 218 by stepped region 210.At least one A little gap structures 216 can serve as the public source contact portion of the array for the storage string 212 in channel structure area 211.Top Portion's selection gate notch 220 can be set to each storage and refer to 218 center, so that storage to be referred to 218 top selection grid Pole (TSG) is divided into two parts, and thus, it is possible to will store to refer to that being divided into two may be programmed (read/write) pages.Although can be The erasing operation to 3D nand memory is executed in memory block rank, but can also execute read operation in memory page rank And write operation.The size of page can have the size of multiple kilobytes (KB).In some embodiments, region 108 further includes that puppet is deposited Storage string 222 is supported so as to the control of implementing process variation during manufacture and/or for additional machinery.
With reference to Fig. 2 B, it illustrates the enlarged plan views in the region 109 in Fig. 1 according to some embodiments of the present disclosure. The region 109 of 3D memory device 100 may include channel structure area 211, through array contact area 107 and top selection gate (TSG) stepped region 224.
Channel structure area 211 in region 109 can be similar with the channel structure area 211 in region 108.The stepped region TSG 224 may include the array for the TSG contact portion 226 being formed in the hierarchic structure.The stepped region TSG 224 can be set in ditch The side of road structural area 211 is simultaneously adjacent with through array contact area 107 in a top view.Array contact area 107 can run through Middle formation is multiple to run through array contact portion 228.
Fig. 3 shows the part of exemplary three dimensional (3D) memory array structure 300 according to some embodiments of the present disclosure Perspective view.Memory array structure 300 includes under substrate 330, the insulating film 331 of 330 top of substrate, 331 top of insulating film The control grid 333 (be otherwise known as " wordline (WL) ") of level and multiple levels that selection gate (LSG) 332 is constituted, it is described The control grid 333 of multiple levels is stacked on the top of LSG 332, to form the film lamination of alternating conductive layer and dielectric layer 335.The dielectric layer adjacent with the control grid of each level is for the sake of clarity not shown in Fig. 3.
The control grid of each level is separated by the gap structure 216-1 and 216-2 through film lamination 335.Storage Array structure 300 further includes the level for controlling the top selection gate (TSG) 334 on the lamination of grid 333.TSG 334, control The lamination of grid 333 and LSG 332 processed is otherwise known as " gate electrode ".Memory array structure 300 further comprise storage string 212 with And the doped source polar curve area 344 in the part in substrate 330 between adjacent LSG 332.Each storage string 212 include across The channel hole 336 that the film lamination 335 of insulating film 331 and alternating conductive layer and dielectric layer extends.Storage string 212 further includes ditch Storage film 337 on the side wall in road hole 336,337 top of storage film channel layer 338 and filled out by the core that channel layer 338 surrounds Fill film 339.Storage unit 340 can be formed in the point of intersection of control grid 333 and storage string 212.Memory array structure 300 into One step includes the multiple bit lines (BL) 341 that storage string 212 is connected to above TSG334.Memory array structure 300 further includes leading to Cross a plurality of metal interconnecting wires 343 that multiple contact structures 214 are connected to gate electrode.The edge of film lamination 335 is configured with Stairstepping, to realize the electrical connection to the gate electrode of each level.Channel structure area 211 and stepped region 210 correspond to Fig. 2A Top view in channel structure area 211 and stepped region 210, wherein one of the stepped region 210 in Fig. 3 can be used as being used for The stepped region TSG 230 of TSG connection.
In Fig. 3, for illustrative purposes, by control grid 333-1,333-2 and 333-3 and a layer of three levels The TSG 334 of grade and the LSG 332 of a level are shown together.In the example present, each storage string 212 may include difference Three storage units 340-1,340-2 and 340-3 corresponding to control grid 333-1,333-2 and 333-3.In some embodiments In, the quantity of the quantity and storage unit that control grid can be more than three, to improve memory capacity.Memory array structure 300 It can also include other structures, for example, through array contact portion, TSG notch, public source contact portion and pseudo- channel structure. For simplicity, these structures are not shown in Fig. 3.
With the demand to the more high storage capacity in NAND flash, 3D storage unit 340 or wordline 333 The quantity of vertical level is also increase accordingly, to generate higher process complexity and higher manufacturing cost.It is stored increasing When the level of the storage unit 340 of array structure 300 or wordline 333, etching deeper channel hole 336 for storage string 212 will become Must be more difficult, forming contact structures 214 in hierarchic structure also becomes more difficult.For example, in order in a large amount of vertical heap Form contact structures 214 on redundancy word line (gate electrode), need large ratio of height to width etching to form contact hole, then in contact hole into The large ratio of height to width of row conductive material deposits.In order to reduce every bit cost of 3D memory, the size of storage organization is reduced, from And allow to manufacture more memory blocks on wafer.However, the wordline lamination increased will also be along the level for being parallel to substrate surface Direction leads to broader hierarchic structure, to generate broader stepped region 210 and lower storage density.
It, can be in two or more crystalline substances in order to alleviate the etching and deposition difficulty in relation to more and more vertical stacking wordline The part of 3D memory device is formed on circle, is incorporated into together by wafer bonding or flip-chip bonding later.Alternatively, 3D memory device can be formed and stacking gradually multiple sections, wherein each section contains the word line stack of lower level series It is folded.However, the bigger lateral dimension of the hierarchic structure due to caused by the wordline of vertical stacking will limit storage density.
Various embodiments in the disclosure describe the structures and methods of the 3D memory with axial contact structure, each Axial contact structure provide needle to the hierarchic structure two or more conductive layers electrical contact.By multiple conductive layers it Between share contact structures, the size of stepped region 210 (in Fig. 2) can be reduced.Correspondingly, the 3D NAND storage can be improved The storage density of device and every bit cost.
Fig. 4 shows the sectional view of the exemplary structure 400 of three-dimensional storage part in accordance with some embodiments, wherein described Structure 400 includes substrate 330 and dielectric film stack 445.WL direction of the sectional view of Fig. 4-17D in Fig. 2A.
Substrate 330 is capable of providing the platform for being used to form subsequent structural.In some embodiments, substrate 330 includes being used for Form any suitable material of three-dimensional storage part.For example, substrate 330 may include any other suitable material, for example, silicon, SiGe, silicon carbide, silicon-on-insulator (SOI), germanium on insulator (GOI), glass, gallium nitride, GaAs, III-V compound And/or any combination of them.
The front surface 330f of substrate 330 is otherwise known as " main surface " of substrate in the text.Material layer can be arranged to lining On the front surface 330f at bottom." most push up " layer or "upper" layer are that the front surface 330f from substrate is farthest or farther away layer." most bottom " Layer or "lower" layer are that front surface 330f from substrate is nearest or closer layer.
In some embodiments, peripheral components can be formed in the external zones 105 on the front surface 330f of substrate 330. In some embodiments, active device region can be formed in the memory block 103 on the front surface 330f of substrate 330.Some In embodiment, substrate 330 may further include the insulating film 331 on front surface 330f.Insulating film 331 can by with the electricity The identical or different material of dielectric coating stack is made.
Peripheral components may include any semiconductor devices appropriate, for example, metal oxide semiconductor field effect transistor Manage (MOSFET), diode, transistor, capacitor etc..The peripheral components can use the store function for supporting storage core In the design of digital signal circuit, analogue signal circuit and/or mixed signal circuit, for example, the peripheral components can be Row decoder and column decoder, driver, page buffer, sensing amplifier, timing and control device.
Active device region in memory block is surrounded by the isolation structure of such as shallow trench isolation.It can be according in memory block The function of array device forms doped region in the active device, for example, p-type doping trap and/or n-type doping trap.
Dielectric film stack 445 extends along the transverse direction for the front surface 330f for being parallel to substrate 330.Dielectric film stack 445 include the dielectric layer 450 (also known as " the first dielectric layer ") and sacrificial layer 452 (also known as " second for alternateing stacking Dielectric layer "), wherein dielectric layer 450 is configured as the bottom and top of dielectric film stack 445.Match this In setting, each sacrificial layer 452 is clipped between two dielectric layers 450, and each dielectric layer 450 is clipped in two sacrificial layers Between 452 (other than the bottom and top).
Dielectric layer 450 and following sacrificial layer 452 are otherwise known as alternating dielectric layer to 454.Dielectric film stack 445 Formation may include setting dielectric layer 450 to all have identical thickness or with different thickness.For example, electricity is situated between The exemplary thickness of matter layer 450 may be in the range of 10nm to 500nm.Similarly, sacrificial layer 452 can all have identical Thickness can have different-thickness.For example, the exemplary thickness of sacrificial layer 452 may be at the range of 10nm to 500nm It is interior.
Although illustrating only 21 layers in total in the dielectric film stack 445 of Fig. 4, but it is to be understood that this is only Achieve the purpose that illustration, can include any amount of layer in dielectric film stack 445.
In some embodiments, dielectric film stack 445 may include other than dielectric layer 450 and sacrificial layer 452 Layer, and can be made from a different material and have different-thickness.
In some embodiments, dielectric layer 450 include any appropriate insulating materials, for example, silica, silicon oxynitride, Silicon nitride, TEOS or the silica in conjunction with F, C, N and/or H.Dielectric layer 450 can also include high-k dielectric material, For example, hafnium oxide, zirconium oxide, aluminium oxide, tantalum oxide or lanthana film.
The formation of dielectric layer 450 on substrate 330 may include any deposition method appropriate, such as chemical vapor deposition It is product (CVD), physical vapour deposition (PVD) (PVD), plasma enhanced CVD (PECVD), rapid thermal CVD (RTCVD), low Pressure chemical vapor deposition (LPCVD), sputtering, Metallo-Organic Chemical Vapor deposit (MOCVD), atomic layer deposition (ALD), high density Plasma CVD (HDP-CVD), thermal oxide, nitridation, any other appropriate deposition method and/or their combination.
In some embodiments, sacrificial layer 452 includes that different from dielectric layer 450 and can be selectively removed Any suitable material.For example, sacrificial layer 452 may include silica, silicon oxynitride, silicon nitride, TEOS, polysilicon, polycrystalline germanium, Poly-SiGe and any combination thereof.In some embodiments, sacrificial layer 452 further includes amorphous semiconductor material, for example, amorphous silicon Or amorphous germanium.Sacrificial layer 452 can be using the technology setting similar with dielectric layer 450, for example, CVD, PVD, ALD, heat Oxidation or nitridation or any combination of them.
In some embodiments, dielectric layer 450 can be silica, and sacrificial layer 452 can be silicon nitride.
Fig. 5 shows the sectional view of the exemplary structure 500 of three-dimensional storage part in accordance with some embodiments, wherein described Structure 500 includes the dielectric ladder 560 being formed in dielectric film stack 445.In dielectric ladder 560, dielectric rank Halfpace rank 562 or " flight " refer to the layer heap of the lateral dimension having the same in the surface for being parallel to substrate surface 330f Stack.Each dielectric stair-step 562 terminates at shorter length compared with following stair-step, by shortage in Fig. 5 Length be shown as lateral dimension " a ".
In some embodiments, each dielectric stair-step 562 includes two or more alternating dielectric layers to 454. Each dielectric stair-step 562 can have the alternating dielectric layer of identical quantity to or different number alternating dielectric Layer is right.As an example, Fig. 5 shows tool, there are two replace dielectric ladder 560 of the dielectric layer to 454.
It in some embodiments, can be real to the dielectric film stack 445 by using pattern mask (not shown) It applies duplicate etching-dressing process and forms multiple steps of dielectric ladder 560.In some embodiments, the patterning Mask may include photoresist or the polymer material based on carbon.The pattern mask can form dielectric rank It is removed after ladder 560.
Etching-the dressing process includes etching process and dressing process.During etching process, each electricity can be removed The part with exposing surface of dielectric step step 562.Each dielectric stair-step 562 or by top level rank Terraced Step Coverage or the rest part for being patterned mask covering are not etched.Etch depth is dielectric stair-step 562 Thickness.In some embodiments, the thickness of dielectric stair-step 562 is two or more alternating dielectric layer to 454 Overall thickness.In the example depicted in fig. 5, the thickness of dielectric stair-step 562 is two or replaces dielectric layer to 454 Thickness.It can have for the etching process of dielectric layer 450 relative to the highly selective of sacrificial layer 452, and/or anti- ?.Correspondingly, alternating dielectric layer below can serve as etching stopping layer to 454.By for each layer of switching erosion Carving technology can be etched with multiple dielectric layers that replace during an etch cycle to 454 dielectric stair-step 562.As a result, forming a stair-step during each etching-finishing circulation.
In some embodiments, can be used such as reactive ion etching (RIE) or other dry method etch technologies it is each to Anisotropic etch etches dielectric stair-step 562.In some embodiments, dielectric layer 450 is silica.In this example In, the etching to silica may include using the RIE based on the gas of fluorine and/or any other appropriate gas, for example, described Gas based on fluorine can be fluorocarbons (CF4), perfluoroethane (C2F6)、CHF3Or C3F6.In some embodiments, can pass through Wet-chemical preparation, the silicon layer for example, the mixture of hydrofluoric acid or hydrofluoric acid and ethylene glycol is made a return journey.In some embodiments In, timed-etch scheme can be used.In some embodiments, sacrificial layer 452 is silicon nitride.In the example present, to nitridation The etching of silicon may include using O2、N2、CF4、NF3、Cl2、HBr、BCl3And/or combination thereof RIE.For removing single layer stack The method and etchant of body should not be limited by the embodiment of the present disclosure.
The dressing process includes using appropriate etch process to the pattern mask (for example, isotropism dry method is lost Quarter or wet etching), so as to which the pattern mask is transversely pulled back.Lateral post-tensioning size decides dielectric The lateral dimension " a " of each step of ladder 560.After pattern mask finishing, the dielectric stair-step 562 of the top A part expose, and the other parts of the dielectric stair-step 562 of the top be still patterned mask covering.It is next to follow Etching-dressing process of ring continues the etching process.
In some embodiments, pattern mask dressing process may include dry etching, for example, using O2、Ar、N2Deng RIE.
In some embodiments, the dielectric stair-step 562 of the top can be covered by dielectric layer 450.Some In embodiment, the dielectric stair-step 562 of the top can be covered further by other dielectric substances.It can be electric to being formed Each etching of dielectric step 560-finishing circulation etching process addition removal dielectric layer 450 and/or other dielectric materials The processing step of material.
Fig. 6 shows the sectional view of the exemplary structure 600 of three-dimensional storage part in accordance with some embodiments, wherein structure 600 include the barrier layer 664 for being arranged on 500 top of structure.
The not only side wall of the top surface of covering dielectric ladder 560 but also covering dielectric ladder 560 of barrier layer 664.Some In embodiment, barrier layer 664 can be optional etching stopping layer.For example, barrier layer 664 is used as in contact etch The etching stopping layer that following structure is protected during technique.In some embodiments, the thickness on the barrier layer 664 on side wall Degree can be identical as the thickness on barrier layer 664 on top surface.In some embodiments, the thickness on the barrier layer 664 on side wall It can be different from the thickness on barrier layer 664 on top surface.In some embodiments, barrier layer 664 can be using similar Technology is made of the material similar with dielectric layer 450.
Fig. 7 shows the sectional view of the exemplary structure 700 of three-dimensional storage part in accordance with some embodiments, wherein structure 700 include the first insulating layer 768 for being arranged on 600 top of structure.
First insulating layer 768 can be to be set on dielectric ladder 560 after barrier layer 664 is formed.First Insulating layer 768 can be made of any appropriate insulator, and can be using similar technology by similar with dielectric layer 450 Material be made.In some embodiments, the first insulating layer 768 can also include spin-coating glass, be suspended in solvent solution The mixture of silica and dopant (boron or phosphorus), and can be the technique setting for using such as spin coating.In some realities It applies in example, the first insulating layer 768 may include low k dielectric material, for example, carbon-doped oxide (CDO or SiOC or SiOC:H) Or fluorine doped oxide (SiOF) etc..The low k dielectric material can be through settings such as CVD, PVD, sputterings.
In some embodiments, flatening process can be executed, for example, RIE eatch-back or chemically mechanical polishing (CMP), To form the coplanar surface parallel with the surface 330f of substrate 330.In some embodiments, the top table of the first insulating layer 768 Face 768S can be coplanar with the top surface 664S of the topmost portion on barrier layer 664.In the example present, barrier layer 664 can be with It is used as polishing stop.
Fig. 8 shows the sectional view of the exemplary structure 800 of three-dimensional storage part in accordance with some embodiments, wherein described Structure 800 includes multiple storage strings 212 across dielectric film stack 445.Storage string 212 corresponds in Fig. 2A -2B and Fig. 3 Storage string 212.For illustrative purposes, Fig. 8 shows two storage strings.Each storage string 212 is passed through by alternately dielectric Layer extends the dielectric film stack 445 of composition, and storage film 337, storage film on the inner surface including storage string 212 Channel layer 338 on 337 and the core filling film 339 surrounded by channel layer 338.In entitled " Method for Forming Gate Structure of Three-Dimensional Memory Device " (application No. is No.16/047, 158 and be filed on July 27th, 2018) co-pending U.S.Patent application in describe the detailed of the NAND storage string Fine texture and method are incorporated by herein by reference.
Fig. 9 shows the sectional view of the exemplary structure 900 of three-dimensional storage part in accordance with some embodiments (along the side WL To), wherein eliminating sacrificial layer 452 and foring multiple horizontal tunnels 970.
After forming storage string 212, can be formed along the direction WL multiple gap structures opening (with reference to Fig. 2A -2B and Fig. 3).These gap structures opening extends across dielectric film stack 445.It later, can be from the opening of gap structure 216 along BL Direction (perpendicular to the direction WL, for example, perpendicular to section shown in Fig. 9) removes sacrificial layer 452.
Can by relative to the selective any appropriate etch process of dielectric layer 450 (for example, isotropism is dry Method etching or wet etching) removal sacrificial layer 452, to make the etch process that there is minimum impact to dielectric layer 450.? In some embodiments, sacrificial layer 452 can be silicon nitride.In the example present, sacrificial layer 452 can be by using CF4、 CHF3、C4F8、C4F6And CH2F2One of or a variety of etchants RIE removal.In some embodiments, it can be used wet Method etches (for example, phosphoric acid) and removes sacrificial layer 452.
After removing sacrificial layer 452, the side wall of storage film 337 is exposed in horizontal tunnel 970.
Figure 10 shows the sectional view of the exemplary structure 1000 of three-dimensional storage part in accordance with some embodiments, wherein institute State structure 1000 include be made of alternating conductive layer and dielectric layer film lamination 335 (for example, correspond to Fig. 3 in film lamination 335).The film lamination 335 being made of alternating conductive layer and dielectric layer includes the conductive layer being clipped between dielectric layer 450 1072.In structure 1000, each stair-step 1076 includes two or more conductive layers and dielectric layer to 1074, each to lead Electric layer and dielectric layer have a conductive layer 1072 and a dielectric layer 450 to 1074.In Figure 10, as an example, often One stair-step 1076 includes two conductive layers and dielectric layer to 1074-1 and 1074-2, they are known respectively as " upper layer to " " lower layer to ".The setting of conductive layer 1072 to after in multiple horizontal tunnels, will be had to alternately dielectric layer and sacrificial now The dielectric ladder 560 of domestic animal layer becomes the hierarchic structure 1060 with alternating conductive layer and dielectric layer.
Conductive layer 1072 may include any suitably electrically conductive material suitable for gate electrode, for example, tungsten (W), aluminium (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN) and/or any combination thereof.Utilize appropriate deposition Method, the conductive material can be with fill level tunnels 970, for example, the deposition method is CVD, physical vapour deposition (PVD) (PVD), plasma enhanced CVD (PECVD), sputtering, hot evaporation, electron beam evaporation plating, Metallo-Organic Chemical Vapor deposition (MOCVD) and/or ALD.In some embodiments, conductive layer 1072 includes the tungsten (W) by CVD deposition.
In some embodiments, conductive layer 1072 can also be poly semiconductor, for example, polysilicon, polycrystalline germanium, polycrystalline germanium Silicon, any other suitable material and/or their combination.In some embodiments, the polycrystalline material can be combined with any The dopant of appropriate type, for example, boron, phosphorus or arsenic.In some embodiments, conductive layer 1072 can also be amorphous semiconductor.
In some embodiments, conductive layer 1072 can be by including WSix、CoSix、NiSixOr AlSixMetal Deng including Silicide is made.The formation of the metal silicide materials may include using above-described similar techniques formed metal layer and Poly semiconductor.The formation of the metal silicide may further include real to the metal layer and polycrystal semiconductor layer that are deposited Heat application annealing process then removes the metal not reacted.
In some embodiments, can be arranged in horizontal tunnel 970 before conductive layer 1072 (being not shown in Figure 10) Gate dielectric layer to reduce the leakage current between adjacent word line (gate electrode), and/or is reduced between grid and channel Leakage current.The gate dielectric layer may include silica, silicon nitride, silicon oxynitride and/or its is any appropriately combined.It is described Gate dielectric layer can also include high-k dielectric material, for example, hafnium oxide, zirconium oxide, aluminium oxide, tantalum oxide, lanthana And/or any combination thereof.The gate dielectric layer can be through the one or more appropriate of such as CVD, PVD and/or ALD Depositing operation setting.
Conductive layer 1072 plays a part of gate electrode in the intersection with storage string 212.In Figure 10, ten conductive layers 1072 can form ten gate electrodes for each storage string 212, for example, TSG 334, LSG 332 and eight control grids 333. Corresponding to eight control grids 333, each storage string 212 can have eight storage units 340.It is noted that in Figure 10 The quantity of the storage string and storage unit that show is intended merely to achieve the purpose that illustration, can increase the quantity, with reality Existing higher memory capacity.
After forming the gate electrode, conductive material and deposition of insulative material can be removed, in said opening to be formed Gap structure 216 refers to so that memory block is divided into storage multiple programmable and can be read (with reference to Fig. 2A -2B).
In some embodiments, the doped source in the part of substrate 330 can be formed using the technology of such as ion implanting Polar curve area 344 (refers to Fig. 3).In the example present, it can be inserted into conductive core in gap structure 216, to be formed for doping The public source contact portion in source electrode line area 344.
Structure 1000 may include other structures, for example, connecing through array contact portion (TAC), TSG notch, public source Contact portion and pseudo- channel structure, are not shown the structure in Figure 10 for simplicity.
Figure 11 shows the sectional view of the exemplary structure 1100 of three-dimensional storage part in accordance with some embodiments, wherein tying Structure 1100 includes multiple with diameter " d in the first insulating layer 7681" the first contact hole 1180.In Figure 11, for each Stair-step 1076 shows first contact hole 1180, this is intended merely to achieve the purpose that illustration.It can be each Multiple first contact holes 1180 are formed on stair-step 1076.In some embodiments, there is no the first contact on pseudo- gradin Hole 1180.
In some embodiments, photoresist or polymer material can be used as mask layer to etch the first contact Hole 1180.Due to the topological structure of the hierarchic structure, the first contact hole 1180 from top surface to stair-step Depth " H " depends on the position of each step.For the 3D nand memory of the wordline with many levels, under First contact hole 1180 of stair-step may be firmly got more than the first contact hole 1180 for upper stair-step.Therefore, from lining First contact hole 1180 of the surface 330f at bottom 330 closer stair-step 1076 rank remoter than the surface 330f from substrate 330 First contact hole 1180 of halfpace rank 1076 needs longer etching period.Selective etch technique can be used, so that The etch-rate of first insulating layer 768 is higher than the etch-rate on conductive layer 1072 and/or barrier layer 664.
In some embodiments, during the etch process of the first contact hole 1180, barrier layer 664 potentially acts as etching and stops Only layer, and following structure can be protected, until being formd on the top on barrier layer 664 for all of hierarchic structure 1060 Until all first contact holes 1180 of grade.Later, it is able to use connecing in first for same mask layer removal barrier layer 664 Part in contact hole 1180.In some embodiments, when gate dielectric layer is set on conductive layer 1072, the etching It further include the gate dielectric layer removed in the first contact hole 1180.
First contact hole 1180 passes through the first insulating layer 768, barrier layer 664 and optional gate dielectric layer and extends, from And expose the upper layer of each stair-step 1076 to the part of the conductive layer 1072 of 1074-1.In some embodiments, first absolutely Edge layer 768 is silica, and barrier layer is the combination of silicon nitride and silica.In the example present, etching silica can be used The anisotropy RIE of chemical etchant is taken, for example, the chemical etchant is CF4、CHF3、C2F6、C3F6And/or its any group It closes.The RIE for taking chemical etchant can be used in etching of silicon nitride, for example, the chemical etchant is O2、N2、CF4、NF3、 Cl2、HBr、BCl3And/or combination thereof.
Diameter " the d of first contact hole 11801" preferably smaller than the lateral dimension " a " of hierarchic structure 1060, in subsequent technique In it will be discussed in detail.
Figure 12 shows the sectional view of the exemplary structure 1200 of three-dimensional storage part in accordance with some embodiments, wherein tying Structure 1200 includes the conductive film 1282 for being arranged on 1100 top of structure.
In some embodiments, the conductive layer 1072 of the conductive film 1282 in the first contact hole 1180 and upper layer to 1074-1 Directly contact.Conductive film 1282 also covers the side wall of the first contact hole 1180.The conduction of bottom in the first contact hole 1180 Thickness " the t of film 12821" can be with the thickness " t on side wall2" identical or different.Conductive film 1282 in first contact hole 1180 Height be to be determined by the depth " H " of the first contact hole 1180.
Conductive film 1282 may include any suitably electrically conductive material, for example, such as tungsten (W), aluminium (Al), copper (Cu), cobalt (Co), the metal or metallic compound of titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN) and/or any combination thereof. The metal or metallic compound, which can be, uses such as CVD, PVD, PECVD, sputtering, hot evaporation, electron beam evaporation plating, MOCVD And/or the appropriate deposition method setting of ALD.
Conductive film 1282 can also be metal silicide, including WSix、CoSix、NiSixOr AlSixDeng.Metal silicide Material can be on the polysilicon layer by the way that metal layer to be placed directly onto the first contact hole 1180, implement thermal annealing work later Skill then removes the metal not reacted and is formed.
In some embodiments, conductive film 1282 includes the combination by the TiN/W/TiN of CVD deposition.
Figure 13 shows the sectional view of the exemplary structure 1300 of three-dimensional storage part in accordance with some embodiments, wherein institute Stating structure 1300 includes multiple conducting rings 1384 and multiple rings opening 1386.Conducting ring 1384 covers the side of the first insulating layer 768 Wall.Conductive layer 1072 of the bottom contact upper layer of conducting ring 1384 to 1074-1.
Conductive film can be removed from the bottom of ring opening 1386 by using the anisotropic etching of such as anisotropy RIE 1282 and conductive layer 1072 and form conducting ring 1384.In some embodiments, it the conductive film 1282 of hierarchic structure 1060 and leads Electric layer 1072 can be tungsten.In the example present, the anisotropic etching for being used to form conducting ring 1384 may include dry method erosion It carves, for example, using O2And CF4Mixture, CClF3Or CBrF3RIE.
Anisotropy RIE may include mean free path to improve ion and the low pressure for reducing random scatter etc. from Daughter system.During anisotropic etching, vertical direction impact structure of the ion along the top surface 330f perpendicular to substrate 330 1300.In some embodiments, the height " H " (shown in Figure 12) of conductive film 1282 can be greater than 1180 bottom of the first contact hole Thickness " t1" overall thickness with the thickness of conductive layer 1072.Therefore, the conduction of the bottom of the first contact hole 1180 can be removed Film 1282 and conductive layer 1072, while retaining the remaining conductive film on 1180 side wall of the first contact hole, to form conducting ring 1384。
Thickness " the t of conducting ring 13843" depend on conductive film 1282 initial sidewall thickness " t2" and the first contact hole 1180 side wall profile.Thickness " t3" RIE process conditions can be further depended on, for example, total etching period, ion direction Angle, pressure, DC bias and RF power etc..In order to reduce dead resistance and metal specific electric load, preferably there is bigger thickness " t3" Conducting ring 1384.However, for the finite diameter " d of the first contact hole 11801" for, it needs between storage performance and area Balance.
For each stair-step 1076, ring opening 1386 is prolonged across the conductive layer 1072 of upper layer stacked body 1074-1 It stretches, diameter " d2" less than the diameter " d of the first contact hole 11801", as shown in figure 13.
Figure 14 shows the sectional view of the exemplary structure 1400 of three-dimensional storage part in accordance with some embodiments, wherein tying Structure 1400 includes the second insulating layer 1488 for being arranged on 1300 top of structure.
The conductive material exposed in 1488 cover ring of second insulating layer opening 1386, for example, conducting ring 1384 and every single order Side wall of the upper layer of halfpace rank 1076 to the conductive layer 1072 of 1074-1.Second insulating layer 1488 can use similar deposition skill Art is made of the material similar with the first insulating layer 768.
Figure 15 shows the sectional view of the exemplary structure 1500 of three-dimensional storage part in accordance with some embodiments, wherein institute Stating structure 1500 includes multiple dead rings 1590 and multiple second contact holes 1592.It can be by from structure 1400 (in Figure 14) Ring opening 1386 bottom etching fall the part of second insulating layer 1488 and dielectric layer 450 and form dead ring 1590, In the anisotropic etching similar with the technology for being used to form conducting ring 1384 can be used layer 1488 and 450 is etched, Different etchants is used just for dielectric substance.In some embodiments, second insulating layer 1488 can be silica. It in the example present, may include using based on the gas of fluorine and/or any other appropriate gas to the etching of silica RIE, for example, the gas based on fluorine can be fluorocarbons (CF4), perfluoroethane (C2F6)、CHF3Or C3F6。
Second contact hole 1592 is across the upper layer of second insulating layer 1488 and each stair-step 1076 to the electricity of 1074-1 Dielectric layer 450 extends, to expose lower layer to the conductive layer 1072 of 1074-2.
Figure 16 A shows the sectional view of the exemplary structure 1600 of three-dimensional storage part in accordance with some embodiments, wherein Structure 1600 includes multiple conductive cores 1694.
Conductive core 1694 can be made of any suitably electrically conductive material, and can be similar with conductive film 1282, and pass through Similar techniques are formed.The conductive material of conductive core 1694 can be arranged on 1500 top of structure, fill the second contact hole 1592. Conductive core 1694 is directly contacted with conductive layer 1072 of the lower layer of each stair-step 1076 to 1074-2.
In some embodiments, the top surface of the first insulating layer 768 can be removed using the flatening process of such as CMP Any conductive material on 768S.
Figure 16 B shows the perspective view of structure 1600, wherein insulating layer and dielectric layer is for the sake of clarity omitted.It leads Electric ring 1384 and conductive core 1694 form the axial contact structure 1696 in hierarchic structure 1060.In some embodiments, ladder The stair-step 1076 of structure 1060 includes two conductive layers and dielectric layer pair, i.e., upper layer is to 1074-1 and lower layer to 1074- 2.Conducting ring 1384 can be electrically connected to conductive layer 1072 of the upper layer to 1074-1 of stair-step 1076.Conductive core 1694 can be with It is electrically connected to conductive layer 1072 of the lower layer to 1074-2 of stair-step 1076.Conducting ring 1384 and dead ring 1590 are formd and are led Electric ring and dead ring to 1697, correspond to stair-step 1076 conductive layer and one of dielectric layer centering.
Figure 17 A-17D shows another embodiment of the contact structures of the gate electrode for three-dimensional storage part.Scheming In 17A-17D, the part of contact structures and hierarchic structure is shown as example.Adopt be indicated by identical reference numerals it is similar Element, to be compared with the corresponding element in Figure 13-16A.
It in the example present,, can be with using the technique similar with described in Figure 13 during the formation of conducting ring 1384 Etch process is executed more long, to form the first contact hole 1786, wherein the first contact hole 1786 can further be worn It crosses the upper layer in stair-step 1076 to extend the dielectric layer 450 of 1074-1, to expose lower layer to the conductive layer of 1074-2 1072 (with reference to the structures 1710 in Figure 17 A).
Figure 17 B shows the sectional view of the exemplary structure 1720 of three-dimensional storage part in accordance with some embodiments, wherein Structure 1720 includes second insulating layer 1488, and second insulating layer 1488 is arranged on conducting ring 1384 in structure 1710, electricity is situated between The side wall of matter layer 450 and the lower layer of stair-step 1076 are on the exposed portion of the conductive layer 1072 of 1074-2.
Figure 17 C shows the sectional view of the exemplary structure 1730 of three-dimensional storage part in accordance with some embodiments, wherein Structure 1730 includes insulation gap body 1790 and contact hole 1792, and wherein contact hole 1792 passes through second insulating layer 1488 in bottom Extend, to expose conductive layer 1072 of the lower layer to 1074-2 of stair-step 1076.
Figure 17 D shows the sectional view of the exemplary structure 1740 of three-dimensional storage part in accordance with some embodiments, wherein Structure 1740 includes conductive core 1794, and wherein conductive core 1740 can be made of the material similar with conductive core 1694, and can To be formed by similar techniques.In the example present, the axial contact structure 1796 similar with axial contact structure 1696 is formd.
By axial contact structure 1696/1796, the conductive path one of the gate electrode of each storage unit can will be directed to It is directly routed to the surface of lining wafer, to realize the wordline and selection grid for being used for 3D memory in later process technique Various configurations.
After forming structure 1600/1740, the 3D memory interconnected about later process (BEOL) metal can be continued Part manufacture, what this will be known to those skilled in the art.In some embodiments, can add to structure 1600/1740 Add the second section of wordline lamination, to further increase the vertical quantity of storage unit.
In some embodiments, hierarchic structure 1060 may include multiple stair-steps 1076, each stair-step 1076 With the N number of conductive layer of quantity and dielectric layer to 1697, wherein N is no less than two integer.In the example present, in addition to conduction Can there are N-1 conducting ring of quantity and dead ring to 1697 except core 1694.Each conducting ring and dead ring include one to 1697 A conducting ring 1384 and a dead ring 1590, wherein dead ring 1590 is provided about the side wall of conducting ring 1384, and It is configured as being electrically isolated conducting ring 1384 and other conducting rings 1384 or conductive core 1694.Conductive core 1694 is located at axial contact The center of structure 1696.In some embodiments, conductive core 1694 can also include filling conductive core 1694 in possibility seam or The insulating core in hole.
Conductive core 1694 and conducting ring 1384 can be laid out such that conducting ring 1384 is corresponding with stair-step 1076 Conductive layer and dielectric layer are in electrical contact 1697 conductive layer 1072.With larger-diameter outer conducting ring can connect to The upper conductive layer of stair-step 1076 and the conductive layer 1072 of dielectric layer pair.Interior conducting ring with small diameter can connect To the lower conductiving layer of stair-step 1076 and the conductive layer 1072 of dielectric layer pair.Upper conductive layer and dielectric layer to from substrate compared with Far, and lower conductiving layer and dielectric layer are to closer from substrate.Conductive core 1694 can connect to the N number of conductive layer of quantity and electricity Bottommost conductive layer (for example, nearest from substrate to) in the stair-step 1076 of dielectric layer pair.
In some embodiments, conducting ring 1384 extends across the first insulating layer 768, to contact leading for hierarchic structure 1060 Electric layer 1072.In some embodiments, conducting ring 1384 also extends through the extension of barrier layer 664, to contact leading for hierarchic structure 1060 Electric layer 1072.In some embodiments, gate dielectric layer can be arranged onto conductive layer 1072.In the example present, it leads Electric ring 1384 further passs through the gate dielectric layer and extends, to contact the conductive layer of hierarchic structure 1060.
In some embodiments, conducting ring and dead ring can be set to lead in addition to surrounding to 1697 dead ring 1590 The side wall of the conductive layer of hierarchic structure is still around except the side wall of electric ring.In some embodiments, the dead ring can be set Set on the side wall of the dielectric layer of the stair-step with the N number of conductive layer of quantity and dielectric layer pair (with shown in Figure 17 D Structure is similar).
Two or more conductive layers that the hierarchic structure is connected by using the axial contact structure, can reduce rank The quantity of halfpace rank, thus, it is possible to reduce total lateral dimension of hierarchic structure.Correspondingly, stepped region can greatly be reduced The area of 210 (shown in Fig. 2A), and can be realized more highdensity storage.
Figure 18 shows the hierarchic structure for being used to form three-dimensional memory array and contact structures in accordance with some embodiments Illustrative methods 1800.The processing step of method 1800 can be used for being formed memory device structures shown in Fig. 4-16A.Method Processing step shown in 1800 does not have exclusiveness simultaneously, can also any processing step in the processing step illustrated by it Before, later or between execute other processing steps.In some embodiments, some processing steps of illustrative methods 1800 can be with It is omitted or may include here for other processing steps not described for the sake of simple.In some embodiments, method 1800 processing step can be according to different order execution, and/or can change.
At processing step 1810, dielectric film stack is set on substrate.The dielectric film stack can be in Fig. 4 The dielectric film stack 445 with alternate dielectric layer (the first dielectric layer) and sacrificial layer (the second dielectric layer).Institute State dielectric layer and sacrificial layer in Fig. 4 dielectric layer 450 and sacrificial layer 452 it is similar, and can be using similar techniques It is arranged.The dielectric layer and following sacrificial layer are referred to as alternately dielectric layer pair.
At processing step 1815, dielectric ladder is formed in the dielectric film stack.The example of dielectric ladder As shown in the dielectric ladder 560 in Fig. 5, wherein the dielectric ladder includes multiple flights, for example, stair-step.Often One stair-step includes two or more alternating dielectric layers pair.As an example, Fig. 5 shows tool, there are two alternately dielectric layers Pair dielectric ladder.Can by the dielectric film stack apply duplicate etching-dressing process and form dielectric Multiple steps of ladder.Firstly, pattern mask is arranged on dielectric film stack and makes its patterning.It is then possible to expose The part of dielectric film stack, and it is etched along the direction perpendicular to substrate main surface, it is situated between until eliminating two electricity Until the part of matter layer pair.Later, pattern mask is carried out along the direction for being parallel to substrate main surface laterally trimmed.It can weigh The multiple etching process and dressing process, until foring closest to the dielectric stair-step of substrate main surface.Finally, Pattern mask can be removed.
At processing step 1820, barrier layer is set above dielectric ladder, wherein the barrier layer can be in Fig. 6 Barrier layer 664, can be made of similar material, and formed using similar techniques.
At processing step 1825, the first insulating layer is set above the dielectric ladder.In some embodiments, institute The first insulating layer is stated to be arranged on the barrier layer.First insulating layer can be the first insulating layer 768 in Fig. 7.It connects down Come, the flatening process for such as chemically-mechanicapolish polishing (CMP) or reactive ion etching can be executed, to form coplanar surface. Fig. 7 shows the example of the structure.
At processing step 1830, multiple storage strings are formed in there is the alternately dielectric film stack of dielectric layer pair. The storage string is similar with the storage string 212 in Fig. 8, and including storage film, channel layer and core filling film.
At processing step 1835, alternately dielectric layer patterns the dielectric film stack of composition, to be formed Multiple gap openings.The gap opening extends along the dielectric step horizontal, and it is perpendicular to pass through the dielectric film stack It is straight to extend.Next, the sacrificial layer of the dielectric ladder is removed in the horizontal direction from the gap opening, thus in the rank Multiple horizontal tunnels are formed in terraced structure.After eliminating the sacrificial layer, the storage is exposed in the multiple tunnel The storage film of string.Fig. 9 shows the example of the structure after the removal sacrificial layer.
At processing step 1840, conductive material is set in the horizontal tunnel, thus be formed with alternating conductive layer and The hierarchic structure of dielectric layer, it is similar with the hierarchic structure 1060 in Figure 10.The conductive layer can by with conductive layer 1072 Similar material is made, and can be using similar techniques setting.In some embodiments, can conductive layer deposition it It is preceding that gate dielectric layer is set on the side wall of horizontal tunnel, wherein the gate dielectric layer includes high-k dielectric material, oxygen SiClx, silicon nitride or silicon oxynitride.After using conductive layer replacement sacrificial layer, the hierarchic structure includes multiple ladder platforms Rank, each stair-step tool there are two conductive layer and dielectric layer pair, for example, upper layer to and lower layer pair.
At processing step 1845, to the first patterning insulating layers, to form multiple first contact holes.Described first connects Contact hole passes through the first insulating layer and optional barrier layer extends, and exposes the conductive layer on the upper layer pair of the stair-step.Figure The first contact hole 1180 in 11 is the example of the multiple first contact hole.
At processing step 1850, conductive film is set above the hierarchic structure.The conductive film is arranged in the rank On the exposed portion of the conductive layer of terraced structure and on the side wall of the first contact hole.The conductive film can be the conduction in Figure 12 Film 1282, and can be using similar techniques setting.
At processing step 1855, the conductive film of the first contact hole bottom is removed by anisotropic etching, thus along the The side wall of one insulating layer forms conducting ring.Example of the conducting ring 1384 as the conducting ring is shown in FIG. 13.It is described to lead Electric ring can be made of the material similar with conducting ring 1384, and similar techniques can be used and formed.
At processing step 1860, second insulating layer is set on the conducting ring above the hierarchic structure.It is described Second insulating layer is similar with the second insulating layer 1488 in Figure 14, and can be and be made using similar techniques of similar material 's.
At processing step 1865, multiple dead rings are formed by the anisotropic etching to second insulating layer.It is described exhausted Edge ring is around the exposed portion of the side wall of the conducting ring and the conductive layer on the upper layer pair in stair-step.In the etching work During skill, the dielectric layer on the upper layer pair can also be removed and the conductive layer of lower layer pair can be exposed.Correspondingly, it forms Multiple second contact holes.Dead ring 1590 and the second contact hole 1592 are shown in Figure 15 as dead ring and the second contact hole Example.
At processing step 1870, multiple conductive cores are formed in the second contact hole.The conductive core contacts stair-step In lower layer pair conductive layer.The conductive core can be the conductive core 1694 in Figure 16, and can be using similar techniques It is formed.Flatening process (for example, CMP) can be used and form coplanar surface.Conductive core, dead ring and conductive core on to Under form axial contact structure.The axial contact structure can provide each of the conductive layer for the hierarchic structure Electrical connection.In each stair-step tool there are two in the case where conductive layer and dielectric layer pair, the number of contact structures can be made Amount halves, to save the area of stepped region.By these axial contact structures, the rear road work in relation to metal interconnecting wires can be continued Sequence technique, to form functionality 3D nand memory.
In some embodiments, hierarchic structure 1060 may include multiple stair-steps 1076, each stair-step 1076 With the N number of conductive layer of quantity and dielectric layer to 1697, wherein N is no less than two integer.In the example present, in addition to leading Can there are N-1 conducting ring of quantity and dead ring to 1697 except battery core 1694.Can using in processing step 1845-1870 Described in similar N-1 conducting ring of technique forming quantity and dead ring pair and conductive core.
In some embodiments, for N-1 conducting ring of forming quantity and dead ring pair, the first contact hole can be formed, The N number of conductive layer of quantity and dielectric layer to expose the stair-step in the hierarchic structure to one of in conductive layer.Later, Conductive film can be set on the side wall of the contact hole and on the conductive layer of exposing.Next, can be from the first contact hole Bottom removes the part of the conductive film and the conductive layer, to form conducting ring, wherein the bottom of the conducting ring is formed For the N number of conductive layer of quantity of the stair-step of the contact hierarchic structure and the conductive layer and dielectric of dielectric layer centering The conductive layer of layer centering.In some embodiments, can with removed during the etch process of the conducting ring next conductive layer and The dielectric layer of dielectric layer pair.
In some embodiments, second insulating layer is set in the first contact hole, it later can be from the bottom of the first contact hole Portion removes the second insulating layer, to form dead ring, thus surrounds the side wall of the conducting ring, and in the first contact hole Expose the side wall of the conductive layer.Continuing with the cyclic process of next conducting ring and dead ring pair, start from being formed Expose the second contact hole of next conductive layer etc. in the stair-step.
In some embodiments, the conductive core of the axial contact structure can be eventually formed.There is number being formed to expose Measure the bottommost conductive layer (for example, closest to substrate) in the stair-step of N number of conductive layer and dielectric layer pair contact hole it Afterwards, conductive material can be set, to fill the contact hole, and flatening process can be used (for example, chemical machinery is thrown Light) form the conductive core for contacting the bottommost conductive layer.The conductive material outside the contact hole can be removed, and can be incited somebody to action The structure is formed to have coplanar surface.
Correspondingly, the hierarchic structure with multiple stair-steps is formd, each step has the N number of conductive layer of quantity.? Multiple axial contact structures are formed in the hierarchic structure.Each axial contact structure can provide quantity N number of conductive path, use In being connected to the N number of conductive layer of quantity, and it is connected to the wordline of the storage string of vertical stacking.It, can by sharing contact structures Greatly reduce the lateral dimension of hierarchic structure, and can be improved the storage density of 3D memory device.
Provide according to various embodiments of the present disclosure has smaller die-size, more compared with other 3D memory devices The 3D memory device of the performance of high device density and raising.
Correspondingly, the various embodiments of three-dimensional storage part and its manufacturing method are described in the disclosure.
In some embodiments, the three-dimensional storage organization includes the film lamination of setting on substrate, wherein the film is folded Layer includes multiple conductive layers and dielectric layer pair, and each conductive layer and dielectric layer are to conductive layer and the first dielectric layer. The three-dimensional storage organization further includes the hierarchic structure being formed in the film lamination, wherein the hierarchic structure includes multiple Rank, each stair-step have two or more conductive layers and dielectric layer pair.The three-dimensional storage organization further comprises shape Multiple axial contact structures in the first insulating layer above hierarchic structure described in Cheng Yu, wherein each axial contact structure includes One or more conducting rings and dead ring pair and conductive core, wherein each conducting ring and dead ring are to including conducting ring and insulation Ring.
In some embodiments, a kind of method being used to form three-dimensional storage organization includes that dielectric film is arranged on substrate Lamination, wherein the dielectric film stack includes multiple alternately dielectric layers pair, each alternately dielectric layer is to the first electricity Dielectric layer and the second dielectric layer different from first dielectric layer.The method also includes in the dielectric film stack Middle formation dielectric ladder, wherein the dielectric ladder includes multiple steps, each dielectric stair-step tool there are two or More alternately dielectric layers pair.The method further includes the first insulating layer is arranged on the dielectric ladder, described Multiple storage strings are formed in dielectric film stack, and substitute second dielectric layer using conductive layer, to be formed with more The hierarchic structure of a step, wherein each stair-step includes two or more conductive layers and dielectric layer pair, each conductive layer With dielectric layer to conductive layer and the first dielectric layer.It is multiple same the method also includes being formed in the hierarchic structure Axis contact structures.
Above to the description of specific embodiment by the abundant summary essence for disclosing the disclosure, those skilled in the art are not needed Excessive test can easily be directed to various application modifications and/or the such specific implementation of adjustment by the knowledge of this field Example, without departing from the General Principle of the disclosure.Therefore, based on the introduction and guide provided in text, it is intended that it is such adjustment and Modification is fallen in the range of the meaning and equivalence of the disclosed embodiments.It should be appreciated that the words or terms in text are For purpose non-limiting for description, thus those skilled in the art should be according to the introduction and guide to this specification Term or wording are explained.
Above by means of illustrating that the function building block of the embodiment of specified function and its relationship describes the disclosure Embodiment.For convenience of description, it is arbitrarily defined the boundary of these function building blocks here.Substitution can be defined Boundary, as long as being appropriately performed specified function and its relationship.
Summary and abstract part may elaborate inventors have contemplated that the disclosure one or more demonstrations Property embodiment, and not all exemplary embodiment, thus be not intended to and the disclosure and appended right are wanted in any manner It asks and is construed as limiting.
The width and range of the disclosure should not be limited by any exemplary embodiment in above-mentioned exemplary embodiment, but It is defined according only to following the claims and its equivalent.

Claims (20)

1. a kind of three-dimensional storage organization, comprising:
Film lamination on substrate is set, wherein the film lamination includes multiple conductive layers and dielectric layer pair, each conductive layer With dielectric layer to including conductive layer and the first dielectric layer；
The hierarchic structure being formed in the film lamination, wherein the hierarchic structure includes multiple steps, each stair-step packet Include two or more conductive layers and dielectric layer pair；And
The multiple axial contact structures being formed in the first insulating layer above the hierarchic structure,
Wherein each axial contact structure includes one or more conducting rings and dead ring pair and conductive core,
Wherein each conducting ring and dead ring are to including conducting ring and dead ring.
2. three-dimensional storage organization according to claim 1, wherein the correspondence that each conducting ring contacts the stair-step is led The conductive layer of electric layer and dielectric layer pair.
3. three-dimensional storage organization according to claim 2, wherein
Each axial contact structure includes at least outer conducting ring and interior conducting ring；And
The outer conducting ring and the upper conductive layer of the stair-step and dielectric layer to corresponding, wherein
The outer conducting ring includes larger diameter, and
The upper conductive layer and dielectric layer are to farther from the substrate.
4. three-dimensional storage organization according to claim 2, wherein
Each axial contact structure includes at least outer conducting ring and interior conducting ring；And
The interior conducting ring and the lower conductiving layer of the stair-step and dielectric layer to corresponding, wherein
The interior conducting ring includes smaller diameter, and
The lower conductiving layer and dielectric layer are to closer from the substrate.
5. three-dimensional storage organization according to claim 1, wherein the conductive core contacts two or more conductive layers and electricity Dielectric layer is to the conductive layer nearest from the substrate in the stair-step of composition.
6. three-dimensional storage organization according to claim 1, wherein
The dead ring of the conducting ring and dead ring pair is provided about the side of the conductive layer of the hierarchic structure The side wall of wall and the conducting ring, wherein the dead ring is configured as making the conducting ring and another conducting ring or described leads Battery core is electrically isolated.
7. three-dimensional storage organization according to claim 6, wherein the dead ring is set to two or more conductive layers With dielectric layer on the side wall of first dielectric layer of the stair-step of composition.
8. three-dimensional storage organization according to claim 1 further includes being arranged in first insulating layer and the ladder knot Barrier layer between structure, and the multiple axial contact structure extends across the barrier layer.
9. three-dimensional storage organization according to claim 1, further comprises:
Gate dielectric layer on the conductive layer, and
The conducting ring of the conductive layer of the hierarchic structure is extended to contact across the gate dielectric layer.
10. a kind of method for being used to form three-dimensional storage organization, comprising:
Dielectric film stack is set on substrate, wherein the dielectric film stack includes multiple alternately dielectric layers pair, it is each Alternately dielectric layer is to including the first dielectric layer and different from the second dielectric layer of first dielectric layer；
Dielectric ladder is formed in the dielectric film stack, wherein the dielectric ladder includes multiple steps, Mei Yi electricity Dielectric step step includes two or more alternating dielectric layers pair；
The first insulating layer is set on the dielectric ladder；
Multiple storage strings are formed in the dielectric film stack；
Second dielectric layer is substituted using conductive layer, to form the hierarchic structure with multiple steps, wherein each ladder Step includes two or more conductive layers and dielectric layer pair, and each conductive layer and dielectric layer are to including conductive layer and described the One dielectric layer；And
Multiple axial contact structures are formed in the hierarchic structure.
11. according to the method described in claim 10, wherein forming the axial contact structure and including:
Formation is for each conductive layer of the stair-step in the hierarchic structure and the conducting ring of dielectric layer pair and absolutely Edge ring pair, wherein the conducting ring and dead ring are to including conducting ring and dead ring.
12. according to the method for claim 11, wherein forming the conducting ring and including:
Form the first contact hole, with expose the stair-step in the hierarchic structure described two or more conductive layers and Dielectric layer to one of in the conductive layer；
Conductive film is set on the side wall of the contact hole and on the conductive layer that is exposed；And
From the bottom of first contact hole remove the conductive layer part and the conductive film, to form conducting ring, wherein The bottom of the conducting ring is formed to contact described two or more conductions of the stair-step in the hierarchic structure Layer and dielectric layer to one of in the conductive layer.
13. according to the method for claim 12, wherein formed the conducting ring further comprise etch next conductive layer and First dielectric layer of dielectric layer pair.
14. according to the method for claim 11, wherein forming the dead ring and including:
Second insulating layer is set in the first contact hole；
The second insulating layer is removed from the bottom of first contact hole；And
Form the dead ring, described two in the stair-step in the hierarchic structure of the dead ring or more More conductive layers and dielectric layer to one of the conductive layer side wall and the conducting ring side wall；And
The second contact hole is formed, to expose next conductive layer in the stair-step.
15. according to the method described in claim 10, wherein forming the axial contact structure and further comprising:
Formed contact hole, with expose two or more conductive layers and dielectric layer in the stair-step of composition from described The nearest conductive layer of substrate；
Conductive material is set, to fill the contact hole；And
Formed conductive core, with contact two or more conductive layers and dielectric layer in the stair-step of composition from the substrate The nearest conductive layer.
16. according to the method for claim 15, further comprising executing flatening process, to remove outside the contact hole The conductive material and form coplanar surface.
17. according to the method described in claim 10, further comprising before first insulating layer in the dielectric rank Barrier layer is set on ladder.
18. all having the multiple of two or more dielectric layers pair according to the method described in claim 10, wherein being formed Dielectric stair-step includes:
Pattern mask is set on the dielectric film stack；
The exposed portion that the dielectric film stack is etched along the direction of the main surface perpendicular to the substrate, until eliminating Until the part for stating two or more dielectric layers pair；
The pattern mask is carried out along the direction for the main surface for being parallel to the substrate laterally trimmed；
The etching and the finishing are repeated, until forming the dielectric stair-step closest to the main surface of the substrate Until；And
Remove the pattern mask.
19. according to the method described in claim 10, wherein substituting second dielectric layer using the conductive layer to be formed The hierarchic structure includes:
The one or more gap structures opening extended along the dielectric step horizontal is formed, wherein the gap structure is open Pass vertically through the dielectric film stack；
Second dielectric layer of the dielectric ladder is removed, to form multiple horizontal tunnels；And
The conductive layer is set in the multiple horizontal tunnel.
20. according to the method for claim 19, further comprising:
Gate dielectric layer is set on the side wall of the horizontal tunnel before the conductive layer is set, wherein the grid is electric Dielectric layer includes high-k dielectric material, silica, silicon nitride or silicon oxynitride.
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