KR20180033952A - Three dimensional flash memory for increasing cell current and manufacturing method thereof - Google Patents

Abstract

According to an embodiment of the present invention, a 3D flash memory for increasing a cell current includes: at least one channel layer made of a III-V group compound including Ga, As, and P; a plurality of electrode layers vertically stacked on the at least one channel layer; a plurality of oxide-nitride-oxide (ONO) layers formed to connect between the plurality of electrode layers and the at least one channel layer; and a plurality of interlayer insulating layers connected to the at least one channel layer, alternatively arranged with the plurality of electrode layers and vertically stacked with respect to the at least one channel layer. The ratio of Ga, As and P included in the III-V group compound is controlled to have higher mobility than the mobility of Poly-Si or Si and temperature resistance of a predetermined temperature or higher. Accordingly, the present invention can improve a threshold voltage distribution of the plurality of electrode layers.

Description

TECHNICAL FIELD [0001] The present invention relates to a three-dimensional flash memory for increasing a cell current and a method for manufacturing the same,

The present invention relates to a three-dimensional flash memory and a method of manufacturing the same. More particularly, the present invention relates to a three-dimensional flash memory and a method of manufacturing the same. More particularly, It is a technology to improve.

A flash memory device is an electrically erasable programmable read only memory (EEPROM), which may be, for example, a computer, a digital camera, an MP3 player, a game system, a memory stick ) And the like. Such a flash memory device electrically controls data input / output by F-N tunneling (Fowler-Nordheim tunneling) or hot electron injection (Hot electron injection).

1, a cell array of a three-dimensional flash memory includes a common source line CSL, a bit line BL and a common source line CSL, And a plurality of cell strings CSTR disposed between the cell strings BL.

The bit lines are arranged two-dimensionally, and a plurality of cell strings CSTR are connected in parallel to each of the bit strings. The cell strings CSTR may be connected in common to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines and one common source line CSL. At this time, a plurality of common source lines (CSL) may be provided, and a plurality of common source lines (CSL) may be arranged two-dimensionally. Here, electrically same voltage may be applied to the plurality of common source lines CSL, or each of the plurality of common source lines CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground selection transistor GST connected to the common source line CSL, a string selection transistor SST connected to the bit line BL, and ground and string selection transistors GST and SST And a plurality of memory cell transistors MCT arranged between the plurality of memory cell transistors MCT. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be connected in common to the sources of the ground selection transistors GST. In addition, a ground selection line GSL, a plurality of word lines WL0-WL3 and a plurality of string selection lines SSL, which are disposed between the common source line CSL and the bit line BL, As the electrode layers of the transistor GST, the memory cell transistors MCT and the string selection transistors SST, respectively. In addition, each of the memory cell transistors MCT includes a memory element.

On the other hand, existing three-dimensional flash memories increase the degree of integration by vertically stacking cells in order to satisfy excellent performance and low price required by consumers.

For example, referring to FIG. 2 showing the structure of a conventional three-dimensional flash memory, an existing three-dimensional flash memory includes interlayer insulating layers 211 and horizontal structures 250 alternately on a substrate 200 And repeatedly formed electrode structures 215 are arranged and manufactured. The interlayer insulating layers 211 and the horizontal structures 250 may extend in the first direction. The interlayer insulating layers 211 may be a silicon oxide layer and the lowermost interlayer insulating layer 211a of the interlayer insulating layers 211 may have a thickness smaller than that of the remaining interlayer insulating layers 211. [ Each of the horizontal structures 250 may include first and second blocking insulating films 242 and 243 and an electrode layer 245. A plurality of electrode structures 215 may be provided and the plurality of electrode structures 215 may be disposed facing each other in a second direction crossing the first direction. The first and second directions may correspond to the x-axis and the y-axis, respectively, of Fig. Between the plurality of electrode structures 215, the trenches 240 that separate them may extend in the first direction. Highly doped impurity regions may be formed in the substrate 200 exposed by the trenches 240 so that the common source line CSL may be disposed. Although not shown, separate insulating films for filling the trenches 240 can be further disposed.

Vertical structures 230 passing through the electrode structure 215 may be disposed. In one example, the vertical structures 230 may be arranged in a matrix form aligned along the first and second directions, from a plan viewpoint. As another example, the vertical structures 230 may be arranged in a zigzag fashion in a first direction, aligned in a second direction. Each of the vertical structures 230 may include a protective film 224, a charge storage film 225, a tunnel insulating film 226, and a channel layer 227. In one example, the channel layer 227 may be disposed in a hollow tubular form therein, in which case a buried film 228 filling the interior of the channel layer 227 may be further disposed. A drain region D may be disposed on the channel layer 227 and a conductive pattern 229 may be formed on the drain region D to be connected to the bit line BL. The bit line BL may extend in a direction that intersects the horizontal electrodes 250, for example, in a second direction. In one example, the vertical structures 230 aligned in the second direction may be connected to one bit line BL.

The charge storage film 225 and the tunnel insulating film 226 included in the first and second blocking insulating films 242 and 243 and the vertical structures 230 included in the horizontal structures 250 are formed in the three- And an ONO (Oxide-Nitride-Oxide) layer, which is an information storage element. That is, some of the information storage elements may be included in the vertical structures 230 and some of the information storage elements may be included in the horizontal structures 250. The charge storage film 225 and the tunnel insulating film 226 in the information storage element are included in the vertical structures 230 and the first and second blocking insulating films 242 and 243 are formed in the horizontal structures 250. [ .

Epitaxial patterns 222 may be disposed between the substrate 200 and the vertical structures 230. The epitaxial patterns 222 connect the substrate 200 and the vertical structures 230. The epitaxial patterns 222 may be in contact with at least one layer of horizontal structures 250. That is, the epitaxial patterns 222 may be arranged to be in contact with the lowermost horizontal structure 250a. According to another embodiment, the epitaxial patterns 222 may be arranged to contact a plurality of layers, for example two layers of horizontal structures 250. On the other hand, when the epitaxial patterns 222 are disposed so as to be in contact with the lowermost horizontal structure 250a, the lowermost horizontal structure 250a may be arranged thicker than the remaining horizontal structures 250a. The lowermost horizontal structure 250a contacting the epitaxial patterns 222 may correspond to the ground selection line GSL of the cell array of the three-dimensional flash memory described with reference to FIG. 1, and the vertical structures 230 ) May correspond to a plurality of word lines WL0-WL3.

Each of the epitaxial patterns 222 has a recessed sidewall 222a. Accordingly, the lowermost horizontal structure 250a contacting the epitaxial patterns 222 is disposed along the profile of the recessed sidewall 222a. That is, the lowermost horizontal structure 250a may be disposed inwardly convexly along the recessed sidewalls 222a of the epitaxial patterns 222. In other words,

In the conventional three-dimensional flash memory having such a structure, the length of the channel layer 227 increases as the number of stages stacked vertically increases. This is because the decrease of the cell current and the threshold voltage dispersion of the electrode layer 245 Resulting in deterioration. Particularly, since the existing three-dimensional flash memory forms the channel layer 227 with Poly-Si or Si having a low mobility, the cell current is reduced and the threshold voltage dispersion is severely degraded.

Therefore, the following embodiments propose a technique for increasing the cell current which is decreased as the length of the channel layer becomes longer in the three-dimensional flash memory and improving the threshold voltage dispersion of the plurality of electrode layers.

Embodiments provide a three-dimensional flash memory and method of fabricating the same that increase the cell current as the length of the channel layer increases and improve the threshold voltage dispersion of the plurality of electrode layers.

Specifically, one embodiment includes a three-dimensional flash memory device that increases the cell current and improves threshold voltage dispersion by forming a channel layer of a Group 3-5 compound with higher mobility than Poly-Si or Si, Memory and a method of manufacturing the same.

According to one embodiment, a three-dimensional flash memory for increasing cell current comprises at least one channel layer formed of a Group 3-5 compound including Ga, As, and P; A plurality of electrode layers vertically stacked on the at least one channel layer; A plurality of ONO (Oxide-Nitride-Oxide) layers formed to connect between the plurality of electrode layers and the at least one channel layer; And a plurality of interlayer insulating layers connected to the at least one channel layer and alternately arranged with the plurality of electrode layers and stacked vertically with respect to the at least one channel layer, The proportion of Ga, As and P contained is adjusted to have a temperature resistance higher than a preset temperature and a mobility higher than that of Poly-Si or Si.

The ratio of Ga, As and P contained in the 3-5 group compound is adjusted to have a temperature resistance of 700 ° C or more and a mobility of 1000 cm ² / Vs or more when the 3-5 group compound is a single crystal compound, -5 group compound is a polycrystalline compound, it can be adjusted to have a temperature resistance of 700 ° C or higher and a mobility of 100 cm ² / Vs or more.

Each of said at least one channel layer being formed with a thickness less than a predetermined thickness; And a second channel layer surrounded by the first channel layer and formed over a predetermined thickness, wherein the first channel layer has a higher temperature tolerance than a group 3-5 compound forming the second channel layer Lt; RTI ID = 0.0 > 3-5 < / RTI >

Wherein the first channel layer is formed of a Group 3-5 compound comprising Ga and P and the second channel layer is formed of a Group 3-5 compound comprising Ga and As or a Group 3-5 compound comprising Ga, Group compound.

The three-dimensional flash memory may further include at least one capping layer covering an upper portion of the at least one channel layer so that the at least one channel layer is not exposed to the outside.

The at least one capping layer may be formed of a conductor.

According to one embodiment, a three-dimensional flash memory that increases cell current includes at least one channel layer formed of a Group 3-5 compound; A plurality of electrode layers vertically stacked on the at least one channel layer; A plurality of ONO (Oxide-Nitride-Oxide) layers formed to connect between the plurality of electrode layers and the at least one channel layer; And a plurality of interlayer insulating layers connected to the at least one channel layer and alternately arranged with the plurality of electrode layers and stacked vertically with respect to the at least one channel layer, The proportion of the Group 3-5 elements involved is adjusted to have a temperature tolerance above a predetermined temperature and a higher mobility than the Poly-Si or Si mobility.

According to one embodiment, a three-dimensional flash memory for increasing cell current comprises at least one channel layer formed of a Group 3-5 compound including Ga, As, and P; A plurality of electrode layers vertically stacked on the at least one channel layer; A plurality of ONO (Oxide-Nitride-Oxide) layers formed to connect between the plurality of electrode layers and the at least one channel layer; A plurality of interlayer insulating layers connected to the at least one channel layer and alternately arranged with the plurality of electrode layers, the interlayer insulating layers vertically stacked on the at least one channel layer; And at least one capping layer covering an upper portion of the at least one channel layer so that the at least one channel layer is not exposed to the outside, wherein Ga, As, and P contained in the 3-5 group compound The ratio is adjusted to have a temperature tolerance above a predetermined temperature and a higher mobility than the Poly-Si or Si mobility.

According to one embodiment, a method of fabricating a three-dimensional flash memory for increasing cell current comprises the steps of: preparing a mold structure on a substrate, in which a plurality of interlayer insulating layers and a plurality of sacrificial layers are alternately arranged; Creating at least one hole through the mold structure to expose the substrate; Forming at least one channel layer of a Group 3-5 compound comprising Ga, As and P in the at least one hole; Removing the plurality of sacrificial layers to form a plurality of vertically extending trenches with respect to the at least one channel layer; And forming a plurality of ONO (Oxide-Nitride-Oxide) layers surrounding each of the plurality of electrode layers in the plurality of trenches, wherein the ratio of Ga, As, and P contained in the 3-5 group compound Is adjusted to have a temperature resistance higher than a predetermined temperature and a mobility higher than that of Poly-Si or Si.

The ratio of Ga, As and P contained in the 3-5 group compound is adjusted to have a temperature resistance of 700 ° C or more and a mobility of 1000 cm ² / Vs or more when the 3-5 group compound is a single crystal compound, -5 group compound is a polycrystalline compound, it can be adjusted to have a temperature resistance of 700 ° C or higher and a mobility of 100 cm ² / Vs or more.

The step of forming at least one channel layer of a Group 3-5 compound in the at least one hole may include forming a first channel layer of less than a predetermined thickness and a second channel layer of a predetermined thickness or more in each of the at least one hole And the first channel layer may be formed of a Group 3-5 compound having a higher temperature resistance than the Group 3-5 compounds forming the second channel layer.

The step of sequentially forming a first channel layer below a predetermined thickness and a second channel layer above a predetermined thickness in said at least one hole in turn comprises depositing a first channel layer of Group 3-5 compound comprising Ga and P And forming the second channel layer with a Group 3 to 5 compound including Ga and As or a Group 3 to 5 compound including Ga, As, and P. [

The method of manufacturing a three-dimensional flash memory may further include forming at least one capping layer as a conductor covering the top of the at least one channel layer so that the at least one channel layer is not exposed to the outside have.

Wherein creating a plurality of ONO layers within each of the plurality of trenches, each of the plurality of ONO layers surrounding the plurality of electrode layers, comprises: depositing a plurality of ONO layers, respectively, in the plurality of trenches; And forming the plurality of electrode layers in the plurality of trenches, in which the plurality of ONO layers are each deposited, respectively.

One embodiment can provide a three-dimensional flash memory and a method of manufacturing the same that increase a cell current that decreases as a channel layer becomes longer and improve threshold voltage dispersion of a plurality of electrode layers.

Specifically, one embodiment includes a three-dimensional flash memory device that increases the cell current and improves threshold voltage dispersion by forming a channel layer of a Group 3-5 compound with higher mobility than Poly-Si or Si, Memory and a method of manufacturing the same.

Accordingly, one embodiment can provide a three-dimensional memory device that improves integration and reliability and a method of manufacturing the same.

FIG. 1 is a simplified circuit diagram showing a cell array of a conventional three-dimensional flash memory.
2 is a perspective view illustrating a structure of a conventional three-dimensional flash memory.
3 is a cross-sectional view illustrating a structure of a three-dimensional flash memory according to an exemplary embodiment of the present invention.
4 is a cross-sectional view illustrating a structure of a three-dimensional flash memory according to another embodiment.
5 is a cross-sectional view illustrating a structure of a three-dimensional flash memory according to another embodiment of the present invention.
6 to 10 are cross-sectional views illustrating a method of fabricating a three-dimensional flash memory according to an embodiment.
11A to 11B are cross-sectional views for explaining another embodiment of a process of forming at least one channel layer shown in FIG.
12A to 12B are cross-sectional views for specifically illustrating a process of generating a plurality of ONO layers shown in FIG.
FIG. 13 is a cross-sectional view illustrating a process of forming at least one capping layer in the method of manufacturing the three-dimensional flash memory shown in FIGS. 6 to 10. FIG.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the embodiments. In addition, the same reference numerals shown in the drawings denote the same members.

Also, terminologies used herein are terms used to properly represent preferred embodiments of the present invention, which may vary depending on the user, intent of the operator, or custom in the field to which the present invention belongs. Therefore, the definitions of these terms should be based on the contents throughout this specification.

3 is a cross-sectional view illustrating a structure of a three-dimensional flash memory according to an exemplary embodiment of the present invention.

3, a three-dimensional flash memory 300 according to an exemplary embodiment includes at least one channel layer 310, a plurality of electrode layers 320, a plurality of ONO layers 330, and a plurality of interlayer insulating layers (340).

Hereinafter, in the three-dimensional flash memory 300, the horizontal direction 301 refers to the second direction of the y-axis described with reference to FIG. 2, and the vertical direction 302 refers to the direction of the z-axis perpendicular to the x- . The three-dimensional flash memory 300 corresponds to the electrode structure in which the vertical structures are arranged in the conventional three-dimensional flash memory described with reference to FIG. 2 (the structure is different). Accordingly, the three-dimensional flash memory 300 can also be applied to the structure described with reference to FIG.

At least one channel layer 310 is formed of a Group 3-5 compound comprising at least one element of Ga, As, or P. At this time, at least one channel layer 310 may be formed to be long in the vertical direction 302.

In addition, although not shown in the drawing, the inside of the at least one channel layer 310 may be formed in a hollow tube shape. In this case, a buried layer 311 filling the inside of the at least one channel layer 310 is further disposed . Also, a drain region may be disposed above the at least one channel layer 310, and a conductive pattern may be formed on the drain region to be connected to the bit line. In this case, the bit line may extend in the horizontal direction 301. Accordingly, when a plurality of at least one channel layer 310 is provided and aligned in the horizontal direction 301, a plurality of channel layers may be connected to a common bit line.

Particularly, the ratio of the Group 3 to 5 elements forming at least one channel layer 310 is adjusted to have a temperature tolerance of a predetermined temperature or higher, and the poly-Si or poly-Si used as the material of the channel layer in the conventional three- Si < / RTI > mobility. For example, the proportion of Group 3 to 5 elements such as As and P is such that when the Group 3-5 compound forming at least one channel layer 310 is a single crystal compound, at least one channel layer 310 is 700 ° C and adjusted to have a more temperature-resistant and 1000cm ² / Vs or more mobility, at least one case of a group III-V compound to form a channel layer 310, a poly crystal compound, at least 700 ° C temperature resistant and 100cm ² / Vs. ≪ / RTI > More specifically, at least one channel layer 310 formed of a Group 3-5 compound, such as GaAs _x P _y , has a temperature resistance of greater than or equal to 700 ° C and a resistivity of greater than 1000 cm ² / Vs or more so as to have a mobility is the number of elements in As and P are each controlled within 100 (particularly 50), when the group III-V compound is a poly-crystal compound, 700 ° C or more temperature-resistant and 100cm ² The number of elements of As and P can be adjusted within 100 (in particular, 50), respectively, so as to have a mobility of more than / Vs. Accordingly, the three-dimensional flash memory 300 including at least one channel layer 310 is resistant to temperature tolerance and can have high mobility.

The plurality of electrode layers 320 are stacked vertically (for example, in the horizontal direction 301) with respect to at least one channel layer 310 formed in the vertical direction 302, and the plurality of interlayer insulating layers 340 (For example, in the horizontal direction 301) with respect to the at least one channel layer 310, as in the case of the plurality of electrode layers 320. That is, the plurality of electrode layers 320 and the plurality of interlayer insulating layers 340 may be alternately arranged and extend in the horizontal direction 301.

Here, the plurality of interlayer insulating layers 340 may be a silicon oxide film or a silicon nitride film, and the thicknesses thereof may all be the same or different from each other. For example, the plurality of interlayer insulating layers 340 may be formed to have a thicker thickness as it goes down to the lower portion of the stack.

The plurality of electrode layers 320 may be formed of a conductive material. Like the plurality of interlayer insulating layers 340, the respective electrode layers 320 may have the same thickness or may be different from each other.

In this case, the plurality of interlayer insulating layers 340 are directly connected to the at least one channel layer 310, but the plurality of electrode layers 320 are formed by the plurality of ONO layers 330 in at least one channel layer 310). In other words, each of the plurality of ONO layers 330 has a shape surrounding each of the plurality of electrode layers 320 (one surface of each of the plurality of electrode layers 320 is exposed to the outside, and the other surfaces are not exposed to the outside Covering shape).

Each of the plurality of ONO layers 330 may include a protective oxide film 331 serving as a protection, a nitride film 332 serving as a charge storage, and a tunnel oxide film 333. The plurality of ONO layers 330 may be connected to each of the plurality of electrode layers 320 and the at least one channel layer 310 to trap the charge to store data.

As described above, the three-dimensional flash memory 300 according to an exemplary embodiment includes at least one channel layer 310 formed of a 3-5 group compound, thereby increasing the cell current, Can be improved. Therefore, the reliability of the three-dimensional flash memory 300 can be improved.

Also, at least one channel layer 310 may be formed in a stacked structure. A detailed description thereof will be described with reference to FIG.

4 is a cross-sectional view illustrating a structure of a three-dimensional flash memory according to another embodiment.

Referring to FIG. 4, the three-dimensional flash memory 400 according to another embodiment includes at least one channel layer 410, a plurality of electrode layers 420, A plurality of ONO layers 430, and a plurality of interlayer insulating layers 440. However, the three-dimensional flash memory 400 differs from the three-dimensional flash memory described in FIG. 3 in that it includes at least one channel layer 410 formed in a stacked structure.

Specifically, each of the at least one channel layer 410 includes a first channel layer 411 formed to have a thickness less than a predetermined thickness, and a second channel 411 formed at a thickness greater than a predetermined thickness and surrounded by the first channel layer 411. [ Layer 412. < / RTI >

In this case, the first channel layer 411 may be formed of a Group 3-5 compound having a higher temperature resistance than the Group 3-5 compounds forming the second channel layer 412. For example, the first channel layer 411 may be formed of a Group 3-5 compound GaP including Ga and P, and the second channel layer 412 may be formed of a Group 3-5 compound GaAs including Ga and As , Ga, As, and P, which is a group III-V compound GaAsP. More specifically, the first channel layer 411 may be formed of a Group 3-5 compound of GaP having a temperature resistance between 800 ° C and 850 ° C, and the second channel layer 412 may be formed of a 600 ° C group of GaAs having a temperature resistance of C or a group 3-5 group of GaAsP. Here, the ratio (number of elements) of the Group 3-5 element (Ga, As, P) forming each of the first channel layer 411 and the second channel layer 412 can be adaptively adjusted , The number of As and the number of elements of P are controlled within 100 (in particular, 50), respectively).

Therefore, the first channel layer 411 has a higher temperature resistance than the second channel layer 412, and thus can serve as a protective layer for preventing the second channel layer 412 from being melted and deposited on the side surface.

The structure of each of the plurality of electrode layers 420, the plurality of ONO layers 430, and the plurality of interlayer insulating layers 440 includes a plurality of electrode layers included in the three-dimensional flash memory described with reference to FIG. 3, Layers and a plurality of interlayer insulating layers, respectively.

As described above, the three-dimensional flash memory 400 according to another embodiment includes at least one channel layer 410 formed to have a stack structure of the first channel layer 411 and the second channel layer 412 It is possible to increase the cell current and improve the threshold voltage dispersion of the plurality of electrode layers 420 while preventing the second channel layer 412 from melting and sideways deposition. Therefore, the reliability of the three-dimensional flash memory 400 can be further improved.

In addition, the three-dimensional flash memory 400 may have a structure for preventing at least one channel layer 410 from being melted and deposited on the upper portion. A detailed description thereof will be described with reference to Fig.

5 is a cross-sectional view illustrating a structure of a three-dimensional flash memory according to another embodiment of the present invention.

Referring to FIG. 5, a three-dimensional flash memory 500 according to another embodiment includes at least one channel layer 510, a plurality of electrode layers 520 A plurality of ONO layers 530, and a plurality of interlayer insulating layers 540. However, the three-dimensional flash memory 500 differs from the three-dimensional flash memory described in FIG. 3 in that it further includes at least one capping layer 550 covering the top of the at least one channel layer 510.

In detail, at least one capping layer 550 may be formed on the at least one channel layer 510 to cover the at least one channel layer 510 so that the channel layer 510 is not exposed to the outside. Accordingly, the at least one capping layer 550 may serve as a protective layer for preventing the at least one channel layer 510 from being melted and deposited on the upper portion.

Here, the at least one capping layer 550 may be formed of a conductive material (e.g., a Group 3-5 compound GaAs _x P _y including Ga, As, and P). In this case, the drain region in which the conductive pattern is formed to be connected to the bit line may be disposed on at least one capping layer 550. The at least one channel layer 510 may be connected to the bit line via at least one capping layer 550, which is a conductive material.

The structure of each of the plurality of electrode layers 520, the plurality of ONO layers 530, and the plurality of interlayer insulating layers 540 includes a plurality of electrode layers included in the three-dimensional flash memory described with reference to Fig. 3, Layers and a plurality of interlayer insulating layers, respectively.

As described above, the three-dimensional flash memory 500 according to another embodiment includes at least one capping layer 550 to improve the cell current and improve the threshold voltage dispersion of the plurality of electrode layers 520 At the same time, it is possible to prevent the at least one channel layer 510 from being melted and being deposited on the upper part. Therefore, the reliability of the three-dimensional flash memory 500 can be further improved.

Also, although not shown in the figure, at least one capping layer 550 may be applied to a three-dimensional flash memory having at least one channel layer of the stack structure described with reference to FIG. In this case, the three-dimensional flash memory can prevent both of the case where at least one channel layer is melted and deposited on the upper and side surfaces.

Hereinafter, with reference to Figs. 6 to 10, a method of manufacturing the three-dimensional flash memory shown in Figs. 3 to 5 will be described in detail. Hereinafter, the constituent parts of the three-dimensional flash memory are formed and created means that the constituent parts are made through various methods such as a chemical method or a physical method.

6 to 10 are cross-sectional views illustrating a method of fabricating a three-dimensional flash memory according to an embodiment.

6 to 10, a three-dimensional flash memory manufacturing apparatus according to an embodiment includes a substrate 610, a plurality of interlayer insulating layers 621 and a plurality of sacrificial layers 622 are alternately arranged The mold structure 620 is prepared.

Here, the substrate 610 may be at least one of materials having semiconductor properties, insulating materials, a semiconductor covered by an insulating material, or a conductor. For example, the substrate 610 may be a silicon wafer, and in such a case, a well region (not shown in the figure) in which an impurity of the first conductivity type is doped may be formed in the substrate 610.

The plurality of interlayer insulating layers 621 included in the mold structure 620 may be a silicon oxide film or a silicon nitride film and may have the same thickness or different from each other. Likewise, the plurality of sacrificial layers 622 included in the mold structure 620 may have the same thickness or different from each other. At this time, the plurality of sacrificial layers 622 may be formed of various materials having an etch selectivity ratio with respect to the plurality of interlayer insulating layers 621. Thus, in the process of etching the plurality of sacrificial layers 622, the etching of the plurality of interlayer insulating layers 621 is minimized, and only the plurality of sacrificial layers 622 can be selectively etched.

The number of stacked layers in which the plurality of interlayer insulating layers 621 and the plurality of sacrificial layers 622 are alternately arranged may be variously modified, and various methods such as a chemical vapor deposition method may be used have.

When the mold structure 620 is prepared on the substrate 610, the three-dimensional flash memory manufacturing apparatus creates at least one hole 710 through the mold structure 620 to expose the substrate 610. For example, the three-dimensional flash memory fabrication apparatus may include anisotropically etching a plurality of interlayer insulating layers 621 and a plurality of sacrificial layers 622 included in the mold structure 620 to expose an upper surface of the substrate 610 At least one hole 710 may be formed.

Next, the three-dimensional flash memory fabrication apparatus forms at least one channel layer 810 with at least one hole in the hole 710 as a group III-V compound containing at least one element of Ga, As, or P.

Here, the three-dimensional flash memory manufacturing apparatus has a temperature tolerance higher than a preset temperature, and has a higher mobility than the poly-Si or Si mobility used as a channel layer material in a conventional three-dimensional flash memory. The ratio can be adjusted to form at least one channel layer 810. For example, a three-dimensional flash memory manufacturing apparatus is a case where a group 3-5 compound forming at least one channel layer 810 is a single crystal compound. 3 at least one channel layer 810 is 700 ° C or more so as to have a temperature resistance and mobility than 1000cm ² / Vs by regulating the ratio of the group III-V elements such as As and P for Ga, such as GaAs _x P _y At least one channel layer 810 may be formed of a Group 5 compound. As another example, a three-dimensional flash memory manufacturing apparatus is a case where a group 3-5 compound forming at least one channel layer 810 is a polycrystalline compound. 3 at least one channel layer 810 is 700 ° C or more and temperature resistance so as to have at least 100cm ² / Vs and the mobility adjusting the ratio of the group III-V elements such as As and P for Ga, such as GaAs _x P _y At least one channel layer 810 may be formed of a Group 5 compound.

In addition, instead of forming at least one channel layer 810 so as to completely fill at least one hole 710, the three-dimensional flash memory device may be configured such that the inside of the at least one channel layer 810 is hollow tube- Can be formed. In this case, the three-dimensional flash memory fabrication apparatus can dispose the buried layer 820 in the at least one channel layer 810. However, at least one channel layer 810 may be formed so as to completely fill the at least one hole 710, without being limited thereto or limited thereto.

Also, the three-dimensional flash memory manufacturing apparatus may form at least one channel layer 810 in a stack structure. A detailed description thereof will be described with reference to Figs. 11A to 11B.

Although not shown in the drawing, when at least one channel layer 810 is formed in at least one hole 710, the three-dimensional flash memory manufacturing apparatus forms a vertical trench separating the mold structure 620 into a plurality of It is possible. Such a process can be performed in the case of manufacturing a three-dimensional flash memory corresponding to the electrode structure described with reference to FIG. 2, but it may be optionally omitted.

The three dimensional flash memory fabrication apparatus then removes the plurality of sacrificial layers 622 to form a plurality of trenches 910 extending vertically to the at least one channel layer 810. At this time, the three-dimensional flash memory manufacturing apparatus selectively removes only a plurality of sacrificial layers 622 among a plurality of interlayer insulating layers 621 and a plurality of sacrificial layers 622 included in the mold structure 620 Various methods can be used. For example, a three-dimensional flash memory manufacturing apparatus can selectively remove a plurality of sacrificial layers 622 by using an etching solution. This removal process may be performed until a plurality of trenches 910 are formed in which at least one channel layer 810 is exposed to the side.

Thereafter, the three-dimensional flash memory fabrication apparatus creates a plurality of ONO layers 1020 surrounding the plurality of electrode layers 1010 in the plurality of trenches 910, respectively. Here, each of the plurality of ONO layers 1020 may include a protective oxide film 1021 serving as a protection, a nitride film 1022 serving as a charge storage, and a tunnel oxide film 1023.

For example, the three-dimensional flash memory fabrication apparatus may previously prepare a plurality of ONO layers 1020 that are formed so as to surround each of the plurality of electrode layers 1010, and then a plurality of ONO layers (not shown) prepared in the plurality of trenches 910 1020 (which surround each of the plurality of electrode layers 1010).

In another example, a three-dimensional flash memory fabrication apparatus includes depositing a plurality of ONO layers 1020 in a plurality of trenches 910, respectively, and forming a plurality of electrode layers 1010 on the plurality of ONO layers 1020 You may. A detailed description thereof will be described with reference to Figs. 12A to 12B.

11A to 11B are cross-sectional views for explaining another embodiment of the process of forming the channel layer shown in FIG.

11A to 11B, a three-dimensional flash memory manufacturing apparatus includes a first channel layer 1130 having a predetermined thickness less than a preset thickness in at least one hole 1120 formed in a mold structure 1110, By forming the channel layer 1140 in order, at least one channel layer 1130 and 1140 can be formed.

Specifically, the 3D flash memory fabrication apparatus conformally deposits a first channel layer 1130 with a Group III-V compound containing Ga and P along at least one hole 1120, The second channel layer 1140 may be deposited on the first channel layer 1130 with a Group 3-5 compound including Ga and As, or a Group 3-5 compound including Ga, As, and P. [

In this case, the 3D flash memory device may form the first channel layer 1130 with a group III-V compound having a temperature resistance higher than that of the group III-V compound forming the second channel layer 1140.

That is, the three-dimensional flash memory manufacturing apparatus forms the first channel layer 1130 by adjusting the ratio of the Group 3-5 elements so as to have a temperature tolerance of a predetermined temperature or more, The second channel layer 1140 may be formed by adjusting the ratio of the Group 3-5 elements so as to have higher mobility than the mobility of Poly-Si or Si used. Accordingly, the first channel layer 1130 can prevent the second channel layer 1140 from being melted and deposited on the side surface.

Similarly, the three-dimensional flash memory fabrication apparatus may be configured such that the second channel layer 1140 has a hollow tube shape inside the second channel layer 1140, instead of filling the at least one hole 1120 completely. . In this case, the three-dimensional flash memory device may dispose the buried layer 1150 in the second channel layer 1140. However, the second channel layer 1140 may be formed so as to completely fill the at least one hole 1120 without limitation or limitation.

12A to 12B are cross-sectional views for specifically illustrating a process of generating a plurality of ONO layers shown in FIG.

12A to 12B, a three-dimensional flash memory manufacturing apparatus conformally deposits a tunnel oxide film 1220, a nitride film 1230, and a protective oxide film 1240 sequentially in conformity with a plurality of trenches 1210, A plurality of ONO layers 1250 may be deposited within the plurality of trenches 1210, respectively.

Next, the three-dimensional flash memory device may form a plurality of electrode layers 1260 with a conductive material on the plurality of ONO layers 1250, respectively. At this time, the three-dimensional flash memory fabrication apparatus may form a plurality of electrode layers 1260 such that a plurality of ONO layers 1250 completely fill the plurality of deposited trenches 1210, respectively.

FIG. 13 is a cross-sectional view illustrating a process of forming at least one capping layer in the method of manufacturing the three-dimensional flash memory shown in FIGS. 6 to 10. FIG.

13, the apparatus for fabricating a three-dimensional flash memory further comprises at least one capping layer 1320 covering at least one channel layer 1310 so as to cover at least one channel layer 1310 without being exposed to the outside, Or may be formed of a conductive material.

Here, it is described that the three-dimensional flash memory manufacturing apparatus forms at least one capping layer 1320 after the process of generating the plurality of ONO layers described with reference to FIG. 10, but is not limited thereto, After forming the at least one channel layer 1310 as described above, at least one capping layer 1320 may be formed immediately after the step of forming the plurality of trenches described with reference to FIG. 9, (1320).

The at least one capping layer 1320 may prevent the at least one channel layer 1310 from being melted and deposited on the top.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (14)

In a three-dimensional flash memory for increasing cell current,
At least one channel layer formed of a Group 3-5 compound including Ga, As, and P;
A plurality of electrode layers vertically stacked on the at least one channel layer;
A plurality of ONO (Oxide-Nitride-Oxide) layers formed to connect between the plurality of electrode layers and the at least one channel layer; And
A plurality of interlayer insulating layers connected to the at least one channel layer and alternately arranged with the plurality of electrode layers, the interlayer insulating layers vertically stacked on the at least one channel layer,
/ RTI >
The ratio of Ga, As, and P contained in the 3-5 group compound
And is adjusted to have a temperature tolerance of a predetermined temperature or higher and a mobility higher than the mobility of Poly-Si or Si. The method according to claim 1,
The ratio of Ga, As, and P contained in the 3-5 group compound
When the Group 3-5 compound is a single crystal compound, it is adjusted to have a temperature resistance of 700 ° C or higher and a mobility of 1000 cm ² / Vs or more. When the Group 3-5 compound is a polycrystalline compound, And a mobility of 100 cm ² / Vs or more. The method according to claim 1,
Each of the at least one channel layer
A first channel layer formed below a predetermined thickness; And
The second channel layer being surrounded by the first channel layer,
/ RTI >
The first channel layer
Group compound having a temperature resistance higher than that of the 3-5 group compound forming the second channel layer. The method of claim 3,
The first channel layer
Ga, and P,
The second channel layer
Group 3 to 5 compounds including Ga and As or Group 3 to 5 compounds including Ga, As, and P. The method according to claim 1,
At least one capping layer covering the top of the at least one channel layer so that the at least one channel layer is not exposed to the outside,
Dimensional flash memory. 6. The method of claim 5,
The at least one capping layer
A three-dimensional flash memory, formed from a conductor. In a three-dimensional flash memory for increasing cell current,
At least one channel layer formed of a Group 3-5 compound;
A plurality of electrode layers vertically stacked on the at least one channel layer;
A plurality of ONO (Oxide-Nitride-Oxide) layers formed to connect between the plurality of electrode layers and the at least one channel layer; And
A plurality of interlayer insulating layers connected to the at least one channel layer and alternately arranged with the plurality of electrode layers, the interlayer insulating layers vertically stacked on the at least one channel layer,
/ RTI >
The ratio of the Group 3-5 elements contained in the 3-5 group compound
And is adjusted to have a temperature tolerance of a predetermined temperature or higher and a mobility higher than the mobility of Poly-Si or Si. In a three-dimensional flash memory for increasing cell current,
At least one channel layer formed of a Group 3-5 compound including Ga, As, and P;
A plurality of electrode layers vertically stacked on the at least one channel layer;
A plurality of ONO (Oxide-Nitride-Oxide) layers formed to connect between the plurality of electrode layers and the at least one channel layer;
A plurality of interlayer insulating layers connected to the at least one channel layer and alternately arranged with the plurality of electrode layers, the interlayer insulating layers vertically stacked on the at least one channel layer; And
At least one capping layer covering the top of the at least one channel layer so that the at least one channel layer is not exposed to the outside,
/ RTI >
The ratio of Ga, As, and P contained in the 3-5 group compound
And is adjusted to have a temperature tolerance of a predetermined temperature or higher and a mobility higher than the mobility of Poly-Si or Si. A method of manufacturing a three-dimensional flash memory for increasing a cell current,
Preparing a mold structure on a substrate, in which a plurality of interlayer insulating layers and a plurality of sacrificial layers are alternately arranged;
Creating at least one hole through the mold structure to expose the substrate;
Forming at least one channel layer of a Group 3-5 compound comprising Ga, As and P in the at least one hole;
Removing the plurality of sacrificial layers to form a plurality of vertically extending trenches with respect to the at least one channel layer; And
Forming a plurality of ONO (Oxide-Nitride-Oxide) layers in the plurality of trenches, each of the plurality of ONO layers surrounding the plurality of electrode layers
Lt; / RTI >
The ratio of Ga, As, and P contained in the 3-5 group compound
The temperature resistance being higher than a predetermined temperature, and the mobility being higher than the mobility of Poly-Si or Si. 10. The method of claim 9,
The ratio of Ga, As, and P contained in the 3-5 group compound
When the Group 3-5 compound is a single crystal compound, it is adjusted to have a temperature resistance of 700 ° C or higher and a mobility of 1000 cm ² / Vs or more. When the Group 3-5 compound is a polycrystalline compound, And a mobility of 100 cm ² / Vs or more. 10. The method of claim 9,
The step of forming at least one channel layer as a Group 3-5 compound in the at least one hole
Forming sequentially a first channel layer below a predetermined thickness and a second channel layer above a predetermined thickness in each of said at least one hole,
Lt; / RTI >
The first channel layer
Group compound having a temperature resistance higher than that of the 3-5 group compound forming the second channel layer. 12. The method of claim 11,
The step of sequentially forming a first channel layer below a predetermined thickness and a second channel layer above a predetermined thickness in said at least one hole,
Group compound comprising Ga and P, forming a first channel layer with a Group 3-5 compound including Ga and P, forming a Group 3-5 compound including Ga and As or a Group 3-5 compound including Ga, As, and P, Forming a channel layer
Dimensional flash memory. 10. The method of claim 9,
Forming at least one capping layer in the conductor to cover the top of the at least one channel layer so that the at least one channel layer is not exposed to the outside
Dimensional flash memory. 10. The method of claim 9,
Wherein creating a plurality of ONO layers within each of the plurality of trenches, each of the plurality of ONO layers surrounding the plurality of electrode layers
Depositing a plurality of ONO layers, respectively, in the plurality of trenches; And
Forming the plurality of electrode layers in the plurality of trenches in which the plurality of ONO layers are respectively deposited,
Dimensional flash memory.

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