CN108649033A - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
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- CN108649033A CN108649033A CN201810231866.1A CN201810231866A CN108649033A CN 108649033 A CN108649033 A CN 108649033A CN 201810231866 A CN201810231866 A CN 201810231866A CN 108649033 A CN108649033 A CN 108649033A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
The invention discloses a kind of semiconductor devices, including:Substrate；Conductor/insulation body lamination, setting is on substrate, it is alternately stacked and is constituted along first direction by conductive layer and insulating layer, including core space arranged side by side in a second direction and stepped region, core space is constant along the thickness of the first direction, and stepped region is successively decreased along the thickness of first direction with increase of the core space at a distance from second direction；First direction is perpendicular to the direction of substrate surface, and second direction is to be parallel to the direction of the substrate surface；Multiple storage channel regions, the core space of conductor/insulation body lamination is extended vertically through along first direction；Multiple illusory channel regions, the stepped region of conductor/insulation body lamination is extended vertically through along first direction, with substrate contact；Multiple illusory channel regions are made of insulating materials.The present invention is etched using mask, fills core space and stepped region respectively, is avoided stepped region bottom epitaxial layer growth defect, is improved the reliability of device.
Description
Technical field
The present invention relates to a kind of semiconductor devices and its manufacturing methods, more particularly to a kind of three-dimensional NAND gate memory list
First transistor and its manufacturing method.
Background technology
In order to improve the density of memory device, industry is dedicated to the memory cell that research and development reduce two-dimensional arrangement extensively
Size method.With the memory cell dimensions continual reductions of two-dimentional (2D) memory device, signal conflict and interference can be shown
It writes and increases, so that being difficult to carry out multi-level-cell (MLC) operation.In order to overcome the limitation of 2D memory devices, industry to grind
The memory device with three-dimensional (3D) structure has been sent out, it is integrated to improve by the way that memory cell is three-dimensionally disposed in substrate
Density.
Sectional view in the manufacturing process of typical 3D NAND device structures is as shown in Fig. 1 a~Fig. 1 d, in usually Si
Substrate (corresponding respectively to core space 1C and illusory (dummy) area 1D) on be preferably formed as separation layer 1s (such as silica),
Deposit multiple dielectric layers on separation layer 1s and stack the laminated construction constituted, for example, the first layer 2A of nitride and oxide the
Two layers of alternate structures of 2B, and preferably, an oxide skin(coating) 2B thickness of bottommost is larger to drive crystal to improve bottom
It is dielectrically separated from effect between pipe and top NAND transistor string.Wherein, the transistor in the core space 1C of memory array
Contained subelement number is more in string therefore layer 2A/2B cycle stackings number is more, and stepped region 1D neutron cells number compared with
Less and super peripheral region is gradually reduced to 0 therefore layer 2A/2B number of cycles gradually decreases so that the lamination knot in the 1D of stepped region
There are step-like distributions shown in Fig. 1 a by structure 2A/2B.Protection/passivation layer of deposition oxide or low-k materials on entire device
3, such as TEOS is silica (referred to as TEOS) prepared by raw material.Preferably, protective layer 3 includes multiple sublayer (not shown),
Such as comparatively dense TEOS prepared by bottom HDPCVD techniques covers entire dielectric layer stacking 2A/2B, it is prepared by middle part LPCVD techniques
The comparatively dense PECVD of more loose TEOS and the top silica, silicon nitride or the silicon oxynitride that prepare.
As shown in the mask vertical view of Fig. 1 b and the cross-sectional device views of Fig. 1 c, for core space and stepped region using different
Mask graph, such as respectively 3C and 3D etch multi-layer laminate structure 2A/2B on substrate by anisotropic etching technics
And it is formed along the distribution of memory cell wordline (WL) extending direction, perpendicular to multiple raceway groove through-holes of substrate surface, including core
Heart district raceway groove hole 3HC and stepped region raceway groove hole 3HD (can go directly substrate surface or have certain over etching).
As shown in Figure 1 d, in order to improve the film quality of follow-up institute's deposited vertical raceway groove, while in order to improve bottom driving
The driving capability of transistor, it usually needs in the boss (or silicon island) of raceway groove hole bottom epitaxial growth monocrystal material, be included in core
The boss 1EC of the heart district and boss 1ED in stepped region.In the process, in order to improve the drive of core space bottom selection transistor
The top of kinetic force while the charge storage for further increasing transistor in NAND transistor string, core space boss 1EC is excellent
Selection of land be more than bottom first medium layer 2A (such as nitride) top and continue more than bottom second dielectric layer 2B (such as
Oxide) height at least 1/3 at, preferably flushed in the middle part of the second dielectric layer 2B of bottom.And in the stepped region 1D of periphery
In, the good gate insulator of quality of forming film is formed around the boss 1ED of stepped region later in order to ensure to remove first medium layer 2A
For layer to be dielectrically separated from grid conducting layer, prevent from leaking electricity, the top of boss 1ED at least should be with the tops bottom first medium layer 2A
(or bottom bottoms second dielectric layer 2B) flush and preferably more than so as core space 1EC.
Then continue to form vertical furrow channel layer and preferably raceway groove filled layer in raceway groove hole based on boss, then
The deep hole that exposure substrate and lamination 2A/2B side walls is formed in region between adjacent raceway groove hole, utilizes deep hole sideetching
First layer or the second layer leave lateral recesses and retain another in removal laminated construction, aoxidize or deposit in lateral recesses
Gate insulating layer (can include multiple sublayers, such as ONO, to improve charge storage) is formed, then deposited metal or is mixed
Miscellaneous polysilicon forms grid conducting layer.Base semiconductor boss 1EC and the gate stack of its side form bottom selection as a result,
Transistor, and vertical furrow channel layer and the gate stack of its side form NAND transistor string, the dielectric layer 2B left is as phase
Dielectric isolation layer between adjacent transistor.
However, as shown in Figure 1 d, during actually etching removal first medium layer 2A, with illusory storage channel region 1D
With the increase of core space 1C distances, strings of transistors neutron cells number is reduced, and the stacking number of layer 2A/2B is reduced, therefore first
The number of dielectric layer 2A is also accordingly reduced namely dielectric layer stacks the distance apart from top device and increases and highly reduce.And it carves
It loses agent and 2A/2B is stacked far above dielectric layer for the etching speed of protective layer 3.In identical etch period, with core space 1C
It compares, etching agent will faster pierce through the protection layer 3 and dielectric layer stack 2A/2B and reach substrate in the 1D of stepped region so that substrate
It is final so that the raceway groove hole 3HD depth of stepped region 1D is more than the raceway groove hole 3HC depth of core space 1C by over etching in advance.
During epitaxial semiconductor boss 1EC/1ED later, under identical deposition process conditions, core space
Boss 1EC height in (and close to part stepped region of core space) can still meet the tops at least above bottom first medium layer 2A
The requirement in portion.But in the part stepped region far from core space (left side in Fig. 1 d), since substrate over etching amount increases, deposition
The semiconductor layer of growth is not enough to reach above-mentioned requirements so that follow-up removal layer 2A is formed during gate stack, gate dielectric
Layer is not enough to the gap being fully filled between boss 1ED and second dielectric layer 2B, and grid conducting layer is possible to be in direct contact, be electrically connected
Boss 1ED is met, component failure is caused.
Further, since etching agent penetrates dielectric stack 2A/2B earlier in stepped region reaches substrate, complete to etch in core space
Before, more etching agents will carry out transversal erosion to dielectric stack, this leads to stepped region raceway groove hole 3HD side walls, and there are large number of orifices
Film quality will be influenced when hole defect, subsequent epitaxial boss or vertical furrow channel layer, device reliability declines.
Invention content
Therefore, it is an object of the invention to overcome drawbacks described above, the reliability of device is improved.
For this purpose, the present invention provides a kind of semiconductor devices, including:
Substrate；
Conductor/insulation body lamination, setting over the substrate, structure are alternately stacked by conductive layer and insulating layer along first direction
At, including core space arranged side by side in a second direction and stepped region, the core space is constant along the thickness of the first direction,
Successively decrease with increase of the core space at a distance from second direction along the thickness of the first direction stepped region；Institute
It is perpendicular to the direction of the substrate surface to state first direction, and the second direction is to be parallel to the direction of the substrate surface；
Multiple storage channel regions extend vertically through the core space of the conductor/insulation body lamination along the first direction；
Multiple illusory channel regions extend vertically through the stepped region of the conductor/insulation body lamination along the first direction, with institute
State substrate contact；The multiple illusory channel region is made of insulating materials.
Wherein, each the bottom of storage channel region has lifting epitaxial layer.
Wherein, the top of epitaxial layer is lifted at least at the 1/3 of bottom medium layer height.
Further comprise, protective layer, covers core space and the stepped region of the conductor/insulation body lamination.
The present invention also provides a kind of method, semi-conductor device manufacturing methods, including：
Multiple first medium layers being alternately stacked along first direction and second dielectric layer are formed on substrate, constitute bunch media
Layer, the dielectric stack include core space and stepped region arranged side by side in a second direction；The core space is along first direction
Thickness is constant, and the stepped region is passed along the thickness of first direction with increase of the core space at a distance from second direction
Subtract；The first direction is perpendicular to the direction of the substrate surface, and the second direction is to be parallel to the substrate surface
Direction；
Using the first photoetching offset plate figure, etch media lamination forms multiple raceway grooves of exposed substrate in device core area
Hole；
Storage channel region is formed in multiple raceway groove holes；
Using the second photoetching offset plate figure, etch media lamination forms multiple trepannings of exposed substrate in device stepped region；
Fill insulant forms illusory channel region in multiple trepannings.
Wherein, further comprise before forming storage channel region, lifting epitaxial layer is formed in multiple raceway groove holes bottom.
Wherein, it forms dielectric stack later to further comprise, forms protective layer in dielectric stack.
Wherein, the step of forming storage channel region includes that deposited semiconductor material fills multiple raceway groove holes and planarization process
Until exposure protective layer；And/or the step of forming insulating layer includes that deposition of insulative material fills multiple trepannings and planarization process
Until exposure protective layer.
Wherein, storage channel region includes gate insulator stacking, semiconductor channel layer, raceway groove filled layer.
According to the semiconductor devices and its manufacturing method of the present invention, is etched respectively using mask, fills core space and step
Area avoids stepped region bottom epitaxial layer growth defect, improves the reliability of device.
Purpose of the present invention, and other purposes unlisted herein, in the range of the application independent claims
It is satisfied.The embodiment of the present invention limits in the independent claim, and specific features limit in dependent claims thereto.
Description of the drawings
Carry out the technical solution that the present invention will be described in detail referring to the drawings, wherein：
Fig. 1 a to Fig. 1 d show the schematic diagram of prior art 3D memory process；
Fig. 2 a to Fig. 2 f show the sectional view of process for fabrication of semiconductor device according to the ... of the embodiment of the present invention；And
Fig. 3 shows the flow chart of manufacturing method according to the ... of the embodiment of the present invention.
Specific implementation mode
Come the feature and its skill of the present invention will be described in detail technical solution referring to the drawings and in conjunction with schematical embodiment
Art effect discloses the semiconductor devices and its manufacturing method that can effectively improve 3D nand memory part reliabilities.It may be noted that
, similar reference numeral indicates similar structure, term use herein " first ", " second ", "upper", "lower" etc.
Etc. can be used for modifying various device architectures.These modifications do not imply that the space, secondary of modified device architecture unless stated otherwise
Sequence or hierarchical relationship.
As shown in Figure 2 a, substrate 10 is provided, material may include body silicon (bulk Si), body germanium (bulk Ge), insulation
Silicon (SOI), germanium on insulator (GeOI) or other compound semiconductor substrates on body, such as SiGe, Si:C、SIGeC、
The combination of GaN, GaAs, InP etc. and these substances.In order to compatible with existing IC manufacturing process, substrate is preferably to contain
The substrate of silicon material, such as Si, SOI, SiGe, Si:C, SiGeC etc..Substrate includes the core space 10C corresponding to semiconductor devices
Part, and the part corresponding to semiconductor devices stepped region 10D.Preferably, pass through LPCVD, PECVD etc. on substrate 10
Technique forms the separation layer 10s for for example aoxidizing silicon material.
Using including LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering, thermal oxide, chemistry
The common process such as oxidation, sequentially form first medium layer 20A and alternately stacked Jie of second dielectric layer 20B on separation layer 10s
Matter layer heap is folded.The material of layer 20A and layer 20B is mutually different to provide larger Etch selectivity, such as selected from silica, nitridation
Silicon, silicon oxynitride, carbon dope silicon nitride, fluorine doped silicon nitride, carbon doped silicon oxide, fluorine-doped silica, amorphous carbon, diamond-like are amorphous
Either one or two of carbon (DLC), germanium oxide, aluminium oxide, aluminium nitride or combinations thereof.In a preferred embodiment of the invention, first is situated between
Matter layer 20A is silicon nitride, and second dielectric layer 20B is silica.In another preferred embodiment of the present invention, the second of bottommost is situated between
Matter layer 20B thickness is more than remaining second dielectric layer 20B (not shown), is also further more than every other first medium layer 20A,
To realize that bottom selection transistor and the good insulation of upper unit strings of transistors are isolated.In some embodiments, medium layer heap
It is step-like to be stacked in device stepped region 10D, and stepped region height reduces with the increase of distance between core space until subtracting
As low as 0.
Using techniques such as CVD, spin coating, spraying, silk-screen printings, protective layer 30 is formed on entire device, material is oxidation
Silicon (B, P, C, F etc., such as TEOS silica can be adulterated) or low-k materials.Wherein low-k materials include but not limited to organic low k materials
Expect (such as organic polymer containing aryl or polynary ring), inorganic low-k material (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen
Film, fluorine silica glass, BSG, PSG, BPSG), porous low k material it is (such as Quito hole two silicon three oxygen alkane (SSQ) low-k materials, porous
Silica, porous SiOCH, it mixes C silica, mix the porous amorphous carbon of F, porous diamond, porous organic polymer).
Photoetching offset plate figure 31P is formed on protective layer 30, only exposes the protective layer 30 of core space.Photoetching offset plate figure 31P classes
Fig. 1 b right part 3C are similar to, are the array of multiple opening figures.Shape in a top view can be rectangle, rectangular, diamond shape,
The various geometries of circle, semicircle, ellipse, triangle, pentagon, pentagon, hexagon, octagon etc..
As shown in Figure 2 b, using photoetching offset plate figure 31P as mask, be sequentially etched protective layer 30, dielectric layer stack 20A/20B,
Separation layer 10s forms the trepanning that multiple raceway groove hole 30HC (being referred to as core space raceway groove hole) of the substrate of exposure core space 10C are constituted
Array.It is preferred that using anisotropic etch process, such as (use CxHyFzEqual fluorohydrocarbons etching gas or SF6、NF3、Cl2、
Carbon-free etching gas such as HBr) anisotropic dry etch process such as dry plasma etch or reactive ion etching.It is preferred that
Ground executes micro over etching, such as gos deep into substrate surface 0.2 to 1nm, to ensure to completely remove the various defect examples of substrate surface
Such as native oxide, crack, contaminant particle.It is further preferred that using wet corrosion technique (such as TMAH is directed to Si)
Etched substrate surface forms multiple periodical micro-pits or microprotrusion (not shown) for use as follow-up CVD deposition or epitaxial growth
Nucleation structure further increases film growth quality.
As shown in Figure 2 c, in core space 10C, the selective epitaxial growth on the substrate that the raceway groove hole bottoms 30HC are exposed
Semiconductor epitaxial layers (or making boss) 10EC.Growth technique such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE,
The techniques such as ALD, and conformality and the good depositing operation of step coverage preferably wherein.Semiconductor layer 10EC materials can be with
Substrate 10C is identical or different, for example, silicon, Zhe Deng IV races simple substance, can also be selected from IV races, iii-v or II-VI group compound
Semiconductor, such as SiGe, Si:C、SiGe:C, Ge, GeSn, InSn, InN, InP, GaN, GaP, GaSn, GaAs etc. and combinations thereof.
Preferably, semiconductor layer 10EC materials apply stress to be mismatched using lattice with substrate difference to storage channel region, to
Improve the driving capability of selection transistor.Preferably, Direct precipitation semiconductor layer 10EC is mono-crystalline structures to improve the following boss
Quality of forming film, or with film formation at low temp technique formed polycrystal layer and then laser short annealing make illuminated region (example
Such as raceway groove hole bottom) it recrystallizes as the larger polycrystalline structure of local monocrystalline or domain to mistake during avoiding monocrystalline from forming a film
High technology temperature brings heat budget problem for having other devices on chip.Preferably, using wet etching or oxygen etc. from
Daughter dry etching (ashing) technique removes photoetching offset plate figure 31P.
As shown in Figure 2 d, vertical storage channel region is formed in core space raceway groove hole 30HC.Optionally, using HDPCVD,
The depositing operation of the good shape retentions such as MOCVD, UHVCVD, MBE, ALD forms gate insulator layer heap on the 30HC side walls of raceway groove hole
Folded (being not shown, then etching bottom exposes epitaxial layer 10EC to first uniform deposition), such as deposited including boundary layer, barrier layer, charge
Reservoir, tunnel layer and combinations thereof, for improving memory transistor performance.The material of gate insulator stack can be silica
(by controlling different deposition process parameters and thickness, different functions may be implemented), silicon nitride or other high-g values.High k materials
Material includes but not limited to be selected from HfO2、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOx's
Hafnium sill, or including being selected from ZrO2、La2O3、LaAlO3、Ta2O5、TiO2、Y2O3、CeO2Rare-earth-based high K dielectric material,
Or including SiN, AlSiN, AlN, Al2O3, with the composite layer of its above-mentioned material.In a preferred embodiment of the invention, grid
Stacked dielectric layer is ONO (oxide-nitride-oxide) laminated construction.Channel region is stored then, with epitaxial layer boss 10EC
Based on, selective epitaxial growth vertical furrow channel layer 40CC.Channel layer 40CC materials are preferably identical as epitaxial layer 10EC or phase
Closely (lattice constant is close, and difference is less than or equal to 15%), such as be also selected from silicon, Zhe Deng IV races simple substance, can also be selected from IV races,
Iii-v or II-VI group compound semiconductor, such as SiGe, Si:C、SiGe:C、Ge、GeSn、InSn、InN、InP、GaN、
GaP, GaSn, GaAs etc. and combinations thereof.Preferably, growth of vertical channel layer 40CC is carried out at the same time doping in situ, to provide or change
Become channel layer conduction type.In some embodiments of the invention, gate insulator stack not formed vertical furrow channel layer it
Preceding formation, but leave to deposit in lateral recesses after subsequent etching removal first medium layer 20A and be formed.It is excellent in the present invention one
It selects in embodiment, epitaxial layer 40CC is not completely filled with core space raceway groove hole 30HC, but then deposition of insulative material or filling
Inert gas (top have is dielectrically separated from plug) and form channel isolation layer 40FC.Then, using CMP, be etched back to etc. it is flat
Change process, until exposure protective layer 30.
As shown in Figure 2 e, using the second photoetching offset plate figure 32P, the dielectric layer etched in the 10D of stepped region stacks 20A/20B,
Form the multiple stepped region deep holes or opening 30HD of exposure substrate.Core space is completely covered in second photoetching offset plate figure 32P, only in platform
Rank area leaves similar to the array that multiple openings are constituted shown in Fig. 1 b left areas 3D.Etching technics is similar to shown in Fig. 2 b
Technique, preferably anisotropic dry etch.Preferably, etch close near deep hole bottom (such as reach last 3 or 5 Jie
Matter layer 2A/2B assembled units) when, it reduces the content of etching gas, increases oxidizing gas (such as O2、O3、H2O or COS) with
Deep hole side wall forms silica base cushion, the adhesion strength for improving follow-up fill insulant.
As shown in figure 2f, the fill insulant in the deep hole 30HD of stepped region forms insulation fill stratum 50.Depositing operation is excellent
The excellent shape retention properties such as ALD, MBE and the good technique of quality of forming film are selected, thermal oxidation technology can also be used.Insulating materials 50 is, for example,
Silica based materials, including but not limited to SiO2、SiON、SiOC、SiOF、Si(OCH)x, BSG (mixing B silica glass), PSG (mix P silicon
Glass), BPSG (mixing B, P silica glass) etc..Then, using the techniques planarization process insulating materials such as CMP, until exposure protective layer
30。
Then, carry out subsequent technique (subsequent drawings are not shown).For example, the dielectric layer between etching vertical storage channel region
The deep hole for forming exposure substrate and dielectric layer side wall is stacked, is left using deep hole isotropic etching removal first medium layer 20A
Lateral recesses.It injects to form common source area in deep hole bottom.Using techniques such as thermal oxide, chemical oxidation, CVD depositions, laterally recessed
The gate insulating layer of silica or high-g value is conformally formed in falling into.Then, using depositions such as MOCVD, MBE, ALD, HDPCVD
Technique, in lateral recesses remainder fill grid conducting layer, material can be polysilicon, poly-SiGe or metal, wherein
Metal may include the metal simple-substances such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La,
Or the alloy of these metals and the conductive nitride or conductive oxide of these metals, it can also be doped with C, F, N, O, B, P, As
Equal elements are to adjust work function.Further preferably pass through the conventional methods such as PVD, CVD, ALD between grid conducting layer and gate insulating layer
The barrier layer (not shown) of nitride is formed, barrier layer material is MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNz, wherein M be Ta,
Ti, Hf, Zr, Mo, W or other element.Then drain region is formed at the top of storage channel region 40CC.
Finally formed semiconductor devices includes：Multiple storage channel regions of vertical substrates distribution, are located at device core area
It is interior；Multiple gate stacks and multiple dielectric layers (second dielectric layer left) between neighboring gates stacking, with storage ditch
Road area is orthogonal and horizontal distribution；Multiple illusory channel regions of vertical substrates distribution, are located in device stepped region, penetrate multiple grids
It stacks and multiple dielectric layers is until substrate.Wherein, each the bottom of storage channel region has semiconductor boss.Preferably, it partly leads
The top of body boss is at least at the 1/3 of bottom medium layer height.Wherein, also there is protective layer in entire top device.
Remaining structure, layout and the material selection of semiconductor devices, as before described in manufacturing method, details are not described herein.
According to the semiconductor devices and its manufacturing method of the present invention, is etched respectively using mask, fills core space and step
Area avoids stepped region bottom epitaxial layer growth defect, improves the reliability of device.
Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art, which could be aware that, to be not necessarily to
It is detached from the scope of the invention and various suitable changes and equivalents is made to device architecture.In addition, can by disclosed introduction
The modification of particular condition or material can be can be adapted to without departing from the scope of the invention by making many.Therefore, the purpose of the present invention does not exist
In being limited to as the preferred forms for realizing the present invention and disclosed specific embodiment, and disclosed device architecture
And its manufacturing method is by all embodiments including falling within the scope of the present invention.
Claims (10)
1. a kind of semiconductor devices, including:
Substrate；
Conductor/insulation body lamination, setting over the substrate, are alternately stacked along first direction by conductive layer and insulating layer and are constituted,
Including core space arranged side by side in a second direction and stepped region, the core space is constant along the thickness of the first direction, institute
The thickness that stepped region is stated along the first direction successively decreases with increase of the core space at a distance from second direction；It is described
First direction is perpendicular to the direction of the substrate surface, and the second direction is to be parallel to the direction of the substrate surface；
Multiple storage channel regions extend vertically through the core space of the conductor/insulation body lamination along the first direction；
Multiple illusory channel regions extend vertically through the stepped region of the conductor/insulation body lamination along the first direction, with the lining
Bottom contacts；The multiple illusory channel region is made of insulating materials.
2. semiconductor devices as described in claim 1, wherein the bottom of each storage channel region has lifting epitaxial layer.
3. semiconductor devices as claimed in claim 2, wherein be lifted the top of epitaxial layer at least over bottom medium floor height
At the 1/3 of degree.
4. semiconductor devices as described in claim 1, further comprises, protective layer, the conductor/insulation body lamination is covered
Core space and stepped region.
5. a kind of method, semi-conductor device manufacturing method, including：
Multiple first medium layers being alternately stacked along first direction and second dielectric layer are formed on substrate, constitute dielectric stack,
The dielectric stack includes core space and stepped region arranged side by side in a second direction；Thickness of the core space along first direction
Constant, the stepped region is successively decreased along the thickness of first direction with increase of the core space at a distance from second direction；
The first direction is perpendicular to the direction of the substrate surface, and the second direction is to be parallel to the side of the substrate surface
To；
Using the first photoetching offset plate figure, etch media lamination forms multiple raceway groove holes of exposed substrate in device core area；
Storage channel region is formed in multiple raceway groove holes；
Using the second photoetching offset plate figure, etch media lamination forms multiple trepannings of exposed substrate in device stepped region；
Fill insulant forms illusory channel region in multiple trepannings.
6. method, semi-conductor device manufacturing method as claimed in claim 5, wherein further comprise before forming storage channel region,
Corrode substrate to form periodic patterns and/or execute over etching.
7. method, semi-conductor device manufacturing method as claimed in claim 5, wherein further comprise before forming storage channel region,
Lifting epitaxial layer is formed in multiple raceway groove holes bottom.
8. method, semi-conductor device manufacturing method as claimed in claim 5, wherein it forms dielectric stack and further comprises later,
Protective layer is formed in dielectric stack.
9. method, semi-conductor device manufacturing method as claimed in claim 8, wherein the step of forming storage channel region includes deposition half
Conductor material fills multiple raceway groove holes and planarization process until exposure protective layer；And/or the step of forming insulating layer includes heavy
Product insulating materials fills multiple trepannings and planarization process until exposure protective layer.
10. method, semi-conductor device manufacturing method as claimed in claim 5, wherein storage channel region includes that gate insulator stacks, partly
Conductor channel layer, raceway groove filled layer.
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| CN109192735A (en) * | 2018-10-15 | 2019-01-11 | 长江存储科技有限责任公司 | 3D memory device and its manufacturing method |
| CN109690774A (en) * | 2018-12-07 | 2019-04-26 | 长江存储科技有限责任公司 | Hierarchic structure and contact structures for three-dimensional storage |
| CN109742080A (en) * | 2018-12-03 | 2019-05-10 | 长江存储科技有限责任公司 | A kind of three-dimensional storage and preparation method thereof |
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