CN107799531A - A kind of 3D nand memories grade layer stack manufacture method - Google Patents
A kind of 3D nand memories grade layer stack manufacture method Download PDFInfo
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- CN107799531A CN107799531A CN201711140523.6A CN201711140523A CN107799531A CN 107799531 A CN107799531 A CN 107799531A CN 201711140523 A CN201711140523 A CN 201711140523A CN 107799531 A CN107799531 A CN 107799531A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
The present invention relates to a kind of 3D nand memories grade layer stack manufacture method, methods described comprises the following steps：Oxide/nitride grade layer stack is formed on a silicon substrate, then forms the gate line slit for extending vertically through the oxide/nitride grade layer stack；The nitride layer in oxide/nitride grade layer stack is removed, forms sunk area；The sunk area is etched back using hydrofluoric acid so that the oxide layer surface planarization in the oxide/nitride grade layer stack；Conductor material is inserted in the sunk area, conductor layer is formed and etches the conductor layer, form conductor/insulation body grade layer stack.The 3D nand memory grade layer stack manufacture methods of the present invention, big header structure is etched back by using hydrofluoric acid (HF), oxide skin(coating) major part phenomenon can be eliminated, so as to improve the filling rate of conductor layer in 3D NAND grade layer stacks, and then improves device performance.
Description
Technical field
The present invention relates to a kind of 3D nand memories grade layer stack manufacture method, is related to 3D nand memories manufacture skill
Art field.
Background technology
With the development of semiconductor technology, it is proposed that various semiconductor storage units.Relative to conventional memory devices such as magnetic
Memory device, semiconductor storage unit have the advantages that access speed is fast, storage density is high.Among this, NAND structures just by
Increasing concern.For further lifting storage density, there are a variety of three-dimensional (3D) NAND devices.
As shown in figs. 1 a-c, it is prior art 3D nand memory grade layer stack manufacturing process schematic diagrames.Specifically include
Following steps：
(1) as shown in Figure 1A, etch to be formed by dry/wet formed with grade layer stack 103 on silicon substrate 101
Gate line slit 102 (Gate Line Slit, GLS) extends vertically through grade layer stack 103；The grade layer stack 103 by according to
The oxide skin(coating) 104 and nitride layer 105 that minor tick is formed form.Wherein nitride layer 105 can be formed by silicon nitride.
(2) as shown in Figure 1B, etched by dry/wet in the grade layer stack 103 removed near gate line slit 102
Nitride layer 105 (such as SiN), formed sunk area 106.
(3) as shown in Figure 1 C, deposited metal tungsten, the sunk area 106 formed afterwards with filling step (2), tungsten is formed
Layer 107.
(4) etching metal tungsten layer 107, new conductor/insulation body grade layer stack 103 is ultimately formed.
But there is following defect in above-mentioned conventional method：
It can be used in the removal technique of silicon nitride layer and arrive phosphoric acid material, and the etch-rate of phosphoric acid material and silicon therein
Concentration is related.If silicon concentration is high, etch-rate is relatively low, if instead the low then etch-rate of silicon concentration is higher.
When etch-rate is relatively low, as shown in Figure 1B, at step (2), oxide often regrows, increased more
Remaining oxide (about 5-10 angstroms of thickness, 1 angstrom=10-10Rice), result in major part phenomenon (Figure 1B circled of oxide skin(coating) 104
It is shown), and then can cause to form bubble or hollow area 108 at step (3), this be not intended to occur during NAND device makes or
Person wants the phenomenon avoided the occurrence of, because this bubble or hollow area eventually result in metal tungsten layer opening or resistance value rises,
So as to have a strong impact on device performance.
Usual this major part phenomenon is difficult to avoid, because the silicon concentration in phosphoric acid material is difficult control, reason is when etching
Silicon concentration can be caused to increase when removing silicon nitride layer.
The content of the invention
In order to solve the above-mentioned technical problem, the purpose of the present invention is a kind of 3D nand memories grade layer stack system of design
New method is made, big header structure is etched back by using hydrofluoric acid (HF), oxide skin(coating) major part phenomenon can be eliminated.
According to an aspect of the invention, there is provided a kind of 3D nand memories grade layer stack manufacture method, comprising with
Lower step：
Oxide/nitride grade layer stack is formed on a silicon substrate, is then formed and is extended vertically through the oxide/nitridation
The gate line slit of thing grade layer stack；
The nitride layer in oxide/nitride grade layer stack is removed, forms sunk area；
The sunk area is etched back using hydrofluoric acid so that the oxide in the oxide/nitride grade layer stack
Layer surface planarizes；
The sunk area is filled using conductor material, conductor layer is formed and etches the conductor layer, form conductor/insulation
Body grade layer stack.
Preferably, the nitride layer is formed by silicon nitride.
Preferably, etch to form the gate line slit and the sunk area using dry/wet.
Preferably, the nitride layer in oxide/nitride grade layer stack is removed using phosphoric acid.
Preferably, the concentration of the hydrofluoric acid is HF：H2O=1:500, the etch-back for time is 1 to 5 minutes.
Preferably, the conductive material includes one or more of combinations in tungsten, cobalt, copper, aluminium and silicide.
Preferably, using thin film deposition processes complete described in state filling process and/or formed oxide/nitride grading layer
Storehouse.
It is furthermore preferred that the thin film deposition processes include chemical vapour deposition technique (CVD), physical vaporous deposition (PVD),
One kind in atomic layer deposition method (ALD).
Preferably, insulating barrier is also formed with the oxide/nitride grade layer stack, the gate line slit is vertical
Through oxide/nitride grade layer stack and insulating barrier.
According to another aspect of the present invention, a kind of 3D nand memories are additionally provided, it is included according to above method system
The conductor/insulation body grade layer stack made.
The 3D nand memory grades layer stack manufacture new method of the present invention, major part is etched back by using hydrofluoric acid (HF)
Structure, oxide skin(coating) major part phenomenon can be eliminated, so as to improve the filling rate of conductor layer in 3D NAND grade layer stacks, and then
Improve device performance.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings：
Figure 1A-C are prior art 3D nand memory grade layer stack manufacturing process schematic diagrames；
Fig. 2A-D are 3D nand memories grade layer stack manufacturing process schematic diagrames of the present invention；
Fig. 3 is that prior art has the latter made grade layer stack photo of major part phenomenon；
Fig. 4 eliminates the latter made grade layer stack photo of major part phenomenon for the present invention.
Embodiment
Embodiments of the invention are more fully described below in reference to accompanying drawing, the preferred embodiments of the present invention are shown in the accompanying drawings
Go out.However, the present invention can be implemented in a different manner, and it should not be construed as limited to embodiments described herein.Whole
Identical reference refers to identical element all the time in individual specification.
Although it should be appreciated that the grade of term first, second can be used to describe various elements here, these elements should not be limited
In these terms.These terms are used to make an element be different from another element.For example, the first element is properly termed as second yuan
Part, similarly, the second element are properly termed as the first element, without departing from the scope of the present invention.As used herein, term " and/
Or " include one or more listed by relevant item any and all combination.
It should be appreciated that when claim an element another element " on ", " being connected to " or during " being coupled to " another element, it can
With the element that another element is directly either connected or coupled on another element or can also have insertion.On the contrary, work as
Claim on an another element of element " directly existing " or during " being directly connected to " or " being directly coupled to " another element, in the absence of inserting
The element entered.Others be used to describe relation between element word should explain in a similar way (for example, " ... it
Between " relative to " between directly existing ... ", " adjacent " relative to " direct neighbor " etc.).Here when one element of title is in another element
When upper, it can be directly coupled to another element, or there may be the element of insertion, Huo Zheyuan in another element up or down
Part can be separated by space or gap.
Terminology used here is not intended to limit the present invention just for the sake of description specific embodiment.As used herein,
Clearly state unless the context otherwise, otherwise singulative " one " and "the" are intended to include plural form simultaneously.It should also manage
Solution, term " comprising ", " comprising ", " comprising " and/or " comprising ", when here in use, specifying the feature, entirety, step
Suddenly, the presence of operation, element and/or component, but it is not precluded from one or more other features, entirety, step, operation, member
The presence or addition of part, component and/or its combination.
The 3D nand memory grade layer stacks manufacturing process of the embodiment of the present invention walks as shown in fig. 2 a-d, including as follows
Suddenly：
S1, as shown in Figure 2 A, formed with grade layer stack 203 on silicon substrate 201, etches to be formed by dry/wet
Gate line slit 202 (Gate Line Slit, GLS) extends vertically through grade layer stack 203；The grade layer stack 203 by according to
The oxide skin(coating) 204 and nitride layer 205 that minor tick is formed form.Wherein nitride layer 205 can be formed by silicon nitride.
In certain embodiments, silicon substrate 201 is made up of monocrystalline silicon, can be also made up of other suitable materials, including but
It is not limited to silicon, germanium, silicon on insulator (Silicon on insulator, SOI) etc..
In certain embodiments, grade layer stack 203 is formed in the following way：
Multiple insulator layers pair are formed on a silicon substrate, and multiple insulator layers are to forming grade layer stack, single insulator
Layer material includes but is not limited to silica, silicon nitride or silicon oxynitride, or the combination of a variety of above materials, in some embodiments
In, there are more insulator layers pair, the insulator layer has different to being made from a different material in grade layer stack
Thickness.That is, the insulator layer pair of some positions and the insulator layer of other positions are to can be by grade layer stack
Different materials is made and has different thickness, for example, in grade layer stack the insulator layer centering of some positions first
The thickness of insulating barrier is 5-40nm, and the thickness of the second insulating barrier is 5-40nm；The first of the insulator layer centering of other positions
The thickness of insulating barrier is 10-40nm, and the thickness of the second insulating barrier is 10-40nm；The of the insulator layer centering of other position
The thickness of one insulating barrier is 50-200nm, and the thickness of the second insulating barrier is 5-40nm.In certain embodiments, multiple insulation are formed
The technique of body layer pair can use thin film deposition technique, including but not limited to chemical vapour deposition technique (Chemical Vapor
Deposition, CVD), physical vaporous deposition (Physical Vapor Deposition, PVD) or atomic layer deposition method
(Atomic Layer Deposition,ALD)。
In certain embodiments, insulating barrier 208 is also formed with grade layer stack 203, gate line slit extends vertically through
Level layer stack 203 and insulating barrier 208.In certain embodiments, insulating barrier 208 includes silica and/or silicon nitride layer.
In certain embodiments, NAND string (not shown) is also formed with silicon substrate 201, NAND string is formed and enters one
Step, which includes being formed, extends vertically through the channel semiconductor of grade layer stack and between channel semiconductor and grade layer stack 203
Dielectric layer.In certain embodiments, channel semiconductor is made up of non-crystalline silicon, polysilicon or monocrystalline silicon.In certain embodiments,
Dielectric layer is multiple layers of combination, including but not limited to tunnel layer, memory cell layers and barrier layer.In certain embodiments, institute
Stating tunnel layer includes insulating materials, including but not limited to silica, silicon nitride or silicon oxynitride, or the group of a variety of above-mentioned materials
Close.In certain embodiments, the thickness of tunnel layer is 5-8nm, and the electronics or hole in channel semiconductor can pass through this layer of tunnel
Channel layer tunnelling is into the memory cell layers of NAND string.In certain embodiments, memory cell layers can be used for storage operation NAND
Electric charge, the storage or removal of the electric charge in memory cell layers determine the on off state of channel semiconductor.Memory cell layers
Material include but is not limited to silicon nitride, silicon oxynitride or silicon, or the combination of a variety of above materials.In certain embodiments,
The thickness of memory cell layers is 5-8nm.In certain embodiments, barrier material is silica, silicon nitride or high-k
Insulating materials, or the combination of a variety of above materials.Such as a silicon oxide layer or one include silica/silicon nitride/oxidation
The thickness of three layers of silicon (ONO) is 6-9nm composite bed.In certain embodiments, the barrier layer may further include one
High k dielectric layer (such as aluminum oxide that thickness is 2-4nm).In certain embodiments, formed dielectric layer can use ALD, CVD,
PVD and other suitable methods.
In certain embodiments, forming NAND string further comprises the epitaxial layer to be formed below the NAND string (in figure
It is not shown), epitaxial layer is silicon layer, and it directly contacts with silicon substrate and from silicon substrate Epitaxial growth.In certain embodiments, outside
Prolong layer and be further doped to desired doped level.
In certain embodiments, formed with the first doped region (not shown), NAND string and gate line on silicon substrate 201
Slit is formed on the first doped region.In certain embodiments, the second doped region is also formed with silicon substrate 201 (in figure not show
Go out), it is located at the bottom of gate line slit, by being further doped to the first doped region that gate line Slot bottom exposes
Arrive.In certain embodiments, there is identical doping type (to be n-type doping or be P for the first doped region and the second doped region
Type adulterates), the impurity concentration adulterated in the second doped region is more than the first doped region.In certain embodiments, the first doping is formed
Area and the second doped region can use injection and/or diffusion technique.
S2, as shown in Figure 2 B, etched by dry/wet remove in grade layer stack 203 nitride layer 205 (such as
SiN), sunk area 206 is formed.
It can be used in the removal technique of nitride layer 205 and arrive phosphoric acid material, and the etch-rate of phosphoric acid material and wherein
Silicon concentration it is related.If silicon concentration is high, etch-rate is relatively low, if instead the low then etch-rate of silicon concentration is higher.Work as erosion
When etching speed is relatively low, as shown in Figure 2 B, oxide often regrows, and increased undesired oxide (about 5-10 angstroms of thickness, 1
Angstrom=10-10Rice), result in the major part phenomenon of oxide skin(coating) 204 (shown in Fig. 2 B circled).
Therefore, in step S2, it is necessary to the silicon concentration in phosphoric acid material strictly be controlled, to avoid producing serious oxide life
Long problem.
S3, as shown in Figure 2 C, the sunk area 206 is etched back using hydrofluoric acid, increased unnecessary during with removing step S2
Oxide so that the surface planarisation of oxide skin(coating) 204.
In certain embodiments, the concentration of hydrofluoric acid is mass ratio 1:500(HF：H2O), etch-back for time is 1 to 5 minutes.
In etch-back for time, by controlling the dosage and injection rate of hydrofluoric acid, using sunk area inner surface described in hydrofluoric acid clean,
So that increased undesired oxide (such as silica) produces chemical reaction when hydrofluoric acid and step S2, so as to generate be dissolved in it is molten
The reactant (such as SiF) of liquid, so as to increased undesired oxide during removal process S2, the major part for eliminating oxide skin(coating) 204 shows
As.
It is attached to because increased undesired oxide is more open on oxide skin(coating) 204, and it is used in the present invention
Hydrofluoric acid concentration is very low, and therefore, above-mentioned hydrofluoric acid clean process can easily remove undesired oxide without injuring
Need the oxide skin(coating) 204 itself retained.
S4, as shown in Figure 2 D, conductor material is inserted after nitride layer is removed in the sunk area 206 formed, is formed
Conductor layer 207, conductor layer 207 is then etched, ultimately forms new conductor/insulation body grade layer stack 203.
In certain embodiments, conductor layer 207 is made of an electrically conducting material, including but not limited to tungsten, cobalt, copper, aluminium and silication
One or more of combinations in thing, above-mentioned filling process can be completed using thin film deposition processes, include but is not limited to chemistry
Vapour deposition process (CVD), physical vaporous deposition (PVD), atomic layer deposition method (ALD) and/or other suitable methods.
In order to verify the technique effect of the present invention, contrasted with prior art.The present invention claps taken prior art respectively
The latter made grade layer stack photo (as shown in Figure 3) of major part phenomenon be present and to eliminate major part phenomenon through the present invention latter made etc.
Level layer stack photo (as shown in Figure 4).From figure 3, it can be seen that the metal tungsten layer that the grade layer stack of major part phenomenon be present is (black
Color part) opening (line to turn white) be present, and latter made grade layer stack is cleaned using HF through the present invention as shown in Figure 4, tungsten
Layer is uniform and without flaws such as openings, perfectly eliminates drawbacks described above.
The 3D nand memory grades layer stack manufacture new method of the present invention, major part is etched back by using hydrofluoric acid (HF)
Structure, can etch away increased undesired oxide (about 5-10 angstroms of thickness, 1 angstrom=10-10Rice), so as to eliminate oxide
Layer major part phenomenon, so as to improve the filling rate of conductor layer in 3D NAND grade layer stacks, and then improve device performance.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Enclose and be defined.
Claims (10)
1. a kind of 3D nand memories grade layer stack manufacture method, it is characterized in that, comprise the steps of：
Oxide/nitride grade layer stack is formed on a silicon substrate, is then formed and is extended vertically through described oxide/nitride etc.
The gate line slit of level layer stack；
The nitride layer in oxide/nitride grade layer stack is removed, forms sunk area；
The sunk area is etched back using hydrofluoric acid so that the oxide skin(coating) table in the oxide/nitride grade layer stack
Face planarizes；
The sunk area is filled using conductor material, conductor layer is formed and etches the conductor layer, form conductor/insulation body etc.
Level layer stack.
2. a kind of 3D nand memories grade layer stack manufacture method according to claim 1, it is characterized in that：
The nitride layer is formed by silicon nitride.
3. a kind of 3D nand memories grade layer stack manufacture method according to claim 1, it is characterized in that：
Etch to form the gate line slit and the sunk area using dry/wet.
4. a kind of 3D nand memories grade layer stack manufacture method according to claim 1, it is characterized in that：
The nitride layer in oxide/nitride grade layer stack is removed using phosphoric acid.
5. a kind of 3D nand memories grade layer stack manufacture method according to claim 1, it is characterized in that：
The concentration of the hydrofluoric acid is HF：H2O=1:500, the etch-back for time is 1 to 5 minutes.
6. a kind of 3D nand memories grade layer stack manufacture method according to claim 1, it is characterized in that：
The conductive material includes one or more of combinations in tungsten, cobalt, copper, aluminium and silicide.
7. a kind of 3D nand memories grade layer stack manufacture method according to claim 1, it is characterized in that：
Using thin film deposition processes complete described in state filling process and/or formed oxide/nitride grade layer stack.
8. a kind of 3D nand memories grade layer stack manufacture method according to claim 7, it is characterized in that：
The thin film deposition processes include chemical vapour deposition technique (CVD), physical vaporous deposition (PVD), atomic layer deposition method
(ALD) one kind in.
9. a kind of 3D nand memories grade layer stack manufacture method according to claim 1, it is characterized in that：
Be also formed with insulating barrier on the oxide/nitride grade layer stack, the gate line slit extend vertically through oxide/
Nitride grade layer stack and insulating barrier.
10. a kind of 3D nand memories, it is characterised in that it includes being manufactured according to claim 1-9 any one methods described
Conductor/insulation body grade layer stack.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108447869A (en) * | 2018-03-14 | 2018-08-24 | 武汉新芯集成电路制造有限公司 | Storage organization and preparation method thereof |
| CN111211129B (en) * | 2020-01-15 | 2023-10-17 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
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| CN103155139A (en) * | 2010-10-14 | 2013-06-12 | 株式会社Eugene科技 | Method and apparatus for manufacturing three-dimensional-structure memory device |
| US20170047341A1 (en) * | 2015-08-10 | 2017-02-16 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing same |
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