CN111584496B

CN111584496B - Memory manufacturing method and memory

Info

Publication number: CN111584496B
Application number: CN202010434153.2A
Authority: CN
Inventors: 姚兰
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-05-21
Filing date: 2020-05-21
Publication date: 2021-04-27
Anticipated expiration: 2040-05-21
Also published as: CN111584496A

Abstract

The embodiment of the disclosure discloses a memory manufacturing method and a memory, wherein the method comprises the following steps: forming a first via and a second via through the first stacked structure; the first stacking structure comprises a core area and a step area which are arranged in parallel, a first through hole penetrates through the core area, a second through hole penetrates through the step area, and the caliber of a top opening of the first through hole is smaller than that of a top opening of the second through hole; depositing a first material in the first via and the second via to form a sacrificial post in the first via; carrying out chemical reaction on a preset reactant and the first material in the second through hole to form an insulating support pillar in the second through hole; forming a second stacked structure on the surface of the first stacked structure including the sacrificial post and the support post; forming a third through hole penetrating through the second stacking structure until the sacrificial post is exposed; forming a fourth through hole penetrating through the second stacking structure until the support pillar is exposed; removing the sacrificial post exposed through the third via hole with an etchant; the chemical reaction between the etchant and the support posts is an inert reaction.

Description

Memory manufacturing method and memory

Technical Field

The disclosed embodiments relate to the field of integrated circuits, and in particular, to a memory manufacturing method and a memory.

Background

With the increasing demand for memory storage density, three-dimensional structures of memory devices have been developed, which include a gate stack structure and a channel pillar vertically penetrating the gate stack structure. The channel pillar may serve as a support in forming the control gate by removing the gate sacrificial layer in the stacked structure. In addition, the channel pillars are also used for information storage.

In order to further improve the memory density, the number of layers of the stack structure for forming the gate stack structure is gradually increased, and the size of the channel pillar is gradually decreased. In the process of forming the control gate, the supporting function of the channel pillar is gradually weakened. In the related art, a Dummy Channel pillar filling a Dummy Channel Hole (Dummy Channel Hole) may be formed to improve a supporting effect on the stack structure during the removal of the gate sacrificial layer. Here, the dummy channel pillar has the same composition structure as the channel pillar, but the dummy channel pillar only plays a supporting role without information storage.

In addition, for the stack structure with a higher layer number, a plurality of sub-stack structures with a smaller layer number can be manufactured in sequence, and the aligned sub-channel columns and the aligned sub-virtual channel columns are formed in the sub-stack structures manufactured in sequence to form the memory. However, a short circuit or the like occurs in the memory formed in this manner, so that the memory fails.

Disclosure of Invention

In view of the above, the present disclosure provides a memory manufacturing method and a memory.

According to a first aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a memory, including:

forming a first via and a second via through the first stacked structure; the first stacking structure comprises a core area and a step area which are arranged in parallel, the first through hole penetrates through the core area, the second through hole penetrates through the step area, and the caliber of a top opening of the first through hole is smaller than that of a top opening of the second through hole;

depositing a first material in the first via and the second via to form a sacrificial post in the first via;

carrying out chemical reaction on a preset reactant and the first material in the second through hole to form a support pillar in the second through hole;

forming a second stacked structure on the surface of the first stacked structure including the sacrificial post and the support post;

forming a third through hole penetrating through the second stacking structure until the sacrificial post is exposed; forming a fourth through hole penetrating through the second stacking structure until the support column is exposed;

removing the sacrificial columns exposed through the third through holes by using an etchant; wherein the chemical reaction between the etchant and the support pillars is an inert reaction.

In some embodiments, the method further comprises:

after the sacrificial post is formed, removing a part of the first material covering the second through hole to form a groove in the first material in the second through hole; the groove is used for increasing the contact area of the preset reactant and the first material in the second through hole.

In some embodiments, the method further comprises:

depositing the first material on the first stacked structure surface while depositing the first material in the first via and in the second via;

forming a support pillar in the second through hole, and simultaneously performing the chemical reaction with a first material on the surface of the first stacked structure by using the preset reactant to form a barrier layer on the surface of the first stacked structure;

the barrier layer covering the sacrificial column is used for blocking the preset reactant from performing the chemical reaction with the sacrificial column.

In some embodiments, the method further comprises:

and after the support columns are formed, removing the barrier layer until the sacrificial columns are exposed.

In some embodiments, the method further comprises:

after the sacrificial post is removed, a first channel post is formed based on the appearance of the first through hole, a second channel post is formed based on the appearance of the third through hole, and a third channel post is formed based on the appearance of the fourth through hole.

In some embodiments, the constituent materials of the sacrificial post include: silicon;

the support column comprises the following components: silicon oxide;

the etching agent comprises: tetramethylammonium hydroxide TMAH.

According to a second aspect of embodiments of the present disclosure, there is provided a memory comprising:

the first gate stack structure and the second gate stack structure are stacked; the first gate stack structure includes: the core area and the step area are arranged in parallel;

the insulating support column penetrates through the step area of the first gate stack structure;

a channel structure comprising:

the first channel column penetrates through the core region of the first gate stack structure;

the second channel column penetrates through the second gate stack structure and is connected with the first channel column;

the third channel column penetrates through the second gate stack structure and is connected with the supporting column;

wherein the support pillar has a different composition structure from the channel structure.

In some embodiments, the top dimension of the first channel pillar is smaller than the top dimension of the support pillar.

In some embodiments, the first trench pillar is located in a via formed after removal of the sacrificial pillar; wherein the chemical reaction between the etchant for removing the sacrificial columns and the support columns is an inert reaction.

In the embodiment of the disclosure, by forming the second via penetrating through the step region of the first stacked structure and forming the support pillar in the second via, since the chemical reaction between the support pillar and the etchant for removing the sacrificial pillar is inert, the support pillar in the second via can be retained while removing the sacrificial pillar, without additionally forming a dummy trench pillar for supporting in the second via, so that damage to a portion of the first stacked structure located on the sidewall of the second via when forming the dummy trench pillar in the second via is reduced, which is beneficial for reducing the probability of short circuit in the first gate stacked structure formed based on the first stacked structure.

And by forming the insulating support pillar, the possibility that two adjacent conductive gates in the step region of the first gate stack structure are contacted with each other can be reduced, and the probability of short circuit of the first gate stack structure is further reduced.

In addition, when the dummy trench pillar is formed in the fourth through hole, the support pillar can protect a part of the first stacked structure on the side wall of the second through hole, so that the rejection rate or the reject ratio caused by short circuit is reduced, and the product yield is improved.

Drawings

FIG. 1 is a schematic diagram illustrating a memory during fabrication in accordance with an exemplary embodiment;

FIG. 2 is a flow diagram illustrating a method of fabricating a memory according to an exemplary embodiment;

FIGS. 3 a-3 i are schematic diagrams illustrating a method of fabricating a memory device according to an exemplary embodiment;

FIG. 4 is a block diagram illustrating the structure of a memory according to an exemplary embodiment.

Detailed Description

The technical solutions of the present disclosure will be further explained in detail with reference to the drawings and examples. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.

In the disclosed embodiment, the term "a is connected to B" includes A, B where a is connected to B in contact with each other, or A, B where a is connected to B in a non-contact manner with other components interposed between the two.

In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.

The technical means described in the embodiments of the present disclosure may be arbitrarily combined without conflict.

In the related art, the control gate in the memory gate stack structure may be formed by a gate-last process. Specifically, for a stacked structure including first dielectric layers (e.g., oxide layers) and second dielectric layers (e.g., nitride layers) that are stacked, a control gate may be formed by removing the second dielectric layers to form a cavity between adjacent first dielectric layers, and then filling a gate dielectric (e.g., metal or polysilicon, etc.) in the cavity. When the second dielectric layer is removed and the cavity is formed and the gate dielectric is not filled, the stacked structure can be supported by the channel column penetrating through the stacked structure, so that the stacked structure is prevented from collapsing.

In order to further improve the storage density, the number of layers of the stacked structure for forming the gate stack structure is gradually increased, the size of the channel column is gradually reduced, the stacked structure is easy to collapse in the process of removing the second dielectric layer, and the yield of the memory is reduced.

In order to solve the problem of collapse of the stacked structure during the process of removing the second dielectric layer, a dummy channel pillar penetrating through the stacked structure is developed. Since the dummy channel pillar serves as a support, the feature size of the dummy channel pillar may be slightly larger than that of the channel pillar actually performing charge storage. Here, the characteristic dimension may include a top diameter or a top cross-sectional area.

Compared with the method of sequentially forming the virtual channel column and the channel column for actually storing the charges, the method of the invention has the advantages that the virtual channel column can be synchronously formed while the channel column for actually storing the charges is formed in the related technology, and the virtual channel column and the channel column for actually storing the charges can have the same structure, so that the virtual channel column and the channel column for actually storing the charges can have the same manufacturing process, the process complexity is reduced, and the manufacturing cost is reduced.

In addition, for the stacked structure with a higher layer number, the memory can be manufactured by adopting a multi-stacking technology. Here, the multiple stacking technique includes: a memory is fabricated by forming a plurality of stacked structures having a smaller number of stacked layers a plurality of times and forming a shorter channel pillar in each stacked structure.

In particular, FIG. 1 is a partial schematic diagram illustrating one fabrication of a memory by a multiple-stack technique according to an exemplary embodiment. Referring to fig. 1, the method for manufacturing the memory may include the following steps:

the method comprises the following steps: firstly, forming a first stacked structure on a substrate, then forming a first through hole penetrating through the first stacked structure in a core area of the first stacked structure, and forming a second through hole penetrating through the first stacked structure in a step area of the first stacked structure;

step two: forming a first epitaxial layer at the bottom of the first through hole, and forming a second epitaxial layer at the bottom of the second through hole; then forming a first sacrificial column in the first through hole and forming a second sacrificial column in the second through hole; the first sacrificial column is used for blocking the component materials of the second stacked structure from entering the first through hole in the process of forming the second stacked structure; a second sacrificial post for blocking a constituent material of the second stack structure from entering the second via hole during formation of the second stack structure;

step three: forming a second stacked structure on the surface of the first stacked structure on which the first sacrificial post and the second sacrificial post are formed;

step four: forming a third through hole penetrating through the second stacked structure until the first sacrificial post is exposed; forming a fourth through hole penetrating through the second stacking structure until the second sacrificial column is exposed;

step five: injecting an etchant through the third through hole to remove the first sacrificial post; injecting an etching agent through the fourth through hole to remove the second sacrificial column;

step six: forming a first isolation layer covering the side wall of the first through hole, the side wall of the third through hole and the bottom of the first through hole, and forming a second isolation layer covering the side wall of the second through hole, the side wall of the fourth through hole and the bottom of the second through hole;

step seven: etching a part of the first isolation layer covering the first epitaxial layer until the first epitaxial layer is exposed; and etching a part of the second isolation layer covering the second epitaxial layer until the second epitaxial layer is exposed.

Referring to fig. 1, a memory structure of a memory may include: a core (core) region and a Step (SS) region. The core region is provided with a plurality of channel columns for information storage. The step area is arranged around the core area and used for transmitting control information to the core area so as to read and write information in the core area.

When the three-dimensional memory is manufactured by using the multi-stacking technology, a virtual channel column which plays a supporting role can be formed in the step area, and a channel column which actually stores information is formed in the core area.

Referring to fig. 1, the stepped region may include: the dielectric layer structure comprises a laminated structure consisting of a first dielectric layer and a second dielectric layer, and a dielectric structure covering the laminated structure. The dummy channel pillar may be formed in the stacked structure and/or the dielectric structure of the step region. Here, the constituent material of the first dielectric layer may include an oxide (e.g., silicon oxide), the constituent material of the second dielectric layer may include a nitride (e.g., silicon nitride), and the constituent material of the dielectric structure may include an oxide (e.g., silicon oxide).

Since the first through hole and the third through hole are formed in the core region of the memory, the second through hole and the fourth through hole are formed in the step region of the memory, and the core region and the step region have different composition structures, the degrees of deformation (Distortion) of the core region and the step region during the formation of the through holes are different, resulting in different alignment (overlay) accuracies of the fourth through hole and the second through hole from those of the first through hole and the third through hole.

Generally, the deformation degree of the stepped region is greater than that of the core region, so that the alignment accuracy of the fourth through hole and the second through hole is lower than that of the first through hole and the third through hole. Therefore, when etching the portion of the second isolation layer covering the second epitaxial layer, the portion of the second isolation layer covering the sidewall of the second via hole is damaged, and the portion of the first stacked structure located on the sidewall of the second via hole is exposed. Particularly, the second isolation layer at a position (joint) region (for example, the region marked in the oval circle in fig. 1) covering the sidewall of the second through hole and close to the connection (joint) region between the second through hole and the fourth through hole is easy to be damaged.

It should be noted that after the etching process is performed to remove a portion of the second isolation layer covering the second epitaxial layer, the conductive material is continuously filled into the second via hole having the second isolation layer formed on the sidewall thereof, so as to form a dummy trench pillar.

When part of the second isolation layer on the sidewall of the second through hole is damaged, the conductive material in the dummy channel pillar may form an electrical contact with the control gate, resulting in a leakage (leakage) in the memory, or the adjacent control gates are electrically connected through the dummy channel pillar, resulting in a short circuit in the memory, and the like, thereby reducing the yield of the product.

In the related art, the second isolation layer may be further protected by covering a Photoresist (PR) on a surface of the second isolation layer covering the second epitaxial layer before removing the first isolation layer covering the first epitaxial layer and removing the photoresist after removing the first isolation layer covering the first epitaxial layer. It will be appreciated that the photoresist can block the etching of the second isolation layer.

However, this method will add extra process flow, which increases the process complexity and cost. Moreover, damage may be caused to the formed structure during the process of removing the photoresist, and it is difficult to ensure the product yield.

In view of the above, the present disclosure provides a method for manufacturing a memory. Referring to fig. 2, the method includes the steps of:

s100: forming a first via and a second via through the first stacked structure; the first stacking structure comprises a core area and a step area which are arranged in parallel, a first through hole penetrates through the core area, a second through hole penetrates through the step area, and the caliber of a top opening of the first through hole is smaller than that of a top opening of the second through hole;

s110: depositing a first material in the first via and the second via to form a sacrificial post in the first via;

s120: carrying out chemical reaction on a preset reactant and the first material in the second through hole to form a support pillar in the second through hole;

s130: forming a second stacked structure on the surface of the first stacked structure including the sacrificial post and the support post;

s140: forming a third through hole penetrating through the second stacking structure until the sacrificial post is exposed; forming a fourth through hole penetrating through the second stacking structure until the support column is exposed;

s150: removing the sacrificial post exposed through the third via hole with an etchant; wherein the chemical reaction between the etchant and the support pillar is an inert reaction.

Illustratively, a plurality of channel pillars may be disposed in the core region for information storage.

The bench region is disposed around the core region, and the bench region may be located at one end of the core region, or the bench region may be located at two opposite ends of the core region. The step area is used to connect the core area with an external circuit. The external circuit transmits control information to the core area through the step area, so that information reading and writing operations are carried out in the core area.

The stepped region may include: the dielectric layer structure comprises a laminated structure formed by a first dielectric layer and a second dielectric layer which are laminated, and a dielectric structure covering the laminated structure. The first medium layer and the second medium layer which are adjacent are used as a laminating unit, and the lengths of the two adjacent laminating units in the same direction are different, so that the laminating structure is step-shaped. When the top opening shape of the first through hole and the second through hole is circular, the top opening caliber may include: the diameter of the top opening or the radius of the top opening.

Since the first and second through holes both penetrate the first stacked structure, the first and second through holes have the same depth. The aperture of the top opening of the first through hole is smaller than that of the second through hole, so the aspect ratio of the first through hole is larger than that of the second through hole. Here, the aspect ratio of the via hole may include: the ratio of the depth of the via to the diameter of the via top opening.

In S110, to simplify the process flow, the first material may be deposited in the first via hole and the second via hole simultaneously. The speed of depositing the first material into the first via and the second via may be approximately the same. Therefore, when both the top opening of the first via and the top opening of the second via are not closed, the volumes of the first material deposited in the first via and the second via may be considered to be the same in the same time.

Because the caliber of the top opening of the first through hole is smaller than that of the top opening of the second through hole, and the depths of the first through hole and the second through hole are the same, the volume of the cavity formed based on the first through hole is smaller than that of the cavity formed based on the second through hole. During the process of depositing the first material into the first via and the second via, when the top opening of the first via is closed by the deposited first material to form the sacrificial post, the top opening of the second via is not yet filled with the first material.

It is understood that after the top opening of the first via is closed by the first material to form the sacrificial post, if the deposition of the first material is continued, the first material deposited to the first via will cover the top of the sacrificial post, and the first material deposited to the second via will continue to be deposited in the cavity formed based on the topography of the second via.

It is noted that after the top opening of the second via is also closed by the deposited first material, if the deposition of the first material is continued, the thickness of the first material covering the top of the sacrificial post may be greater than the thickness of the first material covering the top of the second via.

Illustratively, the first material may be generated by chemical vapor deposition using a predetermined gas to react. The sprayed preset gas can reach the top of the through hole firstly and then move to the bottom of the through hole along the side wall of the through hole, and the content of the preset gas is reduced gradually in the moving process, so that the deposition speed of the first material on the top opening of the through hole is higher than that on the side wall of the through hole, and the deposition speed of the first material on the side wall of the through hole is higher than that on the bottom of the through hole, so that when the top opening of the through hole is closed by the deposited first material, a gap which is not filled by the first material still exists in the through hole.

Since the aperture of the top opening of the first through hole is smaller than the aperture of the top opening of the second through hole, when depositing the first material, the first material may seal the top opening of the first through hole first, so that the first material cannot be deposited into the first through hole continuously. While the top opening of the first via is closed, the top opening of the second via may remain unsealed.

When the top opening of the first through hole is closed, the first material filled in the first through hole forms a sacrificial column. It will be appreciated that the interior of the sacrificial post may have voids, i.e., the sacrificial post may be a columnar structure with a hollow interior.

Illustratively, the support pillars may be generated in a volume greater than the volume of the first material consumed by a chemical reaction of the predetermined reactant with the first material in the second through-holes.

Specifically, when the deposition of the first material is stopped, the top opening of the first via hole is closed, but the top opening of the second via hole may not be closed. By the above chemical reaction, the top of the support pillar can be made flush with the top opening of the second through hole, i.e., the top opening of the second through hole is closed. And the formed support column can play an effective supporting role, the probability of collapse of the first stacking structure in the subsequent process is reduced, and the quality of the memory is ensured.

Illustratively, the first material may include silicon. For example, the first material may be polysilicon. It is understood that the constituent material of the sacrificial post comprises the first material.

The predetermined reactant may include oxygen. When the predetermined reactant includes oxygen, the composition material of the support pillar may include: silicon dioxide.

It should be noted that when oxygen is used to chemically react with polysilicon to form silicon dioxide, the volume of silicon dioxide formed is greater than the volume of polysilicon consumed by the chemical reaction. Therefore, when the total volume of the polysilicon deposited in the second through hole is smaller than the volume of the cavity formed based on the topography of the second through hole, the volume of the support pillar formed through the chemical reaction can be equal to the volume of the cavity formed based on the topography of the second through hole, so that the top of the support pillar is flush with the top opening of the second through hole, the formed gap inside the support pillar can be reduced, and the support pillar can provide effective support effect.

Illustratively, the aperture of the top opening of the first through hole is smaller than the aperture of the top opening of the second through hole, and the aperture of the top opening of the third through hole is smaller than the aperture of the top opening of the fourth through hole.

In the subsequent process, channel columns for information storage can be formed in the first through hole and the third through hole, and a virtual channel column for supporting can be formed in the fourth through hole.

Typically, the channel pillars and dummy channel pillars are cylindrical; or, along the axial direction of the channel column, the cross-sectional shapes of the channel column and the virtual channel column are trapezoidal, the top size of the channel column is larger than the bottom size of the channel column, and the top size of the virtual channel column is larger than the bottom size of the virtual channel column.

Since the storage density of a memory is related to the number of channel pillars for information storage. Therefore, the number of channel columns in a unit area can be increased by reducing the diameter of the channel columns in the core region, and the storage density is further improved.

Specifically, the diameter of the channel pillar can be reduced by reducing the diameters of the top openings of the first via hole and the third via hole.

Since the support pillars and the dummy channel pillars located in the step regions are used for supporting, the supporting effect of the support pillars and the dummy channel pillars on the stacked structure can be improved by appropriately increasing the diameters of the support pillars and the dummy channel pillars.

Specifically, the diameter of the support column can be increased by increasing the caliber of the top opening of the second through hole. The diameter of the dummy trench pillar may be increased by increasing the diameter of the top opening of the fourth via.

Illustratively, the caliber of the top opening of the first through hole is equal to the caliber of the top opening of the third through hole, and the caliber of the top opening of the second through hole is equal to the caliber of the top opening of the fourth through hole.

Illustratively, in S100, a first via hole penetrating a core region in the first stacked structure and a second via hole penetrating a step region of the first stacked structure may be formed through a photolithography process. The pattern design can be carried out on the photomask (mask) used in the photoetching process, so that the photomask simultaneously has the pattern corresponding to the first through hole and the pattern corresponding to the second through hole, and thus, the first through hole and the second through hole can be simultaneously formed by using the same photomask in one photoetching process.

Compared with the method that the first through hole and the second through hole are formed through the two photomasks respectively, the method that the first through hole and the second through hole are formed through the same photomask simultaneously simplifies the process flow and reduces the cost.

Since the third through-hole needs to be formed in alignment with the first through-hole and the fourth through-hole needs to be formed in alignment with the second through-hole, the same photo-mask that can be used for simultaneously forming both the first through-hole and the second through-hole and the third through-hole and the fourth through-hole can be used in S100 and S140.

Compared with the case that different photomasks are used in S100 and S140, one photomask is used for forming the first through hole and the third through hole, and the other photomask is used for forming the second through hole and the fourth through hole, the embodiment of the invention adopts the same photomask, so that the first through hole and the third through hole can be formed at the same time, the second through hole and the fourth through hole can be formed at the same time, the alignment precision of the third through hole and the first through hole and the alignment precision of the fourth through hole and the second through hole can be improved, the quality of a memory is ensured, and the cost caused by using different photomasks is reduced.

It can be understood that forming the first through hole and the third through hole with different top opening calibers, or forming the second through hole and the fourth through hole with different top opening calibers, requires different photomasks, increases the process flow and the process cost,

according to the embodiment of the disclosure, the first through hole and the third through hole with the same caliber of the top opening and the second through hole and the fourth through hole with the same caliber of the top opening are formed, so that the process flow can be simplified, and the process cost can be reduced. Illustratively, the top of the sacrificial post is flush with the top of the first stacked structure. Since the sacrificial post closes the top opening of the first via, the sacrificial post may block the constituent material of the second stack structure from falling into the first via in step S130.

It can be understood that, after the constituent material of the second stacked structure falls into the first via, the constituent material of the second stacked structure that falls into the first via needs to be removed subsequently, and since the constituent material of the second stacked structure is the same as the constituent material of the first stacked structure, when the constituent material of the second stacked structure that falls into the first via is removed, a portion of the first stacked structure located on the sidewall of the first via may be damaged, thereby reducing the performance of the memory.

For example, a chemical reaction between the etchant for removing the sacrificial post and the first stack structure may be an inert reaction, and a chemical reaction between the etchant for removing the sacrificial post and the second stack structure may be an inert reaction. In this way, it can be ensured that the first stack structure and the second stack structure are not damaged when the sacrificial post is removed with the etchant.

In the embodiment of the disclosure, the sacrificial column is formed in the first through hole, the component material of the second stacked structure is blocked by the sacrificial column from falling into the first through hole, and the component material of the sacrificial column is different from the component material of the first stacked structure, so that when the sacrificial column is removed by using an etchant, part of the first stacked structure on the side wall of the first through hole is not damaged, which is beneficial to ensuring the performance of the memory.

Illustratively, the top of the support column is flush with the top of the first stacked structure. Since the top opening of the second through hole is closed by the support pillar, in step S130, the support pillar may block the constituent material of the second stacked structure from falling into the second through hole, and subsequently, the constituent material of the second stacked structure falling into the second through hole does not need to be removed, which reduces the difficulty of the process.

Illustratively, the inert reaction may include: no chemical reaction occurs; alternatively, the first rate of chemical reaction occurs at a much lower rate than the second rate of chemical reaction between the etchant and the sacrificial post.

When the first rate of the chemical reaction between the etchant and the supporting column is far lower than the second rate of the chemical reaction between the etchant and the sacrificial column, it can be considered that the etchant does not damage the supporting column in the process of removing the sacrificial column by using the etchant, which is beneficial to ensuring the integrity of the supporting column, and further ensures that the supporting column has a good protection effect on a part of the first stacked structure on the side wall of the second through hole.

The etchant may include: tetramethylammonium hydroxide TMAH. The etchant may be in liquid or gaseous form.

In the embodiment of the disclosure, by forming the second through hole penetrating through the step region of the first stacked structure and forming the support pillar in the second through hole, since a chemical reaction between the support pillar and an etchant for removing the sacrificial pillar is an inert reaction, the support pillar in the second through hole can be retained while removing the sacrificial pillar, and the support pillar in the second through hole plays a role in supporting the first stacked structure in a subsequent process without additionally forming a dummy channel pillar for supporting in the second through hole, so that damage to a portion of the first stacked structure located on a sidewall of the second through hole when the dummy channel pillar is formed in the second through hole is reduced, and a probability of a short circuit occurring in a subsequent first gate stacked structure formed based on the first stacked structure is favorably reduced.

In some embodiments, the method further comprises:

For example, in the process of performing the chemical reaction, the first material in the second through hole may gradually convert the first material into the constituent material of the support pillar according to the order of contact with the predetermined reactant. Specifically, the first material first contacted with the predetermined reactant reacts first to form the constituent material of the support pillar, and there is a time delay between the initial time of the chemical reaction of the first material second contacted with the predetermined reactant and the first material first contacted with the predetermined reactant.

Moreover, after the first material which contacts the preset reactant reacts to generate the composition material of the support pillar, the composition material of the generated support can cover the surface of the remaining first material, which prevents the preset reactant from continuously contacting with the covered first material, reduces the reaction rate and the reaction degree of the support pillar generated by using the first material, and is not beneficial to improving the support effect of the support pillar.

In the embodiment of the disclosure, after the sacrificial post is formed, part of the first material covering the second through hole is removed to form the groove in the first material in the second through hole, so that the contact area between the preset reactant and the first material in the second through hole is increased, the reaction rate of forming the support post by using the first material is favorably improved, the reaction degree of forming the support post component material by using the first material can be improved, and the support effect of the support post is ensured.

In some embodiments, the method further comprises:

depositing a first material on the surface of the first stacked structure while depositing the first material in the first via hole and the second via hole;

forming a support pillar in the second through hole, and simultaneously carrying out chemical reaction on a preset reactant and a first material on the surface of the first stacking structure to form a barrier layer on the surface of the first stacking structure;

the barrier layer covering the sacrificial column is used for preventing a preset reactant from generating a chemical reaction with the sacrificial column.

It is understood that, since the aperture of the first via is smaller than the aperture of the second via, during the deposition of the first material in the first via, in the second via, and on the surface of the first stacked structure, when the top opening of the first via is closed by the first material to form the sacrificial post, the top opening of the second via may not be closed yet.

After the sacrificial post is formed, the first material is deposited on top of the sacrificial post and in the second via while continuing to deposit the first material. When the deposition of the first material is stopped, the top opening of the second via may still not be closed by the first material; alternatively, the top opening of the second via is closed by the first material, but the thickness of the first material overlying the top of the second via is less than the thickness of the first material overlying the top of the sacrificial post.

For example, when the deposition of the first material is stopped, if the top opening of the second via is still not closed by the first material, the support pillars may be directly formed by a chemical reaction between the predetermined reactant and the first material in the second via. Meanwhile, the first material on the surface of the first stacked structure can also chemically react with the preset reactant to generate a barrier layer, and the barrier layer covering the surface of the sacrificial column can prevent the preset reactant from reacting with the sacrificial column.

It will be appreciated that when the predetermined reactant chemically reacts with the sacrificial post, the first material in the sacrificial post is used to form the constituent material of the support post. The reaction between the etchant for removing the sacrificial column and the constituent materials of the support column is an inert reaction, so if a predetermined reactant chemically reacts with the sacrificial column, the difficulty of subsequently removing the sacrificial column is increased, which is not favorable for ensuring the performance of the memory.

In the embodiment of the disclosure, the barrier layer covering the sacrificial column is formed on the surface of the first stacked structure, so that the probability of chemical reaction between the sacrificial column and the preset reactant is reduced, and the process difficulty of subsequently removing the material filled in the first through hole is reduced.

In addition, in the embodiment of the disclosure, the first material is deposited on the surface of the first stacked structure while the first material is filled in the first through hole and the second through hole, and the barrier layer is formed by using the first material on the surface of the first stacked structure while the support pillar is formed in the second through hole.

In some embodiments, the method further comprises:

after the support posts are formed, the barrier layer is removed until the sacrificial posts are exposed.

Illustratively, the planarization process may be performed on the surface of the first stacked structure on which the barrier layer is formed by Chemical Mechanical Polishing (CMP) to remove the barrier layer.

It should be noted that, since during the deposition of the first material, a part of the first material enters the first through hole and the second through hole, and a part of the first material is deposited on the surface of the first stacked structure, the upper surface of the first material layer formed by the first material deposited on the surface of the first stacked structure is not a flat surface. The upper surface of the first material layer and the lower surface of the first material layer are opposite surfaces, and the lower surface of the first material layer is in contact with the surface of the first stacking structure.

Accordingly, the upper surface of the barrier layer formed based on the first material layer is also not a flat surface. According to the embodiment of the disclosure, the surface of the first stacked structure can be exposed by removing the barrier layer, so that a flat surface is provided for a subsequent process, the alignment precision is improved, and the device performance is ensured.

In some embodiments, the method further comprises:

after the sacrificial post is removed, a first channel post is formed based on the morphology of the first through hole, a second channel post is formed based on the morphology of the third through hole, and a third channel post is formed based on the morphology of the fourth through hole.

Illustratively, the first channel pillar, the second channel pillar, and the third channel pillar may have the same structure. For example, each channel pillar may include an isolation layer and a conductive pillar, pointing along a via sidewall toward a via center. Here, the isolation layer is used to isolate the conductive pillar from making electrical contact with the control gate formed based on the stacked structure, and the conductive pillar is used to provide a channel for charge movement.

The first channel pillar and the second channel pillar may store information by storing charges, and the third channel pillar may include a dummy channel pillar for supporting without storing information.

In the embodiment of the disclosure, the first channel column, the second channel column and the third channel column can be formed at the same time, so that the process flow is simplified, and the manufacturing efficiency is improved.

Example 1

3 a-3 i are flow diagrams illustrating a method of fabricating a memory device according to an exemplary embodiment, the method comprising the steps of:

the method comprises the following steps: forming a first via and a second via through the first stacked structure as shown in connection with fig. 3 a; the first through hole penetrates through the core area of the first stacked structure, the second through hole penetrates through the step area of the first stacked structure, and the caliber of a top opening of the first through hole is smaller than that of a top opening of the second through hole.

Step two: as shown in fig. 3b, a first epitaxial layer is formed at the bottom of the first via, a second epitaxial layer is formed at the bottom of the second via, and then a first material is deposited into the first via with the first epitaxial layer formed therein, the second via with the second epitaxial layer formed therein, and the surface of the first stacked structure to form a sacrificial post in the first via.

Step three: referring to fig. 3c, etching back (stress) the first material deposited in the second through hole to remove a portion of the first material covering the second through hole, and forming a groove in the second through hole; the groove is used for increasing the contact area of the preset reactant and the first material in the second through hole.

Step four: after the grooves are formed, a preset reactant is chemically reacted with the remaining first material in the second through hole to form an insulating support pillar in the second through hole, as shown in fig. 3 d; meanwhile, a preset reactant is utilized to perform a chemical reaction with a first material on the surface of the first stacked structure, so as to form a barrier layer on the surface of the first stacked structure.

In the fourth step, the composition material of the barrier layer is the same as that of the support pillar, and the barrier layer covering the sacrificial pillar is used for blocking the chemical reaction between the preset reactant and the sacrificial pillar.

Step five: after the support posts are formed, the barrier layer is removed by a chemical mechanical polishing process until the sacrificial posts are exposed, as shown in fig. 3 e.

Step five: as shown in fig. 3f, after removing the blocking layer until the sacrificial post is exposed, a second stacked structure is formed on the surface of the first stacked structure, a third through hole penetrating the second stacked structure is formed until the sacrificial post is exposed, and a fourth through hole penetrating the second stacked structure is formed until the support post is exposed.

Step six: as shown in fig. 3g, an etchant is injected through the third via hole to remove the sacrificial post; and then, forming a first isolation layer covering the side wall and the bottom of the first through hole, forming a second isolation layer covering the side wall of the third through hole, and forming a third isolation layer covering the side wall and the bottom of the fourth through hole.

It is understood that the first, second and third spacers may be identical in structure. Specifically, the first isolation layer may include, along the first via sidewall toward the first via center: the charge blocking layer, the charge storage layer, the tunneling layer and the protective layer.

Illustratively, the group layer material of the charge blocking layer may include an oxide (O), such as silicon oxide. The structure of the charge storage layer may include nitride (N), such as silicon nitride. The constituent material of the tunneling layer may include an oxide (O), such as silicon oxide. The constituent material of the protective layer may include polysilicon (S). As such, the isolation layer may comprise a SONO structure.

Step seven: referring to fig. 3h, a portion of the third isolation layer covering the support pillars is etched, and a portion of the first isolation layer covering the first epitaxial layer is etched until the first epitaxial layer is exposed.

Referring to fig. 3h, a dashed line frame near the first epitaxial layer shows a connection region between the first epitaxial layer and the first isolation layer after etching a portion of the first isolation layer; the dashed box near the top of the support pillar shows the connection area of the support pillar and the fourth via after etching part of the third isolation layer.

Illustratively, a first channel layer subsequently formed in the first via may be electrically connected to the first epitaxial layer by etching a portion of the first isolation layer overlying the first epitaxial layer until the first epitaxial layer is exposed.

As shown in fig. 3f, the fourth via may penetrate through the dielectric structure in the second stacked structure. It should be noted that, because the fourth via is not in contact with the stacked structure in the second stacked structure, the stacked structure in the first stacked structure or the second stacked structure is not damaged during etching the portion of the third isolation layer covering the support pillar, and the probability of short circuit of the memory due to damage to the isolation layer can be reduced.

Step eight: as shown in fig. 3i, after the first epitaxial layer is exposed, a first channel layer is formed in the first via, a second channel layer is formed in the third via, and a third channel layer is formed in the fourth via.

Illustratively, the channel layer and the protective layer are made of the same material and are both conductive materials. Therefore, the protective layer is not distinguished from the channel layer in fig. 3 i.

The first channel pillar in the first via may include a first isolation layer and a first channel layer, the second channel pillar in the third via may include a second isolation layer and a second channel layer, and the third channel pillar in the fourth via may include a third isolation layer and a third channel layer.

It is to be noted that the first channel pillar and the second channel pillar may be channel pillars for charge storage, and the third channel pillar may include a dummy channel pillar for supporting without charge storage.

In the related art, it is necessary to form dummy channel pillars in the second via holes as well for support. Since the fabrication process of the dummy trench pillar is the same as that of the trench pillar, the SONO structure covering the second epitaxial layer in the second via hole needs to be etched.

Because the characteristic dimension of the virtual channel hole is larger than that of the channel hole, and the alignment precision of the fourth through hole and the second through hole is lower than that of the first through hole and the third through hole, when the SONO structure covering the second epitaxial structure is etched in the related art, the SONO structure covering the side wall of the second through hole can be etched, even the first dielectric layer and/or the second dielectric layer in the first stacked structure of the side wall of the second through hole are/is etched, so that the conductive material of the virtual channel column in the second through hole is in direct contact with the first stacked structure.

Since the second via hole penetrates through the first dielectric layer and the second dielectric layer of the first stacked structure, the subsequent control gate may be contacted by the conductive material in the dummy channel pillar in the second via hole, which may cause problems such as electric leakage. Alternatively, adjacent gate dielectrics may contact through the conductive material in the dummy channel pillar, causing problems such as shorts and the like, causing the memory to fail.

Since the aperture of the top opening of the first through hole in the core region is smaller than the aperture of the top opening of the second through hole in the step region, in the process of depositing the first material in the first through hole, the second through hole and the surface of the stacked structure, the second through hole is still not filled when the top opening of the first through hole is closed by the first material, so that the subsequently deposited first material can cover the surface of the sacrificial post. And then, a barrier layer can be formed by using the first material covering the first stacking surface to prevent a preset reactant from reacting with the sacrificial column in the first through hole, so that the first material forming the sacrificial column is prevented from being converted into the material forming the support column.

Moreover, since the chemical reaction between the support pillar and the etchant for removing the sacrificial pillar is inert, the present example can remove the sacrificial pillar while retaining the support pillar in the second via without additionally forming a dummy channel pillar for supporting in the second via, thereby reducing damage to a portion of the first stacked structure located on the sidewall of the second via when forming the dummy channel pillar in the second via, which is beneficial for reducing the probability of short circuit in the first gate stacked structure formed based on the first stacked structure.

In addition, when the third channel column is formed in the fourth through hole subsequently, the support column can protect part of the first stacking structure on the side wall of the second through hole, so that the rejection rate or the reject ratio caused by short circuit is reduced, and the product yield is improved.

Fig. 4 is a schematic diagram illustrating a memory 100 in accordance with an exemplary embodiment. Illustratively, the memory 100 may be fabricated by applying the method provided by the embodiments of the present disclosure. Referring to fig. 4, the memory 100 includes:

a first gate stack structure 111 and a second gate stack structure 112 arranged in a stacked manner; the first gate stack structure 111 includes: the core area and the step area are arranged in parallel;

an insulating support pillar 120 penetrating the step region of the first gate stack structure 111;

a channel structure comprising:

a first channel pillar 121 penetrating a core region of the first gate stack structure 111;

a second channel pillar 122 penetrating the second gate stack 112 and connected to the first channel pillar 121;

a third trench pillar 123 penetrating the second gate stack 112 and connected to the support pillar 120;

the support pillar 120 has a different composition structure from that of the channel structure.

Illustratively, in the manufacturing process of the memory 100, the first gate stack structure 111 may be formed based on the first stack structure by removing the second dielectric layer in the first stack structure, forming a gap between adjacent first dielectric layers, and filling the gap with a conductive metal to form a gate layer.

It is understood that when the first gate stack structure 111 is formed, the core region of the first gate stack structure 111 is located at the same position as the core region of the first stack structure, and the step region of the first gate stack structure 111 is located at the same position as the step region of the first stack structure.

Illustratively, the constituent material of the support pillars 120 may include an oxide. Such as silicon dioxide.

The first, second, and

third channel pillars

121, 122, and 123 may have the same composition structure. Specifically, the first channel column 121 may include, in a radial direction of the first channel column, from a sidewall of the first channel column 121 toward a center of the first channel column 121: a charge blocking layer, a charge tunneling layer, a memory layer, and a channel layer.

The second channel pillar 122 may include, in a radial direction of the second channel pillar 122, from a sidewall of the second channel pillar 122 toward a center of the second channel pillar 122: a charge blocking layer, a charge tunneling layer, a memory layer, and a channel layer.

The third channel pillar 123 may include, in a radial direction of the third channel pillar 123, a sidewall of the third channel pillar 123 directed to a center of the third channel pillar 123: a charge blocking layer, a charge tunneling layer, a memory layer, and a channel layer.

Illustratively, the top dimension of the first channel pillar 121 is smaller than the top dimension of the support pillar 120.

The top dimensions may include: area of the top. When the top shape is circular, the top dimension may also include a top diameter or a top radius.

Illustratively, a first trench post 121 in the via hole formed after removal of the sacrificial post; wherein the chemical reaction between the etchant for removing the sacrificial post and the support post 120 is an inert reaction.

In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus, system, and method may be implemented in other ways. The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method for fabricating a memory, comprising:

carrying out chemical reaction on a preset reactant and the first material in the second through hole to form an insulating support pillar in the second through hole;

2. The method of claim 1, further comprising:

3. The method of claim 1, further comprising:

4. The method of claim 3, further comprising:

5. The method of claim 1, further comprising:

6. The method of claim 1,

the composition materials of the sacrificial column comprise: silicon;

the support column comprises the following components: silicon oxide;

the etching agent comprises: tetramethylammonium hydroxide TMAH.

7. A memory, comprising:

a channel structure comprising:

the first channel column penetrates through the core region of the first gate stack structure and is positioned in the through hole formed after the sacrificial column is removed; wherein, the chemical reaction between the etchant for removing the sacrificial columns and the supporting columns is an inert reaction;

the third channel column penetrates through the second gate stack structure and is connected with the supporting column; wherein the support pillar has a different composition structure from the channel structure.

8. The memory of claim 7,

the top size of the first channel column is smaller than that of the support column.