CN112635480B - Three-dimensional memory and manufacturing method thereof - Google Patents
Three-dimensional memory and manufacturing method thereof Download PDFInfo
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- CN112635480B CN112635480B CN202011167768.XA CN202011167768A CN112635480B CN 112635480 B CN112635480 B CN 112635480B CN 202011167768 A CN202011167768 A CN 202011167768A CN 112635480 B CN112635480 B CN 112635480B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The invention provides a three-dimensional memory and a manufacturing method thereof; the method comprises the following steps: providing a substrate structure; the base structure comprises at least: a first sub-stack structure; a plurality of rows of first sub-channel holes passing through the first sub-stacking structure; forming a first stop layer on an M-th row of first sub-channel holes among the plurality of rows of first sub-channel holes; m is a positive integer; forming a second sub-stacked structure on the first sub-stacked structure; forming a plurality of rows of second sub-channel holes in the second sub-stacked structure; wherein an M-th row of second sub-channel holes of the plurality of rows of second sub-channel holes extends into the first stop layer; the other second sub-channel holes except the M-th row of the multiple rows of the second sub-channel holes extend into the corresponding first sub-channel holes; at the position of the M-th row second sub-channel hole, a trench dividing a Top Select Gate (TSG) is formed.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a three-dimensional memory.
Background
The three-dimensional memory solves the limitation brought by a two-dimensional or planar flash memory by vertically stacking a plurality of layers of data storage units, supports the accommodation of higher storage capacity in a smaller space, and further effectively reduces the cost and the energy consumption. However, as the number of layers of the vertically stacked data storage units increases, it becomes more and more difficult to form the channel hole at a time by performing deep hole etching in the stacked structure. In practical application, the difficulty of the process for forming the channel hole at one time is reduced by adopting a manufacturing method of sub-channel hole superposition. The manufacturing method for the sub-channel hole superposition specifically comprises the following steps: firstly, planning a stacking structure of a three-dimensional memory into a plurality of sub-stacking structures, and correspondingly planning a channel hole into a plurality of sub-channel holes aiming at the plurality of sub-stacking structures; and then, in the process of manufacturing the three-dimensional memory, etching the sub-stacking structure at the bottommost layer to form a bottommost sub-channel hole penetrating through the sub-stacking structure at the bottommost layer, sequentially forming a sub-stacking structure at a second layer and a sub-channel hole at the second layer on the sub-stacking structure at the bottommost layer, sequentially forming a sub-stacking structure at a third layer and a sub-channel hole at the third layer on the sub-stacking structure at the second layer and the sub-channel hole at the second layer, and repeating the method until a final stacking structure and a final channel hole are formed. And when the sub-channel holes are superposed, the sub-channel holes in each sub-stack structure are communicated, and all the communicated sub-channel holes form a final channel hole together.
However, the final channel hole formed by the sub-channel hole overlay method in the related art has a risk of leakage in the subsequent process.
Disclosure of Invention
In order to solve the related technical problems, embodiments of the present invention provide a three-dimensional memory and a method for manufacturing the same.
The embodiment of the invention provides a method for manufacturing a three-dimensional memory, which comprises the following steps:
providing a substrate structure; the base structure comprises at least: a first sub-stack structure; a plurality of rows of first sub-channel holes passing through the first sub-stacking structure;
forming a first stop layer on an M-th row of first sub-channel holes among the plurality of rows of first sub-channel holes; m is a positive integer;
forming a second sub-stacked structure on the first sub-stacked structure;
forming a plurality of rows of second sub-channel holes in the second sub-stacked structure; wherein an M-th row of second sub-channel holes of the plurality of rows of second sub-channel holes extends into the first stop layer; the other second sub-channel holes except the M-th row of the multiple rows of second sub-channel holes extend into the corresponding first sub-channel holes; at the position of the M-th row second sub-channel hole, a trench dividing a Top Select Gate (TSG) is formed.
In the above solution, the material of the first stop layer includes tungsten or aluminum oxide.
In the foregoing aspect, the forming a first stop layer on an M-th row of first sub-channel holes among the plurality of rows of first sub-channel holes includes:
forming a first groove on the surface of the M row of first sub-channel holes;
and filling a first material in the first groove to form the first stop layer.
In the foregoing solution, the diameter width of the first trench is greater than the diameter width of the top of each first sub-channel hole in the mth row of first sub-channel holes.
In the above aspect, the base structure further includes: a first sacrificial layer in the rows of first sub-channel holes;
the method further comprises the following steps:
removing the first sacrificial layer; wherein, in the process of removing the first sacrificial layer, the first sacrificial layer in the M-th row of first sub-channel holes is not removed;
forming a memory material layer, wherein the memory material layer covers the side wall of the second sub-channel hole in the Mth row and the top surface of the first stop layer, and covers the side wall and the bottom surface of the communicated first sub-channel hole and the second sub-channel hole;
etching the memory material layer to remove the memory material layer covering the top surface and the bottom surface;
and filling a dielectric material.
In the above aspect, the base structure further includes: a plurality of rows of dummy first sub-channel holes passing through the first sub-stacked structure;
when the first stop layer is formed on the mth row of first sub-channel holes among the plurality of rows of first sub-channel holes, the method includes:
forming a second stop layer on the plurality of rows of dummy first sub-channel holes;
when a plurality of rows of second sub-channel holes are formed in the second sub-stacked structure, the method includes:
forming a plurality of rows of dummy second sub-channel holes in the second sub-stacked structure; wherein the plurality of rows of dummy second sub-channel holes each extend into the corresponding second stop layer.
An embodiment of the present invention further provides a three-dimensional memory, including:
a first sub-stack structure;
a plurality of rows of first sub-channel holes passing through the first sub-stacking structure;
a first stop layer on an M-th row of first sub-channel holes among the plurality of rows of first sub-channel holes; m is a positive integer;
a second sub-stack structure on the first sub-stack structure;
a plurality of rows of second sub-channel holes in the second sub-stacked structure; wherein an M-th row of second sub-channel holes of the plurality of rows of second sub-channel holes extends into the first stop layer; all the other second sub-channel holes except the M row of the second sub-channel holes in the multiple rows extend into the corresponding first sub-channel holes; at the position where the second sub-channel hole of the mth row is located, a trench dividing the top selection gate TSG is formed.
In the above scheme, the material of the first stop layer includes tungsten or aluminum oxide.
In the above solution, a diameter width of the first trench for forming the first stop layer is larger than a top diameter width of each first sub-channel hole in the M-th row of first sub-channel holes.
In the above solution, the three-dimensional memory further includes:
the first sacrificial layer is positioned in the M row of first sub-channel holes;
a memory material layer; the memory material layer covers the side wall of the M-th row of second sub-channel holes and covers the side walls of the communicated first sub-channel holes and second sub-channel holes;
and the dielectric material is positioned in the M-th row of second sub-channel holes and the communicated first sub-channel holes and second sub-channel holes.
In the above solution, the three-dimensional memory further includes:
a plurality of rows of dummy first sub-channel holes passing through the first sub-stacked structure;
a second stop layer on the plurality of rows of dummy first sub-channel holes;
a plurality of rows of dummy second sub-channel holes in the second sub-stacked structure; wherein the plurality of rows of dummy second sub-channel holes extend into the corresponding second stop layers. The embodiment of the invention provides a three-dimensional memory and a manufacturing method thereof; the method comprises the following steps: providing a substrate structure; the base structure comprises at least: a first sub-stack structure; a plurality of rows of first sub-channel holes passing through the first sub-stacking structure; forming a first stop layer on an M-th row of first sub-channel holes among the plurality of rows of first sub-channel holes; m is a positive integer; forming a second sub-stacked structure on the first sub-stacked structure; forming a plurality of rows of second sub-channel holes in the second sub-stacked structure; wherein an M-th row of second sub-channel holes of the plurality of rows of second sub-channel holes extends into the first stop layer; the other second sub-channel holes except the M-th row of the multiple rows of the second sub-channel holes extend into the corresponding first sub-channel holes; and a groove for dividing the TSG is formed at the position of the second sub-channel hole of the Mth row. It can be understood that, in the process of forming the channel holes, since the trenches for dividing the TSG need to be formed in an overlapping manner at the mth row channel holes, based on this, when the mth row channel holes are etched, the probability of deformation occurring at the mth row channel holes is greater than the probability of deformation occurring at the other row channel holes. In the embodiment of the invention, the stop plug (i.e. the first stop layer) is arranged at the top of the mth row first sub-channel hole, and the communication between the mth row first sub-channel and the mth row second sub-channel is cut off through the stop plug, so as to prevent the influence of the deformation of the mth row second sub-channel on the mth row first sub-channel, thereby preventing the memory material layer on the sidewall of the mth row first sub-channel from being damaged, and preventing the electric leakage caused by the conduction between the polysilicon filled in the sidewall of the mth row first sub-channel and the gate dielectric filled in the stacked structure in the subsequent process. Therefore, the risk of leakage of the channel hole in the subsequent manufacturing process can be reduced.
Drawings
FIG. 1a is a schematic diagram of a two-dimensional distribution of channel holes in a three-dimensional memory according to an embodiment of the present invention;
FIG. 1b is a cross-sectional view of a semiconductor structure with a separation TSG formed in a three-dimensional memory according to an embodiment of the present invention;
fig. 1c is a roundness of a channel hole in a three-dimensional memory observed under an electron microscope according to an embodiment of the present invention;
FIG. 1d is a graph illustrating an average roundness value of each of nine rows of channel holes obtained by two different manufacturing methods according to an embodiment of the present invention;
fig. 2 is a first flowchart illustrating an implementation of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention;
FIGS. 3a-3e are schematic process diagrams of a method for manufacturing a three-dimensional memory according to an embodiment of the invention;
FIGS. 4a-4e are schematic diagrams illustrating a process of fabricating a first stop layer according to an embodiment of the present invention;
fig. 5a-5d are schematic process diagrams of a method for filling a dummy trench hole according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating statistical results of inspecting the punch-through of a channel hole in each die on a wafer by black box inspection according to an embodiment of the present invention;
FIG. 7 is a second flowchart illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present invention;
fig. 8a to 8d-2 are schematic process diagrams illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the invention.
Description of the reference numerals:
10-a base structure; 110-a first sub-stack structure; 111-a first material layer; 112-a second material layer; 120-a first sub-channel hole; 120 a-the mth row of first sub-channel holes of the first sub-channel holes; 120 b-other rows of second sub-channel holes of the first sub-channel holes except the M-th row of first sub-channel holes; 130-a first stop layer; 140-a first sacrificial layer; 210-a second sub-stack structure; 220-second sub-channel hole; 220 a-the mth row of first sub-channel holes among the second sub-channel holes; 220 b-other rows of second sub-channel holes than the M-th row of first sub-channel holes; 120' -a dummy first sub-channel hole; 130' -a second stop layer; 220' -a dummy second sub-channel hole.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the following describes specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention.
Three-dimensional memory technologies have significantly increased the number of gate layers in the vertical direction perpendicular to the substrate towards high density and high capacity transfers, such as the transfer of three-dimensional NAND type memories from 64-layer to 128-layer architectures and even more. The increased number of gate layers results in a significant increase in block size for three-dimensional NAND types, which in turn leads to longer read and erase times, longer data transfer times, and lower memory efficiency.
To address the problem of low storage efficiency, the TSG is divided into a plurality of sub-TSGs by one or more trenches, thereby dividing each block into a plurality of sub-blocks. Each sub-block has a corresponding sub-TSG, and each sub-block can be individually operated by controlling the corresponding sub-TSG.
In some embodiments, as shown in the block of fig. 1a, the three-dimensional memory may include a plurality of rows of channel holes, wherein each nine rows of the plurality of rows of channel holes include a Gate Line Slit (GLS) therein, and a trench separating the TSG is superimposed at a position of a fifth row of the nine rows of channel holes.
In some embodiments, a three-dimensional memory includes a plurality of channel holes therein, and forming the channel holes includes: forming a first sub-stack structure on a substrate; forming a first sub-channel hole in the first sub-stack layer; filling polysilicon in the first sub-channel hole to form a first sacrificial layer; forming a second sub-stacked structure on the first sub-stacked structure; forming a TSG on the second sub-stacked structure; etching the TSG and part of the second sub-stacked structure to form a groove so as to separate the TSG; the first sub-stacking structure and the second sub-stacking structure respectively comprise a plurality of first material layers and a plurality of second material layers which are arranged at intervals; when forming the groove for separating the TSG, the groove extends to the first material layer and the second material layer which are arranged at the three layers of the second sub-stack structure; filling trenches separating the TSGs with oxide (where the semiconductor structure is formed as shown in fig. 1 b); forming a second sub-channel hole in the second sub-stacked structure; wherein the second sub-channel holes are communicated with the corresponding first sub-channel holes; a second sub-channel hole is also formed at a position where a groove separating the TSG is formed.
It is understood that the TSG cut trench is located in the fifth row region of the channel, and the trench filling oxide causes the second sub-channel holes at the fifth row position to be deformed and locally inclined more severely than the other rows of the second sub-channel holes. As shown in fig. 1c, the second sub-channel holes at the fifth row region position were observed to have an elliptical shape under microscope observation, and were significantly less in roundness than the second sub-channel holes of the other rows. As shown in fig. 1d, the roundness values of the nine rows of channel holes of the three-dimensional memory are counted, and the roundness value of the fifth row of channel holes is the worst.
At this time, when the first sub-channel hole and the second sub-channel hole which are communicated with each other are collectively subjected to the punch-through process, the memory material layer on the sidewall of the fifth row of channel holes is easily broken. In the subsequent process, the polysilicon filled in the side wall of the fifth row of channel holes is conducted with the gate dielectric filled in the stacked structure after the sacrificial layer is removed, and because the interior of the fifth row of channel holes has a structure consistent with that of other rows of channel holes, each layer of the stacked structure is filled with the gate dielectric, namely the polysilicon at the superposed position of the two sub-stacked structures in the fifth row of channel holes is conducted with the gate dielectric at the superposed position of the two sub-stacked structures in the channel holes, at the moment, when voltage is applied to the gate dielectric in the other rows of channel holes, the polysilicon in the fifth row of channel holes is also electrified, so that the phenomenon of electric leakage occurs.
Therefore, in various embodiments of the present invention, the stop plug is disposed at the top of the mth row first sub-channel hole, and the communication between the mth row first sub-channel and the mth row second sub-channel is cut off by the stop plug, so as to prevent the influence of the deformation of the mth row second sub-channel on the mth row first sub-channel, thereby preventing the memory material layer on the sidewall of the mth row first sub-channel from being damaged, and preventing the leakage caused by the conduction between the polysilicon filled in the sidewall of the mth row first sub-channel and the gate dielectric filled in the stacked structure in the subsequent process. Therefore, the risk of leakage of the channel hole in the subsequent manufacturing process can be reduced.
An embodiment of the invention provides a method for manufacturing a three-dimensional memory, and fig. 2 is a schematic flow chart of the method for manufacturing the three-dimensional memory according to the invention. As shown in fig. 2, the method comprises the steps of:
step 201: providing a substrate structure; the base structure comprises at least: a first sub-stack structure; a plurality of rows of first sub-channel holes passing through the first sub-stacking structure;
step 202: forming a first stop layer on an M-th row of first sub-channel holes among the plurality of rows of first sub-channel holes; m is a positive integer;
step 203: forming a second sub-stacked structure on the first sub-stacked structure;
step 204: forming a plurality of rows of second sub-channel holes in the second sub-stack structure; wherein an Mth row of second sub-channel holes of the plurality of rows of second sub-channel holes extends into the first stop layer; the other second sub-channel holes except the M-th row of the multiple rows of second sub-channel holes extend into the corresponding first sub-channel holes; and a groove for dividing the TSG is formed at the position of the second sub-channel hole of the Mth row.
FIGS. 3a-3e are schematic views illustrating a three-dimensional memory manufacturing process according to an embodiment of the invention. The formation process of the three-dimensional memory of the present embodiment is described below with reference to fig. 5a to 5 d.
In step 201, referring to fig. 3a, the substrate structure 10 at least includes the first sub-stack structure 110 and the first sub-channel hole 120.
In practice, the method for manufacturing the substrate structure 10 in the practice of the present invention may include the following steps:
step 201 a: forming a first sub-stack structure 110;
step 201 b: a first sub-channel hole 120 is formed through the first sub-stacked structure 110, resulting in the base structure 10.
In step 201a, the first sub-stack structure 110 may be formed on a substrate during actual application. Here, the substrate may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one organic semiconductor material, or other semiconductor materials known in the art.
The first sub-stacked structure 110 includes a plurality of first material layers 111 and second material layers 112 arranged at intervals; the first material layer 111 may also be referred to as a dielectric layer, and the material of the first material layer 111 includes, but is not limited to, one or more of a silicon oxide layer and a silicon carbide layer; the second material layer 112 may also be referred to as a dummy gate layer or a sacrificial layer, and the material of the second material layer 112 includes, but is not limited to, one or more of a silicon nitride layer and a silicon oxynitride; in a subsequent process, the second material layer 112 may be removed and filled with a gate material (e.g., metal tungsten (W)) at the removed position, and after the gate material is filled, the corresponding position of the second material layer is referred to as a gate layer (this process is also referred to as a gate-last process). In some embodiments, the first material layer 111 may be made of silicon oxide (SiO)2) Forming; the second material layer 112 may be formed of silicon nitride (SiN), so that the first sub-stack structure 110 formed is a nitride-oxide (NO) stack. In practical applications, the first material Layer 111 and the second material Layer 112 may be formed by a Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD); the first material layer 111 and the second material layer 112 may have the same thickness as each other, or may have different thicknesses from each other.
In step 201b, the first sub-channel hole 120 may include two types of sub-channel holes; wherein the first type of sub-channel holes include an M-th row of first sub-channel holes 120a among the first sub-channel holes 120, and the second type of sub-channel holes include other rows of second sub-channel holes 120b except the M-th row among the first sub-channel holes 120. Here, in some embodiments, the first-type sub-channel holes may be nine rows of first sub-channel holesThe fifth row of the first sub-channel holes 120a of the channel holes 120, and the second type of the sub-channel holes may be specifically the first to fourth rows of the nine rows of the first sub-channel holes 120 and the sixth to ninth rows of the first sub-channel holes 120 b. In practical applications, the cross-sectional shape of the first sub-channel hole 120 may include a circle, a square, or the like. In practical applications, the first sub-channel hole 120 may be formed by a dry etching process. In some embodiments, the dry etching may be plasma etching, and the etching gas may be CF4Etc., or other etching gases known in the art that may be used to etch the first material layer 111 and the second material layer 112.
In practical applications, the substrate structure 10 may further include an epitaxial layer or the like located at the bottom of the first sub-channel hole 120. The epitaxial layer is used for electrically connecting the channel layer in the channel hole with the well region in the substrate.
It should be noted that only the case where the base structure 10 includes only one layer of sub-channel holes is described here. In practical applications, the substrate structure 10 may further include a sub-stack structure and a plurality of sub-channel holes, and when the number of the sub-channel holes is greater than two, other sub-stack structures and sub-channel holes stacked below the first sub-stack structure 110 and the first sub-channel hole 120 exist.
In step 202, referring to fig. 3b, the first stop layer 130 is formed on the mth row first sub-channel hole 120a among the plurality of rows of first sub-channel holes 120.
Here, the mth row first sub-channel hole 120a is a specific one or more rows of the plurality of rows of first sub-channel holes 120, and the divided grooves are overlapped at a portion of the mth row second sub-channel hole above the mth row first sub-channel hole 120a, and thus, the mth row second sub-channel hole has a poor geometrical specification degree, such as a poor roundness. It should be noted that the mth row channel hole (including the mth row first sub-channel hole 120a and the subsequent mth row second sub-channel hole 220a) is not used for storing data.
In practical applications, in some embodiments, the manufacturing method of forming the first stop layer on the mth row of the first sub-channel holes in the plurality of rows of the first sub-channel holes may include:
step 202 a: forming a first trench on a surface of the M-th row first sub-channel hole 120 a;
step 202 b: the first trench is filled with a first material to form the first stop layer 130.
Fig. 4a-4e are schematic views illustrating a process of fabricating the first stop layer 130 according to an embodiment of the invention. The formation process of the first stop layer 130 of the present embodiment is described below with reference to fig. 4a to 4 e.
In step 202a, referring to fig. 4a first, a first mask is formed on the surface of the M-th row first sub-channel hole 120a, the geometric center of the pattern in the first mask is the same as the geometric center of the pattern in the second mask when the M-th row first sub-channel hole 120a is formed, but considering that there may be an offset in the radial direction of the sub-channel hole between the M-th row second sub-channel hole 220b and the M-th row first sub-channel hole 120b, the size of the pattern in the first mask is larger than that of the pattern in the second mask, and in practical applications, the size of the larger pattern cannot affect the size of the adjacent sub-channel hole. In practical applications, the first mask may include a carbon layer, a silicon oxynitride (SiON) layer, and a Photoresist (PR) sequentially disposed along a stacking direction of the first sub-stack structure
Referring next to fig. 4b, photolithography is performed according to the first mask.
Referring next to fig. 4c, the first mask is removed, forming a first trench. It is understood that the width of the first trench is greater than the width of the top of each first sub-channel hole in the mth row of first sub-channel holes. Here, the radial width of the first trench may be understood as a width dimension of the first trench opening in the radial direction of the sub-channel hole; the top diameter width of each first sub-channel hole in the mth row of first sub-channel holes may be understood as the width of the top opening of each first sub-channel hole along the radial direction of the sub-channel hole.
In step 202b, referring to fig. 4d, a first material is deposited in the first trench, forming a first material layer. The first material may be deposited by a process such as CVD or ALD. In some embodiments, the first material, i.e., the material of the first stop layer, may comprise tungsten or aluminum oxide.
In practical applications, referring to fig. 4e, the top surface of the first material layer needs to be polished to make the top surface of the first stop layer 130 flush with the surface of the first sub-stack structure 110. In practical applications, the top surface of the first material layer may be polished by Chemical Mechanical Polishing (CMP).
It is to be understood that, when the three-dimensional memory in the embodiment of the present invention includes only two stacked sub-channel holes, the first stop layer may be disposed at a position between the M-th row two stacked sub-channel holes; when the three-dimensional memory in the embodiment of the present invention includes two or more stacked sub-channel holes, the first stop layer may be disposed at a position between the sub-channel hole of the M-th row of the uppermost layer stack and the sub-channel hole of the next-to-uppermost layer stack adjacent to the sub-channel hole of the uppermost layer stack.
In step 203, referring to fig. 3c, a second sub-stacked structure 210 is formed covering the first sub-stacked structure 110. In practical applications, the total height of the second sub-stack structure 120 may be the same as or different from the total height of the first sub-stack structure 110. In practice, the process of forming the second sub-stacked structure 210 on the first sub-stacked structure 110 is similar to the process of forming the first sub-stacked structure 110 on the substrate in step 201 a. The composition, material, forming process, etc. of the second sub-stacked structure 210 are the same as those of the first sub-stacked structure 110.
In step 204, referring to fig. 3d, a second sub-channel hole structure 220 is formed in the second sub-stacked structure 210 and at a corresponding position above each of the first sub-channel holes 120. Correspondingly, the second sub-channel holes 220 may include two types of sub-channel holes, i.e., a third type sub-channel hole and a fourth type sub-channel hole; wherein the third type of sub-channel hole includes an M-th row of second sub-channel holes 220a in the second sub-channel holes 220, and the fourth type of sub-channel hole includes other rows of second sub-channel holes 220b except the M-th row in the second sub-channel holes 220. Here, in some embodiments, the third type of sub-channel hole may be a fifth row of second sub-channel holes 220a of the nine rows of second sub-channel holes 220, and the fourth type of sub-channel hole may be first to fourth and sixth to ninth rows of second sub-channel holes 220b of the nine rows of second sub-channel holes 220. In practice, the process of forming the second sub-channel hole 220 on the second sub-stacked structure 210 is similar to the process of forming the first sub-channel hole 120 in the first sub-stacked structure 110 in step 201 b.
It should be noted that the bottom of each M-th row of second sub-channel holes 220a extends into the first stop layer 130 above each corresponding M-th row of first sub-channel holes 120a, that is, each M-th row of second sub-channel holes 220a and each corresponding M-th row of first sub-channel holes 120a are separated by the corresponding first stop layer and are not conducted; and the bottom of the second sub-channel holes 220b of the other rows than the mth row in each second sub-channel hole 220 extends into each corresponding first sub-channel hole 120b, i.e., each second sub-channel hole 220b communicates with each corresponding first sub-channel hole 120 b.
In practical applications, the substrate structure 10 may further include a first sacrificial layer 140, and the first sacrificial layer 140 is located in the first sub-channel hole 120. After the step 201b, the method for manufacturing the base structure 10 further includes:
step 201 c: forming a first sacrificial layer 140 in the first sub-channel hole 120;
step 201 d: polishing the top surface of the first sacrificial layer 140; the top surface of the first sacrificial layer 140 is flush with the top surface of the first sub-stack structure 110.
In step 201c, the first sacrificial layer 140 plays a role of supporting when forming the second sub-stacked structure 210 on the first sub-stacked structure 110 and the first sub-channel hole 120 in practical application. The first sacrificial layer 140 may be formed by a CVD or ALD process, and the material of the first sacrificial layer 140 may include polysilicon.
In step 201d, in practical applications, the top surface of the first sacrificial layer 140 needs to be polished to enable the second sub-stack 150 to grow on a flat structure surface. In practical applications, the top surface of the first sacrificial layer 140 may be polished by CMP.
In practical applications, after step 204, a memory layer is formed in the trench hole, and the method includes:
step a: removing the first sacrificial layer 140; wherein, in the process of removing the first sacrificial layer 140, the first sacrificial layer in the mth row of first sub-channel holes 120a is not removed;
step b: forming a memory material layer covering sidewalls of the M-th row of second sub-channel holes 120a and a top surface of the first stop layer 130, and covering sidewalls and a bottom surface of the connected first and second sub-channel holes 120 and 220;
step c: etching the memory material layer to remove the memory material layer covering the top surface and the bottom surface;
step d: and filling a dielectric material.
In step a, it can be understood that the first sacrificial layer in the mth row of first sub-channel holes 120a in the first sub-channel holes 120 is not removed due to the first stop layer 130, and the first sacrificial layers in the other rows of first sub-channel holes 120b except for the mth row in the first sub-channel holes 120 are all removed. In practical applications, the first sacrificial layer 140 may be removed by wet etching. Here, the wet etching may be performed using a developer, such as tetramethylammonium hydroxide (TMAH).
In step b, the process of forming the memory material layer in the channel hole may include: and sequentially forming a blocking layer, a charge capturing layer, a tunneling layer and a channel layer from outside to inside along the radial direction of the first channel hole and the second channel hole, wherein the blocking layer covers the side wall surfaces of the first channel hole and the second channel hole, the charge capturing layer covers the surface of the blocking layer, the tunneling layer covers the surface of the charge capturing layer, and the channel layer covers the surface of the tunneling layer to form an ONOP (oxide-nitride-oxide-polysilicon) structure. The blocking layer is used for blocking the charge in the memory layer from flowing out; the charge trapping layer is used for trapping and storing charges; the tunneling layer is used for generating charges; the channel layer is used for supporting. In practical applications, the memory material layer may be formed by a CVD or ALD process. In practical applications, the first sacrificial layer 140 remains in the mth row of the first sub-channel holes 120a, the memory material layer is formed in the mth row of the second sub-channel holes 220b, and the memory material layer is formed in each of the connected first sub-channel holes 120b and the second sub-channel holes 220 b.
In step c, the bottom of the memory material layer is mainly processed by punch-through to obtain the memory layer. In practical applications, the punch-through process may be implemented by dry etching. In practical applications, as shown in fig. 3e, the first sacrificial layer 140 remains in the M-th row of the first sub-channel hole 120a, the memory layer is formed in the M-th row of the second sub-channel hole 220b, and the memory layer is formed in the connected first sub-channel hole 120b and the second sub-channel hole 220 b.
In step d, in practical applications, the dielectric material may serve as a support and an insulator, and the dielectric material may include silicon oxide. In practical applications, the filling of the dielectric material may be achieved by a CVD or ALD process. In practical applications, as shown in fig. 3e, the first sacrificial layer 140 remains in the M-th row of first sub-channel holes 120a, while the M-th row of second sub-channel holes 220b is filled with the dielectric material, and the connected first sub-channel holes 120b and second sub-channel holes 220b are filled with the dielectric material.
The embodiment of the invention provides a manufacturing method of a three-dimensional memory, and the embodiment of the invention provides a three-dimensional memory and a manufacturing method thereof; the method comprises the following steps: providing a substrate structure; the base structure comprises at least: a first sub-stacking structure; a plurality of rows of first sub-channel holes passing through the first sub-stacking structure; forming a first stop layer on an M-th row of first sub-channel holes among the plurality of rows of first sub-channel holes; m is a positive integer; forming a second sub-stacked structure on the first sub-stacked structure; forming a plurality of rows of second sub-channel holes in the second sub-stacked structure; wherein an M-th row of second sub-channel holes of the plurality of rows of second sub-channel holes extends into the first stop layer; the other second sub-channel holes except the M-th row of the multiple rows of second sub-channel holes extend into the corresponding first sub-channel holes; and a groove for dividing the TSG is formed at the position of the second sub-channel hole of the Mth row. It can be understood that, in the process of forming the channel holes, since the trenches for dividing the TSG need to be formed in an overlapping manner at the mth row channel holes, based on this, when the mth row channel holes are etched, the probability of deformation occurring at the mth row channel holes is greater than the probability of deformation occurring at the other row channel holes. In the embodiment of the invention, the stop plug is arranged at the top of the M-th row first sub-channel hole, and the communication between the M-th row first sub-channel and the M-th row second sub-channel is cut off through the stop plug, so that the influence of the deformation of the M-th row second sub-channel on the M-th row first sub-channel is prevented, the memory material layer on the side wall of the M-th row first sub-channel can be prevented from being damaged, and the electric leakage caused by the conduction of polycrystalline silicon filled in the side wall of the M-th row first sub-channel and a gate dielectric filled in a stacked structure in the subsequent process is also avoided. Therefore, the risk of leakage of the channel hole in the subsequent manufacturing process can be reduced.
In practical application, in the process of forming the control gate of the three-dimensional memory by adopting a gate-last process, when the sacrificial layer is removed and the gate dielectric is not filled, the whole device is supported by the channel hole, but as the number of layers of the data storage units vertically stacked in the height of the conventional three-dimensional memory is increased and the size of the channel through hole is gradually reduced, the supporting force of the channel through hole after the sacrificial layer is removed is insufficient, so that the collapse of the whole structure is easily caused, and the loss is caused.
In order to solve the problem of collapse of the whole structure after the sacrificial layer is removed, a dummy channel hole for supporting is generated. It is understood that the dummy channel hole and the channel hole only have different functions, and the manufacturing process of the dummy channel hole and the channel hole is identical, and the structure is also identical.
In some embodiments, the three-dimensional memory includes a plurality of channel holes and dummy channel holes, and the process of forming the channel holes and the dummy channel holes includes: forming a stacked structure on a substrate; forming a channel hole and a dummy channel hole in the stacked layers, respectively; wherein the channel hole and dummy channel hole pass through the stack structure and extend to the substrate; forming a conductive connection layer (also referred to as an epitaxial layer) at the bottom of the channel hole and the dummy channel hole; forming a memory material layer on the side walls of the channel holes and the dummy channel holes and the top surfaces of the conductive connecting layers at the bottoms of the channel holes and the dummy channel holes; etching (also called punch-through treatment) the memory material layer on the top surface of the conductive connection layer at the bottom of the channel hole and the dummy channel hole to expose the conductive connection layer at the bottom of the channel hole and the dummy channel hole through the memory material layer, so that the channel layer in the channel hole and the dummy channel hole is conducted with the conductive connection layer in the subsequent processing; and filling a channel medium in the channel hole and the dummy channel hole.
In order to solve the problem that deep hole etching is difficult due to the fact that the number of layers of a memory is too high, in some embodiments, a sub-stack structure with a certain number of stacked layers, such as 64 layers, is etched to form sub-channel holes penetrating through the sub-stack structure, then a plurality of layers of sub-stack structures are stacked (for example, two layers of sub-stack structures are stacked, a 128-layer stack structure can be formed), and the sub-channel holes in each sub-stack structure in the plurality of layers of sub-stack structures are ensured to be aligned and connected in the stacking process; these aligned connected sub-channel holes form the channel hole and the dummy channel hole. However, in practical applications, in the process of stacking two sub-stacked structures, in order to ensure complete alignment of the sub-channel holes in the channel holes, the accuracy of alignment of the sub-channel holes in the dummy channel holes is sacrificed, so that there is an offset in alignment between the multiple layers of dummy channel holes. In addition, there may be topography distortions of the dummy channel holes and poor alignment of the circuit patterns of the various layers required in photolithography, which may further offset the alignment between the multiple layers of dummy channel holes. At this time, when the channel hole and the dummy channel hole are subjected to the punch-through process together, the memory material layer on the side wall of the dummy channel hole is easily broken. When the memory material layer on the side wall of the nominal channel hole is damaged, in the subsequent process, the polycrystalline silicon filled in the nominal channel hole can be conducted with the grid medium filled in the stacked structure after the sacrificial layer is removed, and because the inside of the nominal channel hole has a structure consistent with that of the channel hole, each layer of the stacked structure is filled with the grid medium and is connected, namely the polycrystalline silicon at the superposed position of the two sub-stacked structures in the nominal channel hole is conducted with the grid medium at the superposed position of the two sub-stacked structures in the channel hole, at the moment, when voltage is applied to the grid medium at the superposed position of the two sub-stacked structures in the channel hole, the polycrystalline silicon in the nominal channel hole can be electrified, and the phenomenon of electric leakage can occur.
Therefore, in the related art, the dummy trench hole is filled to reduce the risk of the leakage. Specifically, as shown in fig. 5a to 5d, before the channel hole and the dummy channel hole are processed through together, the dummy channel hole is filled with a filling material, and the filling material is consumed to avoid the etching effect on the memory material layer on the sidewalls of the dummy channel hole and the top surface of the conductive connection layer at the bottom of the dummy channel hole, so that the etching process only etches the memory material layer on the top surface of the conductive connection layer at the bottom of the channel hole, thereby ensuring that the memory material layer on the sidewalls of the dummy channel hole is not damaged, and avoiding the leakage caused by the conduction between the polysilicon filled in the dummy channel hole and the gate dielectric filled in the stacked structure in the subsequent process. Therefore, the risk of electric leakage of the dummy channel hole in the subsequent manufacturing process can be reduced.
However, in practical applications, the above filling method for the dummy trench holes, including the high aspect ratio process, has high requirements for tools, and it is difficult to ensure that all the trench holes are not filled and all the dummy trench holes are filled to a predetermined height, which may cause the situation that the punch-through process in the trench holes cannot be performed normally and the yield of the trench holes cannot be ensured. Fig. 6 shows statistical results of inspecting the punch-through of the channel holes in each die on the wafer by means of black box inspection (DVC). The difference in the punch-through of the channel hole is shown in fig. 6. It is considered that the dummy channel hole serves only as a support and not for storing data. Based on the same concept as the foregoing embodiment, instead of the above-described method of filling the dummy sub-channel holes, the dummy sub-channel holes may be filled with stop plugs, which block the connection between different layers of the dummy sub-channel holes, thereby preventing the influence of the deformation of the upper layer of the dummy sub-channel holes on the lower layer of the dummy sub-channel holes. The technological process is simple and convenient to realize, and the yield of the channel holes can be ensured.
Accordingly, the embodiment of the present invention further provides a method for manufacturing a three-dimensional memory, in which the substrate structure 10 further includes: a plurality of rows of dummy first sub-channel holes passing through the first sub-stack structure, as shown in fig. 7, the method of fabricating the three-dimensional memory includes:
step 701: providing a substrate structure; the base structure comprises at least: a first sub-stack structure; a plurality of rows of first sub-channel holes and dummy first sub-channel holes passing through the first sub-stacked structure;
step 702: forming a first stop layer on the M-th row of first sub-channel holes in the plurality of rows of first sub-channel holes, and forming a second stop layer on the plurality of rows of dummy first sub-channel holes; m is a positive integer;
step 703: forming a second sub-stacked structure on the first sub-stacked structure;
step 704: forming a plurality of rows of second sub-channel holes and dummy second sub-channel holes in the second sub-stacked structure; wherein an M-th row of second sub-channel holes of the plurality of rows of second sub-channel holes extends into the first stop layer; the other second sub-channel holes except the M-th row of the multiple rows of second sub-channel holes extend into the corresponding first sub-channel holes; the dummy second sub-channel holes of the multiple rows extend into the corresponding second stop layers; at the position where the second sub-channel hole of the mth row is located, a trench dividing the top selection gate TSG is formed.
FIGS. 8a, 8b-1, 8b-2, 8c-1, 8c-2, 8d-1, 8d-2 are schematic diagrams illustrating a process for fabricating a three-dimensional memory according to an embodiment of the invention. The formation process of the three-dimensional memory of the present embodiment is described below with reference to fig. 8a to 8 d-2.
In step 701, referring to fig. 8a, the substrate structure 10 at least includes the first sub-stack structure 110, the first sub-channel hole 120 and the dummy first sub-channel hole 120'. In some embodiments, the substrate structure 10 may further include a first sacrificial layer 140, the first sacrificial layer 140 being located in the first sub-channel hole and the dummy first sub-channel hole 120'. Meanwhile, the first sub-channel hole 120 includes two types of sub-channel holes; wherein the first type of sub-channel holes include an M-th row of first sub-channel holes 120a among the first sub-channel holes 120, and the second type of sub-channel holes include other rows of second sub-channel holes 120b except the M-th row among the first sub-channel holes 120. Here, in some embodiments, the first type of sub-channel hole may be specifically a fifth row of first sub-channel holes 120a among the nine rows of first sub-channel holes 120, and the second type of sub-channel hole may be specifically first to fourth and sixth to ninth rows of first sub-channel holes 120b among the nine rows of first sub-channel holes 120. The base structure 10 is formed in a manner similar to that described above in reference to 401 and will not be described in detail herein.
It should be noted that, in some embodiments, at least one side of the first sub-stacked structure 110 is formed with a step structure, a dielectric layer is formed on the step structure, and a portion of the dummy first sub-channel hole 120' may also be located in the first sub-stacked structure 110 formed with the step structure and the dielectric layer.
In step 702, referring to fig. 8b-1, a first stopper layer 130 is formed on the mth row of first sub-channel holes 120a among the plurality of rows of first sub-channel holes 120, and a second stopper layer 130 'is formed on the plurality of dummy first sub-channel holes 120'. Meanwhile, referring to fig. 8b-2, the first stopper layer 130 is formed on the M-th row of first sub-channel holes 120a among the plurality of rows of first sub-channel holes 120, and the other rows of second sub-channel holes 120b except for the M-th row among the plurality of rows of first sub-channel holes 120 do not form the stopper layer. The first stop layer 130 and the second stop layer 130' are formed in a manner similar to that described above at 402 and will not be described again.
In step 703, the second sub-stack structure 210 is formed in a manner similar to that in step 403, which is not described herein again.
In step 704, referring to fig. 8c-1, a plurality of rows of second sub-channel holes 220 and dummy second sub-channel holes 220' are formed in the second sub-stacked structure 210; wherein an mth row of second sub-channel holes 220a of the plurality of rows of second sub-channel holes extends into the first stop layer 130; the plurality of rows of dummy second sub-channel holes 220 'each extend into the corresponding second stop layer 130'. Meanwhile, referring to fig. 8c-2, the plurality of rows of dummy second sub-channel holes 220 'each extend into the corresponding second stop layer 130'; the other second sub-channel holes 220b of the plurality of rows of second sub-channel holes except for the mth row extend into the corresponding first sub-channel holes 120 b; the second sub-stack 210 is formed in a manner similar to that described above in 404, and thus will not be described in detail.
It is noted that, in some embodiments, a portion of the dummy first sub-channel hole 120' may also be located in the dielectric layer.
In the subsequent process, referring to fig. 8d-1, the first sacrificial layer remains in the mth row of first sub-channel holes 120a and the dummy first sub-channel holes 120 ', the memory layer is formed in the mth row of second sub-channel holes 220b and the dummy second sub-channel holes 220 ', and the dielectric material is filled in the mth row of second sub-channel holes 220b and the dummy second sub-channel holes 220 '. Meanwhile, referring to fig. 8d-2, the first sacrificial layer remains in the dummy first sub-channel hole 120 ', the memory layer is formed in the dummy second sub-channel hole 220 ', and the dummy second sub-channel hole 220 ' is filled with a dielectric material; the memory layer is formed in each of the connected first sub-channel hole 120b and the second sub-channel hole 220b, and the dielectric material is filled in each of the connected first sub-channel hole 120b and the second sub-channel hole 220 b.
In the embodiment of the invention, the stop plug is arranged at the top of the first dummy sub-channel hole, and the communication between the first dummy sub-channel and the second dummy sub-channel is cut off through the stop plug, so that the influence of the deformation of the second dummy sub-channel on the first dummy sub-channel is prevented, the memory material layer on the side wall of the first dummy sub-channel can be prevented from being damaged, and the electric leakage caused by the conduction of the polycrystalline silicon filled in the side wall of the first dummy sub-channel and the gate dielectric filled in the stacked structure in the subsequent process is avoided. Therefore, the risk of leakage of the channel hole in the subsequent manufacturing process can be reduced.
Based on the manufacturing method of the three-dimensional memory, an embodiment of the present invention further provides a three-dimensional memory, where the three-dimensional memory includes:
a first sub-stack structure;
a plurality of rows of first sub-channel holes passing through the first sub-stacking structure;
a first stop layer on an M-th row of first sub-channel holes among the plurality of rows of first sub-channel holes; m is a positive integer;
a second sub-stacking structure located on the first sub-stacking structure;
a plurality of rows of second sub-channel holes in the second sub-stacked structure; wherein an M-th row of second sub-channel holes of the plurality of rows of second sub-channel holes extends into the first stop layer; all the other second sub-channel holes except the M row of the second sub-channel holes in the multiple rows extend into the corresponding first sub-channel holes; at the position where the second sub-channel hole of the mth row is located, a trench dividing the top selection gate TSG is formed.
Wherein, in some embodiments, the material of the first stop layer comprises tungsten or aluminum oxide.
In some embodiments, a diameter width of the first trench for forming the first stop layer is larger than a top diameter width of each of the first sub-channel holes in the mth row of first sub-channel holes.
In some embodiments, the three-dimensional memory further comprises:
the first sacrificial layer is positioned in the M row of first sub-channel holes;
a memory material layer; the memory material layer covers the side wall of the M-th row of second sub-channel holes and covers the side walls of the communicated first sub-channel holes and second sub-channel holes;
and the plugs are positioned in the second sub-channel holes in the M row and the communicated first sub-channel holes and second sub-channel holes.
In some embodiments, the three-dimensional memory further comprises:
a plurality of rows of dummy first sub-channel holes passing through the first sub-stacked structure;
a second stop layer on the plurality of rows of dummy first sub-channel holes;
a plurality of rows of dummy second sub-channel holes in the second sub-stacked structure; wherein the plurality of rows of dummy second sub-channel holes extend into the corresponding second stop layers.
In practical applications, the three-dimensional memory in the embodiment of the invention may be a three-dimensional NAND-type memory.
It should be noted that: "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (11)
1. A method of fabricating a three-dimensional memory, the method comprising:
providing a substrate structure; the base structure comprises at least: a first sub-stack structure; a plurality of rows of first sub-channel holes passing through the first sub-stacking structure;
forming a first stop layer on an M-th row of first sub-channel holes among the plurality of rows of first sub-channel holes; m is a positive integer;
forming a second sub-stacked structure on the first sub-stacked structure;
forming a plurality of rows of second sub-channel holes in the second sub-stacked structure; wherein an M-th row of second sub-channel holes of the plurality of rows of second sub-channel holes extends into the first stop layer; the other second sub-channel holes except the M-th row of the multiple rows of second sub-channel holes extend into the corresponding first sub-channel holes; at the position where the second sub-channel hole of the mth row is located, a trench dividing the top selection gate TSG is formed.
2. The method of claim 1, wherein the material of the first stop layer comprises tungsten or aluminum oxide.
3. The method of claim 1, wherein forming the first stop layer on an mth row of the first sub-channel holes of the plurality of rows of first sub-channel holes comprises:
forming a first groove on the surface of the M row of first sub-channel holes;
and filling a first material in the first groove to form the first stop layer.
4. The method of claim 3, wherein the first trench has a diameter width greater than a top diameter width of each of the first sub-channel holes in the M-th row of first sub-channel holes.
5. The method of claim 1, wherein the base structure further comprises: a first sacrificial layer in the rows of first sub-channel holes;
the method further comprises the following steps:
removing the first sacrificial layer; wherein, in the process of removing the first sacrificial layer, the first sacrificial layer in the M-th row of first sub-channel holes is not removed;
forming a memory material layer, wherein the memory material layer covers the side wall of the second sub-channel hole in the Mth row and the top surface of the first stop layer, and covers the side wall and the bottom surface of the communicated first sub-channel hole and the second sub-channel hole;
etching the memory material layer to remove the memory material layer covering the top surface and the bottom surface;
and filling a dielectric material.
6. The method of claim 1, wherein the base structure further comprises: a plurality of rows of dummy first sub-channel holes passing through the first sub-stacked structure;
when the first stop layer is formed on the mth row of first sub-channel holes among the plurality of rows of first sub-channel holes, the method includes:
forming a second stop layer on the plurality of rows of dummy first sub-channel holes;
when a plurality of rows of second sub-channel holes are formed in the second sub-stacked structure, the method includes:
forming a plurality of rows of dummy second sub-channel holes in the second sub-stacked structure; wherein the plurality of rows of dummy second sub-channel holes each extend into the corresponding second stop layer.
7. A three-dimensional memory, comprising:
a first sub-stack structure;
a plurality of rows of first sub-channel holes passing through the first sub-stacking structure;
a first stop layer on an M-th row of first sub-channel holes among the plurality of rows of first sub-channel holes; m is a positive integer;
a second sub-stacking structure located on the first sub-stacking structure;
a plurality of rows of second sub-channel holes in the second sub-stack; wherein an M-th row of second sub-channel holes of the plurality of rows of second sub-channel holes extends into the first stop layer; all the other second sub-channel holes except the M row of the second sub-channel holes in the multiple rows extend into the corresponding first sub-channel holes; at the position where the second sub-channel hole of the mth row is located, a trench dividing the top selection gate TSG is formed.
8. The three-dimensional memory according to claim 7, wherein the material of the first stop layer comprises tungsten or aluminum oxide.
9. The three-dimensional memory according to claim 7, wherein a width of the first trench for forming the first stop layer is larger than a top width of each of the first sub-channel holes in the M-th row of the first sub-channel holes.
10. The three-dimensional memory according to claim 7, further comprising:
the first sacrificial layer is positioned in the M row of first sub-channel holes;
a memory material layer; the memory material layer covers the side wall of the M-th row of second sub-channel holes and covers the side walls of the communicated first sub-channel holes and second sub-channel holes;
and the dielectric material is positioned in the M-th row of second sub-channel holes and the communicated first sub-channel holes and second sub-channel holes.
11. The three-dimensional memory according to claim 7, further comprising:
a plurality of rows of dummy first sub-channel holes passing through the first sub-stacked structure;
a second stop layer on the plurality of rows of dummy first sub-channel holes;
a plurality of rows of dummy second sub-channel holes in the second sub-stacked structure; wherein the plurality of rows of dummy second sub-channel holes extend into the corresponding second stop layers.
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