CN111540750B - Method for manufacturing 3D memory device - Google Patents
Method for manufacturing 3D memory device Download PDFInfo
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- CN111540750B CN111540750B CN202010342218.0A CN202010342218A CN111540750B CN 111540750 B CN111540750 B CN 111540750B CN 202010342218 A CN202010342218 A CN 202010342218A CN 111540750 B CN111540750 B CN 111540750B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
The application discloses a method for manufacturing a 3D memory device, comprising: forming a first gate stack structure of a first layer stack and a first channel hole penetrating through the first gate stack structure on a first surface of a wafer; filling a sacrificial material in the first trench hole; forming a second gate stack structure of a second layer stack on the first gate stack structure and a second channel hole penetrating through the second gate stack structure, wherein the second channel hole reaches the top surface of the sacrificial material; removing the sacrificial material through the second channel hole under the condition that the protective layer covers the edge of the wafer, so that the second channel hole is communicated with the first channel hole; and forming a channel pillar in the first channel hole and in the second channel hole. According to the manufacturing method of the 3D memory device, the protective layer is formed at the edge of the wafer, and the etchant used in the step of removing the sacrificial material cannot cause damage to the edge of the wafer, so that the yield of the 3D memory device is remarkably improved.
Description
Technical Field
The present invention relates to a memory technology, and more particularly, to a method of manufacturing a 3D memory device.
Background
The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.
Existing 3D memory devices are mainly used as non-volatile flash memories. Two major non-volatile flash memory technologies employ NAND and NOR architectures, respectively. The read speed is slightly slower in the NAND memory device compared to the NOR memory device, but the write speed is fast, the erase operation is simple, and a smaller memory cell can be realized, thereby achieving higher memory density. Therefore, the 3D memory device adopting the NAND structure is widely used.
In the 3D memory device of the NAND structure, a stack (deck) of a plurality of levels may be stacked to increase a memory density. For example, for 128 levels of memory cells, two stacks may be used, each stack including multiple (e.g., 32 or 64) levels of memory cell strings, with the memory cell strings of the two stacks interconnected with each other. Each stack includes a gate stack structure and a channel pillar extending through the gate stack structure, the gate stack structure providing gate conductors for the select transistor and the memory transistor, and the channel pillar providing channel layers and gate dielectric stacks for the select transistor and the memory transistor.
It is desirable to further improve the structure of the 3D memory device and the method of manufacturing the same, not only to increase the memory density of the 3D memory device, but also to further simplify the manufacturing process, reduce the manufacturing cost, and improve the yield and reliability.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide a method of manufacturing a 3D memory device, in which a protective layer is formed at the edge of a wafer so that the edge of the wafer is not damaged by an etchant in a step of removing a sacrificial material.
According to an aspect of the present invention, there is provided a method of manufacturing a 3D memory device, including: forming a first gate stack structure of a first layer stack and a first channel hole penetrating through the first gate stack structure on a first surface of a wafer; filling a sacrificial material in the first trench hole; forming a second gate stack structure of a second layer stack on the first gate stack structure and a second channel hole penetrating the second gate stack structure, the second channel hole reaching a top surface of the sacrificial material; removing the sacrificial material through the second channel hole with the protective layer covering the edge of the wafer such that the second channel hole is in communication with the first channel hole; and forming a channel pillar in the first channel hole and in the second channel hole.
Preferably, between the steps of forming the second gate stack structure and forming the second channel hole, further comprising: forming a first hard mask over the second gate stack structure; and forming a second hard mask on a second surface of the wafer, the first surface and the second surface being opposite to each other, wherein the second channel hole is formed through an opening of the first hard mask.
Preferably, the first gate stack structure and the second gate stack structure form a continuous sloped sidewall at an edge region of the wafer, the first hard mask extending to the first surface of the wafer via the sloped sidewall.
Preferably, the protective layer is adjacent to the first hard mask, or the protective layer covers the first hard mask.
Preferably, the first hard mask and the second hard mask include at least one silicon oxide layer and at least one silicon nitride layer, respectively, which are alternately stacked.
Preferably, the wafer is composed of single crystal silicon, the sacrificial material is composed of polycrystalline silicon, and the protective layer is composed of silicon oxide.
Preferably, the fill material is removed selectively with respect to the first hard mask and the second hard mask using a tetramethylammonium hydroxide solution as an etchant.
Preferably, a portion of at least one of the first and second hard masks is located on the surface of the wafer edge, and the portion of at least one of the first and second hard masks is removed using a wet etch to re-expose the surface of the wafer edge prior to forming the protective layer.
Preferably, a silicon oxide layer is formed on the surface of the wafer edge as the protective layer.
Preferably, a low pressure tetraethoxysilane growth process is used to form a silicon oxide layer on the re-exposed surface of the wafer edge as the protective layer.
Preferably, a magnetron reactive sputtering process is used to form a silicon oxide layer on the re-exposed surface of the wafer edge as the protective layer.
Preferably, the wafer is warped with the first surface intermediate convex deformation, and before the step of forming the protective layer, the wafer is turned over so that the second surface of the wafer is placed upward.
Preferably, the protective layer is formed between the steps of filling the sacrificial material and forming the second gate stack structure.
Preferably, the first gate stack structure and the second gate stack structure respectively include a plurality of gate conductors and a plurality of interlayer insulating layers separating the gate conductors of adjacent layers from each other.
Preferably, the first gate stack structure and the second gate stack structure are respectively formed by the following steps: forming a sacrificial stacked structure including a plurality of sacrificial layers and a plurality of interlayer insulating layers separating the sacrificial layers of adjacent layers from each other; and replacing the multi-layer sacrificial layer with a multi-layer gate conductor to form a gate stack structure.
Preferably, before the step of forming the channel pillar, the method further includes: and forming an epitaxial layer on the bottom surface of the first channel hole.
Preferably, the channel pillar includes a gate dielectric stack continuously extending on sidewalls of the first and second channel holes, and a channel layer filling the first and second channel holes.
Preferably, the channel pillar includes a gate dielectric stack extending continuously on sidewalls of the first and second channel holes, a core insulating layer in the first and second channel holes, and a channel layer between the core insulating layer and the gate dielectric stack.
Preferably, after the step of forming the protective layer, the wafer edge is used as a grip for mechanical gripping.
According to the method of manufacturing the 3D memory device according to the embodiment of the invention, in the steps of forming the first layer stack and the second layer stack, after the gate stack structure of the first layer stack is formed, the first channel hole penetrating the gate stack structure is formed, and the first channel hole is filled with the sacrificial layer, so that the gate stack structure of the second layer stack can be formed on the entire structure surface of the first layer stack. Further, after forming the protective layer on the surface of the edge of the wafer, a second channel hole penetrating the gate stack structure is formed, and the sacrificial layer is removed through the second channel hole so that the first channel hole communicates with the second channel hole. Since the protective layer covers the surface of the wafer edge, the wafer edge is substantially not damaged by the etchant during the step of removing the sacrificial material, thereby maintaining a complete overall structure and good mechanical strength. In the subsequent steps of the manufacturing method, the wafer is not stuck on the fixing table or broken to generate fragments. Further, after forming the protective layer at the wafer edge, the wafer edge may be used as a grip for mechanical clamping to facilitate subsequent processes. Therefore, the manufacturing method can improve the yield of the 3D memory device.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a schematic configuration diagram of a wafer stage used in a method of forming a 3D memory device.
Fig. 2 illustrates a schematic configuration diagram of a wafer in a method of forming a 3D memory device.
Fig. 3 illustrates a cross-sectional view of a semiconductor structure after forming a two-layered stacked via hole according to a related art 3D memory device manufacturing method.
Fig. 4a and 4b respectively show cross-sectional views of a semiconductor structure in different steps of forming a two-layer stacked via hole according to a 3D memory device manufacturing method of the related art.
Fig. 5 illustrates a flowchart of a method of manufacturing a 3D memory device according to an embodiment of the present invention.
Fig. 6a to 6j show cross-sectional views of a method of manufacturing a 3D memory device at different stages according to an embodiment of the present invention.
Fig. 7a to 7c are sectional views illustrating detailed steps of forming a protective layer in a method of manufacturing a 3D memory device according to an embodiment of the present invention.
Fig. 8a to 8c are sectional views illustrating preferred steps of forming a protective layer in a method of manufacturing a 3D memory device according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The present invention may be embodied in various forms, some examples of which are described below.
Fig. 1 and 2 show schematic configuration diagrams of a wafer fixing stage and a wafer used in a method of forming a 3D memory device, respectively.
As shown in fig. 1, the platen 10 includes a tray 11 and a plurality of seal rings 12 on the tray 11. A gap is formed between the plurality of seal rings 12, and a plurality of air holes 13 are formed in the surface of the tray 11, and are located in the gap and communicated with an air extractor. As shown in fig. 2, the wafer 20 is, for example, a silicon wafer, and a plurality of bare chips 21 are formed in a chip region of the wafer 20. The plurality of die 21 are spaced apart from each other, and scribe lanes are formed between adjacent die. The wafer 20 is placed on the fixed stage 10, and then the suction device sucks the wafer 20 on the fixed stage 10 by drawing a vacuum through the air holes 13, so that the internal structure of the plurality of bare chips 21 can be formed. Then, dicing is performed via dicing streets between the plurality of bare chips 21 to separate adjacent bare chips from each other.
In the above-described type of wafer holding stage, the wafer 20 is held by vacuum suction. In another type of platen, the edge 22 of the wafer 20 is used, for example, as a clamping area for mechanical clamping, and a chuck may be used to clamp the wafer 20 to the platen.
Fig. 3 illustrates a cross-sectional view of a semiconductor structure after forming a two-layered stacked via hole according to a related art 3D memory device manufacturing method. The cross-sectional view is taken, for example, as indicated by line AA in fig. 2, where at least a portion of the structure of die 21 of the wafer adjacent the edge of the wafer is shown, including cell region 210 and edge region 220 of die 21.
As shown, a first layer stack (first stack) gate stack 110 and a second layer stack (second stack) gate stack 120 have been formed on a first surface of wafer 101. The gate stack structure 110 includes a plurality of gate conductors 111, and a plurality of interlayer insulating layers 112 separating the gate conductors 111 of adjacent layers from each other. The gate stack structure 120 includes a plurality of gate conductors 121, and a plurality of interlayer insulating layers 122 separating the gate conductors 121 of adjacent layers from each other.
In the cell region 210, a plurality of first channel holes 211 of the first layer stack penetrate the gate stack structure 110, and a plurality of second channel holes 212 of the second layer stack penetrate the gate stack structure 120. Further, the plurality of first channel holes 211 and the plurality of second channel holes 212 communicate with each other, respectively. In the final 3D memory device, a channel layer and a gate dielectric stack are formed in the channel hole to form a memory cell string together with the gate stack structure. A portion of the surface of the first surface of wafer 101 on which epitaxial layer 131 is formed is exposed at the bottom of the plurality of first channel holes 211. In order to protect the gate stack structure in the etching process for forming the channel hole, a first hard mask, for example, a multi-layered structure of the silicon oxide layer 105, the silicon nitride layer 106, and the silicon oxide layer 107, is formed on the gate stack structure 120 of the second layer stack. In order to protect the internal structure of the wafer 101 during the etching process for forming the channel hole, a second hard mask, for example, a plurality of protective layers formed of a silicon nitride layer 102, a silicon oxide layer 103, and a silicon nitride layer 104, is formed on the second surface of the wafer 101.
In the edge region 220, edges of the layers of the first stacked gate stack structure 110 and the second stacked gate stack structure 120 form continuously extending sloped sidewalls. The silicon oxide layer 105 and the silicon nitride layer 106 in the first hard mask extend laterally from above the gate stack structure 120 of the second layer stack and along the sloped sidewalls to the first surface of the wafer 101. In the edge region 220, the wafer edge 221 of the wafer 101 and adjacent portions of the first and second surfaces provide a clamping region that serves as a mechanical clamp. Channel holes required for the memory cell strings of the 3D memory device are not formed in the edge region 220.
According to the related art method of manufacturing the 3D memory device, in the steps of forming the first layer stack and the second layer stack, after the gate stack structure 110 of the first layer stack is formed, the first channel hole 211 penetrating the gate stack structure 110 is formed, and the first channel hole 211 is filled with the sacrificial layer 132 so that the gate stack structure 120 of the second layer stack may be formed on the entire structure surface of the first layer stack 110, and then, the second channel hole 212 penetrating the gate stack structure 120 is formed (see fig. 4a), and the sacrificial layer 132 is removed through the second channel hole 212 so that the first channel hole 211 communicates with the second channel hole 212 (see fig. 4 b).
The inventors have found that during the etching step for forming the second channel hole 212 of the second layer stack 120, the wafer edge 221 and the adjacent portion of the surface are directly exposed, and the wafer edge (wafer level) is also damaged by the etching process used during the step for forming the second channel hole 212. For example, the damaged region 222 shown in fig. 3 near the wafer edge 221 results in a reduced thickness and mechanical strength of the clamping region of the wafer, which may even cause the wafer to become stuck on a holding table and difficult to remove, or cause the wafer edge to break and contaminate the equipment. Therefore, wafer edge damage is an important cause of reduced yield of 3D memory devices.
Further, the present inventors have proposed that, in a method of manufacturing a 3D memory device, forming a wafer edge protection layer before forming a channel hole of an upper level may significantly improve the yield of the 3D memory device.
Fig. 5 illustrates a flowchart of a method of manufacturing a 3D memory device according to an embodiment of the present invention. Fig. 6a to 6j show cross-sectional views of a method of manufacturing a 3D memory device at different stages according to an embodiment of the present invention. The cross-sectional view is taken, for example, as indicated by line AA in fig. 2, where at least a portion of the structure of die 21 of the wafer adjacent the edge of the wafer is shown, including cell region 210 and edge region 220 of die 21.
In step S01, a first layer stacked gate stack structure 110 is formed on the first surface of wafer 101, as shown in fig. 6 a.
The first stacked gate stack structure 110 includes a plurality of gate conductors 111, and a plurality of interlayer insulating layers 112 separating the gate conductors 111 of adjacent layers from each other. In this embodiment, the wafer 101 is, for example, a single crystal silicon wafer, the gate conductor 111 is, for example, composed of metal tungsten, and the interlayer insulating layer 112 is, for example, composed of silicon oxide
In order to perform a programming operation on memory cells in the 3D memory device, a plurality of well regions and CMOS circuits (not shown) for driving the selection transistors and the memory transistors may be formed in advance in the wafer 101. For example, a high voltage P-well is located under the gate stack structure as a common source region for a plurality of channel pillars.
To form the gate stack structure 110, a stack structure of a plurality of sacrificial layers may be first formed, and then the plurality of sacrificial layers may be replaced with the gate conductor. The sacrificial layer is composed of, for example, silicon nitride. The replacement process includes, for example, removing the sacrificial layer selectively with respect to the interlayer insulating layer using wet etching or vapor etching to form a cavity, and then filling the cavity with metal tungsten using an atomic layer deposition method. A phosphoric acid solution may be used as an etchant in the wet etching, and one or more of C4F8, C4F6, CH2F2, and O2 may be used in the vapor etching. The precursor source used in atomic layer deposition is, for example, tungsten hexafluoride WF6, and the reducing gas used is, for example, silane SiH4 or diborane B2H 6. In the step of atomic layer deposition, the deposition process is realized by obtaining tungsten material by chemical adsorption of a reaction product of tungsten hexafluoride WF6 and silane SiH 4.
In step S02, a first channel hole 121 is formed through the gate stack structure 110 of the first layer stack, as shown in fig. 6 b.
In this step, for example, a resist mask is formed on the surface of the gate stack structure 110 and the second surface of the wafer 101, an opening is formed in the resist mask using a photolithography method, and the gate conductor 111 and the interlayer insulating layer 112 in the gate stack structure 110 are removed through the exposed portion of the opening using an anisotropic etching process, thereby forming a first channel hole 121 extending from the surface of the gate stack structure 110 to the first surface of the wafer 101. Then, the resist layer is removed by solvent dissolution or ashing.
In step S03, the first channel hole 121 is filled with a sacrificial material 121, as shown in fig. 6 c.
In this step, the sacrificial material 121 is filled, for example, using low pressure chemical vapor deposition, and the portion of the sacrificial material 121 outside the first channel hole 121 is removed using chemical mechanical planarization. The sacrificial material 121 includes any one selected from the group consisting of polysilicon, carbon, and tungsten. There may be defects such as voids in the sacrificial material 121, however, after the sacrificial material 121 fills the first channel hole 121, the gate stack structure 110 of the first layer stack may still obtain a complete structure surface for forming the gate stack structure 120 of the second layer stack.
In step S04, a gate stack structure 120 of the second layer stack is formed on the gate stack structure 110 of the first layer stack, as shown in fig. 6 d.
The gate stack structure 120 of the second layer stack includes a plurality of gate conductors 121, and a plurality of interlayer insulating layers 122 separating the gate conductors 121 of adjacent layers from each other. In this embodiment, the gate conductor 121 is composed of, for example, metal tungsten, and the interlayer insulating layer 122 is composed of, for example, silicon oxide.
In this step, the gate stack structure 120 is formed in the same manner as the gate stack structure 110, for example, a plurality of sacrificial layers are replaced with gate conductors to form a stack in which a plurality of gate conductors 121 and a plurality of interlayer insulating layers 122 are alternately stacked, which will not be described in detail.
In step S05, a hard mask is formed in the cell region of wafer 101, as shown in fig. 6 e.
In this step, a multi-layered hard mask is formed, for example, using plasma enhanced chemical vapor deposition. In order to protect the gate stack structure in the etching process for forming the channel hole, a first hard mask, for example, a multi-layered structure of the silicon oxide layer 105, the silicon nitride layer 106, and the silicon oxide layer 107, is formed on the gate stack structure 120 of the second layer stack. In order to protect the internal structure of the wafer 101 in the etching process for forming the channel hole, a second hard mask, for example, a multi-layer structure formed of a silicon nitride layer 102, a silicon oxide layer 103, and a silicon nitride layer 104, is formed on the second surface of the wafer 101.
In step S06, a protective layer 224 is formed at the edge region of wafer 101, as shown in fig. 6 f.
In this step, wafer 101 is removed from the platen, for example, and a protective layer 224 is then formed on the exposed surface of wafer edge 221 using a low pressure tetraethoxysilane growth process (LPTEOS). The protective layer 224 is composed of, for example, silicon oxide.
In the cell region, the silicon oxide layer 105 and the silicon nitride layer 106 in the first hard mask extend laterally over the gate stack structure 120 of the second layer stack, and the silicon nitride layer 102, the silicon oxide layer 103 and the silicon nitride layer 104 in the second hard mask extend laterally over the second surface of the wafer 101.
In the edge region, the edges of the layers of the first layer stack gate stack structure 110 and the second layer stack gate stack structure 120 form continuously extending sloped sidewalls. The silicon oxide layer 105 and the silicon nitride layer 106 in the first hard mask extend along the sloped sidewalls to the first surface of the wafer 101. Protective layer 224 covers the exposed surface of wafer edge 221 and abuts the first hard mask on the first surface of wafer 101 and the second hard mask on the second surface of wafer 101. Thus, the protective layer 224, in conjunction with the first and second hard masks, covers the surface of the wafer 101, thereby protecting the wafer edge 221 during subsequent etching processes.
In step S07, a second channel hole 122 is formed through the gate stack structure 120 of the second layer stack, as shown in fig. 6 g.
In this step, for example, a resist mask is formed on the surface of the gate stack structure 120, an opening is formed in the resist mask using a photolithography method, and the layers in the first hard mask, and the gate conductor 121 and the interlayer insulating layer 122 in the gate stack structure 120 are removed through the exposed portion of the opening using an anisotropic etching process, thereby forming a second channel hole 122 extending from the surface of the gate stack structure 120 to the surface of the gate stack structure 110. The bottom of the second channel hole 122 exposes the top surface of the sacrificial fill material 132 in the first channel hole 121. Then, the resist layer is removed by solvent dissolution or ashing.
In step S08, the sacrificial material 132 is removed through the second channel hole 122 to make the second channel hole 122 and the first channel hole 121 communicate with each other, as shown in fig. 6 h.
In this step, the sacrificial material 132 is selectively removed with respect to the gate conductors 111 and 121, the interlayer insulating layers 112 and 122, the silicon oxide layer 105, the silicon nitride layer 106, the silicon oxide layer 107, and the protective layer 224 using a selective etchant, thereby newly forming the first channel hole 121.
In this embodiment, wafer 101 is comprised of, for example, monocrystalline silicon and sacrificial material 132 is comprised of, for example, polycrystalline silicon. The sacrificial material 132 may be removed using an etchant such as TMAH (i.e., tetramethylammonium hydroxide) solution that selectively removes polysilicon relative to silicon oxide and silicon nitride. Because the protective layer 224, in conjunction with the first and second hard masks, covers the surface of the wafer 101, the wafer edge 221 can be protected during the etching process, thereby ensuring that the wafer 101 can maintain adequate mechanical strength to avoid chipping of the wafer edge.
In step S09, the epitaxial layer 131 is formed at the bottom of the first channel hole 121, as shown in fig. 6 i. The epitaxial layer is composed of, for example, silicon epitaxially grown on the surface of wafer 101.
In step S10, channel pillars 140 are formed in the first and second channel holes 121 and 122, as shown in fig. 6 j.
In this step, a gate dielectric stack is formed on the continuous sidewalls of the first and second channel holes 121 and 122, and a semiconductor material is filled in the first and second channel holes 121 and 122 to form the channel layer 141. The gate dielectric stack is sequentially stacked on the channel layer 141, the tunneling dielectric layer 142, the charge storage layer 143, and the blocking dielectric layer 144.
The channel layer 141 is composed of, for example, doped polysilicon, the tunneling dielectric layer 142 and the blocking dielectric layer 144 are respectively composed of an oxide such as silicon oxide, and the charge storage layer 143 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride and silicon oxynitride containing particles of a metal or a semiconductor. The channel layer 141 serves to provide channel regions of the selection transistor and the memory transistor, and the doping type of the channel layer 141 is the same as the type of the selection transistor and the memory transistor. For example, for N-type select and memory transistors, the channel layer 141 may be N-type doped polysilicon.
In the method of manufacturing the 3D memory device of this embodiment, the protection layer 224 is formed to cover the edge of the wafer in step S06, thereby preventing the wafer edge (wafer level) from being damaged by the etching process used in the step of forming the second channel hole 212. In an alternative embodiment, the protection layer 224 may be formed in an earlier step, for example, the protection layer 224 is formed in steps S03 and S04 to cover the wafer edge, so as to prevent the wafer edge (wafer level) from being damaged by the etching process used in the step of forming the second channel hole 212.
In the above-described 3D memory device 100, the gate stack structure 110 of the first layer stack and the gate stack structure 120 of the second layer stack, respectively, form a plurality of memory transistors together with the channel pillar 140. Taking the first stacked gate stack structure 110 as an example, the gate conductor 111 forms a plurality of memory transistors in a memory cell string together with the channel layer 141, the tunneling dielectric layer 142, the charge storage layer 143, and the blocking dielectric layer 144 inside the channel pillar 140. Further, channel pillars 140 are connected to bit lines at their top ends and to a common source region of wafer 101 at their bottom ends.
In the above-described embodiments, the channel layer 141 fills the first channel hole 121 and the second channel layer 122. In an alternative embodiment, channel pillar 140 further includes a core insulating layer, and channel layer 141, tunnel dielectric layer 142, charge storage layer 143, and blocking dielectric layer 144 form a stacked structure surrounding the core insulating layer.
Fig. 7a to 7c are sectional views illustrating detailed steps of forming a protective layer in a method of manufacturing a 3D memory device according to an embodiment of the present invention.
As shown in fig. 7a, referring to step S05 in fig. 5, a hard mask is formed on the surface of gate stack structure 120 of the second stack and the second surface of wafer 101. The hard mask is, for example, a double-layer structure of a silicon oxide layer 105 and a silicon nitride layer 106. The edges of the layers of the first layer stack gate stack structure 110 and the second layer stack gate stack structure 120 form continuously extending sloped sidewalls. The silicon oxide layer 105 and the silicon nitride layer 106 in the hard mask extend along the sloped sidewalls to the first surface of the wafer 101. Further, the silicon oxide layer 105 and the silicon nitride layer 106 in the hard mask also cover the surface of the wafer edge 221.
As shown in fig. 7b and 7b, referring to step S06 in fig. 5, a protective layer 224 is formed at the edge region of the wafer 101. In this step, the portions of the silicon oxide layer 105 and the silicon nitride layer 106 in the hard mask that are on the surface of the wafer edge 221 are removed using a wet etch, so that the surface of the wafer edge 221 is re-exposed. Then, a silicon oxide layer, for example, 80 nm thick, is formed as the protective layer 224 on the exposed surface of the wafer edge 221 using a low pressure tetraethoxysilane growth process (LPTEOS).
In the above embodiment, the high quality thin silicon oxide layer reformed on the exposed surface of the wafer edge 211 using the low pressure tetraethoxysilane growth process serves as a protective layer to prevent the etching of the wafer edge 22 by the etchant in the subsequent step of removing the polysilicon layer in the channel hole using the etchant. In an alternative embodiment, a magnetron reactive sputtering process is used to re-form a thick silicon oxide layer on the exposed surface of the wafer edge 211 as a protective layer to prevent the etchant from etching the wafer edge 22 in a subsequent step of removing the polysilicon layer in the channel holes with the etchant.
After the formation of the protective layer, S07 through S10 in fig. 5 are continued to form respective portions of the 3D memory device.
Fig. 8a to 8c are sectional views illustrating preferred steps of forming a protective layer in a method of manufacturing a 3D memory device according to an embodiment of the present invention. For simplicity, only wafer 101 and protective layer 224 are shown in fig. 8a to 8c, and the detailed structure of the gate stack structure on the first surface of wafer 101 is not shown.
Prior to the step of forming the protective layer 224, a first stacked gate stack structure 110 and a second stacked gate stack structure 120 are formed on the first surface of the wafer 101. Due to the stress generated by the gate stack structure, wafer 101 warps with convex deformation in the middle of the first surface, as shown in fig. 8 a. If the first surface of wafer 101 is oriented upward and wafer edge 221 is oriented obliquely downward, protective layer 224 will have difficulty covering the lower surface of the wafer edge during the growth process or sputtering process that forms protective layer 224. In this embodiment, wafer 101 is flipped over as shown in fig. 8b such that the second surface of wafer 101 faces upward, the central depression of the second surface is deformed, the wafer edge 221 is oriented obliquely upward, and during the growth process or sputtering process to form protective layer 224, protective layer 224 will cover the entire surface of the wafer edge as shown in fig. 8 c.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.
Claims (17)
1. A method of manufacturing a 3D memory device, comprising:
forming a first gate stack structure of a first layer stack and a first channel hole penetrating through the first gate stack structure on a first surface of a wafer;
filling a sacrificial material in the first trench hole;
forming a second gate stack structure of a second layer stack on the first gate stack structure;
in the case where the warpage of the wafer in which the first-surface-intermediate-projection deformation occurs is generated, the wafer is turned over so that the second surface of the wafer is placed upward, so that the wafer edge of the wafer is oriented obliquely upward;
forming a protective layer covering the edge of the wafer;
forming a second channel hole through the second gate stack structure, the second channel hole reaching a top surface of the sacrificial material;
removing the sacrificial material through the second channel hole with respect to the protective layer such that the second channel hole is in communication with the first channel hole; and
forming a channel pillar in the first channel hole and in the second channel hole.
2. The manufacturing method of claim 1, wherein between the steps of forming the second gate stack structure and forming a second channel hole, further comprising:
forming a first hard mask over the second gate stack structure; and
forming a second hard mask on a second surface of the wafer, the first surface and the second surface being opposite to each other,
wherein the second channel hole is formed through an opening of the first hard mask.
3. The manufacturing method according to claim 2, wherein the first gate stack structure and the second gate stack structure form a continuous sloped sidewall at an edge region of the wafer, the first hard mask extending to the first surface of the wafer via the sloped sidewall.
4. The manufacturing method according to claim 3, wherein the protective layer is adjacent to the first hard mask, or the protective layer covers the first hard mask.
5. The manufacturing method according to claim 4, wherein the first hard mask and the second hard mask respectively comprise at least one silicon oxide layer and at least one silicon nitride layer which are alternately stacked.
6. The manufacturing method according to claim 5, wherein the wafer is composed of single crystal silicon, the sacrificial material is composed of polycrystalline silicon, and the protective layer is composed of silicon oxide.
7. The manufacturing method according to claim 6, wherein the filling material is selectively removed with respect to the first hard mask and the second hard mask using a tetramethylammonium hydroxide solution as an etchant.
8. The method of manufacturing of claim 2, wherein a portion of at least one of the first and second hard masks is located on the surface of the wafer edge, and wherein the portion of at least one of the first and second hard masks is removed using a wet etch to re-expose the surface of the wafer edge prior to forming the protective layer.
9. The manufacturing method according to claim 1, wherein a silicon oxide layer is formed as the protective layer on a surface of the wafer edge.
10. The method of manufacturing of claim 9, wherein a low pressure tetraethoxysilane growth process is used to form a silicon oxide layer on the re-exposed surface of the wafer edge as the protective layer.
11. The method of manufacturing of claim 9, wherein a magnetron reactive sputtering process is used to form a silicon oxide layer on the re-exposed surface of the wafer edge as the protective layer.
12. The manufacturing method according to claim 1, wherein the first gate stack structure and the second gate stack structure respectively include a plurality of gate conductors and a plurality of interlayer insulating layers that separate the gate conductors of adjacent layers from each other.
13. The manufacturing method of claim 12, wherein the first gate stack structure and the second gate stack structure are formed by:
forming a sacrificial stacked structure including a plurality of sacrificial layers and a plurality of interlayer insulating layers separating the sacrificial layers of adjacent layers from each other; and
the multi-layer sacrificial layer is replaced with a multi-layer gate conductor to form a gate stack structure.
14. The manufacturing method according to claim 1, further comprising, before the step of forming the channel pillar: and forming an epitaxial layer on the bottom surface of the first channel hole.
15. The method of manufacturing of claim 1, wherein the channel pillar comprises a gate dielectric stack extending continuously on sidewalls of the first and second channel holes and a channel layer filling the first and second channel holes.
16. The method of manufacturing of claim 1, wherein the channel pillar comprises a gate dielectric stack extending continuously on sidewalls of the first and second channel holes, a core insulating layer in the first and second channel holes, and a channel layer between the core insulating layer and the gate dielectric stack.
17. The manufacturing method according to claim 1, wherein the wafer edge is used as a grip for mechanical gripping after the step of forming the protective layer.
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