CN109524312B

CN109524312B - 3D memory and surface adjustment method

Info

Publication number: CN109524312B
Application number: CN201811356888.7A
Authority: CN
Inventors: 罗世金; 胡明; 鲍琨; 夏志良; 程纪伟; 孙中旺; 张坤
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2018-11-15
Filing date: 2018-11-15
Publication date: 2021-12-03
Anticipated expiration: 2038-11-15
Also published as: CN109524312A

Abstract

The application discloses a 3D memory and a surface correction method, the 3D memory includes: the method comprises the following steps: a 3D storage structure; a backing film located on and adjacent to a surface of the 3D storage structure; and the stress layer is adjacent to the back membrane, wherein the back membrane comprises an opening, the shape of the opening comprises a hole shape or a strip shape of any combination of a polygon, a circle, a ring and the like, the stress layer is positioned in the opening, the opening is used for limiting the pattern of the stress layer, and the correction of the warping in different degrees is realized by adjusting the thickness of the back membrane. The correction structure provides a flat surface for a subsequent covering layer, and is suitable for surface warping with various directions, so that the yield and the reliability of a semiconductor device can be improved.

Description

3D memory and surface adjustment method

Technical Field

The invention relates to semiconductor technology, in particular to a surface warping (bow) correction structure and a correction method of a 3D memory.

Background

The direction of development in semiconductor technology is the reduction of feature size and the increase of integration. For the memory device, the increase in the memory density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.

The 3D memory device is, for example, a semiconductor structure including a wafer and a gate stack structure, in which gate conductors of a selection transistor and a memory transistor are provided using the gate stack structure, channel layers of the selection transistor and the memory transistor are provided using a channel pillar penetrating the stack structure, and a gate dielectric sandwiched between the gate conductors and the channel layers. As a result of stacking a plurality of films composed of different materials, the semiconductor structure generates accumulated stress, resulting in warpage of the semiconductor structure in a plane perpendicular to the stacking direction. In practical situations, due to the asymmetry of the stress applied to the front surface of the wafer, various forms of asymmetric warpage of the wafer, such as saddle-shaped warpage, often occur, which causes problems such as easy occurrence of fragments on the wafer. It is desirable to further improve the surface modification structure of the semiconductor structure and the modification method thereof so as to improve the yield and reliability of the 3D memory device.

Disclosure of Invention

In view of the foregoing problems, it is an object of the present invention to provide a 3D memory and a surface modification method, in which a backside film is formed on the backside of a 3D memory structure, an opening of the backside film is designed according to the direction of warpage, and a stress layer filling the opening is formed, so as to restore a flat surface.

According to an aspect of the present invention, there is provided a surface modification structure of a semiconductor structure, including: a back film located adjacent to and on a surface of the semiconductor structure; and a stress layer adjacent to the backing film.

Preferably, the back membrane includes an opening therein, and the stress layer is located in the opening.

Preferably, the semiconductor structure comprises a wafer and a gate stack structure located on a first surface of the wafer, the back film is located on a second surface of the wafer, and the first surface and the second surface of the wafer are opposite to each other.

Preferably, the number of the openings is at least one, and the shape of the openings comprises a polygon, a circle, a ring and any combination thereof.

Preferably, the openings are symmetrically distributed about a center of the semiconductor structure.

Preferably, the openings are asymmetrically distributed about a center of the semiconductor structure.

Preferably, the openings extend from the surface of the backing film to any depth within the interior of the backing film.

Preferably, the opening extends through the back film to the surface of the semiconductor structure.

Preferably, the material of the stress layer comprises at least one of a material having a shrinkage stress, a material having an expansion stress, and a material having a low stress.

Preferably, the surface of the stress layer is covered with a film, and the thickness of the film does not affect the macroscopic stress of the semiconductor structure.

According to another aspect of the present invention, there is provided a surface modification method of a semiconductor structure, including: forming a back film, wherein the back film is positioned on the surface of the semiconductor structure and is adjacent to the surface of the semiconductor structure; forming an opening on the back film; and forming a stress layer in the opening so as to recover to a flat surface.

Preferably, the step of forming the opening on the back film comprises: measuring surface warpage of the semiconductor structure; designing a mask pattern according to the directionality of the warpage; and etching the back film to form an opening on the back film.

Preferably, a film is formed on the surface of the stress layer, and the thickness of the film does not influence the macroscopic stress of the semiconductor structure.

Preferably, after forming the stress layer located in the opening, the method further includes: and carrying out planarization treatment on the surface of the semiconductor structure, wherein the planarization treatment comprises chemical mechanical polishing.

According to the 3D memory and the surface modification method provided by the embodiment of the invention, the semiconductor structure is a 3D memory device, for example, a back film is formed on the back of the semiconductor structure, an opening positioned in the back film is designed according to the warping direction, and a stress layer filling the opening is formed, so that a flat surface is restored again. The correction method provides a flat surface for the subsequent covering layer, is not only suitable for isotropic surface warping, but also suitable for anisotropic surface warping, and therefore can improve the yield and reliability of semiconductor devices.

The surface modification structure can significantly reduce surface warpage of a semiconductor structure, such as a 3D memory device, thereby allowing more levels of gate conductors to be included in the semiconductor structure. Since the surface modification method has the capability of modifying the anisotropic surface warpage, the anisotropic surface warpage can be restored to a flat surface even if the semiconductor structure contains stress generated by a complicated pattern, which causes the anisotropic surface warpage. The surface correction method can increase the stacking layer number and the complex structure of the 3D memory device, thereby being beneficial to further reducing the chip occupation area of the memory unit and improving the memory density.

Furthermore, the surface correction structure can conveniently control the size and position distribution of stress by controlling the thickness of the back membrane and the parameters of the depth, position, shape and the like of the stress layer, and the process difficulty of controlling surface correction is reduced. In addition, the surface finishing method does not increase heat to release stress and is not limited by thermal budget (thermal budget), so that the window of surface finishing is larger, the process difficulty is reduced, and the quality of surface finishing is improved.

Further, the surface modification structure can not damage the device structure on the surface of the semiconductor structure by forming the back film and the stress layer on the back of the semiconductor structure. The surface correction method does not directly etch the semiconductor structure, so that the mechanical strength of the semiconductor structure is not influenced, and the purposes of surface correction and no damage to the semiconductor structure are achieved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device.

Fig. 2 shows a perspective view of a 3D memory device.

Fig. 3a to 3e show cross-sectional views of stages of a method of manufacturing a modified structure according to an embodiment of the present invention.

Fig. 4a and 4b respectively show cross-sectional views of a modified structure provided according to a first embodiment of the present invention.

Fig. 5a and 5b respectively show cross-sectional views of a modified structure provided according to a second embodiment of the present invention.

Fig. 6a to 6c respectively show sectional views of a modified structure provided according to a third embodiment of the present invention.

Fig. 7a to 7c are graphs respectively illustrating stress simulation data of the semiconductor structure provided according to the first embodiment of the present invention.

Fig. 8 is a graph illustrating in-line experimental data for a semiconductor structure provided in accordance with a first embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.

In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. Hereinafter, unless otherwise specified, "semiconductor structure" refers to an intermediate structure comprising a wafer and a gate stack structure formed thereon.

The inventors of the present application have found that, in a 3D memory device, a semiconductor structure after forming a gate stack structure on a chip is easily warped, and as a result, a capping layer (e.g., a wiring layer) and a conductive via which are subsequently formed are difficult to align with a channel pillar penetrating the gate stack structure, and may cause more serious problems such as chipping of a wafer. The warpage of the semiconductor structure reduces the yield and reliability of the finally formed 3D memory device. As the number of layers of the gate conductor in the gate stack structure increases, for example from 32 to 64 layers, the stress accumulated in the semiconductor structure also increases, resulting in more and more severe warpage. Therefore, an important problem to be solved to improve the storage density of the 3D memory device is to correct the warpage of the semiconductor structure so as to regain a flat surface.

Existing warp correction methods include thermal annealing, deposition of additional stress films, and additional etching of the wafer backside. The stress can be relieved by thermal annealing and additional etching so that the semiconductor structure regains a flat surface. However, thermal annealing itself may cause re-diffusion of dopants in doped regions already formed in the wafer, thereby damaging CMOS circuits formed in the wafer, and additional etching may cause deterioration of mechanical strength of the wafer, thereby causing breakage in subsequent steps. The use of additional stress films can counteract the original stress in the semiconductor structure, however, the material selection and thickness control of the stress film must be controlled very precisely, resulting in difficulties in process implementation.

The inventors of the present application have noticed that the above-mentioned existing warpage correction methods have not yet been able to meet the requirements of 3D memory devices with high memory density, and even caused new problems affecting the yield and reliability of 3D memory devices, and in particular, the above-mentioned existing methods are only suitable for isotropic warpage correction. However, warpage of a semiconductor structure employed in a method of manufacturing a 3D memory device may be directional in nature. None of the above-described conventional methods can correct anisotropic warpage. Thus, the inventors of the present application propose a further improved warpage correction method that is applicable not only to 3D memory devices but also to various types of semiconductor structures.

The present invention may be embodied in various forms, some examples of which are described below.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, a first terminal of the memory cell string 100 is connected to a bit line BL, and a second terminal is connected to a source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M4, and a second select transistor Q2. The gate of the first select transistor Q1 is connected to a string select line SSL, and the gate of the second select transistor Q2 is connected to a ground select line GSL. The gates of the memory transistors M1 through M4 are connected to corresponding ones of the word lines WL1 through WL4, respectively.

As shown in fig. 1b, the first and second select transistors Q1 and Q2 of the memory cell string 100 include

gate conductors

122 and 123, respectively, and the memory transistors M1 through M4 include gate conductors 121, respectively. The

gate conductors

121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. Channel pillar 110 extends through the gate stack structure. In the middle portion of the channel pillar 110, a tunnel dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 are interposed between the gate conductor 121 and the channel layer 111, thereby forming memory transistors M1 through M4. A blocking dielectric layer 114 is sandwiched between the

gate conductors

122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

In this embodiment, the channel layer 111 is composed of, for example, doped polysilicon, the tunneling dielectric layer 112 and the blocking dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the

gate conductors

121, 122, and 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions for controlling the selection transistor and the memory transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the memory transistor. For example, for N-type select and memory transistors, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of channel pillar 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure surrounding the core.

In this embodiment, the first and second selection transistors Q1 and Q2, the memory transistors M1 to M4 use the common channel layer 111 and the blocking dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layer and the blocking dielectric layer of the first and second selection transistors Q1 and Q2 and the semiconductor layer and the blocking dielectric layer of the memory transistors M1 to M4, respectively, may be formed in separate steps from each other.

In a write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 through M4 using FN tunneling efficiency. Taking the memory transistor M2 as an example, while the source line SL is grounded, the ground selection line GSL is biased to a voltage of about zero volts, so that the selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to a high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at the programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at the low voltage VPS 1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges stored in the charge storage layer 113 of the memory transistor M2.

In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer from the on-state of a selected one of the memory transistors M1 through M4, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that a data value can be determined according to the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory transistor M2. The control circuit judges the conductive state of the memory transistor M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2 shows a perspective view of a 3D memory device. For clarity, the respective insulating layers in the 3D memory device are not shown in fig. 2.

The 3D memory device shown in this embodiment includes 4 x 4 and 16 memory cell strings 100 in total, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 64 memory cells in total 4 x 4. It is understood that the present invention is not limited thereto and the 3D memory device may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

In the 3D memory device, the memory cell strings respectively include the respective channel pillars 110, and the

common gate conductors

121, 122, and 123. The

gate conductors

121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the figure.

The internal structure of the channel pillar 110 is shown in fig. 1b and will not be described in detail. Channel pillars 110 extend through gate stack 120 and are arranged in an array, and a plurality of channel pillars 110 in a same column have first ends commonly connected to a same bit line (i.e., one of bit lines BL1 through BL 4), second ends commonly connected to die 101, and second ends forming a common source connection through die 101.

The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit) 102. The gate lines of the channel pillars 110 in the same row are commonly connected to the same string selection line (i.e., one of the string selection lines SSL1 through SSL 4).

The gate conductors 121 of memory transistors M1 and M4 are each connected to a corresponding word line. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit 161, the gate lines of the same level reach the interconnect layer 132 via respective conductive paths 131 to be interconnected with each other, and then are connected to the same word line (i.e., one of the word lines WL1 to WL 4) via a conductive path 133.

The gate conductors of the second select transistors Q2 are connected in one piece. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line slit 161, the gate lines reach the interconnection layer 132 via respective conductive paths 131 to be interconnected with each other, and then are connected to the same ground selection line GSL via the conductive path 133.

Fig. 3a to 3e show cross-sectional views taken along line AA in fig. 2 at various stages of a method of manufacturing a modified structure in accordance with an embodiment of the present invention.

The invention begins with the formation of a semiconductor structure 100 comprising a wafer and a gate stack structure with a backside film 201 underlying and abutting the semiconductor structure 100, as shown in fig. 3 a.

The gate stack structure is located above the semiconductor structure 100, i.e., the first surface of the semiconductor structure 100. The gate stack structure includes, for example, a plurality of levels of gate conductors and interlayer insulating layers that separate gate conductors of adjacent levels from each other. Details of the gate stack structure 120 are not shown in the drawings, however, the gate stack structure 120 may further include a plurality of levels of gate conductors and interlayer insulating layers, with adjacent gate conductors being separated from each other by the interlayer insulating layers. The gate conductor is composed of, for example, tungsten, and the interlayer insulating layer is composed of, for example, silicon oxide. The back film 201 is located below the semiconductor structure 100, i.e., the second surface of the semiconductor structure 100, and the back film 201 is adjacent to the semiconductor structure 100. The wafer is, for example, a single crystal silicon wafer, and in other embodiments, the wafer may also be other wafers of semiconductor material, such as silicon on insulator (SIO), and the like.

Further, the semiconductor structure 100 is flipped and the mask pattern is designed according to the directionality of the warpage of the semiconductor structure 100, as shown in fig. 3 b.

Before designing the mask pattern, the surface warpage of the semiconductor structure 100 is measured. For example, the surface topography parameters of the semiconductor structure 100 are measured using a surface topography tool, thereby obtaining the warp of the surface of the semiconductor structure 100 in a plurality of directions. In an alternative embodiment, the straight marks are formed in advance in the scribe lanes of the semiconductor structure 100, and then the warpage of the surface of the semiconductor structure 100 in a plurality of directions is obtained according to the deformation amount and shape of the straight marks. The warpage of the semiconductor structure 100 is the amount of deformation of the surface of the semiconductor structure 100 in the stacking direction relative to the main surface. The first type of warpage is, for example, a negative deformation amount, i.e., the surface of the semiconductor structure 100 is recessed with respect to the main surface. The second type of warpage is, for example, a positive deformation amount, i.e., the surface of the semiconductor structure 100 is raised with respect to the main surface. In the present application, the peripheral region of the semiconductor structure 100 is used to define the major surface. Therefore, the warpage is the amount of deformation of the middle region of the semiconductor structure 100 relative to the peripheral region. Since the warpage is measured in a plurality of directions on the surface of the semiconductor structure 100, this embodiment can also measure the directionality of the warpage. The surface warpage of the semiconductor structure 100 is isotropic if the warpage in multiple directions is the same. The surface warpage of the semiconductor structure 100 is anisotropic if the warpage in the plurality of directions is different.

The mask 202 is, for example, a photoresist mask covering the back film 201, or a shadow mask (e.g., a metal sheet) located above the back film 201.

The shape of the mask 202 is designed based on the measurement of the warpage, and if the surface warpage of the semiconductor structure 100 is isotropic, an isotropic pattern mask, such as a circular ring, a circular pattern mask, or no mask may be used. If the surface warpage of the semiconductor structure 100 is anisotropic, an anisotropic patterned mask, such as a rectangular, polygonal, elliptical or any combination thereof patterned mask, designed according to the etching pattern to be formed on the back surface of the back film 201, may be employed, the mask being asymmetrically distributed with respect to the center of the semiconductor structure 100.

Further, the back film 201 is etched to form an opening 203 exposing a portion of the surface of the semiconductor structure 100, as shown in fig. 3 c.

The shape and distribution of the openings 203 is controlled by the mask 202, in this embodiment the openings 203 extend from the surface of the backing film 201 to the second surface of the semiconductor structure 100. The opening 203 is formed, for example, by vapor etching. For example, the back film is exposed to hydrogen fluoride gas, which is used as an etchant to perform a vapor phase etching reaction in the process chamber, and the process chamber is maintained at a low pressure state so that water generated by the reaction exists in a gaseous form. Preferably, the mask 202 is removed after etching, for example using dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, by controlling the etching time such that etching stops near the surface of the backing film 201. In other embodiments, the opening 203 may extend to any location within the interior of the backing film 201.

Further, a stress layer 204 is formed in the opening 203, so that the surface of the semiconductor structure is restored to be flat, as shown in fig. 3 d.

The stress Layer 204 is formed by Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD), preferably by plasma CVD.

In this embodiment, the stress layer 204 is made of a material with low stress, the stress layer 204 is made of amorphous carbon, for example, and the stress layer 204 with low stress releases the stress of the semiconductor structure in the X/Y direction by filling the openings 203 with different patterns, so as to restore the semiconductor structure to a flat surface. In alternative embodiments, the material of the stress layer 204 may further have a shrinkage stress or an expansion stress to apply stress to the semiconductor structure 100, for example, the material of the stress layer 204 includes at least one of silicon nitride, silicon oxide, silicon oxynitride, polysilicon, amorphous carbon, and aluminum oxide. When the stress layer 204 has a shrinkage stress, the semiconductor structure 100 has a tendency that the edge is bent toward the back surface and the center is protruded toward the front surface. When the stress layer 204 has an expansion stress, the semiconductor structure 100 has a tendency that the edge is bent toward the front surface and the center is protruded toward the back surface. Warpage of the semiconductor structure may occur due to stress applied to the front surface of the wafer during formation of the gate stack structure on the front surface of the semiconductor structure 100. The stress layer 204 having a suitable stress may be selected according to the warpage type of the semiconductor structure 100, so that the semiconductor structure 100 recovers flatness, or the warpage state of the semiconductor structure 100 is adjusted to a symmetric warpage structure with uniform warpage degrees in various directions. In this embodiment, the stress layer 204 also covers the entire surface of the backing film 201, further enhancing the stress effect on the backside of the semiconductor structure 100.

Preferably, after the stress layer 204 is formed in the opening 203, a film 205 is formed on the surface of the stress layer to flatten the surface of the stress layer 204. The thin film 205 is, for example, an oxide film, the thickness of which should not affect the macroscopic stress of the semiconductor structure 100.

Preferably, after the oxide film on the surface of the stress layer 204 is formed, the stress layer material is annealed. The annealing process may be performed separately after the stress layer is formed, or may be performed in a subsequent process of the 3D memory device. The stress level of the stress layer 204 may also be adjusted by adjusting the process parameters of the annealing process, such as annealing time, temperature, etc., to adjust the shrinkage rate or expansion rate of the stress layer.

Further, the semiconductor structure 100 is flipped over and the surface of the semiconductor structure is planarized, as shown in fig. 3 e. The semiconductor structure is planarized, for example, by Chemical Mechanical Polishing (CMP).

Fig. 4a and 4b respectively show cross-sectional views of a modified structure provided according to a first embodiment of the present invention. The cross-sectional view is taken in a direction parallel to the semiconductor structure, the cross-section of the cross-sectional view passing through the backing film 201. A first embodiment of the invention provides a 3D memory device with a uniformly distributed rectangular stress layer within the backsheet.

As shown in fig. 4a, rectangular openings are formed uniformly distributed on a back film 201, and a stress layer 204 is formed within the rectangular openings. The length direction of the rectangular opening is along the X direction, and the width direction is along the Y direction, so that stress layers which are uniformly distributed in the Y direction and extend along the X direction are formed, and the warpage of the semiconductor structure in the Y direction is corrected.

As shown in fig. 4b, rectangular openings are formed uniformly distributed on the back membrane 201, and a stress layer 204 is formed within the rectangular openings. The length direction of the rectangular opening is along the Y direction, and the width direction is along the X direction, so that stress layers which are uniformly distributed in the X direction and extend along the Y direction are formed, and the warpage of the semiconductor structure in the X direction is corrected.

Fig. 5a and 5b respectively show cross-sectional views of a modified structure provided according to a second embodiment of the present invention. The cross-sectional view is taken in a direction parallel to the semiconductor structure, the cross-section of the cross-sectional view passing through the backing film 201. A second embodiment of the invention provides a modified structure having a non-uniformly distributed rectangular stress layer within a backing film.

As shown in fig. 5a, an opening with a cross section of a rectangular shape is formed on a back membrane 201 in a non-uniform distribution, and a stress layer 204 is formed in the opening. The length direction of the rectangular opening is along the X direction, and the width direction is along the Y direction, so that stress layers which are non-uniformly distributed in the Y direction and extend along the X direction are formed, and the stress layers are used for correcting non-uniform warping of the semiconductor structure in the Y direction.

As shown in fig. 5b, non-uniformly distributed openings having a rectangular cross section are formed in the backing film 201, and a stress layer 204 is formed in the openings. The length direction of the rectangular opening is along the Y direction, and the width direction is along the X direction, so that stress layers which are non-uniformly distributed in the X direction and extend along the Y direction are formed, and the stress layers are used for correcting non-uniform warping of the semiconductor structure in the X direction.

Fig. 6a to 6c respectively show sectional views of a modified structure provided according to a third embodiment of the present invention. The cross-sectional view is taken in a direction parallel to the semiconductor structure, the cross-section of the cross-sectional view passing through the backing film 201. A third embodiment of the present invention provides a modified structure having a circular, rectangular, or any combination thereof stress layer within a backsheet.

As shown in fig. 6a, an opening with a circular cross section is formed on a back film 201, the center of the circular ring is located at the center of the semiconductor structure, and a stress layer 204 is formed in the opening. The annular stress layer 204 is used to correct the isotropic warpage of the semiconductor structure.

As shown in fig. 6b, a plurality of openings having a rectangular cross section are formed on the back film 201, and a stress layer 204 is formed within the openings. The plurality of rectangular openings are distributed at any position on the surface of the back film, and the distribution positions of the rectangular openings can be designed according to the warping property of the semiconductor structure. The stress layer 204 is used to correct the anisotropic warpage of the semiconductor structure.

As shown in fig. 6c, a plurality of openings with rectangular cross-section are formed on the back membrane 201, and the stress layer 204 is formed in the openings. A plurality of rectangular openings with different sizes are distributed at any position on the surface of the back film, and the distribution positions of the rectangular openings can be designed according to the warping property of the semiconductor structure. The stress layer 204 is used to correct the anisotropic warpage of the semiconductor structure.

However, the present invention is not limited thereto, and in other embodiments, the cross section of the opening may be a hole shape in a polygonal shape, a ring shape, etc., a strip shape in a rectangular shape, an arc shape, a ring shape, etc., and any combination of these shapes.

Fig. 7a to 7c are graphs respectively illustrating stress simulation data of the semiconductor structure provided according to the first embodiment of the present invention. A cross-sectional view of the 3D memory device is shown in fig. 4 a.

Fig. 7a shows the stress released by the semiconductor structure in the Y direction as a function of the spacing of the stress layers. As shown in fig. 7a, stress release in a specific direction can be achieved by adjusting the distance between the stress layers, so as to achieve the purpose of repairing the warpage in a specific direction. The larger the pitch of the stress layer, the larger the amount of change in warpage.

Fig. 7b shows the warpage of the semiconductor structure in the X, Y direction and the variation of warpage with the thickness of the back film when no correction structure is formed. As shown in fig. 7b, the semiconductor structure has a large warpage when the modified structure (NO Trench) is not formed. After the correction is carried out in the Y direction, the warpage in the Y direction is obviously inhibited, the warpage in the X direction is slightly reduced, but the change is not obvious, the correction structure of the embodiment of the invention can effectively correct the warpage in a specific direction, and the correction of the warpage in different degrees can be realized by adjusting the thickness of the back film. The greater the warpage, the greater the required backing film thickness.

Fig. 7c shows the warpage of the semiconductor device in the direction X, Y as a function of the depth of the stress layer into the backing film. As shown in fig. 7c, the amount of change of the warpage in the X direction with the depth of the stress layer inserted into the backing film is not large, and the amount of change in the Y direction with the depth of the stress layer inserted into the backing film is particularly significant, so that the magnitude of the stress can be controlled by adjusting the depth of the stress layer inserted into the backing film. The deeper the stress layer is inserted into the back membrane, the greater the amount of change in warpage.

Fig. 8 shows a graph of inline experimental data provided for a semiconductor structure according to a first embodiment of the present invention. A cross-sectional view of the 3D memory device is shown in fig. 4 a.

As shown in fig. 8, before correcting the warpage of the surface of the semiconductor structure, the warpage of the corrected structure in the X-Y direction is zero, and the surface of the corrected structure is a plane. The corrected structure has a warp of-67 in the X-Y direction after bonding with the warped semiconductor structure. The change in the warpage of the modified structure indicates that the modified structure is effective in modifying the anisotropic warpage of the semiconductor structure.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.

Claims

1. A 3D memory, comprising:

a 3D storage structure;

a backing film located on and adjacent to a surface of the 3D storage structure; and

a stress layer abutting the backing film,

wherein the back membrane comprises an opening, the stress layer is positioned in the opening, the shape of the opening comprises a hole shape or a strip shape of a polygon, a circle, a ring shape and any combination thereof, the opening is used for limiting the pattern of the stress layer, the adjustment of warpage of different degrees is realized by adjusting the thickness of the back membrane, the shape of the opening and the material of the stress layer, so that the warpage is corrected or adjusted to be symmetrical warpage with consistent warpage degrees in all directions,

in the case of correcting the warpage, the openings are distributed symmetrically about the center of the 3D storage structure to enable correction of isotropic warpage by the stress layer, or distributed symmetrically about the non-center of the 3D storage structure to enable correction of anisotropic warpage by the stress layer.

2. The 3D memory of claim 1, wherein the 3D storage structure comprises a wafer and a gate stack structure on a first surface of the wafer,

the back film is positioned on the second surface of the wafer, and the first surface and the second surface of the wafer are opposite to each other.

3. The 3D memory according to claim 1, wherein the number of the openings is at least one.

4. The 3D memory of claim 1, wherein the opening extends from a surface of the backing film to any depth inside the backing film.

5. The 3D memory of claim 1, wherein the opening extends through the backing film to the surface of the 3D storage structure.

6. The 3D memory of claim 1, wherein the material of the stress layer comprises at least one of a material having a compressive stress, a material having an expansive stress, and a material having a low stress.

7. The 3D memory according to claim 1, wherein a surface of the stress layer is covered with a thin film, a thickness of the thin film does not affect a macroscopic stress of the 3D memory structure.

8. A surface conditioning method of a 3D memory, comprising:

forming a 3D memory structure;

forming a back film, wherein the back film is positioned on the surface of the 3D storage structure and is adjacent to the surface of the 3D storage structure;

forming an opening on the back film; and

forming a stress layer located within the opening,

wherein the shape of the opening comprises a polygonal shape, a circular shape, an annular shape and a hole shape or a strip shape of any combination thereof, the opening is used for limiting the pattern of the stress layer, the adjustment of the warpage of different degrees is realized by adjusting the thickness of the back membrane, the shape of the opening and the material of the stress layer, so that the warpage is corrected or adjusted to be symmetrical warpage with consistent warpage degrees in all directions,

9. The surface conditioning method of claim 8, wherein the step of forming an opening in the backing film comprises:

measuring surface warpage of the 3D storage structure;

designing a mask pattern according to the directionality of the warpage; and

and etching the back film to form an opening on the back film.

10. The surface conditioning method of claim 8, further comprising: and forming a film on the surface of the stress layer, wherein the thickness of the film does not influence the macroscopic stress of the 3D storage structure.

11. The surface modification method of claim 8, further comprising, after forming the stress layer within the opening: and carrying out planarization treatment on the surface of the 3D storage structure, wherein the planarization treatment comprises chemical mechanical polishing.