CN110676256B

CN110676256B - 3D memory device and method of manufacturing the same

Info

Publication number: CN110676256B
Application number: CN201910972636.5A
Authority: CN
Inventors: 谢柳群; 杨川; 许波; 殷姿
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-10-14
Filing date: 2019-10-14
Publication date: 2023-08-08
Anticipated expiration: 2039-10-14
Also published as: CN110676256A

Abstract

The application discloses a 3D memory device and a method of manufacturing the same. The 3D memory device includes: a substrate; a gate stack structure over the substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; a plurality of channel pillars penetrating the gate stack structure; and a conductive channel penetrating through the gate stack structure, wherein at least part of the bottom surface of the conductive channel is a curved surface. At least part of the bottom surface of the conductive channel in the 3D memory device is a curved surface, so that the uniformity of the outline of the bottom surface of the conductive channel is improved, better electrical parameters can be realized, and the yield and reliability of the 3D memory device are improved.

Description

3D memory device and method of manufacturing the same

Technical Field

The invention relates to the technical field of memories, in particular to a 3D memory device and a manufacturing method thereof.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As feature sizes of semiconductor fabrication processes become smaller, memory density of memory devices becomes higher. In order to further increase the storage density, three-dimensional structured memory devices (i.e., 3D memory devices) have been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can improve integration in multiple per unit area of a wafer, and can reduce cost.

Existing 3D memory devices are mainly used as nonvolatile flash memories. Two main non-volatile flash technologies employ NAND and NOR architectures, respectively. The read speed in the NAND memory device is slightly slower, but the write speed is fast, the erase operation is simple, and smaller memory cells can be realized, thereby achieving higher memory density, as compared to the NOR memory device. Therefore, 3D memory devices employing NAND structures have found wide application.

In a 3D memory device of NAND architecture, a stacked architecture is employed to provide the gate conductors of the select transistors and the memory transistors, and conductive vias through the stacked architecture are employed to interconnect the strings of memory cells. However, the bottom surface of the conductive channel is perpendicular to the sidewalls, which can adversely affect the bottom gate oxide and adversely affect subsequent ion implantation processes.

Accordingly, further improvements in 3D memory devices and methods of manufacturing the same are desired to increase yield and reliability of 3D memory devices.

Disclosure of Invention

In view of the foregoing, it is an object of the present invention to provide a 3D memory device and a method of manufacturing the same, in which at least a portion of a bottom surface of a conductive channel is curved, thereby facilitating improvement of uniformity of ion implantation.

According to a first aspect of the present invention, there is provided a 3D memory device comprising: a substrate; a gate stack structure over the substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; a plurality of channel pillars extending through the gate stack; and a conductive channel penetrating through the gate stack structure, wherein at least part of the bottom surface of the conductive channel is a curved surface.

Preferably, the bottom surface of the conductive channel is a conical surface.

Preferably, the conductive channel extends to the substrate, and a doped region is arranged at a position corresponding to the bottom surface of the conductive channel on the substrate, and the doped region enables the conductive channel to be electrically connected with the substrate.

Preferably, the plurality of channel pillars are connected to a source line via the conductive path.

Preferably, the method further comprises: a CMOS circuit in the substrate, the conductive channels providing electrical connection between the CMOS circuit and external circuitry.

According to a second aspect of the present invention, there is provided a method of manufacturing a 3D memory device, comprising: forming a gate stack structure over a substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; forming a plurality of channel pillars through the insulating stack structure; and forming a conductive channel penetrating through the gate stack structure, wherein at least part of the bottom surface of the conductive channel is a curved surface.

Preferably, the method for forming the gate stack structure includes: forming an insulating stack structure above the substrate, the gate stack structure including a plurality of sacrificial layers and a plurality of interlayer insulating layers alternately stacked; forming a gate line slit penetrating through the insulating laminated structure; and replacing the plurality of sacrificial layers in the insulating laminated structure with a plurality of gate conductors to form a gate laminated structure, wherein the conductive channels are formed in the gate line gaps, and the bottom surface shapes of the gate line gaps are matched with the bottom surface shapes of the conductive channels.

Preferably, the method for forming the gate line slit includes: forming the gate line gap penetrating through the insulating laminated structure by adopting a dry etching process; and processing the bottom surface of the grid line gap by adopting a soft etching process, so that at least part of the bottom surface of the grid line gap is a curved surface.

Preferably, after forming the gate line slit, the method further comprises: and carrying out ion implantation on the substrate through the bottom of the gate line gap to form a doped region.

Preferably, the method further comprises: a source connected to the conductive channel is formed, the plurality of channel pillars being connected to the source via the conductive channel.

According to the 3D memory device and the manufacturing method thereof, at least part of the bottom surface of the conductive channel is a curved surface, so that uniformity of the outline of the bottom surface of the conductive channel is improved, and better electrical parameters can be realized, for example, electrical performance of the lightly doped drain electrode acting on the common source electrode can be improved. Further, since at least a part of the bottom surface of the gate line slit is curved, uniformity of ion implantation can be improved when ion implantation is performed, and adverse effects of ion implantation on the bottom gate oxide layer can be avoided.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1a and 1b show an equivalent circuit diagram and a schematic structure diagram of a memory cell string of a 3D memory device, respectively.

Fig. 2 illustrates a perspective view of a 3D memory device.

Fig. 3a to 3h illustrate cross-sectional views of various stages of a 3D memory device manufacturing method according to an embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.

It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.

If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying … … and adjoining" will be used herein.

In this application, the term "semiconductor structure" refers to a generic term for the entire semiconductor structure formed in the various steps of fabricating a memory device, including all layers or regions that have been formed. Numerous specific details of the invention, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

The invention may be embodied in various forms, some examples of which are described below.

Fig. 1a and 1b show a circuit diagram and a schematic diagram of a memory cell string of a 3D memory device, respectively. The memory cell string shown in this embodiment includes a case of 4 memory cells. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, the memory cell string 100 has a first terminal connected to the bit line BL and a second terminal connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first selection transistor Q1, memory transistors M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the string selection line SSL, and the gate of the second selection transistor Q2 is connected to the ground selection line GSL. The gates of the memory transistors M1 to M4 are connected to the corresponding word lines of the word lines WL1 to WL4, respectively.

As shown in fig. 1b, the first and second select transistors Q1 and Q2 of the memory cell string 100 include gate conductors 122 and 123, respectively, and the memory transistors M1 to M4 include gate conductors 121, respectively. The gate conductors 121, 122, and 123 are aligned with the stacking order of transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 penetrates the gate stack structure. In the middle portion of the channel pillar 110, a tunneling dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 are sandwiched between a gate conductor 121 and a channel layer 111, thereby forming memory transistors M1 to M4. A blocking dielectric layer 114 is interposed between the gate conductors 122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming a first selection transistor Q1 and a second selection transistor Q2. In this embodiment, only 4 storage transistors are given as examples, and it is to be understood that the present invention is not limited thereto, and the number of storage transistors may be any number.

In this embodiment, the channel layer 111 is composed of, for example, doped polysilicon, the tunneling dielectric layer 112 and the blocking dielectric layer 114 are each composed of an oxide, for example, silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, for example, silicon nitride containing microparticles of a metal or semiconductor, and the gate conductors 121, 122, and 123 are composed of a metal, for example, tungsten. The channel layer 111 is used to provide channel regions for controlling the select and memory transistors, and the doping type of the channel layer 111 is the same as the type of the select and memory transistors. For example, for an N-type select transistor and a memory transistor, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of the channel pillar 110 is the channel layer 111, and the tunneling dielectric layer 112, the charge storage layer 113, and the blocking dielectric layer 114 form a gate stack structure around the core sidewalls. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunneling dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a gate stack structure around the core.

In this embodiment, the first and second selection transistors Q1 and Q2 and the memory transistors M1 to M4 use a common channel layer 111 and blocking dielectric layer 114. In the channel pillar 110, a channel layer 111 provides source and drain regions and channel layers of a plurality of transistors. In alternative embodiments, the epitaxial layers and the blocking dielectric layers of the first and second selection transistors Q1 and Q2 and the epitaxial layers and the blocking dielectric layers of the memory transistors M1 to M4 may be formed separately from each other.

In the write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 to M4 using FN tunneling efficiency. Taking the memory transistor M2 as an example, the ground selection line GSL is biased to about zero volt while the source line SL is grounded, so that the selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to the high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at a programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at a low voltage VPS1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges to be stored in the charge storage layer 113 of the memory transistor M2.

In the read operation, the memory cell string 100 judges the amount of charge in the charge storage layer according to the on state of a selected one of the memory transistors M1 to M4, thereby obtaining data representing the amount of charge. Taking memory transistor M2 as an example, word line WL2 is biased at read voltage VRD and the remaining word lines are biased at high voltage VPS2. The on state of the memory transistor M2 is related to its threshold voltage, i.e. to the amount of charge in the charge storage layer, so that the data value can be determined from the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in the on state, and thus, the on state of the memory cell string 100 depends on the on state of the memory transistor M2. The control circuit judges the on state of the memory transistor M2 from the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2 illustrates a perspective view of a 3D memory device. For clarity, the various insulating layers in the 3D memory device are not shown in fig. 2.

The 3D memory device 200 shown in this embodiment includes a total of 16 memory cell strings 100 of 4*4, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 4 x 4 total of 64 memory cells. It is to be understood that the present invention is not limited thereto, and the 3D memory device may include any number of memory cell strings, for example 1024, and the number of memory cells in each memory cell string may be any number, for example 32 or 64.

In a 3D memory device, the memory cell strings include respective channel pillars 110, and common gate conductor layers 121, 122, and 123, respectively. The gate conductor layers 121, 122 and 123 are aligned with the stacking order of transistors in the memory cell string 100, and adjacent gate conductor layers are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the drawing.

The internal structure of the channel pillar 110 is shown in fig. 1b and will not be described in detail herein. In the middle portion of the channel pillar 110, the gate conductor layer 121 forms memory transistors M1 to M4 together with the channel layer 111, the tunneling dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 inside the channel pillar 110. At both ends of the channel pillar 110, gate conductor layers 122 and 123 form select transistors Q1 and Q2 together with a channel layer 111 and a gate dielectric layer 114 inside the channel pillar 110.

The channel pillars 110 extend through the gate stack 120 and are arranged in an array, with the first ends of the plurality of channel pillars 110 of a same column commonly connected to a same bit line (i.e., one of bit lines BL 1-BL 4), the second ends commonly connected to the substrate 101, and the second ends forming a common source (Array Common Source, ACS) connection via the substrate 101.

The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit) 161. The gate lines of the plurality of channel pillars 110 of the same row are commonly connected to the same string selection line (i.e., one of the string selection lines SSL1 to SSL 4).

The gate conductors 121 of the memory transistors M1 and M4 are connected to each other in different layers. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit, the gate lines of the same level reach the interconnection layer 132 via the respective conductive paths 131 to be interconnected with each other and then are connected to the same word line (i.e., one of the word lines WL1 to WL 4) via the conductive paths 133.

The gate conductors of the second selection transistors Q2 are connected in one piece. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line slit 161, the gate lines reach the interconnection layer 132 via the respective conductive paths 131 to be interconnected with each other and then are connected to the same ground selection line GSL via the conductive paths 133.

In other embodiments, there are multiple dummy channel pillars (not shown) in the non-memory region of the 3D memory device 200, which may be the same or different from the internal structure of the channel pillars 110, and which pass through at least a portion of the gate conductors in the gate stack structure. In the final 3D memory device, the dummy channel pillars are not connected to the bit lines, thereby providing only mechanical support, and are not used to form select transistors and memory transistors. Thus, the dummy channel pillars do not form an effective memory cell.

Fig. 3a to 3h illustrate cross-sectional views of various stages of a 3D memory device manufacturing method according to an embodiment of the present invention. The cross-sectional view is taken along line AA in fig. 2.

The method begins with a semiconductor structure in which channel pillars 110 have been formed, as shown in fig. 3 a.

A stacked structure 150 in which interlayer insulating layers 151 and sacrificial layers 152 are alternately stacked is formed on a substrate 101, and a channel pillar 110 penetrating the stacked structure 150 is formed. In this embodiment, the substrate 101 is, for example, a single crystal silicon substrate, the interlayer insulating layer 151 is, for example, composed of silicon oxide, and the sacrificial layer 152 is, for example, composed of silicon nitride.

The sacrificial layer 122 will be replaced with a gate conductor, which is further connected to a word line, as described below. To form a conductive path from the gate conductor to the word line, the plurality of sacrificial layers 122 are, for example, patterned in a step-like manner, i.e., an edge portion of each sacrificial layer 122 is exposed with respect to the overlying sacrificial layer to provide an electrical connection region. After the patterning step of the plurality of sacrificial layers 122, an insulating layer may be used to cover the insulating stack structure. The interlayer insulating layer 108 between the plurality of sacrificial layers 122 and the interlayer insulating layer covering the insulating stack structure are integrally shown in fig. 3 a. However, the present invention is not limited thereto, and the interlayer insulating layer between and over the plurality of sacrificial layers 122 may be formed using a plurality of independent deposition steps.

The internal structure of the channel pillar 110 is shown in fig. 1b and will not be described in detail herein. Referring to fig. 1b, at the middle portion of the channel pillar 110, the channel pillar 110 includes a channel layer 111, a tunneling dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114 stacked in order, and at both ends of the channel pillar 110, the channel pillar 110 includes a channel layer 111 and a gate dielectric layer 114 stacked in order.

Further, a gate line slit 161 is formed in the stacked structure 150 as shown in fig. 3 b.

In this step, for example, a photoresist mask is formed on the surface of the semiconductor structure, followed by anisotropic etching, which may be dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, etching is stopped below the surface of the substrate 101. The photoresist mask is removed after etching by dissolution in a solvent or ashing. After the anisotropic etching, the bottom of the gate line slit 161 is processed using a soft etching (soft etch) process, and a flexible mask is used as a pattern transfer medium, for example, using techniques such as microcontact printing, transfer micro-mold, capillary micro-mold, solvent-assisted micro-mold, near-field photo-etching, soft molding, nano-imprint, etc., so that at least a portion of the bottom surface of the gate line slit 161 is curved.

In this embodiment, the gate line slit 161 is used not only to divide the gate conductor into a plurality of gate lines but also to form a conductive path for common source connection. For this purpose, the gate line slit 161 penetrates the stacked structure 150 to reach the substrate 101.

Further, a doped region 102 is formed in the substrate 101, as shown in fig. 3 c.

In this step, ion Implantation (IMP) is performed in the substrate 101 via the gate line slit 161, and a doped region 102 of N type (using an N type dopant, for example P, as) or P type (using a P type dopant, for example B) is formed in the substrate 101. Doped region 102 serves as a contact region for the common source connection for reducing the contact resistance between the subsequently formed conductive channel and substrate 101. After ion implantation, the semiconductor structure is annealed.

In this embodiment, since at least a portion of the bottom surface of the gate line slit 161 is a curved surface, preferably, the bottom surface of the gate line slit 161 is a tapered surface, the ion distribution conforms to the gaussian distribution when the ion implantation is performed, and the uniformity of the ion implantation can be improved, and adverse effects of the ion implantation on the bottom gate oxide layer 153 can be avoided.

Further, using the gate line slit 161 as an etchant passage, the sacrificial layer 152 in the stacked structure 150 is removed by isotropic etching to form a cavity 162, as shown in fig. 3 d.

The isotropic etching may employ selective wet etching or vapor etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. An etching gas is used as an etchant in a gas phase etching, wherein the semiconductor structure is exposed to the etching gas. In the case where the interlayer insulating layer 151 and the sacrificial layer 152 in the stacked structure 150 are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and one or more of C4F8, C4F6, CH2F2, and O2 may be used in vapor etching. In the etching step, the etchant fills the gate line slit 161. The end of the sacrificial layer 152 in the stack structure 150 is exposed in the opening of the gate line slit 161, and thus, the sacrificial layer 152 is contacted to the etchant. The etchant gradually etches the sacrificial layer 152 from the opening of the gate line slit 161 toward the inside of the stacked structure 150. Due to the selectivity of the etchant, the etching removes the sacrificial layer 152 with respect to the interlayer insulating layer 151 in the stacked structure 150.

Preferably, after the wet etching step described above, an additional etching step may be employed to remove etching products (e.g., silicon oxide) attached on the interlayer insulating layer 151 so that the exposed surface of the interlayer insulating layer 151 in the cavity 162 is planarized.

Further, the gate line slit 161 and the cavity 162 are filled with the metal layer 154 as shown in fig. 3 e. The metal layer 154 is composed of tungsten, for example.

In this step, atomic Layer Deposition (ALD) is used to fill the gate line slit 161 and the cavity 162 with the metal layer 154 using the gate line slit 161 as a deposition path. For example, the precursor source used in atomic layer deposition is, for example, tungsten hexafluoride WF6, and the reducing gas used is, for example, silane SiH4 or diborane B2H6. In the step of atomic layer deposition, a deposition process is performed by obtaining a tungsten material by chemisorption of a reaction product of tungsten hexafluoride WF6 and silane SiH 4.

Preferably, before forming the metal layer 154, a nucleation layer (not shown), for example, composed of silicide or nitride of tungsten, is formed on the exposed surface of the interlayer insulating layer 151 using Atomic Layer Deposition (ALD). The metal layer 154 is formed on the surface of the nucleation layer, the chemisorption characteristic of the precursor source on the surface during atomic layer deposition may be improved, and the adhesion strength of the metal layer 154 on the interlayer insulating layer 151 may be improved.

Further, the gate line slit 161 is reformed in the metal layer 154 as shown in fig. 3 f.

In this step, a photoresist mask is formed on the surface of the semiconductor structure, and then an etch back (etch back) is performed to reform the gate line slit 161 in the metal layer 154, the etch back using sulfur fluoride, nitrogen and chlorine as etchants to remove the tungsten material of the gate line slit 161. Further, the gate line slit 161 not only separates the metal layer 154 into different layers, thereby forming the gate conductors 121, 122, and 123, but also separates the gate conductors of each layer into a plurality of gate lines. On the side walls of the gate line slit 161, the ends of the gate conductors 121, 122, and 123 adjacent to the gate line slit 161 are exposed.

The gate conductors 121, 122, and 123 formed in this step are alternately stacked with the interlayer insulating layer 151, thereby forming the gate stack structure 120. The gate conductors 121, 122 and 123 in the gate stack 120 replace the sacrificial layer 152 in the stack 150 compared to the stack 150.

Further, a dielectric layer 155 is formed to cover the upper surface of the gate stack structure 120 and the sidewalls of the gate line slit 161, as shown in fig. 3 g. Dielectric layer 155 is, for example, silicon oxide, and dielectric layer 155 is formed by a chemical vapor deposition process.

Further, a conductive channel 141 filled in the gate line slit 161 is formed as shown in fig. 3 h. The material of the conductive channel 141 is, for example, metallic tungsten or other conductive material, and in alternative embodiments, the conductive channel 141 may be a reasonable combination of metallic material and insulating material, and the specific structure of the conductive channel 141 is not limited in this application.

The channel pillars 110 form a common source connection through the substrate 100, and the conductive channels 141 provide a conductive path for the common source connection to the source lines SL. In this embodiment, a conductive via 141 extends through the gate stack 120, and a first end of the conductive via 141 is connected to the substrate 101 and contacts the doped region 102 in the substrate 101, thereby making a connection with the substrate 101. Preferably, there is a CMOS circuit in the substrate 101, the conductive via 141 also providing an electrical connection between the CMOS circuit and external circuitry.

In this embodiment, since at least a portion of the bottom surface of the gate line slit 161 is curved, at least a portion of the bottom surface of the conductive channel 141 is curved, and uniformity of the profile of the bottom surface of the conductive channel 141 is improved, so that more excellent electrical parameters can be realized, for example, electrical performance of the lightly doped drain (lightly doped drain, LDD) acting on the common source can be improved.

In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

The embodiments of the present invention are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.

Claims

1. A 3D memory device, comprising:

a substrate;

a gate stack structure over the substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked;

a plurality of channel pillars extending through the gate stack; and

a conductive channel penetrating the gate stack structure, the conductive channel being formed in a gate line slit penetrating the gate stack structure, the bottom surface shape of the gate line slit being matched with the bottom surface shape of the conductive channel,

and forming the grid line gap penetrating through the grid stack structure by adopting a dry etching process, and processing the bottom surface of the grid line gap by adopting a soft etching process so that at least part of the bottom surface of the grid line gap is a curved surface, thereby at least part of the bottom surface of the conductive channel is a curved surface.

2. The 3D memory device of claim 1, wherein the bottom surface of the conductive via is a tapered surface.

3. The 3D memory device of claim 1, wherein the conductive via extends to the substrate, and wherein a doped region is provided at a location of the substrate corresponding to a bottom surface of the conductive via, the doped region electrically connecting the conductive via to the substrate.

4. The 3D memory device of claim 1 or 3, wherein the plurality of channel pillars are connected to a source line via the conductive channel.

5. The 3D memory device of claim 1 or 3, further comprising: a CMOS circuit in the substrate, the conductive channels providing electrical connection between the CMOS circuit and external circuitry.

6. A method of manufacturing a 3D memory device, comprising:

forming a gate stack structure over a substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked;

forming a gate line gap penetrating through the gate stack structure;

forming a plurality of channel pillars penetrating the gate stack structure;

forming a conductive channel penetrating through the gate stack structure, wherein the conductive channel is formed in the gate line gap, the bottom surface shape of the gate line gap is matched with the bottom surface shape of the conductive channel,

7. The method of manufacturing of claim 6, wherein the method of forming the gate stack structure comprises:

forming an insulating stack structure above the substrate, the gate stack structure including a plurality of sacrificial layers and a plurality of interlayer insulating layers alternately stacked; and

and replacing the plurality of sacrificial layers in the insulating laminated structure with a plurality of gate conductors to form a gate laminated structure.

8. The method of manufacturing according to claim 6, further comprising, after forming the gate line slit: and carrying out ion implantation on the substrate through the bottom of the gate line gap to form a doped region.

9. The method of manufacturing according to claim 6, further comprising: a source connected to the conductive channel is formed, the plurality of channel pillars being connected to the source via the conductive channel.