CN110289259B

CN110289259B - 3D memory device and method of manufacturing the same

Info

Publication number: CN110289259B
Application number: CN201910567323.1A
Authority: CN
Inventors: 许锋; 李达; 靳磊
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-06-27
Filing date: 2019-06-27
Publication date: 2020-09-29
Anticipated expiration: 2039-06-27
Also published as: CN110289259A

Abstract

Disclosed is a method of manufacturing a 3D memory device, including: forming a stacked structure on a substrate, wherein the first stacked structure includes a plurality of interlayer insulating layers and a plurality of sacrificial layers that are alternately stacked; forming a plurality of channel pillars penetrating the first stacked structure; replacing the sacrificial layers with a plurality of gate conductor layers to form a laminated structure; wherein the plurality of channel pillars form a plurality of memory transistors with a plurality of first gate conductor layers of the plurality of gate conductor layers, and form a first select transistor and a second select transistor with a second gate conductor layer and a third gate conductor layer of the plurality of gate conductor layers, respectively; the thickness of the interlayer insulating layer between the plurality of first gate conductor layers varies in a direction perpendicular to the surface of the substrate. The embodiment of the invention can balance the erasing speed difference of different layers of storage units caused by different sizes of the channel columns, thereby improving the reliability of the 3D memory.

Description

3D memory device and method of manufacturing the same

Technical Field

The invention relates to the technical field of memories, in particular to a 3D memory device and a manufacturing method thereof.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost. In a three-dimensional memory device such as a 3d nand flash memory, a memory array may include a core (core) region having channel pillars. The channel pillar is formed in a channel hole that vertically penetrates a stack of layers (stack) of the three-dimensional memory device. To increase storage density and capacity, the number of layers (tier) of three-dimensional memories continues to increase, for example, from 64 layers to 96, 128, or more layers. The channel hole of the stacked layers is formed by a single etching or a plurality of etches.

Then, the existing channel hole etching process has the following problems: 1) the channel holes have different diameters, and the upper part of the channel holes is larger than the lower part of the channel holes. This results in an erase speed for the different layers of memory cells. The aperture of the lower part of the channel hole is small, so that the electric field is more concentrated, and the erasing speed of the lower-layer storage unit is higher, thereby not only increasing the working difficulty for circuit design, but also being beneficial to the reliability of a 3D storage device; 2) the process of the lower memory cell is always worse than that of the upper memory cell, resulting in the lower memory cell being prone to have a lower read window.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a 3D memory device and a method of fabricating the same, which can solve the problems and the like.

According to an aspect of the present invention, there is provided a method of manufacturing a 3D memory device, including: forming a stacked structure on a substrate, wherein the first stacked structure includes a plurality of interlayer insulating layers and a plurality of sacrificial layers that are alternately stacked; forming a plurality of channel pillars penetrating the first stacked structure; replacing the sacrificial layers with a plurality of gate conductor layers to form a laminated structure; wherein the plurality of channel pillars form a plurality of memory transistors with a plurality of first gate conductor layers of the plurality of gate conductor layers, and form a first select transistor and a second select transistor with a second gate conductor layer and a third gate conductor layer of the plurality of gate conductor layers, respectively; the thickness of the interlayer insulating layer between the plurality of first gate conductor layers varies in a direction perpendicular to the surface of the substrate.

Preferably, the thickness of the interlayer insulating layer between the plurality of first gate conductor layers is gradually reduced from bottom to top.

Preferably, the second gate conductor layer is located below the first gate conductor layer, and a thickness of an interlayer insulating layer, which is close to the second gate conductor layer, among interlayer insulating layers between the plurality of first gate conductor layers is greater than thicknesses of remaining interlayer insulating layers between the plurality of first gate conductor layers.

Preferably, the third gate conductor layer is located below the first gate conductor layer, and a thickness of an interlayer insulating layer, which is close to the third gate conductor layer, among interlayer insulating layers between the plurality of first gate conductor layers is greater than thicknesses of remaining interlayer insulating layers between the plurality of first gate conductor layers.

Preferably, the plurality of first gate conductor layers vary in thickness in a direction perpendicular to the surface of the substrate.

Preferably, the step of forming the laminated structure comprises: forming a gate line slit penetrating the first stacked structure; removing the plurality of sacrificial layers in the first laminated structure through a gate line gap to form a cavity communicated with the gate line gap; filling metal layers in the grid line gap and the cavity through the grid line gap; and etching the metal layer to reform a gate line gap, thereby dividing the metal layer into the plurality of gate conductor layers of different layers.

Preferably, between the step of forming the gate line slit and the step of forming the cavity, further comprising: and forming a doped region in the substrate by using the gate line gap as an ion implantation channel.

Preferably, between the step of forming the cavity and the step of filling the metal layer, the method further comprises: and sequentially forming an isolation layer and a barrier layer on the surfaces of the plurality of interlayer insulating layers through the gate line gap.

Preferably, between the step of filling the metal layer and the step of reforming the gate line slit, further comprising: and sequentially forming a barrier layer and an isolation layer which seal the end parts of the plurality of gate conductor layers.

Preferably, the isolation layer is a high-K dielectric layer.

Preferably, the barrier layer is composed of at least one selected from titanium, titanium nitride, or a titanium/titanium nitride composite structure.

Preferably, the manufacturing method further includes: and filling a metal layer in the grid line gap to form a conductive channel.

According to another aspect of the present invention, there is provided a 3D memory device including: a substrate; a stacked structure over a substrate, the stacked structure including a plurality of gate conductor layers and a plurality of interlayer insulating layers that are alternately stacked; a plurality of channel pillars penetrating the stacked structure; wherein the plurality of channel pillars form a plurality of memory transistors with a plurality of first gate conductor layers of the plurality of gate conductor layers, and form a first select transistor and a second select transistor with a second gate conductor layer and a third gate conductor layer of the plurality of gate conductor layers, respectively; the thickness of the interlayer insulating layer between the plurality of first gate conductor layers varies in a direction perpendicular to the surface of the substrate.

Preferably, the 3D memory device further includes: a conductive via extending through the stacked structure, the conductive via being connected to bottom ends of the plurality of channel pillars via the substrate; wherein bottom ends of the plurality of channel pillars form a common source connection via the substrate, the conductive channel providing a conductive path connecting the common source to a source line.

Preferably, the 3D memory device further includes a doped region in the substrate, and the conductive channel is in contact with the doped region.

Preferably, the 3D memory device further includes a gate line slit penetrating the stacked structure to divide the plurality of gate conductor layers into a plurality of gate lines, the conductive channel being located in the gate line slit.

Preferably, the 3D memory device further includes: an isolation layer on a surface of the interlayer insulating layer; a barrier layer on a surface of the isolation layer; wherein the barrier layer and the isolation layer further seal ends of the gate conductor layer.

Preferably, the isolation layer is a high-K dielectric layer.

Preferably, wherein the barrier layer is composed of at least one selected from titanium, titanium nitride or a titanium/titanium nitride composite structure.

The 3D memory device and the manufacturing method thereof provided by the invention have the advantages that a first laminated structure is formed on a substrate and comprises a plurality of hierarchical insulating layers and a plurality of sacrificial layers which are alternately stacked, the plurality of sacrificial layers are replaced by a plurality of grid conductor layers, a first grid conductor layer in the plurality of grid conductor layers and a channel column form a memory transistor, the thickness of an interlayer insulating layer between the first grid conductor layers along the direction vertical to the surface of the substrate is changed, the erasing speed difference of different layers of memory units caused by different sizes of the channel column apertures can be balanced, and the reliability of the 3D memory is further improved.

Further, the 3D memory device bottom disturb coupling is improved, thereby increasing the read window of the bottom memory cell.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1a and 1b show a circuit diagram and a schematic structural diagram, respectively, of a memory cell string of a 3D memory device;

FIG. 2 shows a perspective view of a 3D memory device;

fig. 3a to 3f are sectional views showing stages of a method of manufacturing a 3D memory device according to a first embodiment of the present invention;

fig. 4 illustrates a cross-sectional view of a 3D memory device according to a second embodiment of the present invention;

fig. 5 illustrates a cross-sectional view of a 3D memory device according to a third embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.

The term "above" as used herein means above the plane of the substrate, and may refer to direct contact between materials or spaced apart.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, a first terminal of the memory cell string 100 is connected to a bit line BL, and a second terminal is connected to a source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M4, and a second select transistor Q2. The gate of the first select transistor Q1 is connected to a string select line SSL, and the gate of the second select transistor Q2 is connected to a ground select line GSL. The gates of the memory transistors M1 through M4 are connected to corresponding ones of the word lines WL1 through WL4, respectively.

As shown in fig. 1b, the selection transistors Q1 and Q2 of the memory cell string 100 include gate conductor layers 122 and 123, respectively, and the memory transistors M1 to M4 include gate conductor layers 121, respectively. The gate conductor layers 121, 122, and 123 are in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductor layers are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 is adjacent to or through the gate stack structure. In the middle portion of the channel pillar 110, a tunnel dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114 are interposed between the gate conductor layer 121 and the channel layer 111, thereby forming memory transistors M1 through M4. Gate dielectric layers 114 are sandwiched between the gate conductor layers 122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming selection transistors Q1 and Q2.

In this embodiment, the channel layer 111 is composed of, for example, doped polysilicon, the tunnel dielectric layer 112 and the gate dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the gate conductor layers 121, 122, and 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions of the control selection transistor and the control transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the control transistor. For example, for an N-type select transistor and control transistor, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of channel pillar 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure surrounding the semiconductor layers. In an alternative embodiment, the core of channel pillar 110 is a hollow structure, and channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure surrounding the semiconductor layers.

In this embodiment, the selection transistors Q1 and Q2, and the memory transistors M1 to M4 use the common channel layer 111 and gate dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layer and the gate dielectric layer of the selection transistors Q1 and Q2 and the semiconductor layer and the gate dielectric layer of the memory transistors M1 to M4, respectively, may be formed in separate steps from each other. In the channel column 110, semiconductor layers of the selection transistors Q1 and Q2 and semiconductor layers of the memory transistors M1 to M4 are electrically connected to each other.

In a write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 through M4 using FN tunneling efficiency. Taking the memory transistor M2 as an example, while the source line SL is grounded, the ground selection line GSL is biased to a voltage of about zero volts, so that the selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to a high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at the programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at the low voltage VPS 1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges stored in the charge storage layer 113 of the memory transistor M2.

In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer from the on-state of a selected one of the memory transistors M1 through M4, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that a data value can be determined according to the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory transistor M2. The control circuit judges the conductive state of the memory transistor M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2 shows a perspective view of a 3D memory device. For clarity, the respective insulating layers in the 3D memory device are not shown in fig. 2.

The 3D memory device 200 shown in this embodiment includes 4 x 4 for a total of 16 memory cell strings 100, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 4 x 4 for a total of 64 memory cells. It is understood that the present invention is not limited thereto and the 3D memory device may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

In the 3D memory device 200, the memory cell strings respectively include the respective channel pillars 110, and the common gate conductor layers 121, 122, and 123. The gate conductor layers 121, 122, and 123 are in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductor layers are spaced apart from each other with an interlayer insulating layer, thereby forming the gate conductor layer 120 of the gate stack structure. The interlayer insulating layer is not shown in the figure.

The internal structure of the channel pillar 110 is shown in fig. 1b and will not be described in detail. In the middle portion of the channel pillar 110, the gate conductor layer 121 forms memory transistors M1 through M4 together with the channel layer 111, the tunnel dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 inside the channel pillar 110. At both ends of the channel pillar 110, the gate conductor layers 122 and 123 form the selection transistors Q1 and Q2 together with the channel layer 111 and the gate dielectric layer 114 inside the channel pillar 110.

The thickness of the interlayer insulating layer between the gate conductor layers 121 forming the memory transistors M1 to M4 in the direction perpendicular to the substrate surface is varied.

The thickness of the interlayer insulating layer between the gate conductor layers 121 is gradually decreased from bottom to top.

In a preferred embodiment, when the gate conductor layer 122 is located below the gate conductor layer 121, the thickness of the interlayer insulating layer adjacent to the gate conductor layer 122 in the interlayer insulating layer between the gate conductor layers 121 is greater than the thickness of the remaining interlayer insulating layers between the gate conductor layers 121.

In a preferred embodiment, when the gate conductor layer 123 is located below the gate conductor layer 121, a thickness of an interlayer insulating layer adjacent to the gate conductor layer 123 among interlayer insulating layers between the gate conductor layers 121 is greater than thicknesses of remaining interlayer insulating layers between the plurality of gate conductor layers 121.

The channel pillars 110 penetrate through the gate conductor layer 120 and are arranged in an array, wherein first ends of a plurality of channel pillars 110 in a same column are commonly connected to a same bit line (i.e., one of the bit lines BL1 to BL 4), second ends are commonly connected to the substrate 101, and the second ends form a common source connection through the substrate 100.

The gate conductor layer 122 of the string selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit). The gate lines of the channel pillars 110 in the same row are commonly connected to the same string selection line (i.e., one of the string selection lines SSL1 through SSL 4).

The gate conductor layers 121 of the memory transistors M1 and M4 are integrally connected at different layers. If the gate conductor layers 121 of the memory transistors M1 and M4 are split into different gate lines by the gate line slit, the gate lines of the same level reach the interconnect layer 132 via respective conductive paths 131 to be interconnected with each other, and then are connected to the same word line (i.e., one of the word lines WL1 to WL 4) via the conductive path 133.

The gate conductor layers of the ground selection transistor Q2 are integrally connected. If the gate conductor layer 123 of the ground selection transistor Q2 is slit-divided into different gate lines by the gate lines, the gate lines reach the interconnection layer 132 via the respective conductive paths 131 to be interconnected with each other, and then are connected to the same ground selection line GSL via the conductive path 133.

According to the 3D memory device provided by the embodiment of the invention, the thickness of the interlayer insulating layer between the grid conductor layers forming the memory transistor along the direction vertical to the surface of the substrate is changed, so that the erasing speed difference of different layers of memory cells caused by different sizes of the channel columns can be balanced, and the reliability of the 3D memory is further improved.

In a preferred embodiment, the thickness of the gate conductor layer 121 forming the memory transistors M1-M4 in the direction perpendicular to the substrate surface is also varied.

The thickness of the gate conductor layer 121 along the direction perpendicular to the substrate surface gradually decreases from bottom to top. Or when the gate conductor layer 122 is located below the gate conductor layer 121, the thickness of the gate conductor layer 121 close to the gate conductor layer 122 is greater than the thickness of the other gate conductor layers 121. Or when the gate conductor layer 123 is located under the gate conductor layer 121, the thickness of the gate conductor layer 121 close to the gate conductor layer 123 is greater than the thickness of the other gate conductor layers 121.

Fig. 3a to 3f respectively show cross-sectional views of stages of a method of manufacturing a 3D memory device according to a first embodiment of the present invention. The cross-sectional view is taken along line AA in fig. 2.

As shown in fig. 3a, there is shown a basic structure of a 3D memory device manufacturing method according to an embodiment of the present invention, the structure forming step includes: a plurality of interlayer insulating layers 151 and a plurality of sacrificial layers 152 are alternately deposited on the substrate 101 to form a stacked first stacked structure 150. Etching the first stacked structure 150 to form a step structure of the core region; and filling the dielectric layer in the step region to planarize the surface of the core region.

In this embodiment, the substrate 101 is, for example, a single crystalline silicon substrate, and the substrate 101 includes a high voltage P-well region (HVPW) 102.

In this embodiment, the interlayer insulating layer 151 is made of silicon oxide, for example, and the sacrificial layer 152 is made of silicon nitride, for example, and a Chemical Vapor Deposition (CVD), an Atomic Layer Deposition (ALD), or another suitable deposition method may be used to alternately deposit an inter-metal dielectric layer (e.g., silicon oxide, etc.) and a metal replacement sacrificial layer (e.g., silicon nitride, etc.) on the substrate 101, wherein the sacrificial layer 152 is to be replaced with the gate conductor layer 120. The gate conductor layer 120 includes a gate conductor layer 121 forming a memory transistor, a gate conductor layer 122 forming a first selection transistor, and a gate conductor layer 123 forming a second selection transistor. The thickness of the interlayer insulating layer between the gate conductor layers 121 forming the memory transistors M1 to M4 in the direction perpendicular to the substrate surface is varied.

As shown in fig. 3b, a channel pillar 110 is formed through the first stacked structure 150, and the channel pillar 110 stops on the surface of the substrate 101.

For clarity, the internal structure of the channel pillar 110 is not shown in fig. 3 b. Referring to fig. 1b, in the middle portion of the channel pillar 110, the channel pillar 110 includes a channel layer 111, a tunneling dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114, which are sequentially stacked, and at both ends of the channel pillar 110, the channel pillar 110 includes the channel layer 111 and the gate dielectric layer 114, which are sequentially stacked.

Further, for example, a photoresist mask is formed on the surface of the semiconductor structure, and then anisotropic etching is performed to form a gate line slit 161 in the stacked structure 150, as shown in fig. 3 c.

The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time so that the etching stops near the surface of the substrate 101. The photoresist mask is removed by dissolving or ashing in a solvent after etching.

In this embodiment, the gate line slit 161 is used not only to divide the gate conductor into a plurality of gate lines but also to form a conductive path for source connection. For this, the gate line slit 161 penetrates the stacked structure 150 to reach the substrate 101.

Preferably, ion implantation is performed through the gate line slit 161 to form doped regions 102 of N-type (using an N-type dopant, e.g., P, As) or P-type (using a P-type dopant, e.g., B) in the substrate 101. The doped region 102 serves as a contact region for a common source connection for reducing the contact resistance between a subsequently formed conductive channel and the substrate 101.

Further, the sacrificial layer 152 in the stacked structure 150 is removed by isotropic etching using the gate line slit 161 as an etchant channel to form a cavity 162, as shown in fig. 3 d.

The isotropic etching may employ selective wet etching or vapor etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. Etching gases are used as etchants in vapor phase etching, wherein the semiconductor structure is exposed to the etching gas. In the case where the interlayer insulating layer 151 and the sacrificial layer 152 in the stacked-layer structure 150 are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and one or more of C4F8, C4F6, CH2F2, and O2 may be used in vapor phase etching. In the etching step, the gate line slit 161 is filled with an etchant. The end portion of the sacrificial layer 152 in the stacked structure 150 is exposed to the opening of the gate line slit 161, and thus, the sacrificial layer 152 is contacted to the etchant. The etchant gradually etches the sacrificial layer 152 from the opening of the gate line slit 161 toward the inside of the stacked-layer structure 150. The etching removes the sacrificial layer 152 with respect to the interlayer insulating layer 151 in the stack structure 150 due to the selectivity of the etchant.

Preferably, after the above-described wet etching step, an additional etching step may be employed to remove an etching product (e.g., silicon oxide) attached on the interlayer insulating layer 151, so that the exposed surface of the interlayer insulating layer 151 in the cavity 162 is planarized.

Preferably, after the above wet etching step, the isolation layer 153 and the barrier layer 154 are sequentially formed on the exposed surface of the interlayer insulating layer 151, the barrier layer 154 and the isolation layer 153 are sequentially formed at the end portions of the

gate conductors

121, 122 and 123 using the gate line slit 161 as a deposition channel, the metal layer 155 is filled in the gate line slit 161 and the cavity 162 using Atomic Layer Deposition (ALD), and the gate line slit 161 as a deposition channel using Chemical Vapor Deposition (CVD), and a photoresist mask is formed on the surface of the semiconductor structure, followed by etch back (etch back), to newly form the gate line slit 161 in the metal layer 155, as shown in fig. 3 e.

In this embodiment, the isolation layer 153 is a high-K dielectric layer. The barrier layer 154 is titanium, titanium nitride, or a titanium/titanium nitride composite structure.

In this embodiment, the metal layer 155 is composed of, for example, tungsten. The precursor source used in atomic layer deposition is, for example, tungsten hexafluoride WF6, and the reducing gas used is, for example, silane SiH4 or diborane B2H 6. In the step of atomic layer deposition, the deposition process is realized by obtaining tungsten material by chemical adsorption of a reaction product of tungsten hexafluoride WF6 and silane SiH 4.

The etch back uses sulfur fluoride, nitrogen and chlorine as etchants to remove the tungsten material of the gate line slit 161. Further, the gate line slit 161 not only separates the metal layer 155 into different layers to form the

gate conductors

121, 122, and 123, but also separates the gate conductor of each layer into a plurality of gate lines. On the sidewalls of the gate line slit 161, end portions of the

gate conductors

121, 122, and 123 adjacent to the gate line slit 161 are exposed.

The

gate conductors

121, 122, and 123 formed in this step are alternately stacked with the interlayer insulating layers 151, thereby forming the stacked-layer structure 120. In contrast to stack structure 150,

gate conductors

121, 122, and 123 in stack structure 120 replace sacrificial layer 152 in stack structure 150.

Further, the conductive channel 141 of the inner space thereof is filled in the gate line slit 161, as shown in fig. 3 f.

The conductive channel 141 is separated from the

gate conductors

121, 122, and 123 by an isolation layer 154. Similar to the channel pillar 110, the conductive via 141 penetrates the stacked structure 120. The conductive via 141 has a first end connected to the substrate 101 and a second end extending to the top of the stacked structure 120. In a preferred embodiment, the first end of the conductive channel 141 contacts the doped region 102 in the substrate 101, thereby making a connection with the substrate 101.

As described above, channel pillars 110 form a common source connection via substrate 100, and conductive channel 141 provides a conductive path for the common source connection to source line SL.

Fig. 4 illustrates a cross-sectional view of a 3D memory device according to a second embodiment of the present invention. Compared to the first embodiment of the present invention, when the gate conductor layer 122 of the present embodiment is located below the gate conductor layer 121, the thickness of the interlayer insulating layer close to the gate conductor layer 122 in the interlayer insulating layers between the gate conductor layers 121 is greater than the thickness of the remaining interlayer insulating layers between the gate conductor layers 121.

Fig. 5 illustrates a cross-sectional view of a 3D memory device according to a third embodiment of the present invention. When the gate conductor layer 123 is located below the gate conductor layer 121, a thickness of an interlayer insulating layer adjacent to the gate conductor layer 123 among interlayer insulating layers between the gate conductor layers 121 is greater than thicknesses of remaining interlayer insulating layers between the plurality of gate conductor layers 121.

Other details of the three-dimensional memory device, such as the structure of the memory array, the peripheral interconnections, etc., are not material to the present invention and will not be described herein.

In the context of the present invention, the three-dimensional memory device may be a 3D flash memory, such as a 3D nand flash memory.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method of manufacturing a 3D memory device, comprising:

forming a first stacked structure on a substrate, wherein the first stacked structure includes a plurality of interlayer insulating layers and a plurality of sacrificial layers that are alternately stacked;

forming a plurality of channel pillars penetrating the first stacked structure;

replacing the sacrificial layers with a plurality of gate conductor layers to form a laminated structure;

wherein the plurality of channel pillars form a plurality of memory transistors with a plurality of first gate conductor layers of the plurality of gate conductor layers, and form a first select transistor and a second select transistor with a second gate conductor layer and a third gate conductor layer of the plurality of gate conductor layers, respectively;

the thickness of the interlayer insulating layer between the plurality of first gate conductor layers in the direction perpendicular to the surface of the substrate is varied;

when the second grid conductor layer is positioned below the first grid conductor layer, the thickness of the interlayer insulating layer between the second grid conductor layer and the first grid conductor layer is larger than that between the plurality of first grid conductor layers; and/or when the third gate conductor layer is positioned below the first gate conductor layer, the thickness of the interlayer insulating layer between the third gate conductor layer and the first gate conductor layer is larger than that between the plurality of first gate conductor layers.

2. The manufacturing method according to claim 1, wherein a thickness of the interlayer insulating layer between the plurality of first gate conductor layers is gradually reduced from bottom to top.

3. The manufacturing method according to claim 1, wherein the thicknesses of the plurality of first gate conductor layers in a direction perpendicular to the surface of the substrate are varied.

4. The manufacturing method according to claim 1, wherein the step of forming the laminated structure includes:

forming a gate line slit penetrating the first stacked structure;

removing the plurality of sacrificial layers in the first laminated structure through a gate line gap to form a cavity communicated with the gate line gap;

filling metal layers in the grid line gap and the cavity through the grid line gap; and

and etching the metal layer to form a gate line gap again, thereby dividing the metal layer into the plurality of gate conductor layers of different layers.

5. The manufacturing method according to claim 4, further comprising, between the step of forming the gate line slit and the step of forming the cavity: and forming a doped region in the substrate by using the gate line gap as an ion implantation channel.

6. The manufacturing method according to claim 4, further comprising, between the step of forming the cavity and the step of filling the metal layer: and sequentially forming an isolation layer and a barrier layer on the surfaces of the plurality of interlayer insulating layers through the gate line gap.

7. The manufacturing method according to claim 6, wherein between the step of filling the metal layer and the step of reforming the gate line slit, further comprising:

and sequentially forming a barrier layer and an isolation layer which seal the end parts of the plurality of gate conductor layers.

8. The method of manufacturing of claim 7, wherein the isolation layer is a high-K dielectric layer.

9. The manufacturing method according to claim 7, wherein the barrier layer is composed of at least one selected from titanium, titanium nitride, or a titanium/titanium nitride composite structure.

10. The manufacturing method according to claim 4, further comprising: and filling a metal layer in the grid line gap to form a conductive channel.

11. A 3D memory device comprising:

a substrate;

a stacked structure over a substrate, the stacked structure including a plurality of gate conductor layers and a plurality of interlayer insulating layers that are alternately stacked;

a plurality of channel pillars penetrating the stacked structure;

12. The 3D memory device of claim 11, wherein the thickness of the interlayer insulating layer between the plurality of first gate conductor layers is gradually decreased from bottom to top.

13. The 3D memory device of claim 11, wherein the plurality of first gate conductor layers vary in thickness in a direction perpendicular to the surface of the substrate.

14. The 3D memory device of claim 11, further comprising:

a conductive via extending through the stacked structure, the conductive via being connected to bottom ends of the plurality of channel pillars via the substrate;

wherein bottom ends of the plurality of channel pillars form a common source connection via the substrate, the conductive channel providing a conductive path connecting the common source to a source line.

15. The 3D memory device of claim 14, further comprising a doped region in the substrate, the conductive channel being in contact with the doped region.

16. The 3D memory device of claim 14, further comprising a gate line slit that penetrates the stacked structure to divide the plurality of gate conductor layers into a plurality of gate lines, the conductive via being located in the gate line slit.

17. The 3D memory device of claim 11, further comprising:

an isolation layer on a surface of the interlayer insulating layer;

a barrier layer on a surface of the isolation layer;

wherein the barrier layer and the isolation layer further seal ends of the gate conductor layer.

18. The 3D memory device of claim 17, wherein the isolation layer is a high K dielectric layer.

19. The 3D memory device of claim 17, wherein the barrier layer is comprised of at least one selected from titanium, titanium nitride, or a titanium/titanium nitride composite structure.