CN109037226B - 3D memory device and method of manufacturing the same - Google Patents
3D memory device and method of manufacturing the same Download PDFInfo
- Publication number
- CN109037226B CN109037226B CN201811096306.6A CN201811096306A CN109037226B CN 109037226 B CN109037226 B CN 109037226B CN 201811096306 A CN201811096306 A CN 201811096306A CN 109037226 B CN109037226 B CN 109037226B
- Authority
- CN
- China
- Prior art keywords
- gate
- stack structure
- gate stack
- channel
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 135
- 239000004020 conductor Substances 0.000 claims abstract description 66
- 239000011229 interlayer Substances 0.000 claims abstract description 56
- 238000002955 isolation Methods 0.000 claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000003860 storage Methods 0.000 claims abstract description 20
- 230000000149 penetrating effect Effects 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 11
- 230000005641 tunneling Effects 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 230000015654 memory Effects 0.000 description 61
- 238000005530 etching Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 102100032401 Charged multivesicular body protein 2a Human genes 0.000 description 1
- 102100024827 Dynamin-1-like protein Human genes 0.000 description 1
- 101000943253 Homo sapiens Charged multivesicular body protein 2a Proteins 0.000 description 1
- 101000909218 Homo sapiens Dynamin-1-like protein Proteins 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- -1 for example Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011859 microparticle Substances 0.000 description 1
- 239000002159 nanocrystal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The application discloses a 3D memory device and a method of manufacturing the same. The 3D memory device includes: a semiconductor substrate; a channel pillar on the semiconductor substrate; and a first gate stack structure and a second gate stack structure, each gate stack structure being adjacent to the channel pillar and comprising a plurality of gate conductors and a plurality of interlayer insulating layers, respectively, the 3D memory device further comprising a first isolation structure penetrating the channel pillar, the first isolation structure separating the first gate stack structure from the second gate stack structure, wherein the plurality of gate conductors and the plurality of interlayer insulating layers of each gate stack structure are alternately stacked in a direction perpendicular to the surface of the semiconductor substrate, and the gate conductors of the first gate stack structure and the gate conductors of the second gate stack structure are staggered. The grid conductors of the first grid laminated structure and the grid conductors of the second grid laminated structure are staggered, so that the storage density of the 3D storage device is increased, and the space utilization rate of the 3D storage device is improved.
Description
Technical Field
The present invention relates to memory technology, and more particularly, to a 3D memory device and a method of manufacturing the same.
Background
The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As feature sizes of semiconductor fabrication processes become smaller, memory density of memory devices becomes higher. In order to further increase the storage density, three-dimensional structured memory devices (i.e., 3D memory devices) have been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can improve integration in multiple per unit area of a wafer, and can reduce cost.
Existing 3D memory devices are mainly used as nonvolatile flash memories. Two main non-volatile flash technologies employ NAND and NOR architectures, respectively. The read speed in the NAND memory device is slightly slower, but the write speed is fast, the erase operation is simple, and smaller memory cells can be realized, thereby achieving higher memory density, as compared to the NOR memory device. Therefore, 3D memory devices employing NAND structures have found wide application.
In a 3D memory device of a NAND structure, a gate stack structure, channel pillars penetrating the gate stack structure, and conductive channels are mainly included, gate conductors of a selection transistor and a memory transistor are provided by the gate stack structure, channel layers of the selection transistor and the memory transistor are provided by the channel pillars and the gate dielectric stack, and interconnection of memory cell strings is achieved by the conductive channels. However, as the number of layers of the gate stack structure increases, the gate conductor and the insulating layer for separating the gate conductor increase simultaneously in the gate stack structure, and the insulating layer occupies a large amount of space in the 3D memory device, not only increasing the size of the 3D memory device, but also decreasing the space utilization rate.
It is desirable to further improve the structure of the 3D memory device and the method of manufacturing the same, thereby increasing the storage density of the 3D memory device and reducing the size of the 3D memory device.
Disclosure of Invention
The invention aims to provide an improved 3D memory device and a manufacturing method thereof, and the gate conductor of a first gate stack structure and the gate conductor of a second gate stack structure are arranged in a staggered mode, so that the memory density of the 3D memory device is increased, and the space utilization rate of the 3D memory device is improved.
According to an aspect of the present invention, there is provided a 3D memory device including: a semiconductor substrate; a channel pillar on the semiconductor substrate; and a first gate stack structure and a second gate stack structure, each gate stack structure being adjacent to the channel pillar and comprising a plurality of gate conductors and a plurality of interlayer insulating layers, respectively, the 3D memory device further comprising a first isolation structure penetrating the channel pillar, the first isolation structure separating the first gate stack structure from the second gate stack structure, wherein the plurality of gate conductors and the plurality of interlayer insulating layers of each gate stack structure are alternately stacked in a direction perpendicular to a surface of the semiconductor substrate, and the gate conductors of the first gate stack structure and the gate conductors of the second gate stack structure are staggered.
Preferably, the material of the first isolation structure comprises silicon carbide.
Preferably, the material of the interlayer insulating layer of the first gate stack structure is selected from one of an oxide and a nitride, and the material of the interlayer insulating layer of the second gate stack structure is selected from the other of an oxide and a nitride.
Preferably, the first isolation structure equally divides the channel column.
Preferably, the plurality of channel columns are arranged in an array, and each column of the channel columns is arranged in a staggered manner with the channel columns of the adjacent columns.
Preferably, each column of the channel pillars is separated by the same first isolation structure.
Preferably, the semiconductor device further comprises grid line gaps, the grid stack structure is penetrated through, and the plurality of channel columns are located between the grid line gaps.
According to another aspect of the present invention, there is provided a method of manufacturing a 3D memory device, including: forming a gate stack structure on a semiconductor substrate, the gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; and forming a plurality of channel columns penetrating through the gate stack structure, wherein the gate conductors on one side of the channel columns correspond to the positions of the interlayer insulating layers on the other side of the channel columns.
Preferably, the step of forming the gate stack structure includes: forming an insulating stack structure on the semiconductor substrate, the insulating stack structure including a plurality of first interlayer insulating layers and a plurality of second interlayer insulating layers alternately stacked; forming a plurality of first isolation structures penetrating through the channel columns and the insulating laminated structure; forming a plurality of gate line slits penetrating through the insulating laminated structure; replacing the first interlayer insulating layer on one side of the first isolation structure with a gate conductor via the plurality of gate line slits; and replacing the second interlayer insulating layer at the other side of the first isolation structure with the gate conductor via the plurality of gate line slits.
According to the 3D memory device and the manufacturing method thereof provided by the embodiment of the invention, the gate conductor of the first gate stack structure and the gate conductor of the second gate stack structure are arranged in a staggered manner, so that the gate conductor on one side of the channel column is arranged opposite to the interlayer insulating layer on the other side of the channel column, a plurality of memory cells are formed by the gate conductors on both sides of the channel column and the corresponding parts of the channel column respectively, more memory cells are formed by using the channel column more fully, and the purpose of increasing the memory density of the 3D memory device is achieved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.
Fig. 1a and 1b show an equivalent circuit diagram and a schematic structure diagram of a memory cell string of a 3D memory device, respectively.
Fig. 2a shows a perspective view of a 3D memory device according to a first embodiment of the present invention.
Fig. 2b shows a perspective view of a 3D memory device according to a second embodiment of the present invention.
Fig. 3, 4, 6, 7, 9, 10, 12 to 14 illustrate cross-sectional views of stages of a method of manufacturing a 3D memory device according to a second embodiment of the present invention.
Fig. 5, 8, and 11 are top views showing respective stages of a method of manufacturing a 3D memory device according to a second embodiment of the present invention.
Fig. 15a to 16c show effect analysis schematic diagrams of a 3D memory device according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.
If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying and adjoining … …" will be used herein.
Numerous specific details of the invention, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The invention may be embodied in various forms, some examples of which are described below.
Fig. 1a and 1b show a circuit diagram and a schematic diagram of a memory cell string of a 3D memory device, respectively. The memory cell string shown in this embodiment includes a case of 4 memory cells. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.
As shown in fig. 1a, the memory cell string 100 has a first terminal connected to a Bit Line (BL) and a second terminal connected to a Source Line (SL). The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first selection transistor Q1, memory transistors M1 to M4, and a second selection transistor Q2. The gate of the first select transistor Q1 is connected to a string select line (Selection Gate for Drain, SGD) and the gate of the second select transistor Q2 is connected to a source select line (Selection Gate for Source, SGS). The gates of the memory transistors M1 to M4 are connected to corresponding Word lines (Word-Line) WL1 to WL4, respectively.
As shown in fig. 1b, the select transistors Q1 and Q2 of the memory cell string 100 include gate conductors 122 and 123, respectively, and the memory transistors M1 through M4 include gate conductors 121, respectively. The gate conductors 121, 122, and 123 are aligned with the stacking order of transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 is adjacent to or extends through the gate stack. In the middle portion of the channel pillar 110, a tunneling dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114 are sandwiched between a gate conductor 121 and a channel layer 111, thereby forming memory transistors M1 to M4. At both ends of the channel pillar 110, gate conductors 122 and 123 sandwich a gate dielectric layer 114 with the channel layer 111, thereby forming select transistors Q1 and Q2.
In this embodiment, the channel layer 111 is composed of, for example, polysilicon, the tunneling dielectric layer 112 and the gate dielectric layer 114 are each composed of an oxide, for example, silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, for example, silicon nitride containing microparticles of a metal or semiconductor, and the gate conductors 121, 122, and 123 are composed of a metal, for example, tungsten. The channel layer 111 is used to provide channel regions for the control select and control transistors, and the doping type of the channel layer 111 is the same as the types of the select and control transistors. For example, for an N-type select transistor and a control transistor, the channel layer 111 may be N-type doped polysilicon.
In this embodiment, the core of the channel pillar 110 is the channel layer 111, and the tunneling dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of the channel pillar 110 is an additional insulating layer, and the channel layer 111, the tunneling dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 form a stacked structure around the semiconductor layer.
In this embodiment, the selection transistors Q1 and Q2, the memory transistors M1 to M4 use a common channel layer 111 and gate dielectric layer 114. In the channel pillar 110, a channel layer 111 provides source and drain regions and channel layers of a plurality of transistors. In alternative embodiments, the semiconductor layers and gate dielectric layers of the select transistors Q1 and Q2 and the semiconductor layers and gate dielectric layers of the memory transistors M1 to M4 may be formed separately from each other. In the channel pillar 110, the semiconductor layers of the selection transistors Q1 and Q2 and the semiconductor layers of the memory transistors M1 to M4 are electrically connected to each other.
In the write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 to M4 using FN tunneling. Taking the memory transistor M2 as an example, while the source line SL is grounded, the source select line SGS is biased to about zero volts such that the select transistor Q2 corresponding to the source select line SGS is turned off, and the string select line SGD is biased to the high voltage VDD such that the select transistor Q1 corresponding to the string select line SGD is turned on. Further, bit line BL2 is grounded, word line WL2 is biased at a programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at a low voltage VPS1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges to be stored in the charge storage layer 113 of the memory transistor M2.
In the read operation, the memory cell string 100 judges the amount of charge in the charge storage layer according to the on state of a selected one of the memory transistors M1 to M4, thereby obtaining data representing the amount of charge. Taking memory transistor M2 as an example, word line WL2 is biased at read voltage VRD and the remaining word lines are biased at high voltage VPS2. The on state of the memory transistor M2 is related to its threshold voltage, i.e. to the amount of charge in the charge storage layer, so that the data value can be determined from the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in the on state, and thus, the on state of the memory cell string 100 depends on the on state of the memory transistor M2. The control circuit judges the on state of the memory transistor M2 from the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.
Fig. 2a shows a perspective view of a 3D memory device according to a first embodiment of the present invention. For clarity, only a portion of the first isolation structure 102 is shown in fig. 2a, and no other insulating layers in the 3D memory device of the first embodiment of the present invention are shown.
As shown in fig. 2a, the 3D memory device shown in the present embodiment includes: the semiconductor device comprises a semiconductor substrate 101, a plurality of channel pillars 110 positioned above the semiconductor substrate 101, a first gate stack structure 120a and a second gate stack structure 120b positioned above the semiconductor substrate 101 and adjacent to the channel pillars 110, and a first isolation structure 102 penetrating the channel pillars 110, wherein the first gate stack structure 120a comprises a plurality of gate conductors 121a, 122a, 123a and a plurality of interlayer insulating layers which are alternately stacked, and the second gate stack structure 120b comprises a plurality of gate conductors 121b, 122b, 123b and a plurality of interlayer insulating layers which are alternately stacked.
The plurality of trench columns 110 are arranged in an array, each column of trench columns 110 is arranged in a staggered manner with respect to the adjacent columns of trench columns 110, the trench columns 110 in the same column are separated and equally divided by the same first isolation structure 102, and meanwhile, the first isolation structure 102 also separates the first gate stack structure 120a from the second gate stack structure 120 b.
The gate conductors 121a, 122a, 123a of the first gate stack structure 120a and the gate conductors 121b, 122b, 123b of the second gate stack structure 120b are arranged in a staggered manner in a direction perpendicular to the surface of the semiconductor substrate 101, so that the 3D memory device shown in this embodiment includes a total of 2*n memory cell strings of 2n, where n is the number of channel columns 110.
Fig. 2b shows a perspective view of a 3D memory device according to a second embodiment of the present invention. For clarity, the individual insulating layers in the 3D memory device are not shown in fig. 2 b.
As shown in fig. 2b, the 3D memory device shown in the present embodiment includes: the semiconductor device comprises a semiconductor substrate 101, a plurality of channel pillars 110 positioned above the semiconductor substrate 101, a first gate stack structure 120a and a second gate stack structure 120b positioned above the semiconductor substrate 101 and adjacent to the channel pillars 110, a first isolation structure 102 penetrating the channel pillars 110, and a gate line slit 103 penetrating the gate stack structure, wherein the first gate stack structure 120a comprises a plurality of gate conductors 121a, 122a, 123a and a plurality of interlayer insulating layers which are alternately stacked, and the second gate stack structure 120b comprises a plurality of gate conductors 121b, 122b, 123b and a plurality of interlayer insulating layers which are alternately stacked.
The plurality of channel columns 110 are arranged in an array, and are located between the gate line slits 103, each column of channel columns 110 is arranged in a staggered manner with respect to the adjacent columns of channel columns 110, gate stack structures on two sides of the channel columns 110 are separated by a first isolation structure penetrating through the channel columns 110, and gate conductors on one side of the channel columns 110 are opposite to an interlayer insulating layer on the other side, so that staggered arrangement of the gate conductors is achieved, and in addition, the gate conductors on two sides of the channel columns 110 are separated into at least two parts by a second isolation structure, respectively, so that the 3D memory device shown in the embodiment includes 4n memory cell strings in total, where n is the number of the channel columns 110.
In the 3D memory device of the present embodiment, each channel pillar 110 is divided into 4 parts by the isolation structure, and the memory cell string includes a portion corresponding to the respective channel pillar 110 and a gate conductor, respectively. The gate conductors are aligned with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure.
Preferably, a CMOS circuit is included in the substrate semiconductor substrate 101, for example. Conductive vias are used to provide electrical connection between the CMOS circuitry and external circuitry.
Preferably, the 3D memory device shown in this embodiment further comprises dummy channel pillars 140 for providing mechanical support.
Fig. 3,4, 6, 7, 9, 10, 12 to 14 illustrate cross-sectional views of stages of a 3D memory device manufacturing method according to a second embodiment of the present invention, and fig. 5, 8, 11 illustrate top views of stages of a 3D memory device manufacturing method according to a second embodiment of the present invention. The method of manufacturing the inventive memory structure will be described in detail below with reference to fig. 3-14.
The method of manufacturing the 3D memory device of the present embodiment starts with the semiconductor substrate 101, and the insulating stack structure 130 is formed on the semiconductor substrate 101, as shown in fig. 3.
In this step, a first interlayer insulating layer 131 and a second interlayer insulating layer 132 may be stacked on the semiconductor substrate 101 using a deposition process, wherein a material of the first interlayer insulating layer 131 is selected from one of an oxide and a nitride, and a material of the second interlayer insulating layer 132 is selected from the other of the oxide and the nitride. In the present embodiment, the material of the first interlayer insulating layer 131 is oxide, and the material of the second interlayer insulating layer 132 is nitride.
Further, a plurality of first isolation structures 102 are formed throughout the insulating stack 130, the first isolation structures 102 extending into the semiconductor substrate 101, as shown in figure 4,
In this step, the insulating stack structure 130 and a portion of the semiconductor substrate 101 may be patterned using an etching process, a plurality of slits may be formed, and a material for forming the first isolation structure 102 may be filled in the slits, wherein the material of the first isolation structure 102 includes silicon carbide.
Further, a plurality of channel pillars 110 are formed through the insulating stack 130, as shown in fig. 5 to 7, wherein fig. 6 is a cross-sectional view along A-A or B-B line in fig. 5, and fig. 7 is a cross-sectional view along C-C line in fig. 5.
In this step, the insulating stack structure 130 may be patterned by an etching process to form a plurality of channel holes, then the gate dielectric layer 114, the charge storage layer 113, the tunneling dielectric layer 112, and the channel layer 111 are sequentially formed on the inner walls of the channel holes, and finally the contact region 115 is formed to form the channel pillar 110 for source contact through the semiconductor substrate 101. Wherein the first isolation structure 102 separates the insulating stack structures 130 on both sides of the channel pillar 110.
Preferably, the first isolation structures 102 divide the channel pillars 110 equally in the first direction.
Preferably, in this step, a dummy channel pillar may also be formed through the insulating stack 130, which may be the same or different from the internal structure of the channel pillar 110, and through at least a portion of the gate conductor in the gate stack. In the final 3D memory device, the dummy channel pillars are not connected to the bit lines, nor are they used to form select transistors and memory transistors. Thus, the dummy channel pillars do not form an effective memory cell.
Further, gate line slits 103 are formed through the insulating stack structure 130 and around the plurality of channel pillars 110, as shown in fig. 5 and 6, wherein the plurality of channel pillars 110 are located between the gate line slits 103.
Further, the second isolation structure 104 is formed through the insulating stack structure 130 and the plurality of channel pillars 110, as shown in fig. 5 and 6.
In this step, the insulating stack structure 130 may be patterned using an etching process to form a plurality of slits, and the slits are filled with a material for forming the second isolation structure 104, and the insulating stack structure 130 at both sides of the trench pillar 110 is separated into two portions by the second isolation structure 104, respectively, wherein the material of the second isolation structure 104 includes an oxide.
Preferably, the second isolation structure 104 equally divides the channel pillar 110 along the second direction, and the first direction is 90 degrees from the second direction.
Further, using the gate line slit 103 as an etchant passage, the second interlayer insulating layer 132 on the first isolation structure 102 side is removed by isotropic etching to form the cavity 105, as shown in fig. 8 and 9, and fig. 9 is a cross-sectional view taken along line A-A in fig. 8.
In this step, the isotropic etching may employ selective wet etching or vapor etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. An etching gas is used as an etchant in a gas phase etching, wherein the semiconductor structure is exposed to the etching gas. In the case where the first interlayer insulating layer 131 and the second interlayer insulating layer 132 in the insulating stack structure 130 are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and one or more of C 4F8、C4F6、CH2F2 and O 2 may be used in vapor etching. In the etching step, the etchant fills the gate line slit 103. An end portion of the second interlayer insulating layer 132 in the insulating stack structure 130 is exposed to the opening of the gate line slit 103, and thus, the second interlayer insulating layer 132 is contacted to the etchant. The etchant gradually etches the second interlayer insulating layer 132 from the opening of the gate line slit 103 toward the inside of the insulating stack structure 130. Due to the selectivity of the etchant, the etching removes the second interlayer insulating layer 132 with respect to the first interlayer insulating layer 131 in the insulating stack structure 130. The etchant does not etch the second interlayer insulating layer 132 at the other side of the channel pillar 110 due to the barrier of the first isolation structure 102.
Further, using the gate line slit 103 as an etchant channel, the first interlayer insulating layer 131 on the other side of the first isolation structure 102 is removed by isotropic etching to form the cavity 105, as shown in fig. 8 and 10, wherein fig. 10 is a cross-sectional view along line B-B in fig. 8.
In this step, the method of removing the first interlayer insulating layer 131 is similar to that of removing the second interlayer insulating layer 132, and will not be described here again.
Further, using the gate line slit 103 as a deposition path, atomic Layer Deposition (ALD) is used to fill a metal layer in the gate line slit 103 and the cavity 105 to form a gate conductor, and then etching back (etching back) is performed to reform the gate line slit 103, as shown in fig. 11 to 14, wherein fig. 12 is a cross-sectional view along A-A in fig. 11, fig. 13 is a cross-sectional view along B-B in fig. 11, and fig. 14 is a cross-sectional view along C-C in fig. 11.
In this embodiment, the metal layer is composed of tungsten, for example. The gate conductors (121 a, 122a, 123 a) on the first isolation structure 102 side replace the first interlayer insulating layer 131 in the insulating stack structure 130 to form the first gate stack structure 120a. The gate conductors (121 b, 122b, 123 b) on the other side of the first isolation structure 102 replace the second interlayer insulating layer 132 in the insulating stack 130 to form the second gate stack 120b.
Fig. 15a to 16c illustrate effect analysis diagrams of a 3D memory device according to an embodiment of the present invention.
Fig. 15a to 15c show, in which fig. 15b is a cross-sectional view of the N-th layer and the corresponding portion of the channel pillar in the gate stack structure of fig. 15a along the XY plane, and fig. 15c is a cross-sectional view of the n+1-th layer and the corresponding portion of the channel pillar in the gate stack structure of fig. 15a along the XY plane.
In an ideal process, if the number of stacked layers of the gate stack structure is increased, specifically, the number of layers of the gate conductor 121' is increased, so that the memory cell formed by the channel pillar 110' and the gate conductor 121' is increased, and in order to electrically isolate the gate conductor 121', an interlayer insulating layer 130' is also required to be formed between the increased gate conductors 121', so that the size of the 3D memory device is also increased, and in practical application, the gate stack structure has more than 40% of space occupied by the interlayer insulating layer 130' in the Z direction, resulting in that the gate stack structure wastes a lot of resources in the Z direction, for example, for a 64-layer 3D memory device, there are actually 64 layers of gate line metal (the gate conductor 121 ') and 64 layers of dielectric (the interlayer insulating layer 130 '), and the dielectric wastes nearly half of the space of the 3D memory device in the Z direction.
Fig. 16a to 16c show, in which fig. 16b is a cross-sectional view of the N-th layer and the corresponding portion of the channel pillar in the gate stack structure of fig. 16a along the XY plane, and fig. 16c is a cross-sectional view of the n+1-th layer and the corresponding portion of the channel pillar in the gate stack structure of fig. 16a along the XY plane.
In the embodiment of the present invention, to add the memory cells of the 3D memory device, only the gate conductor 121a on one side of the channel pillar 110 and the gate conductor 121b on the other side of the channel pillar 110 need to be staggered, so that the staggered layers of the gate conductors 121a and 121b are implemented in the Z direction, and the memory cells continuously exist in each layer in the Z direction, that is, in the gate stack structure, the portion of the channel pillar 110 corresponding to each layer including the interlayer insulating layer is fully utilized, and the memory cells are formed with the gate conductors 121a and 121b, so that the memory density is increased by at least 1 time in the Z direction.
In addition, the second isolation structures 103 penetrating the channel pillar 110 and the gate stack structure are formed to divide the split-layer gate conductors 121a and 121b on both sides of the channel pillar 110 into two, respectively, and two memory cells are formed on each side of the channel pillar 110 in each layer.
In combination with the improvement in three directions of XYZ, the storage density of the 3D storage device is at least increased to 4 times that of the original 3D storage device, and the size of the 3D storage device is not increased, so that compared with an ideal process, the effect of reducing the size of the 3D storage device is achieved.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present invention are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.
Claims (9)
1. A 3D memory device, comprising:
A semiconductor substrate;
The channel column is positioned on the semiconductor substrate, the core part of the channel column is a channel layer, and the tunneling dielectric layer, the charge storage layer and the gate dielectric layer form a laminated structure surrounding the side wall of the core part; and
A first gate stack structure and a second gate stack structure, each gate stack structure being adjacent to the channel pillar and comprising a plurality of gate conductors and a plurality of interlayer insulating layers, respectively,
The 3D memory device further includes a first isolation structure extending through the channel pillar, the first isolation structure separating the first gate stack structure from the second gate stack structure,
Wherein the plurality of gate conductors and the plurality of interlayer insulating layers of each gate stack structure are alternately stacked in a direction perpendicular to the surface of the semiconductor substrate, and the gate conductors of the first gate stack structure and the gate conductors of the second gate stack structure are arranged in a staggered manner.
2. The 3D memory device of claim 1, wherein the material of the first isolation structure comprises silicon carbide.
3. The 3D memory device of claim 1, wherein the material of the interlayer insulating layer of the first gate stack structure is selected from one of an oxide and a nitride,
The material of the interlayer insulating layer of the second gate stack structure is selected from the other one of oxide and nitride.
4. The 3D memory device of claim 1, wherein the first isolation structure averages the channel pillars.
5. The 3D memory device of any of claims 1-4, wherein a plurality of the channel pillars are arranged in an array, each column of the channel pillars being offset from an adjacent column of the channel pillars.
6. The 3D memory device of claim 5, wherein each column of the channel pillars is separated by the same first isolation structure.
7. The 3D memory device of any of claims 1-4, further comprising a gate line slit, a plurality of the channel pillars being located between the gate line slits throughout the gate stack structure.
8. A method of manufacturing a 3D memory device, comprising:
forming a plurality of channel pillars on a semiconductor substrate; and
Forming a first gate stack structure and a second gate stack structure on the semiconductor substrate, the first gate stack structure surrounding a portion of sidewalls of the plurality of channel pillars, the second gate stack structure surrounding another portion of sidewalls of the plurality of channel pillars, the first gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked, the second gate stack structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked,
The plurality of gate conductors of the first gate stack structure correspond to the plurality of interlayer insulating layers of the second gate stack structure in a direction perpendicular to the surface of the semiconductor substrate, and the plurality of interlayer insulating layers of the first gate stack structure correspond to the plurality of gate conductors of the second gate stack structure.
9. The method of claim 8, wherein forming the first gate stack structure and the second gate stack structure comprises:
Forming an insulating stack structure on the semiconductor substrate, the insulating stack structure including a plurality of first interlayer insulating layers and a plurality of second interlayer insulating layers alternately stacked;
Forming a plurality of first isolation structures penetrating through the channel columns and the insulating laminated structure;
forming a plurality of gate line slits penetrating through the insulating laminated structure;
Replacing the first interlayer insulating layer on one side of the first isolation structure with a gate conductor via the plurality of gate line slits; and
The second interlayer insulating layer at the other side of the first isolation structure is replaced with the gate conductor via the plurality of gate line slits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811096306.6A CN109037226B (en) | 2018-09-19 | 2018-09-19 | 3D memory device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811096306.6A CN109037226B (en) | 2018-09-19 | 2018-09-19 | 3D memory device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109037226A CN109037226A (en) | 2018-12-18 |
| CN109037226B true CN109037226B (en) | 2024-05-10 |
Family
ID=64617019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811096306.6A Active CN109037226B (en) | 2018-09-19 | 2018-09-19 | 3D memory device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109037226B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111211130B (en) * | 2020-01-16 | 2023-01-10 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| KR20210127559A (en) * | 2020-04-14 | 2021-10-22 | 에스케이하이닉스 주식회사 | semiconductor device hainvg resistance changing layer |
| US20220293628A1 (en) * | 2021-03-10 | 2022-09-15 | Macronix International Co., Ltd. | Memory device and method for manufacturing the same and method for operating the same |
| CN113782542B (en) * | 2021-08-26 | 2024-02-27 | 长江存储科技有限责任公司 | Three-dimensional memory and method for manufacturing the same |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263065A (en) * | 2010-05-24 | 2011-11-30 | 三星电子株式会社 | Nonvolatile memory device, method of manufacturing the same, memory module and system including the nonvolatile memory device |
| CN104022120A (en) * | 2014-06-23 | 2014-09-03 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and method for manufacturing the same |
| CN104112750A (en) * | 2009-02-10 | 2014-10-22 | 三星电子株式会社 | Non-volatile memory device and vertical NAND memory |
| CN104170061A (en) * | 2012-04-10 | 2014-11-26 | 桑迪士克科技股份有限公司 | Vertical NAND device with partially silicided word lines and method for manufacturing same |
| CN105448928A (en) * | 2014-08-25 | 2016-03-30 | 旺宏电子股份有限公司 | 3D NAND nonvolatile memory with interlaced vertical grids |
| CN107305895A (en) * | 2016-04-21 | 2017-10-31 | 三星电子株式会社 | Memory device with the common source line including different material layer |
| CN107359164A (en) * | 2016-05-04 | 2017-11-17 | 旺宏电子股份有限公司 | Memory structure and manufacturing method thereof |
| CN108231781A (en) * | 2016-12-22 | 2018-06-29 | 三星电子株式会社 | Vertical memory device |
| CN208796998U (en) * | 2018-09-19 | 2019-04-26 | 长江存储科技有限责任公司 | 3D memory device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160145322A (en) * | 2015-06-10 | 2016-12-20 | 에스케이하이닉스 주식회사 | Electronic device |
-
2018
- 2018-09-19 CN CN201811096306.6A patent/CN109037226B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104112750A (en) * | 2009-02-10 | 2014-10-22 | 三星电子株式会社 | Non-volatile memory device and vertical NAND memory |
| CN102263065A (en) * | 2010-05-24 | 2011-11-30 | 三星电子株式会社 | Nonvolatile memory device, method of manufacturing the same, memory module and system including the nonvolatile memory device |
| CN104170061A (en) * | 2012-04-10 | 2014-11-26 | 桑迪士克科技股份有限公司 | Vertical NAND device with partially silicided word lines and method for manufacturing same |
| CN104022120A (en) * | 2014-06-23 | 2014-09-03 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and method for manufacturing the same |
| CN105448928A (en) * | 2014-08-25 | 2016-03-30 | 旺宏电子股份有限公司 | 3D NAND nonvolatile memory with interlaced vertical grids |
| CN107305895A (en) * | 2016-04-21 | 2017-10-31 | 三星电子株式会社 | Memory device with the common source line including different material layer |
| CN107359164A (en) * | 2016-05-04 | 2017-11-17 | 旺宏电子股份有限公司 | Memory structure and manufacturing method thereof |
| CN108231781A (en) * | 2016-12-22 | 2018-06-29 | 三星电子株式会社 | Vertical memory device |
| CN208796998U (en) * | 2018-09-19 | 2019-04-26 | 长江存储科技有限责任公司 | 3D memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109037226A (en) | 2018-12-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109037227B (en) | 3D memory device and method of manufacturing the same | |
| CN109148461B (en) | 3D memory device and method of manufacturing the same | |
| CN108807410B (en) | 3D memory device and method of manufacturing the same | |
| CN109698201B (en) | 3D memory device and method of manufacturing the same | |
| CN109346473B (en) | 3D memory device and method of manufacturing the same | |
| CN109390349B (en) | 3D memory device and method of manufacturing the same | |
| CN110649033B (en) | 3D memory device and method of manufacturing the same | |
| CN109585454B (en) | 3D memory device and method of manufacturing the same | |
| CN111180451B (en) | 3D memory device and method of manufacturing the same | |
| CN109192735B (en) | 3D memory device and method of manufacturing the same | |
| CN109037226B (en) | 3D memory device and method of manufacturing the same | |
| CN111211130B (en) | 3D memory device and method of manufacturing the same | |
| CN109148459B (en) | 3D memory device and method of manufacturing the same | |
| CN113224079B (en) | 3D memory device and method of manufacturing the same | |
| CN110289259B (en) | 3D memory device and method of manufacturing the same | |
| CN110808254B (en) | 3D memory device and method of manufacturing the same | |
| CN110379812B (en) | 3D memory device and method of manufacturing the same | |
| CN109119425B (en) | 3D memory device | |
| CN109686740B (en) | 3D memory device and method of manufacturing the same | |
| CN110676257A (en) | 3D memory device and method of manufacturing the same | |
| CN111540747B (en) | Method for manufacturing 3D memory device | |
| CN110808252B (en) | 3D memory device and method of manufacturing the same | |
| CN110828469A (en) | 3D memory device and method of manufacturing the same | |
| CN109273452B (en) | 3D memory device and method of manufacturing the same | |
| CN109545793B (en) | 3D memory device and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |