CN113782542B - Three-dimensional memory and method for manufacturing the same - Google Patents
Three-dimensional memory and method for manufacturing the same Download PDFInfo
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Abstract
The present disclosure provides a method of manufacturing a three-dimensional memory, comprising: forming channel pillars on a first surface of a substrate extending into the substrate; wherein, along the radial of channel post, the channel post includes: a conductive channel layer and an insulating functional layer surrounding the channel layer; removing the substrate from the second surface of the substrate to reveal the first end of the channel pillar; wherein the second surface is opposite to the first surface of the substrate; removing the functional layer exposed by the first end to expose the channel layer; wherein the exposed channel layer is oxidized to form an oxide sub-layer; forming a first conductive layer covering the oxide sub-layer; after forming the first conductive layer, performing first ion implantation on the oxide sub-layer to break the continuity of the oxide sub-layer; after the first ion implantation, the first conductive layer and the oxide sub-layer are heat treated to electrically connect the channel layer with the first conductive layer.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a three-dimensional memory and a manufacturing method thereof.
Background
As semiconductor manufacturing processes continue to increase, process feature sizes become smaller and memory devices have increased in storage density. In order to meet the demand for higher memory density, three-dimensional structured memory devices have been developed. The 3D NAND memory has the advantages of high writing speed, simple erasing operation, higher storage density and the like, and is widely applied.
The conventional 3D NAND memory includes a plurality of storage units stacked in a vertical direction, and can increase storage density in multiple times on a wafer per unit area while reducing costs. In the related art, a means of increasing the number of stacked memory cells is generally used to increase the memory density, but the process is more and more complicated while the number of stacked memory chips is continuously increasing. However, during the conversion of multiple processes, the exposure of the wafer to air for too long may cause defects, affecting the performance parameters of the structures formed on the wafer, and eventually causing degradation of the quality of the memory device. Therefore, how to solve the influence of the external environment on the wafer process while the process is continuously complicated, optimize the influence among different processes, and reduce the occurrence of defects becomes a problem to be solved.
Disclosure of Invention
In a first aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a three-dimensional memory, including:
forming a channel pillar extending into a substrate at a first surface of the substrate; wherein, along the radial of channel post, the channel post includes: a conductive channel layer and an insulating functional layer surrounding the channel layer;
Removing the substrate from the second surface of the substrate to reveal the first end of the channel pillar; wherein the second surface and the first surface are opposite surfaces of the substrate;
removing the functional layer exposed by the first end to expose the channel layer; wherein the exposed channel layer is oxidized to form an oxide sub-layer;
forming a first conductive layer covering the oxide sub-layer;
after forming the first conductive layer, performing first ion implantation on the oxide sub-layer to break the continuity of the oxide sub-layer;
after the first ion implantation, the first conductive layer and the oxide sub-layer are heat treated to electrically connect the channel layer and the first conductive layer.
In some embodiments, the method further comprises:
performing a second ion implantation on the first end portion formed with the oxide sub-layer to form a conductive first protective layer covering the first end portion, before forming the first conductive layer; wherein the first protective layer is used for reducing the reaction of oxygen particles with the rest of the channel layer.
In some embodiments of the present invention, in some embodiments,
the forming a channel pillar on a first surface of a substrate extending into the substrate, comprising:
Forming a channel hole extending into the substrate through a stacked structure located on a first surface of the substrate;
forming the functional layer covering the side wall and the bottom of the channel hole;
forming the channel layer covering the functional layer;
before removing the substrate, the method further comprises:
performing third ion implantation on the bottom of the channel layer from the first surface of the substrate to form a conductive second protective layer between the bottom of the channel layer and the functional layer; wherein the second protective layer is used for reducing the reaction of oxygen particles with the channel layer.
In some embodiments of the present invention, in some embodiments,
the composition particles of the oxide sub-layer comprise oxygen particles and first particles;
after the first conductive layer is formed, performing first ion implantation on the oxide sub-layer to break the continuity of the oxide sub-layer, including:
and injecting second particles into the oxide sub-layer, wherein the second particles bombard the oxide sub-layer to break chemical bonds between the oxygen particles and the first particles and form gaps in the oxide sub-layer.
In some embodiments of the present invention, in some embodiments,
the implantation element of the first ion implantation comprises at least one of the following:
Arsenic element; krypton; a xenon element; nitrogen element.
In some embodiments of the present invention, in some embodiments,
the energy range of the implanted element of the first ion implantation is as follows: 100 kilo-electron volts to 3 megaelectron volts.
In some embodiments of the present invention, in some embodiments,
the heat treating the first conductive layer and the oxide sub-layer includes:
and annealing the first conductive layer and the oxide sub-layer to form an integrated structure of the oxide sub-layer and the first conductive layer after ion implantation, and allowing at least part of the implantation elements in the ion implantation process to escape from the oxide sub-layer and form a gas product.
In some embodiments of the present invention, in some embodiments,
the annealing treatment comprises furnace tube annealing, laser annealing or any combination thereof.
In some embodiments, the method further comprises:
the method further comprises the steps of: forming an insulating isolation layer covering the first surface of the substrate; forming a stacked structure covering the isolation layer;
the removing the functional layer exposed by the first end to expose the channel layer includes: removing the functional layer exposed by the first end to form a first recess recessed in the stacking structure along a first direction perpendicular to the substrate; wherein the end of the remaining functional layer is in contact with the isolation layer.
In some embodiments of the present invention, in some embodiments,
after forming the channel pillars, the method further comprises:
forming a groove penetrating through the laminated structure along the direction perpendicular to the substrate and exposing the substrate in the laminated structure of the first surface of the substrate; the laminated structure comprises a plurality of first insulating layers and a plurality of sacrificial layers which are alternately laminated in sequence;
removing the plurality of sacrificial layers in the laminated structure based on the grooves, and forming gaps between adjacent first insulating layers;
filling the gaps to form a plurality of second conductive layers;
forming a second insulating layer covering the side wall of the groove;
the trench including the second insulating layer is filled with a conductive material.
In a second aspect of embodiments of the present disclosure, there is provided a three-dimensional memory, the three-dimensional memory comprising:
a first conductive layer;
a stacked structure stacked with the first conductive layers, the stacked structure including a plurality of second conductive layers and a plurality of first insulating layers stacked alternately; wherein one of the first insulating layers is in contact with the first conductive layer;
a channel pillar extending through the stacked structure and into the first conductive layer; along a radial direction of the channel pillar, the channel pillar includes: a conductive channel layer and an insulating functional layer surrounding the channel layer;
The channel pillar further includes: a second end portion within the first conductive layer, the second end portion comprising: the channel layer and the oxide sub-layer between the channel layer and the first conductive layer; the first conductive layer and the channel layer are electrically connected through the gap.
In some embodiments, the three-dimensional memory further comprises:
and a conductive first protection layer, which is positioned between the oxide sub-layer and the first conductive layer and covers the second end part of the channel column, and is used for reducing the reaction of oxygen particles with the channel layer at the second end part.
In some embodiments, the three-dimensional memory further comprises:
and a conductive second protective layer positioned between the channel layer and the functional layer at the second end portion for reducing reaction of oxygen particles with the channel layer.
In the related art, a wet etching process is generally performed on the exposed oxide sub-layer of the channel layer, and then a conductive material is deposited. However, even if the oxide layer on the surface of the channel layer is removed by wet etching, the re-exposed channel layer is exposed for too long and still oxidized to form an oxide layer, so that the interval time between the processes is tightly controlled, which increases the throughput pressure and reduces the process window. Moreover, the wet etching etchant may etch the second insulating layer in the gate line gap structure, which increases the probability of electrically connecting the conductive material deposited later with the conductive layer in the stacked structure, thereby increasing the probability of device failure due to leakage.
According to the scheme provided by the embodiment of the disclosure, an ion implantation process is adopted to replace a wet etching process for removing the oxide sub-layer. First, a first conductive layer covering the oxide sub-layer is formed, then, first ion implantation is carried out on the oxide sub-layer, continuity of the oxide sub-layer is destroyed, and finally, heat treatment is carried out on the first conductive layer and the oxide sub-layer, so that the channel layer and the first conductive layer are electrically connected.
Compared with the related art, the technical scheme provided by the embodiment of the disclosure does not need to execute a wet etching process for removing the oxide sub-layer, and the first ion implantation does not damage the grid line gap structure, so that the probability of electric connection leakage of the first conductive layer and the conductive layer of the stacked structure is reduced, and the yield of the device is improved. In addition, the first ion implantation process is performed after the first conductive layer is formed, the first conductive layer can prevent the channel layer after the oxide sub-layer is removed from being in contact with the external atmospheric environment, and the probability of further oxidation of the channel layer is reduced, so that the interval time between subsequent processes is prolonged, and the capacity pressure is relieved and the process window is enlarged.
Drawings
FIGS. 1a to 1d are schematic diagrams illustrating a method of fabricating a three-dimensional memory according to an exemplary embodiment;
FIG. 2 is a flow diagram illustrating a method of fabricating a three-dimensional memory according to an embodiment of the present disclosure;
fig. 3a to 3g are schematic views illustrating a method of manufacturing a three-dimensional memory according to an embodiment of the present disclosure;
fig. 4a to 4d are schematic views showing a method of manufacturing a three-dimensional memory according to an embodiment of the present disclosure;
fig. 5a to 5b are schematic views showing a method of manufacturing a three-dimensional memory according to an embodiment of the present disclosure;
fig. 6a to 6c are schematic views showing a structure of a three-dimensional memory according to an embodiment of the present disclosure.
Detailed Description
The technical scheme of the present disclosure is further elaborated below in conjunction with the drawings of the specification and the specific embodiments. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The present disclosure is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the disclosure.
It will be understood that the meanings of the disclosure "on … …", "over … …" and "over … …" are to be interpreted in the broadest sense such that "on … …" means not only that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also that it is "on" something with intervening features or layers therebetween.
In the presently disclosed embodiments, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
In the presently disclosed embodiments, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface.
Fig. 1a and 1b are schematic diagrams illustrating a method of manufacturing a three-dimensional memory according to an exemplary embodiment, the method comprising the steps of:
Step one: referring to fig. 1a, a semiconductor structure is provided; the semiconductor structure includes: a substrate 100, an isolation layer 120 and a stack structure 110, a gate line gap structure 13 penetrating the stack structure 110 and the isolation layer 120 and extending into the substrate 100, and a channel pillar 14; wherein, along the first direction, the stacked structure 110 includes: a plurality of second conductive layers 111 and a plurality of first insulating layers 112, which are alternately stacked in this order;
step two: referring to fig. 1b, in a radial direction of the channel pillar 14, the channel pillar 14 includes: the conductive channel layer 142 and the insulating functional layer 143, the functional layer 143 may include a composite layer of silicon oxide/silicon nitride/silicon oxide (ONO). Etching to remove the substrate 100 to expose the first end 141 of the channel pillar 14, and etching to remove the functional layer 143 exposed by the first end 141 to expose the channel layer 142; wherein the exposed channel layer 142 is oxidized to an oxide sub-layer 147.
Illustratively, the process of etching away the first end may be one or any combination of wet etching, dry etching.
It is emphasized that the channel layer material comprises monocrystalline silicon and/or polycrystalline silicon material. After the channel pillars are removed, the channel layer is exposed. During the transition and waiting processes of the process, the channel layer is in direct contact with air, and the silicon of the channel layer is oxidized to form an oxide sub-layer. However, this oxide sub-layer is not required by the process, but rather the presence of the oxide sub-layer may disrupt the electrical connection of the first conductive layer formed in the subsequent step four to the channel layer, affecting the electrical performance of the memory device.
Step three: referring to fig. 1c, the oxide sub-layer 147 is etched away.
Illustratively, the process of etching to remove the oxide sub-layer may be one or any combination of wet etching and dry etching.
Step four: referring to fig. 1D, a conductive material covers the first end 141 and the stack structure 110 to form a first conductive layer 170, which is electrically connectable with the channel layer 142 of the channel pillar 14, and serves as an array common source (Array Common Source, ACS) of the 3D NAND for supplying power to the memory cell. The conductive material may be polysilicon or monocrystalline silicon, and is preferably polysilicon in this embodiment.
The first direction may be the Z direction in the drawing, the second direction may be the X direction in the drawing, and the radial direction of the channel pillars 14 may be parallel to the X direction.
However, in the actual memory manufacturing process, the mutual influence of the sequential processes may cause defects. Specifically, referring to fig. 1b, after the functional layer 143 exposed at the first end 141 is removed, the channel layer 142 is exposed, where the channel layer 142 may be polysilicon or monocrystalline silicon, and is preferably a polysilicon material. The exposed channel layer 142 is exposed to air and oxidized to silicon oxide, so that a silicon oxide layer is generated on the exposed channel layer 142 surface.
In order to make the first conductive layer 170 formed in the fourth step electrically connected to the channel layer 142, the oxide sub-layer 147 is removed by etching in the third step as shown in fig. 1 b.
For example, the oxide sub-layer 147 may be removed using a hydrofluoric acid (HF) wet etch process. Specifically, the silicon oxide surface is treated with hydrofluoric acid to form a silicon-hydrogen interface on the channel layer 142, thereby suppressing the oxidation process.
However, if the time interval from step three to step four is too long (process waiting time, qtime), the oxide layer 147 will still be formed by the continuous oxidation of the channel layer 142, and the electrical connection between the first conductive layer 170 and the channel layer 142 will still be affected, and too short process waiting time (Q-time) will increase the throughput pressure, limiting the process window.
Further, referring to fig. 1b and 1c, the gate line gap structure 13 includes a second insulating layer 135 and a core 134, wherein the second insulating layer 135 includes a first sub-layer 132 and a second sub-layer 133, and the first sub-layer 132 is a high dielectric material having a dielectric constant higher than that of silicon dioxide, and is preferably an alumina material in the embodiment of the present disclosure. The second sub-layer 133 is an insulating material, including a silicon oxide material and a silicon nitride material. Silicon oxide materials are preferred in embodiments of the present disclosure.
In step three, in the conventional hydrofluoric acid etching process, the first sub-layer 132 (aluminum oxide layer) and the second sub-layer 133 (silicon oxide layer) in the gate line gap structure 13 are etched by hydrofluoric acid to form the second recess 150 recessed toward the stacked structure along the first direction. After the first conductive layer 170 is formed in the fourth step, the first conductive layer 170 contacts the second conductive layer 111 as shown in fig. 1d, resulting in the occurrence of a defect of bottom select gate leakage. Meanwhile, the surface treated by HF is slowly oxidized, a silicon oxide layer is formed on the surface after a long time, the process waiting time is required to be strictly controlled, the productivity pressure is increased, and the process window is limited.
Based on this, the embodiment of the disclosure provides a method for manufacturing a three-dimensional memory.
Fig. 2 is a flow chart illustrating a method of manufacturing a three-dimensional memory according to an embodiment of the present disclosure, and fig. 3a to 3g are schematic views illustrating a method of manufacturing a three-dimensional memory according to an embodiment of the present disclosure. As shown in connection with fig. 2, 3a to 3g, the method comprises the steps of:
s100: referring to fig. 3a, channel pillars 14 extending into the substrate 100 are formed on a first surface of the substrate 100; wherein, along the radial direction of the channel pillar 14, the channel pillar 14 includes: a conductive channel layer and an insulating functional layer surrounding the channel layer;
S200: referring to fig. 3b, the substrate 100 is removed from the second surface of the substrate 100 to reveal the first ends 141 of the channel pillars 14; wherein the second surface and the first surface are opposite surfaces of the substrate 100;
s300: referring to fig. 3c, the functional layer 143 exposed by the first end 141 is removed to expose the channel layer 142; wherein the exposed channel layer 142 is oxidized to form an oxide sub-layer 147;
s400: referring to fig. 3d, a first conductive layer 170 is formed to cover the oxide sub-layer 147;
s500: referring to fig. 3e, after the first conductive layer 170 is formed, first ion implantation is performed on the oxide sub-layer 147 to break the continuity of the oxide sub-layer 147;
s600: referring to fig. 3e, after the first ion implantation, the first conductive layer 170 and the oxide sub-layer 147 are heat treated to electrically connect the channel layer 142 and the first conductive layer 170.
Specifically, referring to fig. 3a, exemplary constituent materials of the substrate 100 may include: elemental semiconductor materials (e.g., silicon, germanium), group iii-v compound semiconductor materials, group ii-vi compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. Embodiments of the present disclosure are preferably polysilicon materials.
Illustratively, the constituent materials of the channel layer 142 of the channel pillar 14 may include: monocrystalline silicon material, polycrystalline silicon material. Embodiments of the present disclosure are preferably polysilicon materials.
Illustratively, the channel layer, the functional layer, the first conductive layer may be formed by any technique known to those skilled in the art, such as a low temperature chemical vapor deposition (Low Temperature ChemicalVapor Deposition, LTCVD) process, a low pressure chemical vapor deposition (Low Pressure Chemical VaporDeposition, LPCVD) process, a rapid thermal chemical vapor deposition (Rapid Thermo Chemical Vapor Deposition, RTCVD) process, an atomic layer deposition (Atomics Layer Deposition, ALD) process, or an ion-enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process.
Referring to fig. 3b, an exemplary removal process of the substrate 100 may include: dry etching, wet etching, chemical mechanical polishing planarization, or a combination thereof. The dry etching gas may include: CF (compact flash) 4 ，C 2 F 6 ，NF 3 ，Cl 2 ，O 2 ，NH 3 Or a combination of the above gases. The wet etchant may include: HF, H 3 PO 4 KOH, or a combination of the above solutions.
After the substrate 100 is removed, a conductive layer may be reformed at the location of the original substrate 100 to electrically connect the plurality of channel structures, forming an Array Common Source (ACS) that powers the memory cells.
In some embodiments, the conductive layer includes a metal silicide layer in contact with the semiconductor channel of the channel structure to reduce contact resistance, and further includes a metal layer in contact with the metal silicide layer to further reduce overall resistance. As a result, the thickness of the semiconductor layer (N-type doped or P-type doped) that is part of the array common source can be reduced without affecting the array common source conductance.
It is emphasized that the second surface and the first surface are opposite surfaces referenced with respect to the substrate 100 in a first direction perpendicular to the surface of the substrate 100.
Referring to fig. 3c, after the step S200 is performed, the channel layer 142 is exposed, the channel layer 142 loses the protection of the functional layer 143 and is directly in contact with the external environment, and the polycrystalline silicon or monocrystalline silicon material of the channel layer 142 is oxidized to silicon oxide by contact with oxygen element in the environment during the process conversion and the wafer transfer, so that the oxide sub-layer 147 is formed on the exposed surface of the channel layer 142. The oxygen element may be oxygen from the atmosphere, an oxidizing etchant (hydrogen peroxide, nitric acid or any combination of other oxidizing etchants) in wet etching, or an oxidizing element involved in other processes.
Illustratively, the process of etching to remove the first end 141 may be one or any combination of wet etching, dry etching.
Referring to fig. 3d, the first conductive layer 170 material includes a single crystal silicon material, a polycrystalline silicon material, an amorphous silicon material.
Referring to fig. 3e, oxide sub-layer 147 isolates exposed channel layer 142 from first conductive layer 170, affecting the conductive contact of channel layer 142 with first conductive layer 170. The oxide sub-layer 147 is subjected to a first ion implantation, and the oxide sub-layer 147 is subjected to physical bombardment with high-energy particles, so that a crack or gap occurs in the continuous and complete oxide sub-layer 147, thereby breaking the continuity of the oxide sub-layer 147 and enabling the channel layer 142 to be in contact with the first conductive layer 170. The angle of ion implantation may be 0 ° to 180 ° with respect to the first conductive layer 170. The ion implantation element includes one or any combination of arsenic element, indium element, neon element, argon element, krypton element, xenon element, and nitrogen element.
Referring to fig. 3e, after the first ion implantation, the first conductive layer 170 and the oxide layer are heat treated, and the silicon lattice damage of the first conductive layer 170 and the channel layer 142 is repaired, so that the first conductive layer 170 and the channel layer 142 are better contacted, and the conductive connection is optimized.
In the embodiment of the disclosure, an ion implantation process is adopted to replace a wet etching process for removing the oxide sub-layer. First, a first conductive layer covering the oxide sub-layer is formed, then, first ion implantation is carried out on the oxide sub-layer, continuity of the oxide sub-layer is destroyed, and finally, heat treatment is carried out on the first conductive layer and the oxide sub-layer, so that the channel layer and the first conductive layer are electrically connected.
According to the embodiment of the disclosure, the gate line gap structure is not damaged while the channel layer is removed, so that the probability of electric connection leakage between the first conductive layer and the conductive layer of the stacked structure is reduced, and the yield of the device is improved. Further, the first ion implantation process is performed after the first conductive layer is formed, the channel layer after the oxide sub-layer is removed is not in contact with the external environment, and the probability of further oxidation of the channel layer is reduced, so that the interval time between the subsequent processes is prolonged, and the capacity pressure is relieved and the process window is enlarged.
In some embodiments, referring to fig. 3c and 3f, the method further comprises:
after step S300 is performed and before step S400 is performed, performing a second ion implantation on the first end portion 141 formed with the oxide sub-layer 147 to form a conductive first protection layer 148 covering the first end portion 141; wherein the first protection layer 148 is used to reduce the reaction of oxygen particles with the remaining channel layer 142.
It is emphasized that the oxygen particles may comprise oxygen particles from the oxide sub-layer or may comprise oxygen particles from the external environment.
In some embodiments, the second ion implantation may be ion implantation of the oxide layer, and the first protection layer having ion doping is formed on the surface of the oxide layer. The first protective layer can reduce the reaction of oxygen particles in the oxide sub-layer with the remaining channel layer, and the first protective layer has conductivity and can be electrically connected with the first conductive layer and the channel layer, so that the electrical performance of the memory device is not affected.
In some embodiments, the second ion implantation may be ion implantation to the channel layer, where the high-energy ions bombard the oxide layer to break the oxide layer, and then pass through the oxide layer to reach the channel layer, so as to form a first protection layer with ion doping on the surface of the channel layer. The formed first protective layer can protect the remaining channel layer from reacting with the oxide sub-layer and oxygen particles in the external environment, and the first protective layer has conductivity and can be electrically connected with the first conductive layer and the channel layer, thereby not affecting the electrical performance of the memory device.
In some embodiments, the second ion implantation may be ion implantation of the channel layer and the oxide sub-layer, ion doping of the channel layer and the oxide sub-layer, and forming doped first protection layers on the surface of the oxide sub-layer and the surface of the channel layer, respectively. The first protective layer may reduce reaction of the remaining channel layer with the oxide sub-layer and oxygen particles in the external environment, and has conductivity to be electrically connected with the first conductive layer and the channel layer, thereby not affecting the electrical performance of the memory device.
The implantation element of the second ion implantation may include one or any combination of arsenic element, indium element, neon element, argon element, krypton element, xenon element, and nitrogen element.
According to the assumptions made by diel-gruff, the charge on the wafer or polysilicon surface affects the rate at which the oxidizing agent reaches the oxidation interface during subsequent oxidation, and thus the growth rate of the silicon oxide layer. The negative charges on the surface of the polysilicon in the subsequent oxidation reaction can accelerate the speed of the oxidizing agent reaching the oxidation interface in the oxidation process, so that the oxidation speed is accelerated, namely, the more the negative charges on the surface of the wafer or the polysilicon layer are, the more easily the silicon oxide layer is oxidized. Based on this, the generation of the silicon oxide film can be suppressed by controlling the negative charge amount of the polysilicon surface by means of ion implantation.
In the embodiment of the present disclosure, the first protective layer 148 having ion doping and conductivity is formed on the surface of the channel layer 142 and/or on the surface of the oxidized oxide sub-layer 147 by performing the second ion implantation on the exposed channel layer 142 and/or oxide sub-layer 147. The protective layer can control negative charge accumulation, thereby inhibiting the growth of a surface oxide film, reducing the oxidation degree of the residual channel layer 142, maintaining the thickness of the channel layer, and reducing the probability of failure of the memory device. Further, the first protective layer has conductivity, and can be electrically connected with the first conductive layer and the channel layer, so that the electrical performance of the memory device is not affected.
In some embodiments, the method further comprises:
referring to fig. 3g, forming channel pillars 14 extending into the substrate 100 at a first surface of the substrate 100, comprises:
forming a channel hole extending into the substrate 100 through the stacked structure 110 located at the first surface of the substrate 100;
forming a functional layer 143 covering the sidewall and bottom of the channel hole;
forming a channel layer 142 covering the functional layer 143;
before removing the substrate 100, the method further comprises:
performing a third ion implantation on the bottom of the channel layer 142 from the first surface of the substrate 100 to form a conductive second protective layer 149 between the bottom of the channel layer 142 and the functional layer 143; wherein the second protective layer 149 is used to reduce the reaction of oxygen particles with the channel layer 142.
Along the radial direction of the channel pillar 14, the functional layer 143 includes a blocking sublayer 144, a storage sublayer 145, and a tunneling sublayer 146. Wherein the barrier sublayer 144 may comprise silicon oxide, silicon oxynitride, high dielectric, or any combination thereof. The storage sub-layer 145 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. Tunneling sublayer 146 may comprise silicon oxide, silicon oxynitride, or any combination thereof. In the disclosed embodiment, the combination of the functional layers 143 is preferably a composite layer of silicon oxide/silicon nitride/silicon oxide (ONO).
In some embodiments, the tunneling sublayer is located between the channel layer and the storage sublayer. The storage sub-layer is also called a charge trapping sub-layer, and the storage or removal of charge in the charge trapping sub-layer determines the switching state of the semiconductor channel. The charge moves between the storage sub-layer and the channel layer through the tunneling effect of the tunneling sub-layer to realize the conduction of the channel layer or not, and then realizes the storage and the erasure through programming. Furthermore, the storage sub-layer may store charge, and electrons are stored in the storage sub-layer without being lost when the memory is powered down.
Further, the blocking sub-layer is located between the storage sub-layer and the second conductive layer, plays a role in insulation and isolation, and is used for blocking charges in the storage sub-layer from moving to the second conductive layer, so that good performance of the memory is guaranteed.
In some embodiments, the stacked structure 110 includes: the plurality of second conductive layers 111 and the plurality of first insulating layers 112 are alternately stacked in this order.
Illustratively, the constituent materials of the plurality of second conductive layers 111 may include: single crystal silicon material, polycrystalline silicon material, metallic tungsten material, or other conductive materials known in the art. Embodiments of the present disclosure are preferably metallic tungsten materials.
Illustratively, the constituent materials of the plurality of first insulating layers 112 may include: silicon oxide material, silicon nitride material, silicon oxynitride material, or other insulating materials known in the art. Embodiments of the present disclosure are preferably silicon oxide materials.
It is emphasized that the constituent materials of the different first conductive layers 170 may be different, and the constituent materials of the different first insulating layers 112 may be different.
After the channel layer 142 is formed, a third ion implantation is performed on the channel layer 142 from the top of the channel pillar 14 to reduce the negative charge amount of the channel layer 142, and a second protective layer 149 having ion doping is formed between the bottom of the channel layer 142 and the functional layer 143. After performing step S200, the second protective layer 149 may control the accumulation of negative charges on the surface of the channel layer 142, and reduce the formation of an oxide film. The third ion implantation element includes one or any combination of arsenic element, indium element, neon element, argon element, krypton element, xenon element, and nitrogen element.
In some embodiments, the method further comprises:
as described with reference to fig. 3e, the constituent particles of the oxide sub-layer 147 include oxygen particles and first particles;
after the first conductive layer 170 is formed, the first ion implantation is performed on the oxide sub-layer 147 to break the continuity of the oxide sub-layer 147, including:
the second particles are injected into the oxide sub-layer 147, and the second particles bombard the oxide sub-layer 147 to break chemical bonds between the oxygen particles and the first particles and form gaps in the oxide sub-layer 147.
Illustratively, the oxide sub-layer 147 comprises a first of the particles, which may be silicon particles in the channel layer 142, or other particles. The polysilicon layer in the channel layer 142 may be doped to optimize the conductivity of the channel layer 142, wherein the doping element may include one or any combination of boron, arsenic, phosphorous, germanium, gallium, antimony. As such, the first particles of the oxide sub-layer 147 are not just silicon particles, and the oxide sub-layer 147 composition may also include other elemental particles that are prone to oxidation.
The first ion-implanted energetic particles bombard the oxide sub-layer 147, breaking the silicon oxygen bonds of the silicon oxide, forming gaps in the oxide sub-layer 147, such that the first conductive layer 170 forms an electrical connection with the channel layer 142.
In some embodiments, the implanted element of the first ion implantation comprises at least one of:
arsenic element; an indium element; a neon element; argon element; krypton; a xenon element; nitrogen element.
The electrical connection between the first conductive layer 170 and the channel layer 142 is achieved by breaking the continuity of the oxide sub-layer 147 by physical bombardment, the formation of an oxide layer can be suppressed by reducing the accumulation of negative charges on the surface of the channel layer 142, and the channel layer 142 can be protected from oxidation by forming an ion-doped protective layer or the channel layer 142 which has been partially oxidized can be protected from further oxidation.
In some embodiments, the implant element energy range of the first ion implant is: 100 kilo-electron volts to 3 megaelectron volts.
In the embodiment of the disclosure, the ions required to be injected by the first ions reach the surface of the oxide layer, and a certain amount of energy is required to bombard the ions and break the continuity of the oxide layer, so that the first conductive layer and the channel layer form an electrical connection. Based on the above, the energy and depth of the first ion implantation are required, and the depth of the ion implantation is controlled by controlling the energy of the first ion implantation, so that the ions can contact the oxide layer to break the continuity of the oxide layer, and meanwhile, the channel layer is not broken by the ion implantation.
In some embodiments, the method further comprises:
the heat treatment of the first conductive layer 170 and the oxide sub-layer 147 includes:
the first conductive layer 170 and the oxide sub-layer 147 are annealed to form a unitary structure of the first ion-implanted oxide sub-layer 147 and the first conductive layer 170, and to allow at least a portion of the implanted elements of the ion implantation process to escape from the oxide sub-layer 147 and form gaseous products.
The annealing process may repair the silicon lattice damage of the first conductive layer 170 and the channel layer 142, so that the first conductive layer 170 and the channel layer 142 are better contacted, and the conductive connection is optimized.
Further, the first ion implantation element includes krypton, xenon, nitrogen or a combination thereof, and after the first conductive layer 170 is formed, gas elements can escape from the oxide sub-layer 147 through an annealing heat treatment process, so that the lattice of the first conductive layer 170 and the channel layer 142 is not affected, and thus the resistance of the first conductive layer is not changed, which is beneficial to ensuring the conductive performance of the first conductive layer.
In some embodiments, the annealing process includes furnace annealing, laser annealing, or any combination thereof.
Illustratively, the furnace tube annealing process is performed in furnace tube equipment, the typical process temperature is 700 ℃ to 1100 ℃, and pure nitrogen is used as the process gas for high-temperature annealing to repair lattice damage, reduce resistance and improve conductivity.
By way of example, the laser annealing process may include: the surface of the first conductive layer 170 is irradiated with a laser beam to melt amorphous silicon or polycrystalline silicon of the first conductive layer 170, and re-crystallize the amorphous silicon or polycrystalline silicon into polycrystalline silicon, repair lattice damage, reduce resistance, and improve conductivity.
In some embodiments, the method further comprises:
referring to fig. 4a, an insulating spacer 120 is formed to cover the first surface of the substrate 100; forming a stack structure 110 covering the isolation layer 120;
Step S300 further includes: removing the functional layer 143 exposed by the first end 141 to expose the channel layer 142, including: removing the functional layer 143 exposed by the first end 141 to form a first recess 160 recessed toward the stacked structure 110 in a first direction perpendicular to the substrate 100; wherein the end of the remaining functional layer 143 is in contact with the isolation layer 120.
The isolation layer 120 is disposed between the substrate 100 and the stack structure 110, and may include an insulating material layer, and may also include multiple material layers of an insulating material and a conductive material.
In some embodiments, as shown in fig. 4a, the isolation layer 120 may include: the first insulating sub-layer 121, the first conductive sub-layer 122, and the second insulating sub-layer 123 are sequentially disposed along the first direction, the first insulating sub-layer 121 is located between the first conductive sub-layer 122 and the substrate 100, and the second insulating sub-layer 123 is located between the first conductive sub-layer 122 and the stacked structure 110.
The material of the first insulating sub-layer 121 and the second insulating sub-layer 123 may be one of silicon oxide, silicon nitride, and silicon oxynitride, and the silicon oxide is preferred in this embodiment; the material of the first conductive sub-layer 122 may be one of monocrystalline silicon and polycrystalline silicon, which is preferred in this embodiment.
By way of example, the removal process may include: dry etching, wet etching, or any combination of the above.
In some embodiments, the method further comprises:
referring to fig. 4b, after forming the channel pillar 14, in the stacked structure of the first surface of the substrate 100, a trench 130 penetrating the stacked structure in a direction perpendicular to the substrate 100 and exposing the substrate 100 is formed; wherein the laminated structure includes a plurality of first insulating layers 112 and a plurality of sacrificial layers 113 alternately laminated in this order.
The first insulating layer 112 material may be one of silicon oxide, silicon nitride, silicon oxynitride, and the preferred embodiment of the present disclosure is a silicon oxide material.
The sacrificial layer material may comprise one of silicon nitride, silicon oxynitride, single crystal silicon, polysilicon materials, with silicon nitride materials being preferred in embodiments of the present disclosure.
Referring to fig. 4c, the plurality of sacrificial layers in the stacked structure 110 are removed based on the trenches 130, forming gaps between adjacent first insulating layers 112;
referring to fig. 4d, the gaps are filled, and a plurality of second conductive layers 111 are formed;
forming a second insulating layer 135 covering sidewalls of the trench 130;
the trench 130 including the second insulating layer 135 is filled with a conductive material.
The second conductive layer 111 may be made of one of tungsten metal, monocrystalline silicon, and polycrystalline silicon, and in this embodiment, tungsten metal is preferred. The trench 130 is filled with a second insulating layer 135 and a core 134 to form a gate line gap structure 13, where the second insulating layer 135 includes a first sub-layer 132 and a second sub-layer 133, and the first sub-layer 132 is a high dielectric material with a dielectric constant higher than that of silicon dioxide, and in this embodiment, an alumina material is preferred. The second sub-layer 133 is an insulating material, including a silicon oxide material, a silicon nitride material, and in the presently disclosed embodiment, is preferably a silicon oxide material. The core 134 material comprises a silicon oxide material, a silicon nitride material, a single crystal silicon material, a polysilicon material, a metal tungsten material, and the insulating material and the conductive material are selected depending on whether the gate line gap structure 13 is a common source lead structure.
The following describes in detail the specific application of the method for manufacturing a three-dimensional memory according to the embodiments of the present disclosure in a wafer bonding process with reference to fig. 5a to 5 b.
In the three-dimensional memory manufacturing process, in order to realize stacking more memory cells on one wafer, a solution is adopted in which memory cells are manufactured on one wafer, control circuits are manufactured on another wafer, and finally, two wafers are bonded.
The method for manufacturing the three-dimensional memory provided by the embodiment of the disclosure can be applied to a wafer bonding process besides manufacturing the memory on a single wafer.
Referring to fig. 5a, steps S100, S200, S300, S400 shown in fig. 2 are performed on the first wafer 10 to form a memory cell structure having a channel pillar 14 and a first conductive layer 170, the channel layer 142 of the first end 141 of the channel pillar 14 forming an oxide sub-layer 147; the first wafer 10 is bonded to the second wafer 20 through the first bonding surface 180 and the second bonding surface 190, and a control circuit structure may be formed on the second wafer 20.
Referring to fig. 5b, step S500 shown in fig. 2 is performed on the first wafer 10, and the first ion implantation of the oxide sub-layer 147 is performed on the oxide sub-layer 147 to break the continuity of the oxide sub-layer 147;
S600: referring to fig. 3e, after the first ion implantation, the first conductive layer 170 and the oxide sub-layer 147 are heat-treated, and then step S600 is performed to electrically connect the channel layer 142 and the first conductive layer 170.
It will be appreciated that the application of the method of three-dimensional memory according to the embodiments of the present disclosure to wafer bonding is not limited to the embodiments of fig. 5a and 5b, and that other embodiments of the method of the present disclosure may be used on the first wafer 10 because of the bonding between individual wafers.
The specific structure of a three-dimensional memory provided by the embodiments of the present disclosure is described in detail below with reference to fig. 6a to 6 c. Referring to fig. 6a, the three-dimensional memory 1000 includes:
a first conductive layer 170;
a stacked structure 110 stacked with the first conductive layers 170, the stacked structure 110 including a plurality of second conductive layers 111 and a plurality of first insulating layers 112 stacked alternately; wherein a first insulating layer is in contact with the first conductive layer;
a channel pillar 14 penetrating the stacked structure and extending into the first conductive layer 170; along the radial direction of the channel pillar, the channel pillar 14 includes: a conductive channel layer 142 and an insulating functional layer 143 surrounding the channel layer;
The channel pillar 14 further includes: a second end 140 within the first conductive layer 170, the second end comprising: the channel layer 142 and the oxide sub-layer 147 between the channel layer 142 and the first conductive layer 170; wherein the oxide sub-layer has a gap, and the first conductive layer 170 is electrically connected to the channel layer 142 through the gap.
The constituent materials of the channel layer 142 and the first conductive layer 170 may include: monocrystalline silicon material, polycrystalline silicon material.
It should be emphasized that, as shown in fig. 1b and 3c, in the process of removing the functional layer at the second end portion to expose the channel layer, the polysilicon or the monocrystalline silicon of the channel layer directly contacts with oxygen element in the external environment, is oxidized into silicon oxide, and forms a continuous oxide sub-layer on the surface of the channel layer, so as to affect the electrical connection between the first conductive layer and the channel layer. The oxygen element may be oxygen from the atmosphere, an oxidizing etchant (hydrogen peroxide, nitric acid or any combination of other oxidizing etchants) in wet etching, or an oxidizing element involved in other processes.
In the embodiments of the present disclosure, the oxide sub-layer is a film layer having intermittent gaps, and does not continuously cover the channel layer surface. A portion of the first conductive layer or a portion of the channel layer may extend into the gap where contact is made with each other to form an electrical connection.
In some embodiments, the first ion implantation process may be used to physically bombard the oxide sub-layer with energetic particles such that the oxide sub-layer forms a gap. And performing heat treatment annealing on the silicon of the first conductive layer and the channel layer, and enabling the first conductive layer and the channel layer to extend to a gap to realize electrical connection while repairing lattice defects.
In some embodiments, referring to FIG. 6b, the three-dimensional memory 1000 further comprises:
a conductive first protective layer 148 is disposed between the oxide sub-layer 147 and the first conductive layer 170 and covers the second end 140 of the channel pillar for reducing oxygen particle reaction with the channel layer at the second end.
The first protection layer is provided with ion doping and can be arranged on the surface of the oxide sub-layer, the reaction between the rest channel layer and the oxide sub-layer and the reaction between the rest channel layer and oxygen particles in the external environment are reduced by isolating the contact between the channel layer and the oxygen particles, and the first protection layer is provided with conductivity and can be electrically connected with the first conductive layer and the channel layer, so that the electrical performance of the memory device is not affected.
In some embodiments, the first protective layer may be formed by performing a second ion implantation on the second end portion.
It should be emphasized that the second end and the first end are both end portions of the channel pillar extending to the first conductive layer, and the second end is formed by performing steps S300, S400, S500 and S600 on the first end. The two end structures are thus different structures formed by subjecting the same end of the channel pillar to different manufacturing steps, the first end comprising a conductive channel layer and an insulating functional layer surrounding the channel layer, the second end comprising a conductive channel layer, an oxide sub-layer with a slit.
In some embodiments, referring to FIG. 6c, the three-dimensional memory 1000 further comprises:
a conductive second protective layer 149 is disposed between the channel layer 142 and the functional layer 143 of the second end 140 for reducing oxygen particles from reacting with the channel layer.
Illustratively, the functional layer 143 includes a blocking sublayer 144, a storage sublayer 145, and a tunneling sublayer 146. Wherein the barrier sublayer 144 may comprise silicon oxide, silicon oxynitride, high dielectric, or any combination thereof. The storage sub-layer 145 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. Tunneling sublayer 146 may comprise silicon oxide, silicon oxynitride, or any combination thereof. In the disclosed embodiment, the combination of the functional layers 143 is preferably a composite layer of silicon oxide/silicon nitride/silicon oxide (ONO).
In the embodiment of the present disclosure, the second protection layer 149 may be disposed between the tunneling sublayer 146 and the channel layer 142, and after the functional layer 143 is removed to expose the channel layer, the second protection layer may reduce negative charge aggregation on the surface of the channel layer, thereby reducing the generation of an oxide film, and reducing the probability of failure of the device caused by insufficient electrical connection between the first conductive layer and the channel layer.
In some embodiments, a third ion implantation may be performed on the channel layer at the second end along the top of the channel pillar, forming a second protection layer between the tunneling sub-layer and the channel layer.
In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other manners. The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (13)
1. A method of manufacturing a three-dimensional memory, comprising:
forming a channel pillar extending into a substrate at a first surface of the substrate; wherein, along the radial of channel post, the channel post includes: a conductive channel layer and an insulating functional layer surrounding the channel layer;
removing the substrate from the second surface of the substrate to reveal the first end of the channel pillar; wherein the second surface and the first surface are opposite surfaces of the substrate;
removing the functional layer exposed by the first end to expose the channel layer; wherein the exposed channel layer is oxidized to form an oxide sub-layer;
Forming a first conductive layer covering the oxide sub-layer;
after forming the first conductive layer, performing first ion implantation on the oxide sub-layer to break the continuity of the oxide sub-layer;
after the first ion implantation, the first conductive layer and the oxide sub-layer are heat treated to electrically connect the channel layer and the first conductive layer.
2. The method according to claim 1, wherein the method further comprises:
performing a second ion implantation on the first end portion formed with the oxide sub-layer to form a conductive first protective layer covering the first end portion, before forming the first conductive layer; wherein the first protective layer is used for reducing the reaction of oxygen particles with the rest of the channel layer.
3. A method according to claim 1 or 2, characterized in that,
the forming a channel pillar on a first surface of a substrate extending into the substrate, comprising:
forming a channel hole extending into the substrate through a stacked structure located on a first surface of the substrate;
forming the functional layer covering the side wall and the bottom of the channel hole;
forming the channel layer covering the functional layer;
Before removing the substrate, the method further comprises:
performing third ion implantation on the bottom of the channel layer from the first surface of the substrate to form a conductive second protective layer between the bottom of the channel layer and the functional layer; wherein the second protective layer is used for reducing the reaction of oxygen particles with the channel layer.
4. The method of claim 1, wherein the constituent particles of the oxide sub-layer comprise oxygen particles and first particles;
after the first conductive layer is formed, performing first ion implantation on the oxide sub-layer to break the continuity of the oxide sub-layer, including:
and injecting second particles into the oxide sub-layer, wherein the second particles bombard the oxide sub-layer to break chemical bonds between the oxygen particles and the first particles and form gaps in the oxide sub-layer.
5. The method of claim 1, wherein the first ion implanted implant element comprises at least one of:
arsenic element; an indium element; a neon element; argon element; krypton; a xenon element; nitrogen element.
6. The method of claim 1, wherein the first ion implantation implant has an implant element energy range of: 100 kilo-electron volts to 3 megaelectron volts.
7. The method of claim 1, wherein the thermally treating the first conductive layer and the oxide sub-layer comprises:
and annealing the first conductive layer and the oxide sub-layer to form an integrated structure of the oxide sub-layer and the first conductive layer after ion implantation, and allowing at least part of the implantation elements in the ion implantation process to escape from the oxide sub-layer and form a gas product.
8. The method of claim 7, wherein the annealing treatment comprises furnace tube annealing, laser annealing, or any combination thereof.
9. The method of claim 7, wherein the step of determining the position of the probe is performed,
the method further comprises the steps of: forming an insulating isolation layer covering the first surface of the substrate; forming a stacked structure covering the isolation layer;
the removing the functional layer exposed by the first end to expose the channel layer includes: removing the functional layer exposed by the first end to form a first recess recessed in the stacking structure along a first direction perpendicular to the substrate; wherein the end of the remaining functional layer is in contact with the isolation layer.
10. The method of claim 1, wherein the step of determining the position of the substrate comprises,
After forming the channel pillars, the method further comprises:
forming a groove penetrating through the laminated structure along the direction perpendicular to the substrate and exposing the substrate in the laminated structure of the first surface of the substrate; the laminated structure comprises a plurality of first insulating layers and a plurality of sacrificial layers which are alternately laminated in sequence;
removing the plurality of sacrificial layers in the laminated structure based on the grooves, and forming gaps between adjacent first insulating layers;
filling the gaps to form a plurality of second conductive layers;
forming a second insulating layer covering the side wall of the groove;
the trench including the second insulating layer is filled with a conductive material.
11. A three-dimensional memory, comprising:
a first conductive layer;
a stacked structure stacked with the first conductive layers, the stacked structure including a plurality of second conductive layers and a plurality of first insulating layers stacked alternately; wherein one of the first insulating layers is in contact with the first conductive layer;
a channel pillar extending through the stacked structure and into the first conductive layer; along a radial direction of the channel pillar, the channel pillar includes: a conductive channel layer and an insulating functional layer surrounding the channel layer;
The channel pillar further includes: a second end portion located within the first conductive layer, the second end portion protruding from the functional layer; the second end portion includes: the channel layer and the oxide sub-layer between the channel layer and the first conductive layer; the first conductive layer and the channel layer are electrically connected through the gap.
12. The three-dimensional memory of claim 11, further comprising:
and a conductive first protection layer, which is positioned between the oxide sub-layer and the first conductive layer and covers the second end part of the channel column, and is used for reducing the reaction of oxygen particles with the channel layer at the second end part.
13. A three-dimensional memory according to claim 11 or 12, characterized in that said three-dimensional memory further comprises:
and a conductive second protective layer positioned between the channel layer and the functional layer at the second end portion for reducing reaction of oxygen particles with the channel layer.
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| KR20110001527A (en) * | 2009-06-30 | 2011-01-06 | 주식회사 하이닉스반도체 | Method for fabricating vertical channel type non-volatile memory device |
| CN109037226A (en) * | 2018-09-19 | 2018-12-18 | 长江存储科技有限责任公司 | 3D memory device and its manufacturing method |
| CN110600479A (en) * | 2013-08-29 | 2019-12-20 | 三星电子株式会社 | Semiconductor device having vertical channel structure and method of manufacturing the same |
| CN111223870A (en) * | 2020-02-21 | 2020-06-02 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN112542466A (en) * | 2020-12-09 | 2021-03-23 | 长江存储科技有限责任公司 | Three-dimensional memory manufacturing method |
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| JP2016062898A (en) * | 2014-09-12 | 2016-04-25 | 株式会社東芝 | Nonvolatile semiconductor memory and manufacturing method thereof |
| KR20180012640A (en) * | 2016-07-27 | 2018-02-06 | 삼성전자주식회사 | Vertical memory device and method of manufacturing the same |
| KR102574451B1 (en) * | 2019-02-22 | 2023-09-04 | 삼성전자 주식회사 | Integrated circuit device and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20110001527A (en) * | 2009-06-30 | 2011-01-06 | 주식회사 하이닉스반도체 | Method for fabricating vertical channel type non-volatile memory device |
| CN110600479A (en) * | 2013-08-29 | 2019-12-20 | 三星电子株式会社 | Semiconductor device having vertical channel structure and method of manufacturing the same |
| CN109037226A (en) * | 2018-09-19 | 2018-12-18 | 长江存储科技有限责任公司 | 3D memory device and its manufacturing method |
| CN111223870A (en) * | 2020-02-21 | 2020-06-02 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN112542466A (en) * | 2020-12-09 | 2021-03-23 | 长江存储科技有限责任公司 | Three-dimensional memory manufacturing method |
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