CN112542466A - Three-dimensional memory manufacturing method - Google Patents
Three-dimensional memory manufacturing method Download PDFInfo
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- CN112542466A CN112542466A CN202011430304.3A CN202011430304A CN112542466A CN 112542466 A CN112542466 A CN 112542466A CN 202011430304 A CN202011430304 A CN 202011430304A CN 112542466 A CN112542466 A CN 112542466A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
Methods for fabricating a three-dimensional memory are provided. The method for manufacturing the three-dimensional memory includes: forming a stacked structure on a substrate, a channel hole penetrating the stacked structure and extending into the substrate, and an epitaxial layer extending away from the substrate on a bottom surface of the channel hole; sequentially forming a functional layer and a protective layer on the top surface of the epitaxial layer and the inner wall of the channel hole; performing a first etch to remove at least a portion of the functional layer and the protective layer overlying the epitaxial layer to expose the epitaxial layer; performing a second etching to remove the remaining protective layer to expose the functional layer; and forming a polysilicon channel layer by depositing polysilicon on the exposed functional layer. The step of second etching and the step of depositing polysilicon are performed consecutively. During the steps of performing the second etch and depositing polysilicon, the exposed epitaxial layer is not in contact with air. Therefore, the interface between the channel layer and the epitaxial layer has smaller defect density, and the low-temperature threshold voltage distribution of the three-dimensional memory is improved.
Description
Technical Field
The present application relates generally to the field of semiconductor design and fabrication, and more particularly, to a method of improving a fabrication process of a channel structure in a three-dimensional memory.
Background
A memory is a widely used semiconductor device. To overcome the limitation of the storage capacity of the conventional two-dimensional memory, modern technologies often adopt a stacked memory chip manner to achieve higher integration.
Taking a NAND three-dimensional memory as an example, a memory cell string having a memory function is formed using a channel structure provided through a stacked structure. In forming the channel structure, it is necessary to replace the protective layer with a polysilicon material (e.g., which includes an amorphous silicon material). Before the protective layer is removed, a protective layer removal pre-cleaning process is typically performed to remove oxides formed on the silicon epitaxial layer.
However, in conventional processes, the step of removing the protective layer and the step of depositing the polysilicon are usually not continuous, and the two steps are usually required to be completed on two machines. When transferring the substrate between different machines, the silicon epitaxial layer inevitably comes into contact with air, so that it is oxidized again. The larger the oxide thickness on the silicon epitaxial layer, the higher the defect density formed on the interface between the silicon epitaxial layer and the channel layer when the channel layer is formed. Further, the threshold voltage of the transistor may be affected, resulting in insufficient low-temperature performance of the channel.
Therefore, how to reduce the process steps of exposing the silicon epitaxial layer until the channel layer is formed and reduce the oxidation degree on the silicon epitaxial layer when the channel layer is formed is a problem to be solved in the field.
It should be appreciated that this background section is intended in part to provide a useful background for understanding the technology. This background section, however, may also include views, concepts or insights that are part of what is not known or understood by those of ordinary skill in the relevant art prior to the corresponding effective application date of the subject matter disclosed herein.
Disclosure of Invention
The present application provides a method of fabricating a three-dimensional memory that at least partially addresses the above-identified problems of the prior art.
The present application provides a method of fabricating a three-dimensional memory, which can simplify process steps, improve process efficiency, and reduce process costs.
The application provides a method for manufacturing a three-dimensional memory, which can reduce the defect density of an interface between a channel layer and an epitaxial layer and improve the low-temperature threshold voltage distribution of the three-dimensional memory.
According to an aspect of the present application, a method for fabricating a three-dimensional memory includes: forming a stacked structure on a substrate, a channel hole penetrating the stacked structure and extending into the substrate, and an epitaxial layer extending away from the substrate on a bottom surface of the channel hole; sequentially forming a functional layer and a protective layer on the top surface of the epitaxial layer and the inner wall of the channel hole; performing a first etch to remove at least a portion of the functional layer and the protective layer overlying the epitaxial layer to expose the epitaxial layer; performing a second etching to remove the remaining protective layer to expose the functional layer; and depositing polysilicon on the exposed functional layer to form a polysilicon channel layer.
According to an embodiment of the present application, the second etching step of removing the remaining protective layer and the step of depositing the polysilicon to form the polysilicon channel layer may be performed using the same apparatus.
According to an embodiment of the present application, the step of the second etching to remove the remaining protective layer and the step of depositing the polysilicon to form the polysilicon channel layer may be performed continuously.
According to one embodiment of the present application, the apparatus may be a furnace apparatus, and the working chamber of the furnace apparatus is isolated from the outside air during the step of performing the second etching and depositing the polycrystalline silicon.
According to one embodiment of the present application, the protective layer may be an amorphous silicon layer.
According to an embodiment of the present application, performing the second etching may include: chlorine gas is introduced into the device.
According to an embodiment of the present application, the process temperature of the apparatus may be in a range of 300 ℃ to 500 ℃ during the second etching.
According to one embodiment of the present application, the time for the chlorine gas to pass into the apparatus may be in the range of 20 minutes to 50 minutes.
According to an embodiment of the present application, after performing the first etching, the method may further include: performing ashing treatment to remove the residue after the first etching; and performing wet stripping and pre-cleaning processes to remove the residue after the ashing process and the oxide formed on the epitaxial layer after the first etching.
According to one embodiment of the present application, performing the wet stripping and pre-cleaning process may include: hydrofluoric acid is applied to the trench hole to a predetermined thickness.
According to an embodiment of the present application, the predetermined thickness may be
To
According to an embodiment of the present application, performing the wet stripping and pre-cleaning process may further include: after applying the hydrofluoric acid for a predetermined time, the trench hole is treated with the diluted sulfuric acid for a predetermined time.
Drawings
Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. In the drawings:
FIG. 1 is a flow chart illustrating a method for fabricating a three-dimensional memory according to an exemplary embodiment of the present application;
fig. 2a to 2f are schematic cross-sectional views illustrating various stages in a process for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application;
fig. 3 is a flowchart showing a processing method between a first etching step and a channel layer forming step according to a comparative embodiment; and
fig. 4 is a flowchart illustrating a processing method between the first etching step and the channel layer forming step according to an exemplary embodiment of the present application.
Detailed Description
Exemplary embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the application are shown. This application may, however, be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
It will also be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers may be present. When an element or layer is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. To this end, the term "connected" may refer to physical, electrical, and/or fluid connections, with or without intervening elements.
Like reference numerals refer to like elements throughout the specification. In the drawings, the thickness of layers and regions are exaggerated for clarity.
It should be noted that in the present description, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not indicate any limitation on the features, and do not particularly indicate any precedence order. Thus, a first etch discussed below may also be referred to as a second etch, and vice versa, without departing from the teachings of one or more embodiments.
While certain embodiments may be implemented differently, the specific process sequence may be performed differently than described. For example, two processes described in succession may be executed substantially concurrently, or in reverse order to that described, or other processes may be interposed between the two processes. However, it should be noted that when two processes are described as being "continuously performed", it means that the two processes are performed one after another, and no other process is performed between the two processes.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. In an exemplary embodiment, when the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, when the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.
As used herein, "about" or "approximately" includes the stated value as well as the average value within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the specified quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, ± 5% of the stated value.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present application and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present application may be presented in a variety of forms, some examples of which are described below.
Fig. 1 shows a flow diagram of a method 100 for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application. As shown in fig. 1, a method 100 for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application includes:
s10: forming a stacked structure on a substrate, a channel hole penetrating the stacked structure and extending into the substrate, and an epitaxial layer extending away from the substrate on a bottom surface of the channel hole;
s20: sequentially forming a functional layer and a protective layer on the top surface of the epitaxial layer and the inner wall of the channel hole;
s30: performing a first etch to expose the epitaxial layer by removing at least a portion of the functional layer and the protective layer covering the epitaxial layer;
s40: performing a second etching to expose the functional layer by removing the remaining protective layer; and S50: the polysilicon channel layer is formed by depositing a polysilicon material on the exposed functional layer.
According to an exemplary embodiment of the present application, the above-described second etching operation (step S40) and the deposition operation of polysilicon (step S50) are continuously performed.
Further, the second etching operation (step S40) and the deposition operation of polysilicon (step S50) are performed sequentially using the same apparatus (e.g., the same furnace apparatus).
Further, during the second etching operation (step S40) and the deposition operation of polysilicon (step S50), especially when the steps S40 and S50 are switched, the working chamber of the device is isolated from the outside air so that the exposed epitaxial layer is not in contact with the air.
A method 100 for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application will be described in detail below with reference to fig. 2a to 2 f.
According to an exemplary embodiment of the present application, step S10 may include, for example: providing a substrate 1; depositing a stacked structure 2 on a top surface of a substrate 1; performing a channel etch in the stacked structure 2 to form a channel hole 3 extending through the stacked structure 2 and below the top surface of the substrate 1; and an epitaxial layer 4 is formed on the bottom surface of the channel hole 3 in a direction away from the substrate 1.
Fig. 2a shows a cross-sectional view of the structure formed after the above-described step S10.
According to an exemplary embodiment of the present application, the substrate 1 may be a semiconductor substrate such as a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, a Silicon-on-Insulator (SOI) substrate, or a Germanium-on-Insulator (GOI) substrate. In other embodiments, the substrate 1 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, silicon carbide, or the like, and the substrate 1 may also be a stacked structure, such as a silicon/germanium-silicon stack or the like. The substrate 1 may be ion-doped, P-doped, or N-doped. A plurality of peripheral devices such as field effect transistors, capacitors, inductors and/or pn junction diodes, etc. may also be formed in the substrate 1. The substrate 1 may also have peripheral circuitry therein.
The stacked structure 2 may be used to form a memory string extending in a vertical direction with respect to the substrate 1. As shown in fig. 2a, in an exemplary embodiment of the present application, the stacked structure 2 may include interlayer dielectric layers 2-1 and sacrificial dielectric layers 2-2 that are alternately stacked. The interlevel dielectric layer 2-1 may be, but is not limited to, a nitride layer, including, for example, silicon nitride. The sacrificial dielectric layer 2-2 may be, but is not limited to, an oxide layer, including, for example, silicon oxide. In subsequent process steps, the sacrificial dielectric layer 2-2 may be replaced with a gate layer.
According to an exemplary embodiment of the present application, the stacked structure 2 may be formed by a process such as a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD).
Further, the stacked structure 2 may include a Single sub-stacked (Single stack) unit (as shown in fig. 2 a), or may include a plurality of sub-stacked (Multiple stack) units stacked sequentially. It is understood that the greater the number of gate layers included in the stacked structure 2, the more memory cells included in the formed memory cell string, and the higher the integration of the device. For example, the number of layers of the gate layer may be set to 32 layers, 64 layers, 96 layers, 128 layers, or the like according to actual needs.
According to an exemplary embodiment of the present application, the channel hole 3 may be formed as a through hole extending through the stack 2 and into the substrate 1, using, for example, an etching process, which may be, for example, dry etching or wet etching, such as Deep Reactive Ion Etching (DRIE). In another embodiment, it is also possible to stop the above-described etching process before the channel hole 3 reaches the substrate 1 and to extend the channel hole 3 further into the substrate 1 by performing a punching process.
According to an exemplary embodiment of the present application, the epitaxial layer 4 may be formed on the bottom surface of the channel hole 3 using a Selective Epitaxial Growth (SEG) process (e.g., Vapor Phase Epitaxy (VPE), Liquid Phase Epitaxy (LPE), molecular beam epitaxy (MPE), etc.). In this exemplary embodiment, the epitaxial layer 4 may be, but is not limited to, a polysilicon layer. According to an exemplary embodiment, before performing the selective epitaxial growth process, an epitaxial growth pre-clean (pre-clean) process may be performed to clean the etched trench hole 3. Furthermore, any suitable doping process, such as an Ion Metal Plasma (IMP) process, may also be performed on the polysilicon layer to form the epitaxial layer 4.
According to an exemplary embodiment of the present application, the method 100 for manufacturing a three-dimensional memory may further include: a functional layer and a protective layer are sequentially formed on the top surface of the epitaxial layer 4 and the inner wall of the channel hole 3 (step S20). The structure including the functional layer and the protective layer formed through this step S20 is hereinafter also referred to as a SONO (i.e., amorphous silicon layer-oxide layer-nitride layer-oxide layer) structure.
The step S20 for forming the SONO structure will be described in detail below with reference to fig. 2 b.
First, the functional layer 5 may be formed by deposition on the top surface of the epitaxial layer 4 and the inner wall of the channel hole 3. Specifically, the steps include: depositing oxide on the top surface of the epitaxial layer 4 and the inner wall of the channel hole 3 to form a gate dielectric layer 51; depositing nitride on the surface of the gate dielectric layer 51 to form a charge storage layer 52; and depositing an oxide on the surface of the charge storage layer 52 to form a tunnel dielectric layer 53. According to an exemplary embodiment, the deposition process in this step may be implemented by a method of Atomic Layer Deposition (ALD).
In other words, the functional layer 5 may be implemented as a channel sidewall stack structure with oxide/nitride/oxide, also referred to as an ONO stack structure.
Next, the protection layer 6 covering the tunnel dielectric layer 53 may be formed by depositing an amorphous silicon layer (a-Si), thereby forming the SONO structure as described above. In this exemplary embodiment, the deposition of the protective layer 6 may be achieved using a method such as Chemical Vapor Deposition (CVD).
The protective layer 6 may be used to prevent the functional layers such as the tunnel dielectric layer 53 from being damaged in the subsequent first etching process of the SONO structure, so as to affect the overall performance of the three-dimensional memory.
According to an exemplary embodiment of the present application, the method 100 for manufacturing a three-dimensional memory may further include: a first etch is performed on the SONO structure (i.e., step S30).
Next, step S30 will be described in detail with reference to fig. 2 c.
As shown in fig. 2c, the step S30 of performing the first etching on the SONO structure may specifically include: the bottom surface of the SONO structure is etched in a direction towards the epitaxial layer 4 to remove a portion of the protective layer 6 and the functional layer 5, which may in particular be a portion covering the epitaxial layer 4, thereby exposing the epitaxial layer 4. By exposing the epitaxial layer 4, it may be allowed to connect with a channel layer 7 (see fig. 2e) subsequently formed within the channel hole 3, thereby forming a circuit loop in which the memory cell string operates.
Further, a trench 41 having a certain depth may also be formed in the epitaxial layer 4 by removing a top portion of the epitaxial layer 4 in contact with the SONO structure.
In step S30, an anisotropic etching method may be used to etch the SONO structure and the top portion of the epitaxial layer 4 to form the trench 41, for example, dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation may be used. It is to be understood that the etching method used to form the trench 41 is not limited thereto. Further, the etching can be stopped at a certain depth of the epitaxial layer 4 by controlling the etching time.
According to an exemplary embodiment of the present application, the method 100 for manufacturing a three-dimensional memory may further include a step S40 for performing a second etching on the protective layer 6 to remove it.
In order to form a channel layer in contact with the functional layer 5, it is necessary to remove the protective layer 6 deposited on the sidewall of the channel hole and then deposit a polysilicon material to cover the functional layer 5 exposed on the sidewall of the channel hole and the epitaxial layer 4 exposed at the bottom of the channel hole, thereby forming a polysilicon channel layer 7 (see fig. 2 e).
A schematic cross-sectional view after step S40 has been performed on the protective layer 6 is shown in fig. 2 d.
According to an exemplary embodiment of the present application, the protective layer 6 is formed of an amorphous silicon (a-Si) material, and may use chlorine gas (Cl) by using a Furnace (FUR) device2) As an etchant to remove the protective layer 6. Specifically, the amorphous silicon (a-Si) in the protective layer 6 may react with chlorine gas to generate gaseous silicon chloride by introducing chlorine gas into the working chamber of the furnace tube device through the gas inlet of the furnace tube device, and setting the working temperature of the furnace tube device within a range of about 300 degrees celsius (deg.c) to about 500 deg.c, thereby removing the protective layer 6. During the steps S40 and S50 performed by the furnace apparatus, the working chamber of the furnace apparatus may be isolated from the outside air, thereby ensuring that the exposed epitaxial layers are not in contact with the air.
Further, according to an exemplary embodiment, the process time period of the amorphous silicon removal operation may be set within a range of about 20 minutes to about 50 minutes.
However, it should be understood that the above process conditions (including process temperature, process duration, etc.) for removing the protective layer using the furnace apparatus given herein are merely exemplary and not limiting. For example, the process conditions may be changed according to actual requirements, and specifically, the process conditions may be adjusted according to the deposition thickness of the protection layer, the material of the protection layer (e.g., amorphous silicon, polysilicon, etc.), and the like.
In addition, the protective layer is removed in the high temperature furnace tube using chlorine gas as an etchant in the above embodiments, but it should be understood that this is merely exemplary and not limited thereto. For example, depending on the material included in the protective layer (e.g., amorphous silicon, etc.), any suitable gas capable of reacting with the material included in the protective layer may be used as the etchant.
On the other hand, in step S40 of removing the protection layer 6, the oxide layer formed on the surface of the exposed epitaxial layer 4 during the transfer of the SONO structure to the furnace device may also be at least partially removed. This will be described in more detail below.
According to an exemplary embodiment of the present application, the method 100 for manufacturing a three-dimensional memory may further include: a polysilicon channel layer is formed by depositing a polysilicon material on the exposed functional layer 5 and the exposed epitaxial layer 4 (i.e., step S50).
A schematic cross-sectional view after performing step S50 for forming a polysilicon channel layer is shown in fig. 2 e.
According to the exemplary embodiment, after performing the second etching on the protection layer 6 by using the furnace apparatus, a polysilicon material is deposited into the trench hole by using a furnace high temperature deposition process in the same furnace apparatus. Specifically, as shown in fig. 2e, a polysilicon material is deposited to the tunnel dielectric layer 53 of the functional layer 5 exposed by the second etching and the exposed epitaxial layer 4, thereby forming a polysilicon channel layer 7 on the surfaces of the tunnel dielectric layer 53 and the epitaxial layer 4.
According to an exemplary embodiment of the present application, the steps S40 and S50 may be performed in-situ on the same tool by continuously performing both the second etching operation (step S40) and the polysilicon deposition operation (step S50) using the same furnace apparatus. In this way, the epitaxial layer 4 can be prevented from being exposed to air during the switching of step S40 and step S50, thereby reducing the degree of oxidation on the surface of the epitaxial layer 4.
According to an example embodiment of the present application, the method 100 for fabricating a three-dimensional memory may further include filling a dielectric layer in the trench hole.
A schematic cross-sectional view after performing the step of filling the trench hole with a dielectric layer is shown in fig. 2 f.
In particular, as shown in fig. 2f, the channel hole may be filled with a filling dielectric layer 8 to form an insulating core of the channel structure. Meanwhile, the filling of the filling dielectric layer 8 can support the channel structure and improve the stability of the channel structure. The fill dielectric layer 8 may comprise a dielectric oxide layer such as silicon oxide. Further, in the filling process, a plurality of insulating gaps can be formed in the filling dielectric layer 8 by controlling the trench filling process to relieve the structural stress.
A masking process, typically using Photoresist (PR), may be performed before performing the first etch S30 on the SONO structure. Thus, after the first etch is completed, other processes such as photoresist removal, pre-cleaning, etc. also need to be performed on the SONO structure to remove photoresist residues and/or oxides that may adversely affect the channel performance.
A processing method between the first etching S30 and the channel layer forming step S50 according to an exemplary embodiment of the present application will be described below in comparison with the related art.
Fig. 3 is a flowchart illustrating a processing method 200 between a first etching step and a channel layer forming step according to a comparative embodiment.
Referring to fig. 3, according to a comparative embodiment, a processing method 200 between a first etching step and a channel layer forming step in a channel structure fabrication process may include: ashing treatment (step S11), wet stripping treatment (step S21), protective layer removal pre-cleaning treatment (step S31, hereinafter simply referred to as pre-cleaning treatment), protective layer removal treatment (step S41), and protective layer removal post-cleaning treatment (step S51, hereinafter simply referred to as post-cleaning treatment).
In step S11, the first post-etch residue (e.g., photoresist) is removed by performing an ashing (Asher) process on the SONO structure. Generally, the photoresist may include an organic material. In this step, for example, oxygen (O) may be utilized2) Burning off the residual photoresist on the SONO structure after the first etchingTo convert it into carbon dioxide (CO)2) And (4) discharging.
In step S21, a Wet Strip (Wet Strip) process is performed on the SONO structure to remove the ashed residues (e.g., the burned-off residues of the photoresist, etc.). In this step, dilute sulfuric acid (H) may be utilized2SO4) And cleaning the ashed SONO structure with hydrofluoric acid (HF). In particular, for example, a thickness of about one can be applied to the inner wall of the SONO structure
Hydrofluoric acid (HF), using H after the reaction is finished2SO4Rinsing for about 15 to 25 minutes. Further, by H2SO4The washing time of (a) may be 18 minutes.
As mentioned above, epitaxial layers are susceptible to oxidation to oxide when in contact with air, and excessive residue of the oxide can have a non-negligible effect on the overall performance of the final memory.
After exposing the epitaxial layer by the first etching step, the SONO structure is further subjected to an ashing process (step S11), a wet stripping process (step S21), and the like. During the performance of steps S11 and S21, the exposed epitaxial layer (which may comprise a material such as monocrystalline or polycrystalline silicon) may be oxidized to varying degrees depending on factors such as the exposure time of the epitaxial layer to air, the material of the epitaxial layer itself, and so forth. Thus, a pre-cleaning process for removing the oxide may be performed before removing the protective layer.
In step S31, a Pre-clean (Pre-clean) operation is performed on the SONO structure to remove oxide formed on the exposed epitaxial layer. In this step, HF may be applied again to the inner wall of the SONO structure for a pre-cleaning process, for example, a thickness of about
HF of (2).
In step S41, the protective layer is removed using a furnace apparatus using chlorine gas as an etchant. Specifically, chlorine gas is introduced into the furnace tube apparatus at a temperature of about 300 degrees Celsius (C.) to about 500 ℃ for about 20 minutes to about 50 minutes.
In step S51, a Post-clean (Post-clean) operation is performed on the SONO structure with the ADM solution to reduce impurities in the SONO structure. Specifically, the ADM solution may be ammonia water under a temperature environment of about 70 ℃.
According to a comparative embodiment, after step S51 is completed, the SONO structure needs to be transferred to a channel polysilicon deposition machine for depositing polysilicon to perform a polysilicon channel layer formation step.
However, during the process of transferring the SONO structure from the furnace device to the polysilicon deposition tool, the exposed epitaxial layer may be oxidized again. As mentioned previously, the more oxide on the epitaxial layer, the more likely an epitaxial-Channel interface (SEG-Channel interface) with a higher defect density is formed, thereby degrading the low temperature performance of the transistor.
Fig. 4 is a flow chart illustrating a processing method 300 between a first etching step and a channel layer forming step according to an exemplary embodiment of the present application.
As shown in fig. 4, the method 300 may include: ashing treatment (step S12), wet stripping and pre-cleaning treatment (step S22), and resist removal treatment (step S32). The protective layer removing process S32 may correspond to the second etching step S40 in the method 100.
In step S12, an ashing process is performed on the SONO structure. According to an exemplary embodiment of the present application, the step S12 for the ashing process may be substantially the same as the step S11 in the method 300. Therefore, it will not be described herein in detail.
In step S22, a wet strip and a pre-clean process are performed on the SONO structure simultaneously. In this step, HF and diluted H, which are applied in a larger amount than HF in step S21 according to the comparative embodiment, may be utilized2SO4The SONO structure is processed to simultaneously remove the ashed residue and oxide. Specifically, in step S22, for example, the inner wall of the SONO structure may be applied with a thickness of about
To about
Further, e.g., about
HF) after the reaction is completed by using H2SO4Rinsing for about 15 to 25 minutes. Further, by H2SO4The washing time of (a) may be 18 minutes.
In step S32, the protective layer is removed using a furnace apparatus using chlorine gas as an etchant. According to an exemplary embodiment of the present application, step S32 may be substantially the same as step S31 in method 300. Therefore, it will not be described herein in detail.
According to the exemplary embodiment of the present application, after the step S32 of removing the protection layer is completed, the polysilicon deposition operation is continuously performed in the furnace apparatus, without the need of first transferring the SONO structure to a cleaning apparatus to perform a cleaning operation and then transferring the SONO structure to a polysilicon deposition machine, as in the method 200 according to the comparative example, so that the chance of oxidation of the epitaxial layer is effectively reduced, and the oxidation degree is reduced.
In addition, in the method 300 according to the embodiment of the present application, although the SONO structure needs to be transferred from the cleaning apparatus to the furnace apparatus after the step S22 for removing the oxide on the epitaxial layer is performed, which also results in the epitaxial layer being oxidized again, the amount of oxide formed in the process is small, and the portion of oxide can be at least partially removed in the process of removing the protection layer by using the furnace apparatus, so that the influence of the finally remaining amount of oxide on the overall performance of the three-dimensional memory is within an acceptable range.
According to an exemplary embodiment of the present application, the second etching operation (step S40) and the polysilicon deposition operation (step S50) may be performed on the SONO structure sequentially by the same furnace apparatus. The SONO structure does not need to be transferred in the process, so that the chance that the epitaxial layer is oxidized due to contact with air is reduced.
Thus, the method for manufacturing a three-dimensional memory according to the exemplary embodiment of the present application may reduce density defects on an interface between an epitaxial layer and a channel layer by reducing the chance of the epitaxial layer contacting air. Thus, the method for manufacturing a three-dimensional memory according to the exemplary embodiment of the present application may realize a three-dimensional memory having a more converged threshold voltage distribution under a low temperature environment.
On the other hand, in comparison with the operation procedure of the comparative embodiment, taking the processing method between the first etching step and the channel layer forming step as an example, the method according to the exemplary embodiment of the present application omits step S31 for pre-cleaning and step S51 for post-cleaning, and makes it possible to perform both functions of wet stripping and pre-cleaning at once by increasing the application amount of HF in step S22. Thus, the method for manufacturing a three-dimensional memory according to the exemplary embodiment of the present application significantly simplifies process steps.
Thus, the method for manufacturing the three-dimensional memory according to the exemplary embodiment of the present application may effectively improve process efficiency and reduce process costs by reducing the number of steps of the process. Meanwhile, with the reduction of the number of the process steps, the chance of the contact of the epitaxial layer and air can be effectively reduced, so that the oxidation degree of the epitaxial layer is effectively reduced.
In addition, in the subsequent process of the method for preparing the three-dimensional memory, the method further comprises the step of removing the sacrificial dielectric layer in the alternately stacked insulating dielectric layers and sacrificial dielectric layers, and replacing the step of forming the gate layer with the metal layer. The embodiments and process flows in this application only show the stacked structure before gate layer formation. The final product of the three-dimensional memory should be provided with a stacked structure of alternating insulating and gate layers.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the respective embodiments cannot be used in an advantageous combination.
The embodiments of the present application are described above. However, these embodiments are for illustrative purposes only, and are not intended to limit the scope of the present application. The scope of the application is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present application, and such alternatives and modifications are intended to be within the scope of the present application.
Claims (12)
1. A method for fabricating a three-dimensional memory, the method comprising:
forming a stacked structure on a substrate, a channel hole penetrating the stacked structure and extending into the substrate, and an epitaxial layer extending on a bottom surface of the channel hole away from the substrate;
sequentially forming a functional layer and a protective layer on the top surface of the epitaxial layer and the inner wall of the channel hole;
performing a first etch to remove at least a portion of the functional layer and the protective layer overlying the epitaxial layer to expose the epitaxial layer;
performing second etching to remove the remaining protective layer to expose the functional layer; and
and depositing polysilicon on the exposed functional layer to form a polysilicon channel layer.
2. The method of claim 1, wherein the step of removing the remaining protective layer and the step of depositing polysilicon to form a polysilicon channel layer are performed using the same apparatus.
3. The method of claim 1 or 2, wherein the step of removing the remaining protective layer by the second etching and the step of depositing polysilicon to form a polysilicon channel layer are performed sequentially.
4. The method of claim 2, wherein the apparatus is a furnace apparatus, and wherein a working chamber of the furnace apparatus is isolated from outside air during the steps of performing the second etching and depositing polysilicon.
5. The method of claim 2, wherein the protective layer is an amorphous silicon layer.
6. The method of claim 5, wherein performing the second etch comprises:
chlorine gas was fed to the apparatus.
7. The method of claim 6, wherein during the second etching, a processing temperature of the apparatus is in a range of 300 ℃ to 500 ℃.
8. The method of claim 6, wherein the chlorine gas is passed into the apparatus for a time in the range of 20 minutes to 50 minutes.
9. The method of claim 1, wherein after performing the first etch, the method further comprises:
performing ashing treatment to remove the residue after the first etching; and
and performing wet stripping and pre-cleaning treatment to remove the residue after the ashing treatment and the oxide formed on the epitaxial layer after the first etching.
10. The method of claim 9, wherein performing the wet strip and pre-clean process comprises:
hydrofluoric acid is applied to the channel hole to a predetermined thickness.
11. The method of claim 10, wherein the predetermined thickness is
To
12. The method of claim 10 or 11, wherein performing the wet strip and pre-clean process further comprises: treating the channel hole with diluted sulfuric acid for a predetermined time after applying the hydrofluoric acid for a predetermined time.
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