CN107946314B - 3D nand memory drain selection pipe and forming method thereof - Google Patents
3D nand memory drain selection pipe and forming method thereof Download PDFInfo
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- CN107946314B CN107946314B CN201711183455.1A CN201711183455A CN107946314B CN 107946314 B CN107946314 B CN 107946314B CN 201711183455 A CN201711183455 A CN 201711183455A CN 107946314 B CN107946314 B CN 107946314B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- Non-Volatile Memory (AREA)
Abstract
The present invention proposes drain selection pipe and forming method thereof in a kind of 3D nand memory, include: first pair of stack layer deposit hard mask layer in deposition, and etch and form deep hole, deposit non-impurity-doped polysilicon fills deep hole, extra polysilicon is removed, and carries out the ion implanting of boron；Silicon nitride hard mask layer is removed, deposits remaining silica in first pair of stack layer, and continue to deposit multipair stack layer；The multipair stack layer of formation is etched to form multiple holes；Deposit is in multiple holes of formation to form polycrystalline silicon channel；Unformed silicon is deposited in channels, and annealing forms polysilicon, forms drain terminal contact after ion implanting；Stack layer silicon nitride forms drain selection pipe oxide layer by thermal oxide after wet etching, to source electrode polycrystalline, finally deposits tungsten and forms gate contact.The forming process of this method is conducive to reduce the high temperature process in 3D NAND technique, to avoid influence of the accumulation of heat to device performance.
Description
Technical field
The present invention relates to field of semiconductor manufacture, and in particular to a kind of 3D nand memory drain selection pipe and its formation
Method.
Background technique
As the demand to integrated level and memory capacity is continuously improved, 3D (three-dimensional) nand memory comes into being.3D
Nand memory is a kind of novel product based on plane nand memory, and the main characteristics of this product are to turn plane result
Stereochemical structure is turned to, silicon area is greatly saved, manufacturing cost is reduced, increases memory capacity.
In 3D nand memory, storage string is connected by selecting pipe with bit line and source line respectively up and down.Prior art
In, after vertical-channel is etched to silicon substrate, metal is formed by the method for monocrystalline silicon epitaxy at exposed substrate monocrystal silicon
Oxide transistor requires the height of epitaxial monocrystalline silicon to be less than in silica/nitridation silicon bench to form lower selecting pipe
The half of first layer silica.
Existing lower selecting pipe structure be formed as selective epitaxial growth process growth monocrystalline silicon, this technique heat demand compared with
Greatly, technological temperature is typically about 850 DEG C, is easy to influence the transistor device performances such as peripheral circuit.
Existing monocrystalline silicon epitaxy technique is higher to preceding process requirements, and the technological fluctuation of preceding processing procedure easily causes outside monocrystalline silicon
Delay forms cavity and the height of epitaxial silicon is inhomogenous.
The present invention proposes a kind of 3D nand memory drain selection pipe, avoids introducing high temperature system during forming it into
Journey, conducive to the high temperature process reduced in 3D NAND technique, to avoid influence of the accumulation of heat to device performance.
Summary of the invention
The present invention relates to a kind of 3D nand memory drain selection pipes, it is characterised in that selecting pipe channel forms sediment in stack layer
It is formed during product by polysilicon deposition.
The invention further relates to a kind of 3D nand memory drain selection pipe forming methods, in turn include the following steps:
Step 1: being sequentially depositing silicon oxide layer, silicon nitride layer, silicon oxide layer on a silicon substrate, form first pair of stack layer；
Step 2: deposit silicon nitride does hard mask layer on being formed by first pair of stack layer；
Step 3: forming photoresist, and etch above-mentioned stack layer and form deep hole；
Step 4: deposit non-impurity-doped polysilicon filling is formed by deep hole, which covers hard mask layer；
Step 5: chemical mechanical grinding removes extra polysilicon, including on hard mask layer and the polycrystalline of prominent deep hole
Silicon, and carry out the ion implanting of boron；
Step 6: removing silicon nitride hard mask layer using dry etching；
Step 7: remaining silica in first pair of stack layer of deposit, the silicon oxide layer and polysilicon formed before covering
Layer；
Step 8: continuing to deposit multipair silicon nitride, silica stack layer；
Step 9: utilizing memory block channel hole array etching technics, step 5 formation is etched to the multipair stack layer of formation
Polysilicon layer, form multiple holes；
Step 10: deposit forms memorizer tunnel layer, accumulation layer and barrier layer in multiple holes of formation, and is formed more
Crystal silicon channel.Silica, silicon nitride, silica are selected in tunnel layer, accumulation layer and barrier layer respectively；Step 11: forming sediment in channels
The unformed silicon of product, annealing form polysilicon, form drain terminal contact after ion implanting；Stack layer silicon nitride after wet etching,
Drain selection pipe oxide layer is formed by thermal oxide to source electrode polycrystalline, tungsten is finally deposited and forms gate contact.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.The size of each component is only in the accompanying drawings
For the purpose illustrated, be it is schematical, be not drawn to be drawn.
Attached drawing 1 is the 3D nand memory drain selection for forming first pair of lamination on a silicon substrate according to the method for the present invention
Tube section figure；
Attached drawing 2 is to form the 3D nand memory drain selection tube section figure after hard mask layer according to the method for the present invention；
Attached drawing 3 is to form photoresist according to the method for the present invention and perform etching the 3D nand memory source after forming deep hole
Pole selecting pipe sectional view；
Attached drawing 4 is to form the 3D nand memory drain selection tube section figure after polysilicon according to the method for the present invention；
Attached drawing 5 is to remove the 3D nand memory drain selection tube section figure after polysilicon according to the method for the present invention；
Attached drawing 6 is the 3D nand memory drain selection tube section figure after removing hard exposure mask according to the method for the present invention；
Attached drawing 7 is the 3D NAND storage formed in the first stack layer after remaining silicon oxide layer according to the method for the present invention
Device drain selection tube section figure；
Attached drawing 8 is the 3D nand memory drain selection tube section after forming multiple stack layers according to the method for the present invention
Figure；
Attached drawing 9 is the 3D nand memory drain selection tube section figure behind multiple holes according to the method for the present invention；
Attached drawing 10 is to form the 3D nand memory drain selection tube section after polycrystalline silicon channel according to the method for the present invention
Figure；
Attached drawing 11 is the 3D nand memory drain selection tube section figure formed according to the method for the present invention.
Specific embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this public affairs in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can be by this public affairs
The range opened is fully disclosed to those skilled in the art.
The present invention relates to a kind of 3D nand memory drain selection pipes, it is characterised in that selecting pipe channel forms sediment in stack layer
It is formed during product by polysilicon deposition.
The present invention relates to a kind of 3D nand memory drain selection pipe forming methods, include the following steps:
As shown in Figure 1, being sequentially depositing silicon oxide layer, silicon nitride layer, silicon oxide layer on a silicon substrate, first pair of stacking is formed
Layer.
Deposit silicon nitride does hard mask layer, such as Fig. 2 on being formed by first pair of stack layer later.
Such as Fig. 3, it is subsequently formed photoresist, and etches above-mentioned stack layer and forms deep hole；
Such as Fig. 4, the filling of non-impurity-doped polysilicon is deposited later and is formed by deep hole, which covers hard mask layer；
Chemical mechanical grinding removes extra polysilicon, including going forward side by side on hard mask layer and the polysilicon of prominent deep hole
The ion implanting of row boron, as shown in Figure 5；
Silicon nitride hard mask layer is removed using dry etching, as shown in Figure 6；
Remaining silica in first pair of stack layer is deposited, the silicon oxide layer and polysilicon layer of formation before covering, such as
Fig. 7；
Later, as shown in Figure 8, continue to deposit multipair silicon nitride, silica stack layer；
Then, using memory block channel hole array etching technics, Fig. 5 formation are etched to more to the multipair stack layer of formation
Crystal silicon layer forms multiple holes, as illustrated in FIG. 9；
Figure 10 is shown, and deposit forms memorizer tunnel layer, accumulation layer and barrier layer in multiple holes of formation, and is formed
Polycrystalline silicon channel.Silica, silicon nitride, silica are selected in tunnel layer, accumulation layer and barrier layer respectively.
Figure 11 is shown, and deposits unformed silicon in channels, and annealing forms polysilicon, forms drain terminal contact after ion implanting.
Stack layer silicon nitride forms drain selection pipe oxide layer by thermal oxide after wet etching, to source electrode polycrystalline, finally deposits
Tungsten forms gate contact.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (5)
1. a kind of 3D nand memory drain selection pipe forming method, includes the following steps:
Step 1: being sequentially depositing silicon oxide layer, silicon nitride layer, silicon oxide layer on a silicon substrate, form first pair of stack layer；
Step 2: deposit silicon nitride does hard mask layer on being formed by first pair of stack layer；
Step 3: forming photoresist, and etch above-mentioned stack layer and form deep hole；
Step 4: deposit non-impurity-doped polysilicon filling is formed by deep hole, which covers hard mask layer；
Step 5: removing extra polysilicon, and carry out the ion implanting of boron；
Step 6: removing silicon nitride hard mask layer；
Step 7: remaining silica in first pair of stack layer of deposit, the silicon oxide layer and polysilicon layer formed before covering；
Step 8: continuing to deposit multipair silicon nitride, silica stack layer；
Step 9: being etched to the polysilicon layer of step 5 formation to the multipair stack layer of formation, form multiple holes；
Step 10: deposit forms memorizer tunnel layer, accumulation layer and barrier layer in multiple holes of formation, and forms polysilicon
Channel；
Step 11: depositing unformed silicon in channels, annealing forms polysilicon, forms drain terminal contact after ion implanting；Stack layer
Silicon nitride forms drain selection pipe oxide layer by thermal oxide after wet etching, to source electrode polycrystalline, finally deposits tungsten
Form gate contact.
2. a kind of 3D nand memory drain selection pipe forming method according to claim 1, it is characterised in that: in institute
It states in step 5 and removes extra polysilicon using chemical mechanical grinding.
3. a kind of 3D nand memory drain selection pipe forming method according to claim 1, it is characterised in that: in institute
It states in step 6 and removes silicon nitride hard mask layer using dry etching.
4. a kind of 3D nand memory drain selection pipe forming method according to claim 1, it is characterised in that: in institute
It states in step 9 and forms the hole using memory block channel hole array etching technics.
5. a kind of 3D nand memory drain selection pipe forming method according to claim 1, it is characterised in that: described
Tunnel layer, accumulation layer and barrier layer in step 10 select silica, silicon nitride, silica to be formed respectively.
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| CN107946314B true CN107946314B (en) | 2018-12-14 |
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| CN109065546A (en) * | 2018-08-31 | 2018-12-21 | 长江存储科技有限责任公司 | The manufacturing method of 3D memory device |
| CN109727981B (en) * | 2019-01-31 | 2021-05-18 | 长江存储科技有限责任公司 | 3D NAND memory and forming method thereof |
| CN110085599A (en) * | 2019-03-25 | 2019-08-02 | 长江存储科技有限责任公司 | Three-dimensional storage and preparation method thereof |
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| CN106257675A (en) * | 2015-06-18 | 2016-12-28 | 旺宏电子股份有限公司 | Non-volatile memory device and manufacture method thereof |
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| KR20100133212A (en) * | 2009-06-11 | 2010-12-21 | 주식회사 하이닉스반도체 | 3d-nonvolatile memory device and method for fabricating the same |
| KR20110060752A (en) * | 2009-11-30 | 2011-06-08 | 주식회사 하이닉스반도체 | Method for fabricating vertical channel type non-volatile memory device |
| EP2731110B1 (en) * | 2010-12-14 | 2016-09-07 | SanDisk Technologies LLC | Architecture for three dimensional non-volatile storage with vertical bit lines |
| US8877624B2 (en) * | 2013-01-10 | 2014-11-04 | Micron Technology, Inc. | Semiconductor structures |
| CN103904118B (en) * | 2014-03-10 | 2016-08-31 | 北京大学 | There is the field-effect transistor of memory function and three-dimensionally integrated method thereof |
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