CN107093577A - The manufacture method of contact hole - Google Patents
The manufacture method of contact hole Download PDFInfo
- Publication number
- CN107093577A CN107093577A CN201710248901.6A CN201710248901A CN107093577A CN 107093577 A CN107093577 A CN 107093577A CN 201710248901 A CN201710248901 A CN 201710248901A CN 107093577 A CN107093577 A CN 107093577A
- Authority
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- China
- Prior art keywords
- contact hole
- etching
- barrier layer
- manufacture method
- etching barrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
The invention discloses a kind of manufacture method of contact hole, including step：Step 1: forming etching barrier layer.Step 2: forming interlayer film.Step 3: lithographic definition goes out the forming region of contact hole.Step 4: carrying out first time contact hole etching by stop layer of etching barrier layer.The etching barrier layer of the forming region of contact hole is all removed and contact hole is formed Step 5: carrying out second of contact hole etching, by setting etching barrier layer the over etching amount of silicon substrate is determined completely by the thickness of etching barrier layer, so as to reduce the over etching amount of silicon substrate.The row metal silicification reaction Step 6: titanium deposition and titanium nitride layer are gone forward side by side.Step 7: being filled up completely with metal level in the contact hole.The present invention is carved to the damage caused by silicon substrate during reducing contact hole etching because crossing, and is reduced technological fluctuation and is reduced resulting electric leakage, improves the yield of product.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, more particularly to a kind of manufacture method of contact hole.
Background technology
In existing self-aligned contact hole (Self Aligned Contact, SAC) technique, SRAM
(SRAM) there is the problem of electric leakage is bigger than normal in unit (cell), existing SAC processes include step：
In Semiconductor substrate such as surface of silicon formation interlayer film, afterwards, chemical wet etching formation is carried out to interlayer film and is contacted
Hole, in integrated circuits, with the increase of integrated level, the source region of the MOS transistor such as nmos pass transistor in SRAM unit and
The bottom size of contact hole at the top of drain region is typically used and defined by the side wall autoregistration of the side of two neighboring polysilicon gate, with
The increase of integrated level, the fluctuation of the technique of self-aligned contact hole can increase the electric leakage of sram cell, so that product can be reduced
Yield.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of manufacture method of contact hole, can reduce contact hole etching mistake
Carved in journey because crossing to the damage caused by silicon substrate, reduce technological fluctuation and reduce resulting electric leakage, improve the yield of product.
In order to solve the above technical problems, the manufacture method for the contact hole that the present invention is provided, it is characterised in that including following step
Suddenly：
Step 1: in surface of silicon formation etching barrier layer；The surface of silicon is formed in need to be formed at top
The doped region of contact hole.
Step 2: forming interlayer film on the surface of the etching barrier layer.
Step 3: defining the forming region of the contact hole using photoetching process.
Step 4: carry out first time contact hole etching, the first time contact hole etching be using the etching barrier layer as
Stop layer performs etching to the interlayer film and all removes the interlayer film of the forming region of the contact hole；
Step 5: carrying out second of contact hole etching, second of contact hole etching is by the formation area of the contact hole
The etching barrier layer in domain all removes and forms the contact hole, in order to ensure that the etching barrier layer is all removed institute
Over etching can be carried out to the silicon substrate by stating second of contact hole etching, and the thickness of the etching barrier layer is less than the interlayer film
Thickness, by set the etching barrier layer make the silicon substrate over etching amount completely by the etching barrier layer thickness
Determine and less than the over etching amount of the silicon substrate determined by the thickness of the interlayer film, the thickness of the etching barrier layer
The over etching amount of the more thin silicon substrate is smaller.
Step 6: titanium deposition and titanium nitride layer, the titanium and titanium nitride layer be formed at the contact hole lower surface and
Sideways, lower surface formation Titanium silicide of the metal silication reaction in the contact hole, the over etching amount of the silicon substrate are carried out
After reduction, transversal erosion of the Titanium silicide to the bottom of the contact hole is reduced.
Step 7: being filled up completely with metal level in the contact hole.
Further improve is that the thickness of the etching barrier layer is tens to hundreds of angstroms, and the thickness of the interlayer film is
Thousands of to tens thousand of angstroms.
Further improve is that the metal that step 7 is filled in the contact hole is tungsten.
Further improve is that the material of the interlayer film is silica, and the material of the etching barrier layer is silicon nitride.
Further improve is that the contact hole is the contact hole at the top of the source region of MOS transistor and drain region, the MOS
Contact hole at the top of the polysilicon gate of transistor is also formed simultaneously.
Further improve be, in the step of forming the MOS transistor step one formed the etching barrier layer it
It is preceding also to include step：
Step 11, in the surface of silicon gate dielectric layer, polysilicon layer and hard mask layers.
Step 12, lithographic definition go out the forming region of the polysilicon gate, successively to the forming region of the polysilicon gate
The outer hard mask layers, the polysilicon layer and the gate dielectric layer is performed etching, the polysilicon layer after etching
It is used as the polysilicon gate.
Step 13, the side formation side wall in the polysilicon gate.
Step 14, the hard mask layers removal by the subregion at the top of the polysilicon gate, the hardmask
The top surface for the polysilicon gate that layer is removed region exposes, the bottom position of the contact hole at the top of the follow-up polysilicon gate
It is removed in the hard mask layers in region.
Step 15, the surface of silicon in the polysilicon gate both sides form source region and drain region.
Subsequent step one is carried out afterwards.
Further improve is that the material of the hard mask layers is silicon nitride, and the material of the side wall is silicon nitride, institute
The material for stating interlayer film is silica, and the material of the etching barrier layer is silicon nitride.
Further improve is that the gate dielectric layer is gate oxide, is formed using thermal oxidation technology.
Further improve be, source region described in step 15 and with the drain region respectively with the both sides of the polysilicon gate
The surface autoregistration of the side wall, the source region and the drain region are formed simultaneously using source and drain ion implantation technology.
Further improve is that the MOS transistor is nmos pass transistor, and the source region and the drain region are all by N+ district's groups
Into.
Further improve is that the MOS transistor is PMOS transistor, and the source region and the drain region are all by P+ district's groups
Into.
Further improve is that the contact hole at the top of the source region and the drain region is all self-aligned contacts
Hole, the bottom size of the self-aligned contact hole is defined by the side wall autoregistration of the two neighboring polysilicon gate.
Further improve is to grow the etching barrier layer using chemical vapour deposition technique in step one；In step 2
The interlayer film is grown using chemical vapour deposition technique.
Further improve is also to include being planarized using chemical mechanical milling tech after the interlayer film is formed
The step of.
Compared to the prior art, the present invention is specially provided with the etching barrier layer of a thinner thickness in interlayer film bottom,
In the etching of contact hole, the etching to interlayer film uses etching barrier layer for stop layer so that the depth model of whole contact hole
In enclosing, the fluctuation of the etching technics of interlayer film to the etching technics of whole contact hole has no effect；Carved to interlayer film
After erosion is completed, then etching barrier layer is performed etching, due to the thinner thickness of etching barrier layer, in order to remove etching resistance completely
Barrier, the over etching amount (OE) to silicon substrate also can be less, under conditions of same percentage over etching amount, due to the present invention's
The thickness of etching barrier layer substantially reduce as be reduced to interlayer film 1/tens, can finally make the over etching amount of silicon substrate
Substantially reduce；So and the etching technics of contact hole can produce larger over etching to cause silicon to silicon substrate in the prior art
Substrate surface is produced in the etching technics for damaging different, of the invention contact holes only by the etching technics of relatively thin etching barrier layer
Can be related to the over etching of silicon substrate, so as to substantially reduce damage of the etching to surface of silicon of contact hole, so as to drop
The low electric leakage for thus damaging the device caused, improves the yield of product.Wherein, percentage over etching amount refers to that (etching apparatus is set
The etch thicknesses put-actual (real) thickness for the film layer that is etched)/actual (real) thickness for the film layer that is etched.
Further, since the over etching amount of silicon substrate is substantially reduced so that the side depth of the silicon groove of the bottom of contact hole
Reduce, while after the completion of SiN etching barrier layers etching, still have residual in contact hole bottom sidewall and surface of silicon junction,
So it can also play a protective role, so in the forming process of follow-up metal silicide, metal silicide is Titanium silicide
Transversal erosion to the bottom of contact hole can be reduced, and this can cause the pattern of the bottom of contact hole to substantially improve；So, and it is existing
The thickness inequality of metal silicide can be formed in one direction after the bottom formation metal silicide of contact hole in method
Lateral corrasion is different, and the present invention can reduce transversal erosion meeting of the Titanium silicide to the bottom of contact hole, so as to reduce thus institute
The electric leakage of generation, so as to improve the yield of product.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the flow chart of present invention method；
Fig. 2A-Fig. 2 I are the schematic diagrames of the device architecture in each step of present invention method.
Embodiment
As shown in figure 1, being the flow chart of present invention method；It is the embodiment of the present invention as shown in Fig. 2A to Fig. 2 I
Contact hole 101 is in the schematic diagram of device architecture in each step of method, the manufacture method of contact hole of the embodiment of the present invention 101
Contact hole 101 at the top of the source region of MOS transistor in MOS transistor such as sram cell and drain region, the MOS transistor it is many
The contact hole 101 at the top of crystal silicon grid 2 is also formed simultaneously, and present invention method comprises the following steps：
The following step related to device unit construction is formed first is carried out before one the step of contact hole 101 are formed：
Step 11, as shown in Figure 2 A, is covered in the surface gate dielectric layer (not shown) of silicon substrate 1, polysilicon layer 2 and hard
Mold layer 3.Preferably, the material of the hard mask layers 3 is silicon nitride.The gate dielectric layer is gate oxide, using thermal oxide
Technique is formed.
Step 12, as shown in Figure 2 B, lithographic definition goes out the forming region of the polysilicon gate 2, successively to the polysilicon
The hard mask layers 3, the polysilicon layer 2 and the gate dielectric layer outside the forming region of grid 2 are performed etching, after etching
The polysilicon layer 2 be used as the polysilicon gate 2.In Fig. 2A and Fig. 2 B, the polysilicon layer and the polysilicon gate are all adopted
Represented with mark 2, Fig. 2A represents that the situation before polysilicon layer etching, Fig. 2 B form polysilicon gate after representing polysilicon layer etching
Situation.
Step 13, the side formation side wall 4 in the polysilicon gate 2.Side wall 4 adds dry method using the cvd dielectric layer of side wall
Etching technics is formed.Specially：
As described in Fig. 2 C, the dielectric layer 4 of side wall is formed on the surface for foring the silicon substrate 1 of the polysilicon gate 2.
Preferably, the dielectric layer material of the side wall 4 is silicon nitride.
As shown in Figure 2 D, the dry etch process formation only side of polysilicon gate 2 is carried out to the dielectric layer 4 of the side wall
The institute on the surface of the silicon substrate 1 outside side wall 4, the surface of hard mask layers 3 at the top of polysilicon gate 2 and polysilicon gate 2
The dielectric layer 4 for stating side wall is all removed.
Step 14, as shown in Figure 2 E, the hard mask layers 3 of the subregion at the top of polysilicon gate 2 are removed,
The top surface that the hard mask layers 3 are removed the polysilicon gate 2 in region exposes, the follow-up top of polysilicon gate 2
The bottom of contact hole 101 be removed positioned at the hard mask layers 3 in region.
Step 15, on the surface of the silicon substrate 1 of the both sides of polysilicon gate 2 form source region (not shown) and drain region (not
Show).Preferably, the source region and with the drain region respectively with the surface of the side wall 4 of the both sides of the polysilicon gate 2 from
Alignment, the source region and the drain region are formed simultaneously using source and drain ion implantation technology.
In present invention method, the MOS transistor is nmos pass transistor, and the source region and the drain region are all by N+
District's groups into.Or, the MOS transistor be PMOS transistor, the source region and the drain region all by P+ district's groups into.
The step of carrying out following formation contact hole 101 afterwards：
Step 1: as shown in Figure 2 F, etching barrier layer 5 is formed on the surface of silicon substrate 1；The surface of silicon substrate 1 is formed with
Need to form source region and the drain region that the doped region of contact hole 101 is such as formed above at top.Preferably, using chemical vapor deposition
Area method grows the etching barrier layer 5.
Step 2: as shown in Figure 2 G, interlayer film 6 is formed on the surface of the etching barrier layer 5.Preferably, using chemistry
Vapour deposition process grows the interlayer film 6.Also include being put down using chemical mechanical milling tech after the interlayer film 6 is formed
The step of smoothization.
Step 3: as illustrated in figure 2h, the forming region of the contact hole 101 is defined using photoetching process.
Step 4: as illustrated in figure 2h, carrying out first time contact hole etching, the first time contact hole etching is carved with described
Erosion barrier layer 5 is that stop layer is performed etching to the interlayer film 6 and by the interlayer film of the forming region of the contact hole 101
6 all remove.
Step 5: as shown in figure 2i, second of contact hole etching is carried out, second of contact hole etching is by the contact
The etching barrier layer 5 of the forming region in hole 101 all removes and forms the contact hole 101, in order to ensure the etching
Barrier layer 5, which is all removed second of contact hole etching, to carry out over etching, the etching barrier layer to the silicon substrate 1
5 thickness is less than the thickness of the interlayer film 6, by setting the etching barrier layer 5 to make the over etching amount of the silicon substrate 1 complete
Determined and less than the mistake of the silicon substrate 1 determined by the thickness of the interlayer film 6 by the thickness of the etching barrier layer 5 entirely
Etch amount, the over etching amount of the more thin silicon substrate 1 of thickness of the etching barrier layer 5 is smaller.In present invention method,
The material of the interlayer film 6 is silica, and the material of the etching barrier layer 5 is silicon nitride.The thickness of the etching barrier layer 5
For tens to hundreds of angstroms, the thickness of the interlayer film 6 is thousands of to tens thousand of angstroms.Preferably, positioned at the source region and the drain region
The contact hole 101 at top is all self-aligned contact hole 101, and the bottom size of the self-aligned contact hole 101 is by adjacent two
The autoregistration of side wall 4 definition of the individual polysilicon gate 2.
Step 6: as shown in figure 2i, titanium deposition and titanium nitride layer, the titanium and titanium nitride layer are formed at the contact hole
101 lower surface and side, carry out lower surface formation Titanium silicide of the metal silication reaction in the contact hole 101, institute
After the over etching amount reduction for stating silicon substrate 1, transversal erosion of the Titanium silicide to the bottom of the contact hole 101 is reduced.
Step 7: as shown in figure 2i, metal level is filled up completely with the contact hole 101.Preferably, in the contact hole
The metal filled in 101 is tungsten.
The present invention is described in detail above by specific embodiment, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (14)
1. a kind of manufacture method of contact hole, it is characterised in that comprise the following steps：
Step 1: in surface of silicon formation etching barrier layer；The surface of silicon forms in need formed at top and contacted
The doped region in hole；
Step 2: forming interlayer film on the surface of the etching barrier layer；
Step 3: defining the forming region of the contact hole using photoetching process；
Step 4: carrying out first time contact hole etching, the first time contact hole etching is using the etching barrier layer as termination
Layer performs etching to the interlayer film and all removes the interlayer film of the forming region of the contact hole；
Step 5: carrying out second of contact hole etching, second of contact hole etching is by the forming region of the contact hole
The etching barrier layer all removes and forms the contact hole, in order to ensure that the etching barrier layer is all removed described
Secondary contact hole etching can carry out over etching to the silicon substrate, and the thickness of the etching barrier layer is less than the thickness of the interlayer film
Degree, by setting the etching barrier layer to make the over etching amount of the silicon substrate be determined completely by the thickness of the etching barrier layer
And less than the over etching amount of the silicon substrate determined by the thickness of the interlayer film, the thickness of the etching barrier layer is thinner
The over etching amount of the silicon substrate is smaller；
Step 6: titanium deposition and titanium nitride layer, the titanium and titanium nitride layer are formed at lower surface and the side of the contact hole,
Lower surface formation Titanium silicide of the metal silication reaction in the contact hole is carried out, the over etching amount of the silicon substrate is reduced
Afterwards, transversal erosion of the Titanium silicide to the bottom of the contact hole is reduced；
Step 7: being filled up completely with metal level in the contact hole.
2. the manufacture method of contact hole as claimed in claim 1, it is characterised in that：The thickness of the etching barrier layer is tens
To hundreds of angstroms, the thickness of the interlayer film is thousands of to tens thousand of angstroms.
3. the manufacture method of contact hole as claimed in claim 1, it is characterised in that：What step 7 was filled in the contact hole
Metal is tungsten.
4. the manufacture method of contact hole as claimed in claim 1 or 2, it is characterised in that：The material of the interlayer film is oxidation
Silicon, the material of the etching barrier layer is silicon nitride.
5. the manufacture method of contact hole as claimed in claim 1, it is characterised in that：The contact hole is the source of MOS transistor
Contact hole at the top of contact hole at the top of area and drain region, the polysilicon gate of the MOS transistor is also formed simultaneously.
6. the manufacture method of contact hole as claimed in claim 5, it is characterised in that：In the step of forming the MOS transistor
Also include step before step one forms the etching barrier layer：
Step 11, in the surface of silicon gate dielectric layer, polysilicon layer and hard mask layers；
Step 12, lithographic definition go out the forming region of the polysilicon gate, successively to the forming region of the polysilicon gate outside
The hard mask layers, the polysilicon layer and the gate dielectric layer are performed etching, the polysilicon layer conduct after etching
The polysilicon gate；
Step 13, the side formation side wall in the polysilicon gate；
Step 14, the hard mask layers removal by the subregion at the top of the polysilicon gate, the hard mask layers quilt
The top surface for removing the polysilicon gate in region exposes, and the bottom of the contact hole at the top of the follow-up polysilicon gate is located at institute
Hard mask layers are stated to be removed in region；
Step 15, the surface of silicon in the polysilicon gate both sides form source region and drain region；
Subsequent step one is carried out afterwards.
7. the manufacture method of contact hole as claimed in claim 6, it is characterised in that：The material of the hard mask layers is nitridation
Silicon, the material of the side wall is silicon nitride, and the material of the interlayer film is silica, and the material of the etching barrier layer is nitridation
Silicon.
8. the manufacture method of contact hole as claimed in claim 7, it is characterised in that：The gate dielectric layer is gate oxide, is adopted
Formed with thermal oxidation technology.
9. the manufacture method of contact hole as claimed in claim 6, it is characterised in that：Source region described in step 15 and with the leakage
The surface autoregistration of area respectively with the side wall of the both sides of the polysilicon gate, the source region and the drain region using source and drain from
Sub- injection technology is formed simultaneously.
10. the manufacture method of the contact hole as described in claim 6 or 9, it is characterised in that：The MOS transistor is NMOS brilliant
Body pipe, the source region and the drain region all by N+ district's groups into.
11. the manufacture method of the contact hole as described in claim 6 or 9, it is characterised in that：The MOS transistor is PMOS brilliant
Body pipe, the source region and the drain region all by P+ district's groups into.
12. the manufacture method of contact hole as claimed in claim 9, it is characterised in that：Pushed up positioned at the source region and the drain region
The contact hole in portion is all self-aligned contact hole, and the bottom size of the self-aligned contact hole is by the two neighboring polysilicon
The side wall autoregistration definition of grid.
13. the manufacture method of contact hole as claimed in claim 7, it is characterised in that：Chemical vapor deposition is used in step one
Method grows the etching barrier layer；The interlayer film is grown using chemical vapour deposition technique in step 2.
14. the manufacture method of contact hole as claimed in claim 13, it is characterised in that：Also include after the interlayer film is formed
The step of being planarized using chemical mechanical milling tech.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710248901.6A CN107093577A (en) | 2017-04-17 | 2017-04-17 | The manufacture method of contact hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710248901.6A CN107093577A (en) | 2017-04-17 | 2017-04-17 | The manufacture method of contact hole |
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Family
ID=59636990
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| CN201710248901.6A Pending CN107093577A (en) | 2017-04-17 | 2017-04-17 | The manufacture method of contact hole |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110190024A (en) * | 2019-04-15 | 2019-08-30 | 上海华力集成电路制造有限公司 | The manufacturing method of contact hole |
| CN111128871A (en) * | 2019-12-27 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Etching process method of contact hole |
| CN113224002A (en) * | 2021-04-27 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Method for manufacturing through hole |
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| CN1457087A (en) * | 2002-05-07 | 2003-11-19 | 海力士半导体有限公司 | Contact hole forming method of semiconductor component |
| CN101123208A (en) * | 2006-08-10 | 2008-02-13 | 中芯国际集成电路制造(上海)有限公司 | Forming method for contact hole |
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| CN102433546A (en) * | 2010-09-29 | 2012-05-02 | 东京毅力科创株式会社 | Film formation method and film formation apparatus |
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| CN110190024A (en) * | 2019-04-15 | 2019-08-30 | 上海华力集成电路制造有限公司 | The manufacturing method of contact hole |
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| CN113224002A (en) * | 2021-04-27 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Method for manufacturing through hole |
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