CN109950203A - The integrated manufacturing method of semiconductor devices - Google Patents
The integrated manufacturing method of semiconductor devices Download PDFInfo
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- CN109950203A CN109950203A CN201910211378.9A CN201910211378A CN109950203A CN 109950203 A CN109950203 A CN 109950203A CN 201910211378 A CN201910211378 A CN 201910211378A CN 109950203 A CN109950203 A CN 109950203A
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- polysilicon gate
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Abstract
The invention discloses a kind of integrated manufacturing methods of semiconductor devices, comprising steps of form gate oxide, polysilicon gate and side wall, polysilicon gate is divided into that top needs to form the first polysilicon gate of metal silicide and top does not need to form the second polysilicon gate of metal silicide；It forms SAB layers and is patterned；It is coated with the first coating；It carries out returning for the first coating to carve, the first coating at the top of Hui Kehou polysilicon gate is all removed；It carries out first time dry etching the top surface of the first polysilicon gate is reduced under the top surface of side wall, the top surface of the second polysilicon gate remains with SAB layers；Remove the first coating；Metal silicide is formed in the case where SAB layers of autoregistration define.The present invention can form sunk structure at the top of the first polysilicon gate and be laterally extended the horn structure to be formed so as to eliminate metal silicide and thereby improve the process window of contact hole, while being also avoided that and generating thickness loss to the second polysilicon gate and resistance is avoided to increase.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture methods, more particularly to a kind of integrated system of semiconductor devices
Make method.
Background technique
It usually requires various different desired semiconductor devices integrating progress in semiconductor integrated circuit manufacture
Manufacture, semiconductor devices are usually MOS transistor, and MOS transistor includes gate structure and source-drain area, are using polysilicon gate shape
At gate structure in, usually will form side wall, source region and drain region in the side of polysilicon gate and pass through with polysilicon gate two sides
Side wall is that autoregistration boundary progress source and drain is injected to be formed.In general, being needed to form at the top of source region and drain region and polysilicon gate
Metal silicide such as cobalt silicide (cobalt-salicide) reduces contact resistance；But the top of some polysilicon gates is simultaneously
It does not need to form metal silicide.
It therefore include the situation with the polysilicon gate for not including metal silicide in the presence of top is formed simultaneously in existing method.And
In existing method, the forming region of metal silicide generally use metal silicide stop (Salicide Block, SAB) layer into
Row autoregistration definition.
In existing method, the side wall of polysilicon gate side is usually to be formed using deposit comprehensively plus the technique autoregistration of etching
In the side of polysilicon gate, the top surface of polysilicon gate is often positioned on the top surface of side wall.On the top of polysilicon gate
Portion is formed after metal silicide, and metal silicide often forms horn structure in side coping, and this horn structure is also
It can be laterally prominent in the region on the outside of polysilicon gate.In general, the region between two adjacent polysilicon gates is source region or leakage
The forming region in area, needs to form contact hole at the top of source region and drain region, and laterally projecting horn structure can reduce contact hole
Process window namely contact hole, be unfavorable for the size reduction of device.
Metal silicide at the top of polysilicon gate forms horn structure in order to prevent, and a kind of existing manufacturing method is, in side
After wall is formed, it is coated with a layer photoresist, again photoresist carve later and the photoresist of Hui Kehou is made to be only located at polycrystalline
Region between Si-gate, the quarter of returning for carrying out polysilicon later make the top surface of each polysilicon gate fall below side coping
At the position on surface.Although this method can eliminate the horn structure formed by metal silicide at the top of polysilicon gate；But
The polysilicon gate of metal silicide is not needed to be formed for top, the thickness of polysilicon gate can reduce, this will increase polysilicon gate
Dead resistance, influence the performance of the polysilicon gate of non-metallic suicides forming region.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of integrated manufacturing methods of semiconductor devices, can need shape
Extend transverse at the top of side wall at sunk structure is formed at the top of the polysilicon gate of metal silicide so as to eliminate metal silicide
The horn structure of formation, while being also avoided that and forming sunk structure at the top for not needing to be formed the polysilicon gate of metal silicide
So as to make the dead resistance for the polysilicon gate for not needing to be formed metal silicide be maintained or reduce, connecing for device can be improved
The process window of contact hole and the performance for improving device.
In order to solve the above technical problems, the integrated manufacturing method of semiconductor devices provided by the invention includes the following steps:
It multiple is folded by gate dielectric layer and polysilicon gate Step 1: being formed simultaneously on a semiconductor substrate using identical technique
Gate structure made of adding；Side wall is formed in the side of the polysilicon gate, the top surface of the polysilicon gate is higher than described
The top surface of side wall.
The polysilicon gate is divided into top and needs to form the first polysilicon gate of metal silicide and top does not need to be formed
Second polysilicon gate of metal silicide.
Step 2: forming SAB layers, lithographic definition goes out to need to form the forming region of metal silicide and performs etching to institute
SAB layers are stated to be patterned, it is graphical after the SAB layer forming region by the metal silicide open and will described in
It is covered outside the forming region of metal silicide, the first polysilicon gate top surface exposure and second polysilicon gate top
Portion is covered with SAB layers described.
Step 3: the region between the polysilicon gate is filled up completely by the first coating of coating, first coating
And extend to the top of the polysilicon gate.
It is carved Step 4: carrying out returning for first coating, first coating of Hui Kehou is only filled with described more
Region between crystal silicon grid, first coating at the top of the polysilicon gate are all removed.
Step 5: carrying out first time dry etching, etch rate of the first time dry etching to the polysilicon gate
Greater than to SAB layers of the etch rate and greater than the etch rate to first coating, done by the first time
Method etching etches into the top surface of first polysilicon gate at the position lower than the top surface of the side wall and guarantee
The top surface for the metal silicide that the subsequent top surface in first polysilicon gate is formed is lower than the side wall
Top surface, the top surface of second polysilicon gate remains with SAB layers described after the first time dry etching is completed
And the SAB layers of the thickness requirement retained is blocked in the top surface of second polysilicon gate and forms the metal silication
Object.
Step 6: removal first coating.
Step 7: forming the metal silicide, the top of first polysilicon gate under SAB layers of autoregistration definition
The top surface of the metal silicide on portion surface is lower than the top surface of the side wall.
A further improvement is that the semiconductor substrate is silicon substrate.
A further improvement is that the material of the side wall includes silicon oxide or silicon nitride.
A further improvement is that SAB layers of the material includes silica.
A further improvement is that the metal silicide includes cobalt silicide.
A further improvement is that first coating is photoresist.
A further improvement is that removing first coating using cineration technics in step 6.
A further improvement is that first coating being coated in step 3 with a thickness of
A further improvement is that in step 5, first polysilicon gate after the first time method etching is completed
Top surface is lower than the top surface of the side wall
A further improvement is that in step 5, second polysilicon gate after the first time method etching is completed
Top surface retain the SAB layers with a thickness of
A further improvement is that semiconductor devices is MOS transistor device, the MOS transistor further includes source region and leakage
Area is formed in step 1 after the side wall and before the formation of step 2 is SAB layers described, further includes carrying out heavy doping
Source and drain injection technology forms the source region and described in the side autoregistration of the side wall of the corresponding polysilicon gate two sides
The step of drain region.
A further improvement is that further including lightly doped drain injection region, the shape in step 1 in the source region and the drain region
It further include carrying out lightly doped drain injection technology corresponding described at the polysilicon gate later and before the formation side wall
The autoregistration of polysilicon gate two sides forms the step of lightly doped drain injection region in the source region and the drain region.
A further improvement is that in step 2, it is graphical after the SAB layers by each source region and each drain region table
Face exposure；In step 7, the metal silicide is also formed in each source region and each drain region surface.
A further improvement is that further including following steps after step 7:
Contact etching stop layer is formed, interlayer film is formed, forms contact hole, top, institute in first polysilicon gate
The top for stating the top of the second polysilicon gate, the top of the source region and the drain region is all formed with the corresponding contact hole.
A further improvement is that the material of the contact etching stop layer includes silicon nitride；The material packet of the contact hole
Include tungsten.
The present invention after SAB layer pattern, is coated with first and covers using the SAB layer after graphical as autoregistration condition
Layer simultaneously carries out back quarter, carries out first time dry etching again later, using first time dry etching to SAB layers, polysilicon gate and the
Etch rate difference, that is, first time dry etching between one coating is to three kinds of material etch selections than only existing to needs to realize
The first polysilicon gate that metal silicide is formed on top performs etching and is formed the sunk structure i.e. top table of the first polysilicon gate
Face is lower than the sunk structure that the top surface of side wall is formed, and top does not need to form the second polysilicon gate of metal silicide
Top surface still remains with SAB layers, in this way after autoregistration forms metal silicide, can prevent in the first polysilicon gate
Top form the contact hole that the horn structure formed at the top of side wall and thereby raising device are extended transverse to by metal silicide
Process window；Meanwhile the thickness for being able to maintain the second polysilicon gate is not consumed, so as to make the parasitism electricity of the second polysilicon gate
Resistance is maintained or reduces, so as to improve the performance of device.
In addition, the present invention only forms sunk structure in the first polycrystalline silicon gate surface and obtains the thickness of the second polysilicon gate
The realization of holding does not need to can be realized using additional photoetching process realization using SAB layers of autoregistrations definition, therefore of the invention
Cost it is relatively low.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the flow chart of the integrated manufacturing method of semiconductor devices of the embodiment of the present invention；
Fig. 2A-Fig. 2 H is the device junction composition in each step of present invention method.
Specific embodiment
As shown in Figure 1, being the flow chart of the integrated manufacturing method of semiconductor devices of the embodiment of the present invention, such as Fig. 2A to Fig. 2 H
It is shown, it is the device junction composition in each step of present invention method, the Integrated manufacture of semiconductor devices of the embodiment of the present invention
Method includes the following steps:
Step 1: as shown in Figure 2 A, being formed simultaneously on semiconductor substrate 1 using identical technique multiple by gate dielectric layer
The gate structure being formed by stacking such as gate oxide 3 and polysilicon gate；Side wall 5 is formed in the side of the polysilicon gate, it is described more
The top surface of crystal silicon grid is higher than the top surface of the side wall 5.In general, it is different according to the type of the semiconductor devices,
The surface of the semiconductor substrate 1 is also formed with the well region 2 of different doping types；For example, for N-type semiconductor device, it is described
Well region 2 is p-type doping；For P-type semiconductor device, the well region 2 is n-type doping.
The polysilicon gate is divided into top and needs to form the first polysilicon gate 4a of metal silicide 8 and top does not need shape
At the second polysilicon gate 4b of metal silicide 8.
The semiconductor substrate 1 is silicon substrate.
The material of the side wall 5 includes silicon oxide or silicon nitride.
Semiconductor devices is MOS transistor device, and the MOS transistor further includes source region and drain region, the shape in step 1
It further include the source and drain injection technology for carrying out heavy doping later and before the formation SAB layer 6 of step 2 at the side wall 5
In the step of side autoregistration of the side wall 5 of the corresponding polysilicon gate two sides forms the source region and the drain region.
Further include lightly doped drain injection region in the source region and the drain region, formed in step 1 the polysilicon gate it
It afterwards and is formed before the side wall 5, further includes carrying out lightly doped drain injection technology in the corresponding polysilicon gate two sides
Autoregistration forms the step of lightly doped drain injection region in the source region and the drain region.
Step 2: as shown in Figure 2 A, forming SAB layer 6.The material of the SAB layer 6 includes silica.
Lithographic definition, which goes out to need to form the forming region of metal silicide 8 and performs etching, carries out figure to the SAB layer 6
Change, it is graphical after the SAB layer 6 by the forming region opening of the metal silicide 8 and by the metal silicide 8
It covers outside forming region, is covered at the top of the first polysilicon gate 4a top surface exposure and the second polysilicon gate 4b
The SAB layer 6.
The SAB layer 6 after graphical exposes each source region and each drain region surface.
Step 3: as shown in Figure 2 A, being coated with the first coating 7, first coating 7 will be between the polysilicon gate
Region is filled up completely and extends to the top of the polysilicon gate.
First coating 7 is photoresist.Coating first coating 7 with a thickness of
Step 4: as shown in Figure 2 B, carrying out returning for first coating 7 and carving, first coating 7 of Hui Kehou is only
It is filled in the region between the polysilicon gate, first coating 7 at the top of the polysilicon gate is all removed.
Step 5: as shown in Figure 2 C, carrying out first time dry etching, the first time dry etching is to the polysilicon gate
Etch rate be greater than to the etch rate of the SAB layer 6 and greater than the etch rate to first coating 7, pass through
The top surface of the first polysilicon gate 4a is etched into the top surface lower than the side wall 5 by the first time dry etching
Position at and guarantee the top table of the metal silicide 8 that the subsequent top surface in the first polysilicon gate 4a is formed
Face can generate a sunk structure lower than the top surface of the side wall 5, as shown in virtual coil 101.The first time method is carved
The top surface of the first polysilicon gate 4a is lower than the top surface of the side wall 5 after erosion is completed
The top surface of the second polysilicon gate 4b remains with SAB layers described after the first time dry etching is completed
6 and the thickness requirement of the SAB layer 6 that is retained be blocked in the top surface of the second polysilicon gate 4b and form the metal
Silicide 8.The top surface of the second polysilicon gate 4b retains after the first time method etching is completed the SAB layers
6 with a thickness ofIt is found that the holding that the thickness of the second polysilicon gate 4b obtains as shown in virtual coil 102,
Top surface is still higher than the top surface of the side wall, this meeting so that the resistance of the second polysilicon gate 4b be able to maintain it is lower
Value.
Step 6: as shown in Figure 2 D, removing first coating 7.
First coating 7 is removed using cineration technics.
Step 7: as shown in Figure 2 D, form the metal silicide 8 in the case where 6 autoregistration of SAB layer defines, described the
The top surface of the metal silicide 8 of the top surface of one polysilicon gate 4a is lower than the top surface of the side wall 5.
The metal silicide 8 includes cobalt silicide.
The metal silicide 8 is also formed in each source region and each drain region surface.
Further include following steps:
As shown in Figure 2 E, contact etching stop layer 9 is formed.The material of the contact etching stop layer 9 includes silicon nitride.This
In inventive embodiments method, can are as follows: the contact etching stop layer 9 with a thickness ofLeft and right.
As shown in Figure 2 F, interlayer film 10 is formed；It, can are as follows: interlayer film 10 includes in present invention methodIt is left
Oxide layer that right high-density plasma (HDP) technique is formed andThe oxidation that the TEOS SACVD technique of left and right is formed
Layer.It needs to be planarized using chemical mechanical milling tech later.
As shown in Figure 2 G, the opening 11a of contact hole 11 is formed；As illustrated in figure 2h, metal layer is filled in the opening 11a
Form the contact hole 11.In the top of the first polysilicon gate 4a, the top of the second polysilicon gate 4b, the source region
Top and the top in the drain region be all formed with the corresponding contact hole.The material of the contact hole includes tungsten.
The embodiment of the present invention is used as autoregistration condition using the SAB layer 6 after graphical, SAB layer 6 graphically after, be coated with
First coating 7 simultaneously carries out back carving, and carries out first time dry etching again later, using first time dry etching to SAB layer 6, more
Etch rate difference, that is, first time dry etching between crystal silicon grid and the first coating 7 realizes three kinds of material etch selection ratios
Needs are performed etching in the first polysilicon gate 4a that metal silicide 8 is formed on top only and form sunk structure i.e. the first polycrystalline
The top surface of Si-gate 4a is lower than the sunk structure that the top surface of side wall 5 is formed, and top does not need to form metal silicide 8
The top surface of the second polysilicon gate 4b still remain with SAB layer 6, in this way after autoregistration forms metal silicide 8, energy
It enough prevents from being formed at the top of the first polysilicon gate 4a and extends transverse to the wedge angle knot formed at the top of side wall 5 by metal silicide 8
The process window of the contact hole of structure and thereby raising device；Meanwhile the thickness for being able to maintain the second polysilicon gate 4b is not consumed, from
And the dead resistance of the second polysilicon gate 4b can be made to be maintained or reduce, so as to improve the performance of device.
In addition, the embodiment of the present invention only forms sunk structure on the first surface polysilicon gate 4a and makes the second polysilicon gate 4b
The realization that is maintained of thickness do not need to realize using additional photoetching process, being defined using 6 autoregistration of SAB layer can be real
It is existing, therefore cost of the invention is relatively low.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of integrated manufacturing method of semiconductor devices, which comprises the steps of:
Step 1: using identical technique be formed simultaneously on a semiconductor substrate it is multiple by gate dielectric layer and polysilicon gate superposition and
At gate structure；Side wall is formed in the side of the polysilicon gate, the top surface of the polysilicon gate is higher than the side wall
Top surface；
The polysilicon gate is divided into top and needs to form the first polysilicon gate of metal silicide and top does not need to form metal
Second polysilicon gate of silicide；
Step 2: forming SAB layers, lithographic definition goes out to need to form the forming region of metal silicide and performs etching to described
SAB layers are patterned, it is graphical after the SAB layer by the forming region opening of the metal silicide and by the gold
Belong to and being covered outside the forming region of silicide, at the top of the first polysilicon gate top surface exposure and second polysilicon gate
It is covered with SAB layers described；
Step 3: the region between the polysilicon gate is filled up completely and is prolonged by the first coating of coating, first coating
Reach the top of the polysilicon gate；
It is carved Step 4: carrying out returning for first coating, first coating of Hui Kehou is only filled in the polysilicon
Region between grid, first coating at the top of the polysilicon gate are all removed；
Step 5: carrying out first time dry etching, the first time dry etching is greater than the etch rate of the polysilicon gate
To SAB layers of the etch rate and greater than the etch rate to first coating, carved by the first time dry method
Erosion by the top surface of first polysilicon gate etch into lower than at the position of the top surface of the side wall and guarantee it is subsequent
It is lower than the side coping in the top surface for the metal silicide that the top surface of first polysilicon gate is formed
Surface, the top surface of second polysilicon gate remains with described SAB layers and institute after the first time dry etching is completed
The top surface that the SAB layers of the thickness requirement retained is blocked in second polysilicon gate forms the metal silicide；
Step 6: removal first coating；
Step 7: forming the metal silicide, the top table of first polysilicon gate under SAB layers of autoregistration definition
The top surface of the metal silicide in face is lower than the top surface of the side wall.
2. the integrated manufacturing method of semiconductor devices as described in claim 1, it is characterised in that: the semiconductor substrate is silicon
Substrate.
3. the integrated manufacturing method of semiconductor devices as claimed in claim 2, it is characterised in that: the material of the side wall includes
Silicon oxide or silicon nitride.
4. the integrated manufacturing method of semiconductor devices as claimed in claim 2, it is characterised in that: described SAB layers of material packet
Include silica.
5. the integrated manufacturing method of semiconductor devices as claimed in claim 2, it is characterised in that: the metal silicide includes
Cobalt silicide.
6. the integrated manufacturing method of semiconductor devices as claimed in claim 2, it is characterised in that: first coating is light
Photoresist.
7. the integrated manufacturing method of semiconductor devices as claimed in claim 6, it is characterised in that: using grey chemical industry in step 6
Skill removes first coating.
8. the integrated manufacturing method of semiconductor devices as claimed in claim 6, it is characterised in that: what is be coated in step 3 is described
First coating with a thickness of
9. the integrated manufacturing method of semiconductor devices as described in claim 1, it is characterised in that: in step 5, described first
The top surface of first polysilicon gate is lower than the top surface of the side wall after secondary method etching is completed
10. the integrated manufacturing method of semiconductor devices as described in claim 1, it is characterised in that: in step 5, described first
The top surface of second polysilicon gate retains after secondary method etching is completed the SAB layers with a thickness of
11. the integrated manufacturing method of semiconductor devices as described in claim 1, it is characterised in that: semiconductor devices is MOS brilliant
Body tube device, the MOS transistor further include source region and drain region, are formed after the side wall in step 1 and step 2
Formed it is SAB layers described before, further include carry out heavy doping source and drain injection technology the corresponding polysilicon gate two sides institute
State the step of side autoregistration of side wall forms the source region and the drain region.
12. the integrated manufacturing method of semiconductor devices as claimed in claim 11, it is characterised in that: the source region and the leakage
Further include lightly doped drain injection region in area, formed after the polysilicon gate and formed before the side wall in step 1,
It further include carrying out lightly doped drain injection technology to form the source region and described in corresponding polysilicon gate two sides autoregistration
The step of lightly doped drain injection region in drain region.
13. the integrated manufacturing method of semiconductor devices as claimed in claim 11, it is characterised in that: in step 2, graphically
The SAB layers afterwards expose each source region and each drain region surface；In step 7, in each source region and each leakage
Area surface is also formed with the metal silicide.
14. the integrated manufacturing method of semiconductor devices as claimed in claim 13, which is characterized in that after step 7, also wrap
Include following steps:
Form contact etching stop layer, form interlayer film, form contact hole, first polysilicon gate top, described the
The top at the top of two polysilicon gates, the top of the source region and the drain region is all formed with the corresponding contact hole.
15. the integrated manufacturing method of semiconductor devices as claimed in claim 14, it is characterised in that:
The material of the contact etching stop layer includes silicon nitride；
The material of the contact hole includes tungsten.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113809004A (en) * | 2021-09-17 | 2021-12-17 | 恒烁半导体(合肥)股份有限公司 | Manufacturing method, circuit and application of memory |
| CN116435275A (en) * | 2023-06-09 | 2023-07-14 | 粤芯半导体技术股份有限公司 | Semiconductor structure and preparation method thereof |
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