CN109950203B - Integrated manufacturing method of semiconductor device - Google Patents
Integrated manufacturing method of semiconductor device Download PDFInfo
- Publication number
- CN109950203B CN109950203B CN201910211378.9A CN201910211378A CN109950203B CN 109950203 B CN109950203 B CN 109950203B CN 201910211378 A CN201910211378 A CN 201910211378A CN 109950203 B CN109950203 B CN 109950203B
- Authority
- CN
- China
- Prior art keywords
- polysilicon gate
- metal silicide
- top surface
- semiconductor device
- integrated manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses an integrated manufacturing method of a semiconductor device, which comprises the following steps: forming a gate oxide layer, a polysilicon gate and a side wall, wherein the polysilicon gate is divided into a first polysilicon gate of which the top is required to form metal silicide and a second polysilicon gate of which the top is not required to form metal silicide; forming an SAB layer and patterning; coating a first covering layer; carrying out back etching on the first covering layer, and removing the first covering layer on the top of the polysilicon gate after the back etching; carrying out first dry etching to lower the top surface of the first polysilicon gate to be below the top surface of the side wall, wherein an SAB layer is reserved on the top surface of the second polysilicon gate; removing the first covering layer; and forming metal silicide under the SAB layer self-alignment definition. The invention can form a concave structure at the top of the first polysilicon gate, thereby eliminating a sharp-angled structure formed by the transverse extension of metal silicide, improving the process window of the contact hole, avoiding the thickness loss of the second polysilicon gate and avoiding the increase of resistance.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for integrally manufacturing a semiconductor device.
Background
In the manufacture of semiconductor integrated circuits, semiconductor devices with various requirements are generally required to be integrated together for manufacture, the semiconductor devices are generally MOS transistors, each MOS transistor comprises a gate structure and a source drain region, in the gate structure formed by using a polysilicon gate, side walls are generally formed on the side surfaces of the polysilicon gate, and the source drain region and the drain source region are formed by performing source drain injection by using the side walls on the two sides of the polysilicon gate as self-aligned boundaries. Generally, a metal silicide such as cobalt silicide (cobalt-silicide) needs to be formed on the top of the source and drain regions and the polysilicon gate to reduce contact resistance; some polysilicon gates do not require the formation of a metal suicide on top.
There are cases in the prior art methods where polysilicon gates are formed with and without metal silicide on top. In the conventional method, the formation region of the metal silicide is usually self-aligned defined by using a metal silicide Block (SAB) layer.
In the existing method, the sidewall of the side of the polysilicon gate is usually formed on the side of the polysilicon gate in a self-aligned manner by adopting a full deposition and etching process, and the top surface of the polysilicon gate is often located on the top surface of the sidewall. After the metal silicide is formed on top of the polysilicon gate, the metal silicide tends to form a pointed structure on top of the sidewalls, which also projects laterally into the region outside the polysilicon gate. Generally, the region between two adjacent polysilicon gates is a formation region of a source region or a drain region, contact holes need to be formed at the tops of the source region and the drain region, and the laterally protruding sharp-angled structures can reduce process windows of the contact holes, namely the contact holes, which is not beneficial to size reduction of devices.
In order to prevent the metal silicide on the top of the polysilicon gates from forming a sharp corner structure, a conventional manufacturing method includes coating a layer of photoresist after the sidewalls are formed, then performing a back etching on the photoresist and making the back etched photoresist only in the region between the polysilicon gates, and then performing a back etching on the polysilicon to lower the top surface of each polysilicon gate to a position lower than the top surface of the sidewalls. The method can eliminate the sharp-angled structure formed by metal silicide on the top of the polysilicon gate; however, for a polysilicon gate that does not need to have a metal silicide formed on the top, the thickness of the polysilicon gate may be reduced, which may increase the parasitic resistance of the polysilicon gate and affect the performance of the polysilicon gate in the non-metal silicide forming region.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an integrated manufacturing method of a semiconductor device, which can form a concave structure at the top of a polysilicon gate needing to form metal silicide so as to eliminate a sharp corner structure formed by the metal silicide transversely extending to the top of a side wall, and can avoid forming a concave structure at the top of the polysilicon gate not needing to form the metal silicide so as to keep or reduce the parasitic resistance of the polysilicon gate not needing to form the metal silicide, improve the process window of a contact hole of the device and improve the performance of the device.
In order to solve the above technical problem, the integrated manufacturing method of the semiconductor device provided by the present invention comprises the following steps:
step one, simultaneously forming a plurality of grid electrode structures formed by overlapping grid dielectric layers and polysilicon grids on a semiconductor substrate by adopting the same process; and forming a side wall on the side surface of the polysilicon gate, wherein the top surface of the polysilicon gate is higher than that of the side wall.
The polysilicon gate is divided into a first polysilicon gate of which the top is required to form metal silicide and a second polysilicon gate of which the top is not required to form metal silicide.
Step two, forming an SAB layer, defining a forming area needing to form metal silicide by photoetching, etching to pattern the SAB layer, opening the forming area of the metal silicide by the patterned SAB layer, covering the forming area of the metal silicide, and exposing the top surface of the first polysilicon gate and covering the top of the second polysilicon gate with the SAB layer.
And step three, coating a first covering layer, wherein the first covering layer completely fills the region between the polysilicon gates and extends to the top of the polysilicon gates.
And fourthly, carrying out back-etching on the first covering layer, wherein the first covering layer after back-etching is only filled in the area between the polysilicon gates, and the first covering layer on the top of the polysilicon gates is removed.
And fifthly, carrying out first dry etching, wherein the etching rate of the first dry etching to the polysilicon gate is greater than the etching rate to the SAB layer and greater than the etching rate to the first covering layer, etching the top surface of the first polysilicon gate to a position lower than the top surface of the side wall through the first dry etching, ensuring that the top surface of the metal silicide formed on the top surface of the first polysilicon gate is lower than the top surface of the side wall subsequently, and after the first dry etching is finished, the SAB layer is reserved on the top surface of the second polysilicon gate and the reserved thickness of the SAB layer requires to block the metal silicide formed on the top surface of the second polysilicon gate.
And sixthly, removing the first covering layer.
And seventhly, forming the metal silicide under the SAB layer self-alignment definition, wherein the top surface of the metal silicide on the top surface of the first polysilicon gate is lower than the top surface of the side wall.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, the material of the sidewall comprises silicon oxide or silicon nitride.
In a further refinement, the material of the SAB layer comprises silicon oxide.
In a further refinement, the metal silicide comprises a cobalt silicide.
In a further improvement, the first capping layer is a photoresist.
In a further improvement, in the sixth step, an ashing process is used to remove the first capping layer.
In a further improvement, the thickness of the first cover layer applied in step three is
In a further improvement, in step five, after the first etching, the top surface of the first polysilicon gate is lower than the top surface of the side wall
In a fifth step, the thickness of the SAB layer remaining on the top surface of the second polysilicon gate after the first etching is completed is set to
The semiconductor device is further improved to be an MOS transistor device, the MOS transistor further comprises a source region and a drain region, and after the side wall is formed in the first step and before the SAB layer is formed in the second step, the method further comprises the step of performing a heavily doped source-drain injection process to form the source region and the drain region in a self-alignment mode on the side faces of the side walls on the two sides of the corresponding polysilicon gate.
The source region and the drain region further comprise lightly doped drain injection regions, and after the polysilicon gate is formed in the first step and before the side walls are formed, the method further comprises the step of performing a lightly doped drain injection process to form the lightly doped drain injection regions of the source region and the drain region on two corresponding side faces of the polysilicon gate in a self-alignment manner.
In a further improvement, in the second step, the patterned SAB layer exposes the surface of each of the source regions and each of the drain regions; and seventhly, forming the metal silicide on the surfaces of the source regions and the drain regions.
The further improvement is that after the seventh step, the method further comprises the following steps:
and forming a contact etching stop layer, forming an interlayer film, forming contact holes, and forming the corresponding contact holes on the top of the first polysilicon gate, the top of the second polysilicon gate, the top of the source region and the top of the drain region.
In a further improvement, the material of the contact etch stop layer comprises silicon nitride; the material of the contact hole comprises tungsten.
The invention uses the SAB layer after being patterned as a self-alignment condition, after the SAB layer is patterned, coating a first covering layer and carrying out back etching, then carrying out first dry etching, and utilizing the etching rate difference among the SAB layer, the polysilicon gate and the first covering layer, namely the etching selection ratio of the first dry etching to the three materials to realize that only the first polysilicon gate which needs to form metal silicide at the top is etched and a concave structure is formed, namely the concave structure formed by the top surface of the first polysilicon gate lower than the top surface of the side wall, while the top surface of the second polysilicon gate on top of which no metal silicide needs to be formed still remains with the SAB layer, therefore, after the metal silicide is formed in a self-alignment mode, a sharp-angled structure formed by the fact that the metal silicide transversely extends to the top of the side wall can be prevented from being formed on the top of the first polysilicon gate, and therefore a process window of a contact hole of a device is improved; meanwhile, the thickness of the second polysilicon gate can be kept from being consumed, so that the parasitic resistance of the second polysilicon gate can be kept or reduced, and the performance of the device can be improved.
In addition, the invention only forms a concave structure on the surface of the first polysilicon gate to keep the thickness of the second polysilicon gate without adopting an additional photoetching process, and can be realized by adopting SAB layer self-alignment definition, so the cost of the invention is lower.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a flowchart of an integrated manufacturing method of a semiconductor device according to an embodiment of the present invention;
fig. 2A-2H are device structure diagrams in steps of a method according to an embodiment of the invention.
Detailed Description
Fig. 1 is a flowchart of an integrated manufacturing method of a semiconductor device according to an embodiment of the present invention, and fig. 2A to 2H are device structure diagrams in steps of the method according to the embodiment of the present invention, and the integrated manufacturing method of a semiconductor device according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 2A, a plurality of gate structures formed by overlapping gate dielectric layers such as a gate oxide layer 3 and a polysilicon gate are simultaneously formed on a semiconductor substrate 1 by adopting the same process; and forming a side wall 5 on the side surface of the polysilicon gate, wherein the top surface of the polysilicon gate is higher than that of the side wall 5. Generally, according to different types of the semiconductor devices, well regions 2 with different doping types are further formed on the surface of the semiconductor substrate 1; for example, for an N-type semiconductor device, the well region 2 is P-type doped; for a P-type semiconductor device, the well region 2 is doped N-type.
The polysilicon gate is divided into a first polysilicon gate 4a on top of which the metal silicide 8 needs to be formed and a second polysilicon gate 4b on top of which the metal silicide 8 does not need to be formed.
The semiconductor substrate 1 is a silicon substrate.
The material of the side wall 5 comprises silicon oxide or silicon nitride.
The semiconductor device is an MOS transistor device, the MOS transistor further comprises a source region and a drain region, and after the side wall 5 is formed in the first step and before the SAB layer 6 is formed in the second step, the method further comprises the step of performing a heavily doped source-drain injection process to form the source region and the drain region in a self-alignment mode on the side faces of the side wall 5 on the two sides of the corresponding polysilicon gate.
And the source region and the drain region also comprise lightly doped drain injection regions, and the lightly doped drain injection process is carried out after the polysilicon gate is formed in the first step and before the side walls 5 are formed, so that the lightly doped drain injection regions of the source region and the drain region are formed on the two corresponding side surfaces of the polysilicon gate in a self-alignment manner.
Step two, as shown in fig. 2A, an SAB layer 6 is formed. The material of the SAB layer 6 comprises silicon oxide.
Defining a forming area needing to form the metal silicide 8 by photoetching, etching and patterning the SAB layer 6, wherein the patterned SAB layer 6 opens the forming area of the metal silicide 8 and covers the outside of the forming area of the metal silicide 8, the top surface of the first polysilicon gate 4a is exposed, and the top of the second polysilicon gate 4b is covered with the SAB layer 6.
The patterned SAB layer 6 exposes the surface of each source region and each drain region.
And thirdly, as shown in fig. 2A, coating a first covering layer 7, wherein the first covering layer 7 completely fills the region between the polysilicon gates and extends to the top of the polysilicon gates.
The first cover layer 7 is photoresist. The thickness of the first cover layer 7 applied is
Step four, as shown in fig. 2B, performing a back etching on the first capping layer 7, wherein the first capping layer 7 after the back etching is only filled in the region between the polysilicon gates, and all the first capping layer 7 on the top of the polysilicon gates are removed.
Step five, as shown in fig. 2C, performing a first dry etching, wherein the etching rate of the first dry etching to the polysilicon gate is greater than the etching rate to the SAB layer 6 and greater than the etching rate to the first cover layer 7, and the top surface of the first polysilicon gate 4a is etched to a low level by the first dry etchingA recess structure is formed at the top surface of the sidewall 5 and the top surface of the metal silicide 8 formed on the top surface of the first polysilicon gate 4a is lower than the top surface of the sidewall 5, as shown by the dotted line 101. After the first etching method is completed, the top surface of the first polysilicon gate 4a is lower than the top surface of the side wall 5
The SAB layer 6 is remained on the top surface of the second polysilicon gate 4b after the first dry etching is completed, and the thickness of the remained SAB layer 6 is required to block the formation of the metal silicide 8 on the top surface of the second polysilicon gate 4 b. The thickness of the SAB layer 6 remained on the top surface of the second polysilicon gate 4b after the first etching is finished is as follows
As indicated by the dotted circle 102, the thickness of the second polysilicon gate 4b is maintained, and the top surface thereof is still higher than the top surface of the sidewall, which enables the resistance of the second polysilicon gate 4b to be kept low.
Step six, as shown in fig. 2D, the first cover layer 7 is removed.
The first capping layer 7 is removed using an ashing process.
Seventhly, as shown in fig. 2D, the metal silicide 8 is formed under the self-aligned definition of the SAB layer 6, and the top surface of the metal silicide 8 on the top surface of the first polysilicon gate 4a is lower than the top surface of the sidewall 5.
The metal silicide 8 comprises cobalt silicide.
The metal silicide 8 is also formed on the surface of each of the source regions and the drain regions.
Also comprises the following steps:
as shown in fig. 2E, a contact etch stop layer 9 is formed. The material of the contact etch stop layer 9 comprises silicon nitride. In the method of the embodiment of the present invention,can be as follows: the contact etch stop layer 9 has a thickness of
Left and right.
As shown in fig. 2F, an interlayer film 10 is formed; in the method of the embodiment of the invention, the method can be as follows: the interlayer film 10 comprises
Oxide layer formed by High Density Plasma (HDP) process and
and the left and right oxide layers are formed by a TEOS SACVD process. And then, a chemical mechanical polishing process is needed for planarization.
As shown in fig. 2G, an opening 11a of the contact hole 11 is formed; as shown in fig. 2H, the opening 11a is filled with a metal layer to form the contact hole 11. And the corresponding contact holes are formed at the top of the first polysilicon gate 4a, the top of the second polysilicon gate 4b, the top of the source region and the top of the drain region. The material of the contact hole comprises tungsten.
In the embodiment of the invention, the patterned SAB layer 6 is used as a self-alignment condition, after the SAB layer 6 is patterned, the first covering layer 7 is coated and etched back, then the first dry etching is carried out, the etching rate difference among the SAB layer 6, the polysilicon gate and the first covering layer 7, namely the etching selection ratio of the first dry etching to the three materials is utilized for the first dry etching, only the first polysilicon gate 4a needing to form the metal silicide 8 at the top is etched and a concave structure is formed, namely the concave structure is formed on the top surface of the first polysilicon gate 4a and is lower than the top surface of the side wall 5, and the SAB layer 6 is still remained on the top surface of the second polysilicon gate 4b without forming the metal silicide 8 at the top, so that after the metal silicide 8 is formed in a self-alignment manner, the formation of a side wall structure formed by transversely extending the metal silicide 8 to the top of the contact hole 5 at the top of the first polysilicon gate 4a can be prevented, and the sharp-angled corner of the device is improved A process window; meanwhile, the thickness of the second polysilicon gate 4b can be kept from being consumed, so that the parasitic resistance of the second polysilicon gate 4b can be kept or reduced, and the performance of the device can be improved.
In addition, in the embodiment of the invention, the thickness of the second polysilicon gate 4b is maintained only by forming the recessed structure on the surface of the first polysilicon gate 4a without using an additional photolithography process, and the SAB layer 6 is self-aligned and defined, so that the cost of the invention is low.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. An integrated manufacturing method of a semiconductor device, comprising the steps of:
step one, simultaneously forming a plurality of grid electrode structures formed by overlapping grid dielectric layers and polysilicon grids on a semiconductor substrate by adopting the same process; forming a side wall on the side surface of the polysilicon gate, wherein the top surface of the polysilicon gate is higher than the top surface of the side wall;
the polysilicon gate is divided into a first polysilicon gate of which the top is required to form metal silicide and a second polysilicon gate of which the top is not required to form metal silicide;
step two, forming a metal silicide barrier layer, defining a forming area needing to form metal silicide by photoetching, etching to pattern the metal silicide barrier layer, opening the forming area of the metal silicide by the patterned metal silicide barrier layer and covering the forming area of the metal silicide, wherein the surface of the top of the first polysilicon gate is exposed, and the top of the second polysilicon gate is covered by the metal silicide barrier layer;
coating a first covering layer, wherein the first covering layer completely fills the region between the polysilicon gates and extends to the top of the polysilicon gates;
fourthly, carrying out back-etching on the first covering layer, wherein the first covering layer after back-etching is only filled in the area between the polysilicon gates, and the first covering layer on the top of the polysilicon gates is removed;
fifthly, performing first dry etching, wherein the etching rate of the first dry etching to the polysilicon gate is greater than the etching rate to the metal silicide barrier layer and greater than the etching rate to the first covering layer, the top surface of the first polysilicon gate is etched to a position lower than the top surface of the side wall through the first dry etching, the top surface of the metal silicide formed on the top surface of the first polysilicon gate in the follow-up process is ensured to be lower than the top surface of the side wall, the metal silicide barrier layer is reserved on the top surface of the second polysilicon gate after the first dry etching is completed, and the reserved thickness of the metal silicide barrier layer requires to prevent the metal silicide from being formed on the top surface of the second polysilicon gate;
sixthly, removing the first covering layer;
and seventhly, forming the metal silicide under the self-alignment definition of the metal silicide barrier layer, wherein the top surface of the metal silicide on the top surface of the first polysilicon gate is lower than the top surface of the side wall.
2. An integrated manufacturing method of a semiconductor device according to claim 1, characterized in that: the semiconductor substrate is a silicon substrate.
3. An integrated manufacturing method of a semiconductor device according to claim 2, characterized in that: the material of the side wall comprises silicon oxide or silicon nitride.
4. An integrated manufacturing method of a semiconductor device according to claim 2, characterized in that: the material of the metal silicide barrier layer comprises silicon oxide.
5. An integrated manufacturing method of a semiconductor device according to claim 2, characterized in that: the metal silicide comprises cobalt silicide.
6. An integrated manufacturing method of a semiconductor device according to claim 2, characterized in that: the first covering layer is photoresist.
7. An integrated manufacturing method of a semiconductor device according to claim 6, characterized in that: and sixthly, removing the first covering layer by adopting an ashing process.
8. An integrated manufacturing method of a semiconductor device according to claim 6, characterized in that: the thickness of the first covering layer coated in the step three is
9. An integrated manufacturing method of a semiconductor device according to claim 1, characterized in that: in step five, the top surface of the first polysilicon gate after the first dry etching is lower than the top surface of the side wall
10. An integrated manufacturing method of a semiconductor device according to claim 1, characterized in that: in step five, the thickness of the metal silicide barrier layer reserved on the top surface of the second polysilicon gate after the first dry etching is equal to
11. An integrated manufacturing method of a semiconductor device according to claim 1, characterized in that: the semiconductor device is an MOS transistor device, the MOS transistor further comprises a source region and a drain region, and after the side wall is formed in the first step and before the metal silicide barrier layer is formed in the second step, the method further comprises the step of performing a heavily doped source-drain injection process to form the source region and the drain region in a self-alignment mode on the side faces of the side wall on the two sides of the corresponding polysilicon gate.
12. An integrated manufacturing method of a semiconductor device according to claim 11, characterized in that: and the source region and the drain region also comprise lightly doped drain injection regions, and the lightly doped drain injection process is carried out after the polysilicon gate is formed in the step one and before the side walls are formed, so that the lightly doped drain injection regions of the source region and the drain region are formed on the two corresponding side surfaces of the polysilicon gate in a self-aligning manner.
13. An integrated manufacturing method of a semiconductor device according to claim 11, characterized in that: in the second step, the patterned metal silicide barrier layer exposes the surfaces of the source regions and the drain regions; and seventhly, forming the metal silicide on the surfaces of the source regions and the drain regions.
14. An integrated manufacturing method of a semiconductor device according to claim 13, further comprising, after the seventh step, the steps of:
and forming a contact etching stop layer, forming an interlayer film, forming contact holes, and forming the corresponding contact holes on the top of the first polysilicon gate, the top of the second polysilicon gate, the top of the source region and the top of the drain region.
15. An integrated manufacturing method of a semiconductor device according to claim 14, wherein:
the material of the contact etching stop layer comprises silicon nitride;
the material of the contact hole comprises tungsten.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910211378.9A CN109950203B (en) | 2019-03-20 | 2019-03-20 | Integrated manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910211378.9A CN109950203B (en) | 2019-03-20 | 2019-03-20 | Integrated manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109950203A CN109950203A (en) | 2019-06-28 |
| CN109950203B true CN109950203B (en) | 2020-11-24 |
Family
ID=67010948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910211378.9A Active CN109950203B (en) | 2019-03-20 | 2019-03-20 | Integrated manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109950203B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113809004A (en) * | 2021-09-17 | 2021-12-17 | 恒烁半导体(合肥)股份有限公司 | Manufacturing method, circuit and application of memory |
| CN116435275A (en) * | 2023-06-09 | 2023-07-14 | 粤芯半导体技术股份有限公司 | Semiconductor structure and preparation method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101226962B (en) * | 2008-02-22 | 2013-07-17 | 苏州赛芯电子科技有限公司 | HVMOS and semiconductor device integrating HVMOS and CMOS |
| CN104124209B (en) * | 2013-04-27 | 2017-02-15 | 上海华虹宏力半导体制造有限公司 | CMOS device manufacturing method |
| CN104617044B (en) * | 2013-11-05 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and preparation method thereof |
| CN107994065B (en) * | 2016-10-27 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
-
2019
- 2019-03-20 CN CN201910211378.9A patent/CN109950203B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109950203A (en) | 2019-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9397004B2 (en) | Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings | |
| US20170222018A1 (en) | Self-aligned bottom up gate contact and top down source-drain contact structure in the premetallization dielectric or interlevel dielectric layer of an integrated circuit | |
| CN104835838A (en) | Gate structures with various widths and method for forming same | |
| JP2008034865A (en) | Method of fabricating semiconductor device | |
| US20090114991A1 (en) | Semiconductor devices having a contact structure and methods of fabricating the same | |
| US11545493B2 (en) | Memory devices and methods of fabricating the same | |
| US20080079071A1 (en) | Semiconductor device for preventing reciprocal influence between neighboring gates and method for manufacturing the same | |
| US9263321B2 (en) | Semiconductor device and manufacturing method thereof | |
| US11742414B2 (en) | Semiconductor device with fins | |
| CN111463215B (en) | Memory structure and manufacturing method thereof | |
| TW202029339A (en) | Structure and mehtod for interconnect with self-alignment | |
| US7348254B2 (en) | Method of fabricating fin field-effect transistors | |
| CN109950203B (en) | Integrated manufacturing method of semiconductor device | |
| US8487397B2 (en) | Method for forming self-aligned contact | |
| US10811304B2 (en) | Increased isolation of diffusion breaks in FinFET devices using an angled etch | |
| KR101095739B1 (en) | Semiconductor device and method for forming the same | |
| CN107369621B (en) | Fin field effect transistor and forming method thereof | |
| US8809941B2 (en) | Semiconductor device and method for fabricating the same | |
| CN110571187B (en) | Method for manufacturing semiconductor device | |
| KR100924880B1 (en) | Method for manufacturing sidewall spacer of semiconductor device | |
| KR100586553B1 (en) | Gate of semiconductor device and method thereof | |
| US11527409B2 (en) | Contact slots forming method applying photoresists | |
| US6468919B2 (en) | Method of making a local interconnect in an embedded memory | |
| US20230135946A1 (en) | Self-Aligned Gate Contact Fin Field Effect Transistor and Method for Manufacturing the Same | |
| CN110970299B (en) | Semiconductor device and method of forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |