CN116435275A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN116435275A CN116435275A CN202310678208.8A CN202310678208A CN116435275A CN 116435275 A CN116435275 A CN 116435275A CN 202310678208 A CN202310678208 A CN 202310678208A CN 116435275 A CN116435275 A CN 116435275A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 105
- 238000002955 isolation Methods 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000010410 layer Substances 0.000 claims description 268
- 239000011229 interlayer Substances 0.000 claims description 89
- 238000000034 method Methods 0.000 claims description 57
- 239000003989 dielectric material Substances 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 229910021332 silicide Inorganic materials 0.000 claims description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 230000010354 integration Effects 0.000 abstract description 7
- 238000001259 photo etching Methods 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000007769 metal material Substances 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 238000005530 etching Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000001459 lithography Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
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- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
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- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000005389 semiconductor device fabrication Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure includes: a substrate; the grid structure is positioned on the substrate; the gate structure includes: grid, insulating isolation side wall and conductive side wall; the grid electrode comprises a grid dielectric layer and a grid electrode conducting layer; the gate dielectric layer is positioned on the upper surface of the substrate; the grid electrode conducting layer is positioned on the upper surface of the grid dielectric layer; the insulating isolation side walls are positioned on the side wall surfaces of the two opposite sides of the grid electrode; the conductive side wall is positioned on the surface of the insulating isolation side wall, which is far away from the grid electrode; the source region is positioned in the substrate, positioned on one side of the grid electrode and contacted with the conductive side wall; the drain region is positioned in the substrate, is positioned at one side of the grid electrode far away from the source region, and is contacted with the conductive side wall. The conductive side wall can be directly contacted with the source region and the drain region and the conductive side wall, and the interconnection of the bottom device and the upper metal is realized by utilizing the conductivity of the conductive side wall, so that the alignment error caused by photoetching of the contact hole is reduced under the condition of ensuring the integration level of the device, and the precision of the semiconductor structure is improved.
Description
Technical Field
The present disclosure relates to integrated circuit technology, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
As semiconductor devices are widely used, the requirements for downsizing and integration of the semiconductor devices are increasing.
The conventional semiconductor device fabrication process includes: firstly, forming a grid electrode, a lightly doped drain and a side wall, injecting and diffusing a source drain and forming a self-aligned metal silicide; and depositing an insulating medium layer, carrying out chemical mechanical planarization on the insulating medium layer, photoetching the contact hole, etching the contact hole in the insulating medium layer, filling conductive materials in the contact hole, and realizing interconnection of the bottom device and the upper metal. However, as device dimensions shrink and integration requirements increase, higher requirements are placed on the resolution and alignment accuracy of lithography, but alignment errors due to contact hole lithography become larger as device dimensions shrink.
Therefore, in the process of manufacturing a semiconductor device, how to reduce the alignment error caused by contact hole lithography and improve the precision of the semiconductor structure is a technical problem that needs to be solved at present.
Disclosure of Invention
Based on this, it is necessary to provide a semiconductor structure and a method for manufacturing the same, which aims to effectively achieve improvement of the precision of the semiconductor structure.
The embodiment of the application provides a semiconductor structure, which comprises the following components:
a substrate;
a gate structure located on the substrate; the gate structure includes: grid electrode, insulating isolation side wall and conductive side wall; the grid electrode comprises a grid dielectric layer and a grid electrode conducting layer; the gate dielectric layer is positioned on the upper surface of the substrate; the grid electrode conducting layer is positioned on the upper surface of the grid dielectric layer; the insulating isolation side walls are positioned on the side wall surfaces of the two opposite sides of the grid electrode; the conductive side wall is positioned on the surface of the insulating isolation side wall, which is far away from the grid electrode;
the source region is positioned in the substrate, positioned at one side of the grid electrode and contacted with the conductive side wall;
the drain region is positioned in the substrate, is positioned at one side of the grid electrode far away from the source region and is contacted with the conductive side wall.
The semiconductor structure comprises: a substrate; the grid structure is positioned on the substrate; wherein the gate structure comprises: grid, insulating isolation side wall and conductive side wall; the grid electrode comprises a grid dielectric layer and a grid electrode conducting layer; the gate dielectric layer is positioned on the upper surface of the substrate; the grid electrode conducting layer is positioned on the upper surface of the grid dielectric layer; the insulating isolation side walls are positioned on the side wall surfaces of the two opposite sides of the grid electrode; the conductive side wall is positioned on the surface of the insulating isolation side wall, which is far away from the grid electrode; the source region is positioned in the substrate, positioned on one side of the grid electrode and contacted with the conductive side wall; the drain region is positioned in the substrate, is positioned at one side of the grid electrode far away from the source region, and is contacted with the conductive side wall. The contact holes can be omitted, the conductive side walls are directly contacted with the source region and the drain region, and the conductive side walls are contacted with the conductive side walls, so that interconnection between the bottom-layer device (the source region and the drain region) and the upper-layer metal is realized by utilizing the conductivity of the conductive side walls.
Optionally, the semiconductor structure further includes a metal silicide layer located on an upper surface of the source region, an upper surface of the drain region, and an upper surface of the gate conductive layer.
Optionally, the semiconductor structure further includes:
the interlayer dielectric layer is positioned on the upper surface of the substrate and covers the grid structure, the source region and the drain region;
the first conductive plug is positioned in the interlayer dielectric layer and is electrically connected with the grid electrode;
the second conductive plug is positioned in the interlayer dielectric layer, positioned on one side of the first conductive plug and contacted with the conductive side wall;
and the third conductive plug is positioned in the interlayer dielectric layer and is positioned at one side of the first conductive plug far away from the second conductive plug and is contacted with the conductive side wall.
Optionally, the interlayer dielectric layer includes:
the first interlayer dielectric layer is positioned on the upper surface of the substrate, is positioned at the periphery of the grid structure and covers the source region and the drain region;
the second interlayer dielectric layer is positioned on the upper surface of the first interlayer dielectric layer and the upper surface of the grid structure;
the first conductive plug, the second conductive plug and the third conductive plug are all located in the second interlayer dielectric layer.
Optionally, the upper surface of the conductive side wall is flush with the upper surface of the gate electrode, and/or the upper surface of the first interlayer dielectric layer is flush with the upper surface of the gate electrode structure.
Based on the same inventive concept, the present application also provides a method for preparing a semiconductor structure, including:
providing a substrate;
forming a grid electrode on the upper surface of the substrate, wherein the grid electrode comprises a grid dielectric layer and a grid electrode conducting layer; the gate dielectric layer is positioned on the upper surface of the substrate; the grid electrode conducting layer is positioned on the upper surface of the grid dielectric layer;
forming an insulating isolation side wall on the side wall of the grid electrode;
forming a source region and a drain region in the substrate, wherein the source region and the drain region are respectively positioned at two opposite sides of the grid electrode;
and forming a conductive side wall on the surface of the insulating isolation side wall, which is far away from the grid electrode.
The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a grid electrode on the upper surface of the substrate, wherein the grid electrode comprises a grid dielectric layer and a grid electrode conducting layer; the gate dielectric layer is positioned on the upper surface of the substrate; the grid electrode conducting layer is positioned on the upper surface of the grid dielectric layer; forming an insulating isolation side wall on the side wall of the grid electrode; forming a source region and a drain region in the substrate, wherein the source region and the drain region are respectively positioned at two opposite sides of the grid electrode; and forming a conductive side wall on the surface of the insulating isolation side wall, which is far away from the grid electrode. The contact holes can be omitted, the conductive side walls are directly contacted with the source region and the drain region, and the conductive side walls are contacted with the conductive side walls, so that interconnection between the bottom-layer device (the source region and the drain region) and the upper-layer metal is realized by utilizing the conductivity of the conductive side walls.
Optionally, after forming a source region and a drain region in the substrate, before forming the conductive sidewall on a surface of the insulating isolation sidewall remote from the gate, the method further includes:
and forming a metal silicide layer on the upper surface of the source region, the upper surface of the drain region and the upper surface of the grid electrode.
Optionally, the grid electrode, the insulating isolation side wall and the conductive side wall jointly form a grid electrode structure; after forming the conductive side wall on the surface of the insulating isolation side wall, which is far away from the grid electrode, the method further comprises the following steps:
forming an interlayer dielectric layer on the upper surface of the substrate, wherein the interlayer dielectric layer covers the gate structure, the source region and the drain region; the grid structure comprises a grid, an insulating isolation side wall and a conductive side wall;
forming a first interconnection hole, a second interconnection hole and a third interconnection hole in the interlayer dielectric layer, wherein the first interconnection hole exposes the grid electrode; the second interconnection hole is positioned at one side of the first interconnection hole, and the conductive side wall is exposed; the third interconnection hole is positioned at one side of the first interconnection hole away from the second interconnection hole, and the conductive side wall is exposed;
and forming a first conductive plug, a second conductive plug and a third conductive plug, wherein the first conductive plug is positioned in the first interconnection hole, the second conductive plug is positioned in the second interconnection hole, and the third conductive plug is positioned in the third interconnection hole.
Optionally, forming an interlayer dielectric layer on the upper surface of the substrate includes:
forming an interlayer dielectric material layer on the upper surface of the substrate, wherein the interlayer dielectric material layer coats the grid structure;
flattening the interlayer dielectric material layer to obtain a first interlayer dielectric layer;
forming a second interlayer dielectric layer on the upper surface of the first interlayer dielectric layer and the upper surface of the gate structure; the first interconnection hole, the second interconnection hole and the third interconnection hole are all located in the second interlayer dielectric layer.
Optionally, the upper surface of the conductive side wall is flush with the upper surface of the gate electrode, and/or the upper surface of the first interlayer dielectric layer is flush with the upper surface of the gate electrode structure.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment of the present application;
FIG. 2 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure after a substrate is provided;
fig. 3 is a schematic cross-sectional view of a structure obtained after forming a gate in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 4 is a schematic cross-sectional structure of a structure obtained after forming an insulating isolation sidewall in the method for manufacturing a semiconductor structure according to various embodiments of the present disclosure;
fig. 5 is a schematic cross-sectional structure of a semiconductor structure obtained after forming a source region and a drain region in the method for manufacturing a semiconductor structure according to various embodiments of the present application;
fig. 6 is a schematic cross-sectional structure of a structure obtained after forming a conductive sidewall in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;
fig. 7 is a schematic cross-sectional view of a structure obtained after forming a metal silicide layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 8 is a schematic cross-sectional view of a structure obtained after forming a first conductive plug, a second conductive plug, and a third conductive plug in an interlayer dielectric layer in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;
fig. 9 is a schematic cross-sectional structure of a structure obtained after forming an interlayer dielectric material layer in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;
fig. 10 is a schematic cross-sectional view of a structure obtained after forming a first interconnect hole, a second interconnect hole, and a third interconnect hole in a second interlayer dielectric layer in a method for manufacturing a semiconductor structure according to an embodiment of the present application.
Reference numerals illustrate:
10. a substrate; 20. a gate; 201. a gate dielectric layer; 202. a gate conductive layer; 30. insulating isolation side walls; 40. a source region; 50. a drain region; 60. a conductive sidewall; 70. a metal silicide layer; 80. an interlayer dielectric layer; 801. an interlayer dielectric material layer; 8011. a first interlayer dielectric layer; 8012. a second interlayer dielectric layer; 90. a gate structure; 100. a first interconnect hole; 101. a second interconnect hole; 102. a third interconnect hole; 103. a first conductive plug; 104. a second conductive plug; 105. and a third conductive plug.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
As semiconductor devices are widely used, the requirements for downsizing and integration of the semiconductor devices are increasing.
The conventional semiconductor device fabrication process includes: firstly, forming a grid electrode, a lightly doped drain and a side wall, injecting and diffusing a source drain and forming a self-aligned metal silicide; and depositing an insulating medium layer, carrying out chemical mechanical planarization on the insulating medium layer, photoetching the contact hole, etching the contact hole in the insulating medium layer, filling conductive materials in the contact hole, and realizing interconnection of the bottom device and the upper metal. However, as device dimensions shrink and integration requirements increase, higher requirements are placed on the resolution and alignment accuracy of lithography, but alignment errors due to contact hole lithography become larger as device dimensions shrink.
Therefore, how to reduce the alignment error caused by contact hole lithography and improve the precision of semiconductor structure in the current manufacturing process of semiconductor devices under the condition of ensuring the integration level is a technical problem to be solved.
In view of the above-mentioned shortcomings of the prior art, an object of the present application is to provide a method for manufacturing a semiconductor structure, which aims to effectively improve the precision of the semiconductor structure.
Referring to fig. 1, the present application provides a method for preparing a semiconductor structure, which includes the following steps:
s10: providing a substrate;
s20: forming a grid electrode on the upper surface of the substrate, wherein the grid electrode comprises a grid dielectric layer and a grid electrode conducting layer; the gate dielectric layer is positioned on the upper surface of the substrate; the grid electrode conducting layer is positioned on the upper surface of the grid dielectric layer;
s30: forming an insulating isolation side wall on the side wall of the grid electrode;
s40: forming a source region and a drain region in the substrate, wherein the source region and the drain region are respectively positioned at two opposite sides of the grid electrode;
s50: and forming a conductive side wall on the surface of the insulating isolation side wall, which is far away from the grid electrode.
According to the preparation method of the semiconductor structure, firstly, a substrate is provided, a grid electrode is formed on the substrate, wherein the grid electrode comprises a grid dielectric layer and a grid electrode conducting layer, secondly, an insulating isolation side wall is formed on the side wall of the grid electrode, a source region and a drain region are formed in the substrate, and then, a conducting side wall is formed on the surface, far away from the grid electrode, of the insulating isolation side wall. The contact holes can be omitted, the conductive side walls are directly contacted with the source region and the drain region, and the conductive side walls are contacted with the conductive side walls, so that interconnection between the bottom-layer device (the source region and the drain region) and the upper-layer metal is realized by utilizing the conductivity of the conductive side walls.
The following describes in detail the method for manufacturing the semiconductor structure according to the embodiment of the application of fig. 2 to 10.
In step S10, referring to step S10 in fig. 1 and fig. 2, a substrate 10 is provided.
In some examples, substrate 10 may include, but is not limited to, a silicon substrate. Of course, in other examples, the substrate 10 may also be a sapphire substrate, a gallium nitride substrate, a germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, among others.
In an alternative embodiment, after step S10, a step of cleaning the substrate 10 may be further included. By cleaning the substrate 10, impurities on the surface of the substrate 10 can be removed, so that the influence of the impurities on the subsequent process is avoided, and the performance of the device is further ensured.
Specifically, the cleaning solution may be used to clean the substrate 10, or the cleaning solution may be used to clean the substrate 10 by purging the substrate 10 with a gas such as nitrogen.
In step S20, referring to step S20 in fig. 1 and fig. 3, a gate 20 is formed on the upper surface of the substrate 10, and the gate 20 includes a gate dielectric layer 201 and a gate conductive layer 202; the gate dielectric layer 201 is located on the upper surface of the substrate 10; the gate conductive layer 202 is located on the upper surface of the gate dielectric layer 201.
Optionally, forming the gate 20 on the upper surface of the substrate 10, where the gate 20 includes the gate dielectric layer 201 and the gate conductive layer 202 may include:
s201: forming a gate dielectric material layer (not shown) on the upper surface of the substrate 10;
s202: forming a gate conductive material layer (not shown) on the upper surface of the gate dielectric layer material layer;
s203: the gate conductive material layer and the gate dielectric material layer are patterned to obtain a gate dielectric layer 201 and a gate conductive layer 202.
Alternatively, in step S201, a gate dielectric material layer may be formed on the upper surface of the substrate 10 using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; the gate dielectric material layer may include, but is not limited to, an oxide layer, such as a silicon oxide layer or the like.
Optionally, in step S202, a gate conductive material layer may be formed on the upper surface of the gate dielectric layer by using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process; the gate conductive material layer may include, but is not limited to, a doped polysilicon layer or a metal layer, etc.
Optionally, in step S203, the gate conductive material layer and the gate dielectric material layer may be patterned by using, but not limited to, a photolithography etching process to obtain the gate conductive layer 202 and the gate dielectric layer 201; specifically, a dry etching process may be used to pattern the gate conductive material layer and the gate dielectric material layer, so as to obtain the gate dielectric layer 201 and the gate conductive layer 202.
In step S30, referring to step S30 in fig. 1 and fig. 4, an insulating spacer 30 is formed on the sidewall of the gate 20.
Optionally, forming the insulating isolation sidewall 30 on the sidewall of the gate 20 may include the following steps:
s301: forming an insulating isolation material layer on the exposed upper surface of the substrate 10, the side wall of the gate 20 and the upper surface of the gate 20;
s302: an etching process is used to remove the insulating isolation material layer on the exposed upper surface of the substrate 10 and the upper surface of the gate 20, so as to obtain the insulating isolation sidewall 30.
Alternatively, in step S301, an insulating isolation material layer may be formed using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, which is equal to the exposed upper surface of the substrate 10, the sidewall of the gate electrode 20, and the upper surface of the gate electrode 20; the insulating isolation material layer may be a single-layer structure, and in this case, the insulating isolation material layer may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer; the insulating spacer material layer may have a stacked structure, and may include a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in this order from the gate electrode 20 in a direction away from the gate electrode 20.
Optionally, in step S302, a dry etching process may be used to remove the insulating isolation material layer on the exposed upper surface of the substrate 10 and the upper surface of the gate 20, so as to obtain the insulating isolation sidewall 30.
In step S40, referring to step S40 in fig. 1 and fig. 5, a source region 40 and a drain region 50 are formed in the substrate 10, and the source region 40 and the drain region 50 are respectively located at two opposite sides of the gate 20.
Alternatively, a particle implantation process may be used to implant dopant ions, either P-type or N-type, into the substrate 10 to form the source region 40 and the drain region 50.
In step S50, referring to step S50 in fig. 1 and fig. 6, a conductive sidewall 60 is formed on a surface of the insulating isolation sidewall 30 away from the gate 20.
Alternatively, the conductive sidewall 60 may be formed of any conductive material, and exemplary, the conductive sidewall 60 may include a metal sidewall.
In this embodiment, a metal material layer (not shown) may be deposited on the insulating isolation sidewall 30, and the metal material layer is processed by a dry etching process to form the conductive sidewall 60. The method specifically comprises the following steps:
s501: forming a metal material layer (not shown) on the upper surface of the substrate 10, the upper surface of the insulating spacer side wall 30 and the upper surface of the gate electrode 20;
s502: the metal material layer is patterned to obtain the conductive sidewall 60.
Specifically, in step S501, a metal material layer may be formed on, but not limited to, the upper surface of the substrate 10, the upper surface of the insulating spacer 30, and the upper surface of the gate 20.
Specifically, in step S502, patterning the metal material layer to obtain the conductive sidewall 60 may include:
s5021: forming a hard mask layer (not shown) on an upper surface of the metal material layer;
s5022: forming a photoresist layer (not shown) on an upper surface of the hard mask layer;
s5023: exposing and developing the photoresist layer to obtain a patterned photoresist layer;
s5024: etching the hard mask layer based on the patterned photoresist layer to obtain a patterned hard mask layer; specifically, the hard mask layer may be etched using, but not limited to, a dry etching process;
s5025: removing the patterned photoresist layer; etching the metal material layer based on the patterned hard mask layer to obtain the conductive side wall 60; specifically, the patterned photoresist layer may be removed using, but not limited to, an ashing process; the metal material layer may be etched using, but not limited to, a dry etching process;
s5026: removing the patterned hard mask layer; specifically, the patterned hard mask layer may be removed using, but not limited to, a chemical mechanical polishing process or an etching process.
Alternatively, in some embodiments, the conductive sidewall 60, the insulating spacer sidewall 30, and the gate 20 shown in fig. 6 may together form a gate structure 90.
In an alternative embodiment, referring to fig. 7, after forming the source region 40 and the drain region 50 in the substrate 10, before forming the conductive sidewall 60 on the surface of the insulating spacer sidewall 30 away from the gate 20, the method further includes: a metal silicide layer 70 is formed on the upper surface of the source region 40, the upper surface of the drain region 50, and the upper surface of the gate electrode 20.
Alternatively, when the substrate 10 includes silicon, a metal layer (not shown) may be deposited on the substrate 10, and the deposited structure may be annealed to react the metal in the metal layer with the silicon, and a metal silicide layer 70 may be formed on the upper surface of the source region 40, the upper surface of the drain region 50, and the upper surface of the gate electrode 20, the metal silicide layer 70 serving to reduce contact resistance.
In an alternative embodiment, referring to fig. 8, after forming the conductive sidewall 60 on the surface of the insulating isolation sidewall 30 away from the gate 20, the method further includes: forming an interlayer dielectric layer 80 on the upper surface of the substrate 10, wherein the interlayer dielectric layer 80 covers the gate structure 90, the source region 40 and the drain region 50; the gate structure 90 includes a gate 20, an insulating spacer sidewall 30, and a conductive sidewall 60; forming a first interconnection hole 100, a second interconnection hole 101 and a third interconnection hole 102 in the interlayer dielectric layer 80, the first interconnection hole 100 exposing the gate electrode 20; the second interconnection hole 101 is located at one side of the first interconnection hole 100, exposing the conductive sidewall 60; the third interconnection hole 102 is located at a side of the first interconnection hole 100 away from the second interconnection hole 101, exposing the conductive sidewall 60; a first conductive plug 103, a second conductive plug 104, and a third conductive plug 105 are formed, the first conductive plug 103 being located in the first interconnect hole 100, the second conductive plug 104 being located in the second interconnect hole 101, the third conductive plug 105 being located in the third interconnect hole 102.
In this embodiment, the interlayer dielectric layer 80 may be formed on the upper surface of the substrate 10 by a thermal oxidation process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. Interlayer dielectric layer 80 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
Alternatively, the first, second and third interconnection holes 100, 101 and 102 may be used to fill the conductive plugs. In the present embodiment, the distribution positions of the first interconnect hole 100, the second interconnect hole 101, and the third interconnect hole 102 and the first conductive plug 103, the second conductive plug 104, and the third conductive plug 105 are merely examples, and in practical application, the distribution positions of the first interconnect hole 100, the second interconnect hole 101, and the third interconnect hole 102 and the first conductive plug 103, the second conductive plug 104, and the third conductive plug 105 may be determined according to actual needs.
In this embodiment, the conductive plugs are electrically led out conductive structures that can be used to electrically led out the source region 40, the drain region 50, and the gate 20. In order to distinguish the conductive plugs, as shown in fig. 8, a conductive plug in contact with the gate electrode 20 may be used as the first conductive plug 103, a conductive plug in contact with the source region 40 may be used as the second conductive plug 104, and a conductive plug in contact with the drain region 50 may be used as the third conductive plug 105. Alternatively, in an alternative embodiment, the first conductive plug, the second conductive plug, and the third conductive plug may be determined according to the distribution positions of the source region, the drain region, and the gate electrode, which is not limited in this embodiment.
Optionally, the distance between the second conductive plug 104 and the third conductive plug 105 is smaller than the distance between the source region 40 and the drain region 50, so that the distance for electrical extraction becomes shorter, the parasitic resistance can also be made smaller, and the performance of the semiconductor device can be improved.
In an alternative embodiment, referring to fig. 9, an interlayer dielectric material layer 801 is formed on the upper surface of the substrate 10, and the interlayer dielectric material layer 801 wraps the gate structure 90; planarization is performed on the interlayer dielectric material layer 801 to obtain a first interlayer dielectric layer 8011. Referring to fig. 10, a second interlayer dielectric layer 8012 is formed on the upper surface of the first interlayer dielectric layer 8011 and the upper surface of the gate structure 90; the first, second and third interconnection holes 100, 101 and 102 are located in the second interlayer dielectric layer 8012.
In practical applications, the interlayer dielectric material layer 801 formed on the upper surface of the substrate 10 is uneven, and in order to obtain the flat and scratch-free first interlayer dielectric layer 8011, the interlayer dielectric material layer 801 may be subjected to a planarization process by Chemical Mechanical Polishing (CMP), specifically, the surface of the interlayer dielectric material layer 801 is polished to obtain the first interlayer dielectric layer 8011 shown in fig. 10.
In this embodiment, a thermal oxidation process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process may be used to form the second interlayer dielectric layer 8012 on the upper surface of the first interlayer dielectric layer 8011 and the upper surface of the gate structure 90. The second interlayer dielectric layer 8012 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. Alternatively, the first, second, and third interconnection holes 100, 101, and 102 may be formed in the second interlayer dielectric layer 8012, and specifically, the display positions of the first, second, and third interconnection holes 100, 101, and 102 may be as shown in fig. 10. In practical applications, the positions of the first interconnection hole 100, the second interconnection hole 101, and the third interconnection hole 102 may be determined according to practical situations, which are not limited herein.
In an alternative embodiment, the upper surface of the conductive sidewall 60 is flush with the upper surface of the gate 20 and/or the upper surface of the first interlayer dielectric layer 8011 is flush with the upper surface of the gate structure 90.
Alternatively, as shown in fig. 9 or 10, the upper surface of the conductive sidewall 60 is at a level with the upper surface of the gate 20. As shown in fig. 10, the upper surface of the first interlayer dielectric layer 8011 is at a level with the upper surface of the gate structure 90, or the upper surface of the conductive sidewall 60 is at a level with the upper surface of the gate 20, and the upper surface of the first interlayer dielectric layer 8011 is at a level with the upper surface of the gate structure 90.
Based on the same inventive concept, please continue to refer to fig. 6 to fig. 10, the present application further provides a semiconductor structure, as shown in fig. 6, comprising: a substrate 10; a gate structure 90 located on the substrate 10; wherein the gate structure 90 includes: gate 20, insulating spacer sidewall 30, and conductive sidewall 60; the gate 20 includes a gate dielectric layer 201 and a gate conductive layer 202; the gate dielectric layer 201 is located on the upper surface of the substrate 10; the gate conductive layer 202 is located on the upper surface of the gate dielectric layer 201; sidewall surfaces of the insulating spacer spacers 30 on opposite sides of the gate 20; the conductive side wall 60 is positioned on the surface of the insulating isolation side wall 30 far away from the grid electrode 20; the source region 40 is located in the substrate 10 and on one side of the gate 20 and contacts the conductive sidewall 60; drain region 50 is located within substrate 10 on a side of gate 20 remote from source region 40 and in contact with conductive sidewall 60.
According to the semiconductor structure, the conductive side wall 60 can be directly contacted with the source region 40 and the drain region 50 and the conductive side wall 60 without etching the contact hole, and the interconnection between the bottom layer device (source region and drain region) and the upper layer metal is realized by utilizing the conductivity of the conductive side wall 60, so that under the condition of ensuring the integration level of the device, the alignment error brought by photoetching of the contact hole is reduced, and the precision of the semiconductor structure is improved.
In some examples, substrate 10 may include, but is not limited to, a silicon substrate. Of course, in other examples, the substrate 10 may also be a sapphire substrate, a gallium nitride substrate, a germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, among others.
In some examples, gate dielectric layer 201 may include, but is not limited to, an oxide layer, such as a silicon oxide layer or the like; the gate conductive layer 202 may include a doped polysilicon layer or a metal layer, etc.
Optionally, the insulating isolation sidewall 30 may have a single-layer structure, and in this case, the insulating isolation sidewall 30 may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer; the insulating spacer 30 may also have a stacked structure, and may include a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer sequentially stacked from the gate electrode 20 in a direction away from the gate electrode 20.
Alternatively, the conductive sidewall 60 may be formed of any conductive material, and exemplary, the conductive sidewall 60 may include a metal sidewall.
In some examples, the semiconductor structure further includes a metal silicide layer 70, the metal silicide layer 70 being located on an upper surface of the source region 40, an upper surface of the drain region 50, and an upper surface of the gate conductive layer 202.
Alternatively, as shown in fig. 7, when the substrate 10 includes silicon, a metal material layer (not shown) may be deposited on the substrate 10, and the deposited structure may be annealed to react metal in the metal material layer with the silicon, and a metal silicide layer 70 may be formed on the upper surface of the source region 40, the upper surface of the drain region 50, and the upper surface of the gate electrode 20, the metal silicide layer 70 being used to reduce contact resistance.
In one example, as shown in fig. 8, the semiconductor structure further includes: an interlayer dielectric layer 80 on the upper surface of the substrate 10 and covering the gate structure 90, the source region 40 and the drain region 50; the first conductive plug 103 is located in the interlayer dielectric layer 80 and is electrically connected with the gate 20; the second conductive plug 104 is located in the interlayer dielectric layer 80, is located at one side of the first conductive plug 103, and contacts the conductive sidewall 60; the third conductive plug 105 is located in the interlayer dielectric layer 80, and is located at a side of the first conductive plug 103 away from the second conductive plug 104, and contacts the conductive sidewall 60.
In this embodiment, the interlayer dielectric layer 80 may include, but is not limited to, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
In this embodiment, the conductive plugs are electrically led out conductive structures that can be used to electrically led out the source region 40, the drain region 50, and the gate 20. In order to distinguish the conductive plugs, as shown in fig. 8, a conductive plug in contact with the gate electrode 20 may be used as the first conductive plug 103, a conductive plug in contact with the source region 40 may be used as the second conductive plug 104, and a conductive plug in contact with the drain region 50 may be used as the third conductive plug 105. Alternatively, in an alternative embodiment, the first conductive plug 103, the second conductive plug 104, and the third conductive plug 105 may be determined according to the distribution positions of the source region 40, the drain region 50, and the gate 20, which is not limited in this embodiment.
Optionally, the distance between the second conductive plug 104 and the third conductive plug 105 is smaller than the distance between the source region 40 and the drain region 50, so that the distance for electrical extraction becomes shorter, the parasitic resistance can also be made smaller, and the performance of the semiconductor device can be improved.
In one example, as shown in fig. 9, the interlayer dielectric layer 80 includes: a first interlayer dielectric layer 8011 located on the upper surface of the substrate 10, located at the periphery of the gate structure 90, and covering the source region 40 and the drain region 50; as shown in fig. 10, a second interlayer dielectric layer 8012 is disposed on the upper surface of the first interlayer dielectric layer 8011 and the upper surface of the gate structure 90; the first conductive plug 103, the second conductive plug 104 and the third conductive plug 105 are all located in the second interlayer dielectric layer 8012.
In one example, the upper surface of the conductive sidewall 60 is flush with the upper surface of the gate 20.
In another example, the upper surface of the first interlayer dielectric layer 8011 is flush with the upper surface of the gate structure 90.
In yet another example, the upper surface of the conductive sidewall 60 is flush with the upper surface of the gate 20, and the upper surface of the first interlayer dielectric layer 8011 is flush with the upper surface of the gate structure 90.
Alternatively, as shown in fig. 9 or 10, the upper surface of the conductive sidewall 60 is at a level with the upper surface of the gate 20. As shown in fig. 10, the upper surface of the first interlayer dielectric layer 8011 is at a level with the upper surface of the gate structure 90, or the upper surface of the conductive sidewall 60 is at a level with the upper surface of the gate 20, and the upper surface of the first interlayer dielectric layer 8011 is at a level with the upper surface of the gate structure 90.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or other steps.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A semiconductor structure, comprising:
a substrate;
a gate structure located on the substrate; the gate structure includes: grid electrode, insulating isolation side wall and conductive side wall; the grid electrode comprises a grid dielectric layer and a grid electrode conducting layer; the gate dielectric layer is positioned on the upper surface of the substrate; the grid electrode conducting layer is positioned on the upper surface of the grid dielectric layer; the insulating isolation side walls are positioned on the side wall surfaces of the two opposite sides of the grid electrode; the conductive side wall is positioned on the surface of the insulating isolation side wall, which is far away from the grid electrode; the conductive side wall is formed by a conductive material and comprises a metal side wall;
the source region is positioned in the substrate, positioned at one side of the grid electrode and contacted with the conductive side wall;
the drain region is positioned in the substrate, is positioned at one side of the grid electrode far away from the source region and is contacted with the conductive side wall.
2. The semiconductor structure of claim 1, further comprising a metal silicide layer located on an upper surface of the source region, an upper surface of the drain region, and an upper surface of the gate conductive layer.
3. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:
the interlayer dielectric layer is positioned on the upper surface of the substrate and covers the grid structure, the source region and the drain region;
the first conductive plug is positioned in the interlayer dielectric layer and is electrically connected with the grid electrode;
the second conductive plug is positioned in the interlayer dielectric layer, positioned on one side of the first conductive plug and contacted with the conductive side wall;
and the third conductive plug is positioned in the interlayer dielectric layer and is positioned at one side of the first conductive plug far away from the second conductive plug and is contacted with the conductive side wall.
4. The semiconductor structure of claim 3, wherein the interlayer dielectric layer comprises:
the first interlayer dielectric layer is positioned on the upper surface of the substrate, is positioned at the periphery of the grid structure and covers the source region and the drain region;
the second interlayer dielectric layer is positioned on the upper surface of the first interlayer dielectric layer and the upper surface of the grid structure;
the first conductive plug, the second conductive plug and the third conductive plug are all located in the second interlayer dielectric layer.
5. The semiconductor structure of claim 4, wherein an upper surface of the conductive sidewall is flush with an upper surface of the gate electrode and/or an upper surface of the first interlayer dielectric layer is flush with an upper surface of the gate electrode structure.
6. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a grid electrode on the upper surface of the substrate, wherein the grid electrode comprises a grid dielectric layer and a grid electrode conducting layer; the gate dielectric layer is positioned on the upper surface of the substrate; the grid electrode conducting layer is positioned on the upper surface of the grid dielectric layer;
forming an insulating isolation side wall on the side wall of the grid electrode;
forming a source region and a drain region in the substrate, wherein the source region and the drain region are respectively positioned at two opposite sides of the grid electrode;
forming a conductive side wall on the surface of the insulating isolation side wall, which is far away from the grid electrode; the conductive side wall is formed by conductive materials and comprises a metal side wall.
7. The method of claim 6, further comprising, after forming the source region and the drain region in the substrate, forming the conductive sidewall on a surface of the insulating spacer away from the gate electrode, and then:
and forming a metal silicide layer on the upper surface of the source region, the upper surface of the drain region and the upper surface of the grid electrode.
8. The method of manufacturing a semiconductor structure according to claim 6, wherein the gate electrode, the insulating isolation sidewall and the conductive sidewall together form a gate structure; after forming the conductive side wall on the surface of the insulating isolation side wall, which is far away from the grid electrode, the method further comprises the following steps:
forming an interlayer dielectric layer on the upper surface of the substrate, wherein the interlayer dielectric layer covers the gate structure, the source region and the drain region;
forming a first interconnection hole, a second interconnection hole and a third interconnection hole in the interlayer dielectric layer, wherein the first interconnection hole exposes the grid electrode; the second interconnection hole is positioned at one side of the first interconnection hole, and the conductive side wall is exposed; the third interconnection hole is positioned at one side of the first interconnection hole away from the second interconnection hole, and the conductive side wall is exposed;
and forming a first conductive plug, a second conductive plug and a third conductive plug, wherein the first conductive plug is positioned in the first interconnection hole, the second conductive plug is positioned in the second interconnection hole, and the third conductive plug is positioned in the third interconnection hole.
9. The method of claim 8, wherein forming an interlayer dielectric layer on the upper surface of the substrate comprises:
forming an interlayer dielectric material layer on the upper surface of the substrate, wherein the interlayer dielectric material layer coats the grid structure;
flattening the interlayer dielectric material layer to obtain a first interlayer dielectric layer;
forming a second interlayer dielectric layer on the upper surface of the first interlayer dielectric layer and the upper surface of the gate structure; the first interconnection hole, the second interconnection hole and the third interconnection hole are all located in the second interlayer dielectric layer.
10. The method of manufacturing a semiconductor structure according to claim 9, wherein an upper surface of the conductive sidewall is flush with an upper surface of the gate electrode, and/or an upper surface of the first interlayer dielectric layer is flush with an upper surface of the gate electrode structure.
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