CN102332401A - Forming method of MOS (Metal Oxide Semiconductor) device - Google Patents
Forming method of MOS (Metal Oxide Semiconductor) device Download PDFInfo
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- CN102332401A CN102332401A CN201110213523A CN201110213523A CN102332401A CN 102332401 A CN102332401 A CN 102332401A CN 201110213523 A CN201110213523 A CN 201110213523A CN 201110213523 A CN201110213523 A CN 201110213523A CN 102332401 A CN102332401 A CN 102332401A
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Abstract
The invention discloses a forming method of an MOS (Metal Oxide Semiconductor) device, comprising the following steps of: providing a semiconductor substrate, wherein a grid electrode structure including a side wall is formed on the surface of the semiconductor substrate; injecting doping ions to the semiconductor substrate at two sides of the grid electrode structure by taking the grid electrode structure as a mask to form a source electrode and a drain electrode; introducing plasma such as oxygen gas and the like to the surfaces of the source electrode and the drain electrode, and forming oxidation resisting layers on the surfaces of the source electrode and the drain electrode; after the oxidation resisting layers are formed, carrying out annealing treatment to activate the doping ions; forming insulating medium layers for covering on the oxidation resisting layers and the grid electrode structure; forming mask layers with openings on the surfaces of the insulating medium layers, wherein the positions of the openings are opposite to the positions of the source electrode and the drain electrode; removing the insulating medium layers along the openings until the oxidation resisting layers are exposed; removing the exposed oxidation resisting layers to form a through hole for exposing the source electrode, the drain electrode and part of the side wall; and forming a conductive plug for filling the through hole. By using the method provided by the invention, the performance of the MOS device is improved, and the production efficiency is increased.
Description
Technical field
The present invention relates to semiconductor applications, particularly MOS device formation method.
Background technology
In semiconductor fabrication process, often need to form the MOS device.Usually, the step of making the MOS device comprises: at first on Semiconductor substrate, form grid oxide layer and polysilicon layer, said polysilicon layer of etching and grid oxide layer form grid until exposing said Semiconductor substrate successively then; Then, be that mask injects dopant ion to Semiconductor substrate with formed grid, form shallow doped source, drain electrode; Form to cover the side wall of the sidewall of said grid again, and be that mask injects dopant ion to Semiconductor substrate, formation source, drain electrode with said side wall and grid; Then Semiconductor substrate is carried out rapid thermal annealing (RTA, rapid thermal anneal), with the dopant ion of activation of source, drain electrode., publication number introduced a kind of formation method of MOS device in being the United States Patent (USP) of US20040140569 in detail.But in said RTA process, the dopant ion of source, drain electrode can spread everywhere, and a part of dopant ion can break away from source, drain electrode, accumulates on the semiconductor substrate surface, thereby causes that source, drain resistance value squint.For fear of the source, the drain resistance value squints, and in actual process, can after formation source, drain electrode, form one deck barrier oxide layer at semiconductor substrate surface, be diffused on the semiconductor substrate surface with the dopant ion of the source of preventing, drain electrode.In order to prevent that said barrier oxide layer from increasing the resistance between conductive plunger and the Semiconductor substrate, in the step of follow-up formation conductive plunger, adopt etching technics to remove said barrier oxide layer.
Along with the miniaturization of semiconductor device, the density of MOS device is increasing, so under many circumstances, the part of conductive plunger is formed directly into the surface of the side wall 20 of grid structure.Please refer to Fig. 1 and Fig. 2, the method for existing formation conductive plunger is to form first through hole 10 that exposes barrier oxide layer 30 through etching technics earlier; Remove the barrier oxide layer 30 of said first through hole 10 bottoms again, to be formed for forming second through hole 40 of conductive plunger.Because first through hole 10 is expose portion side wall 20 simultaneously, so in the step of removing said barrier oxide layer 30, can be damaged to side wall 20, thereby influence the performance of semiconductor device.
Summary of the invention
The problem that the present invention solves provides a kind of MOS device formation method, in the step of removing barrier oxide layer, damages the problem of side wall easily to solve existing MOS device formation method.
For addressing the above problem, the present invention provides a kind of MOS device formation method, comprising: Semiconductor substrate is provided, and said semiconductor substrate surface is formed with grid structure, and said grid structure comprises side wall;
With said grid structure is mask, injects dopant ion, formation source, drain electrode to the Semiconductor substrate of grid structure both sides;
To source, drain surface aerating oxygen plasma, in the source, drain surface forms barrier oxide layer, carries out annealing in process then, the dopant ion in said annealing in process activation of source, drain region;
Form the insulating medium layer that covers said barrier oxide layer and grid structure;
Form the mask layer with opening at said dielectric laminar surface, the position of said opening is corresponding with the position of source, drain electrode;
Remove said insulating medium layer along said opening, until exposing said barrier oxide layer;
Remove the barrier oxide layer that is exposed, form the through hole of source of exposure, drain electrode, said through hole is the expose portion side wall also;
Form the conductive plunger of filling full said through hole.Alternatively, the process conditions that form said barrier oxide layer are: pressure is 8-16mtorr, and the flow of oxygen gas plasma is 80-120sccm, and voltage is the negative 230V of negative 200-, sedimentation time 25-40 second.
Alternatively, the thickness of formed barrier oxide layer is the 40-50 dust.
Alternatively, adopt the method for dry etching to remove said barrier oxide layer.
Alternatively, the material of said insulating medium layer is the silex glass of high-density phosphorus.Alternatively, said grid structure comprises that also grid and said side wall are formed on the grid both sides.
Alternatively, the step that forms conductive plunger is included in via bottoms and forms metal silicide layer, and the metal material of said metal silicide layer is a titanium.
Compared with prior art, technical scheme of the present invention has the following advantages: earlier to said source, drain surface aerating oxygen plasma, said oxygen gas plasma and semiconductor substrate materials react; In the source, drain surface forms barrier oxide layer; The thickness of formed barrier oxide layer is little, thus in subsequent technique, remove easily, and be not easy to damage side wall; Therefore improved process efficiency through technical scheme of the present invention, and the performance of formed device;
Further; After forming barrier oxide layer, the anneal dopant ion of activation of source, drain electrode of technical scheme of the present invention; In annealing process, said barrier oxide layer stops that the dopant ion of source, drain electrode is diffused into semiconductor substrate surface, thereby makes that the resistance value of source, drain electrode is stable.
Description of drawings
Fig. 1 and Fig. 2 are the cross-sectional view of existing MOS device forming process;
Fig. 3 is the schematic flow sheet of the MOS device formation method that provides of embodiments of the invention;
Fig. 4 to Fig. 6, Fig. 8 to Figure 12 are the cross-sectional view of the MOS device forming process that provides of embodiments of the invention;
Fig. 7 is the sketch map that concerns of the thickness of oxide layer that obtains in surface of silicon growth and measuring position.
Embodiment
Can know by background technology,, be used to form in the step of barrier oxide layer of via bottoms of conductive plunger, can be damaged to side wall, thereby influence the performance of semiconductor device in removal source, drain surface along with the development of device miniaturization.
The inventor studies to the problems referred to above; Finding in the prior art, generally is to adopt chemical vapor deposition method to form said barrier oxide layer, and the thickness of formed barrier oxide layer generally is the scope at the 300-400 dust; So difficult when removing, can be damaged to side wall.The inventor expects reducing the thickness of formed barrier oxide layer thus, just can reduce the thickness that needs the barrier oxide layer of removal in the subsequent technique, the relatively easy removal, thus can avoid side wall is caused damage.But find through attempting, adopt chemical vapor deposition method to be difficult to form thickness, and more uniform barrier oxide layer less than 300 dusts.
The inventor provides a kind of MOS device formation method in the present invention through further research.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with accompanying drawing and embodiment specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
Fig. 3 is the schematic flow sheet of the MOS device formation method that provides of embodiments of the invention, comprising:
Step S101 provides Semiconductor substrate, and said semiconductor substrate surface is formed with grid structure, and said grid structure comprises side wall;
Step S102 is a mask with said grid structure, injects dopant ion, formation source, drain electrode to the Semiconductor substrate of grid structure both sides;
Step S103 is to source, drain surface aerating oxygen plasma, in the source, drain surface forms barrier oxide layer;
Step S104, form said barrier oxide layer after, carry out annealing in process, the dopant ion of said annealing in process activation of source, drain electrode;
Step S105 forms the insulating medium layer that covers said barrier oxide layer and grid structure;
Step S106 forms the mask layer with opening at said dielectric laminar surface, and the position of said opening is corresponding with the position of source, drain electrode;
Step S107 removes said insulating medium layer along said opening, until exposing said barrier oxide layer;
Step S108 removes the barrier oxide layer that is exposed, and forms the through hole of source of exposure, drain electrode, and said through hole is the expose portion side wall also;
Step S109 forms the conductive plunger of filling full said through hole.
Fig. 4 to Fig. 6, and Fig. 8 to Figure 12 is the cross-sectional view of the MOS device forming process that provides of embodiments of the invention.
With reference to figure 4, Semiconductor substrate 100 is provided, said Semiconductor substrate 100 surfaces are formed with grid structure, and said grid structure comprises grid, and the side wall 130 that is positioned at the grid both sides;
Said Semiconductor substrate 100 can be all Semiconductor substrate of supporting to form the MOS device.In the present embodiment, said Semiconductor substrate 100 is silicon substrate or SOI substrate.
In the present embodiment, said grid comprises the gate dielectric layer 110 and gate electrode layer 120 that is formed on Semiconductor substrate 100 surfaces successively, and side wall 130 covers said grid side walls.The material of said gate dielectric layer 110 is silicon dioxide or hafnium, and the material of said gate electrode layer 120 is polysilicon or metal material.
As an embodiment, after forming said grid, be mask with said grid, inject dopant ion to Semiconductor substrate 100, form shallow doped region; Form side wall 130 then in said grid both sides.
With reference to figure 5, be mask with said grid structure, inject dopant ion to the Semiconductor substrate 100 of grid structure both sides, formation source, drain electrode 140.
Be example to form the PMOS transistor in the present embodiment, the present invention is carried out schematic illustration.
In the present embodiment, inject P type dopant ion to said Semiconductor substrate 100, such as the boron ion.Injecting P type energy of ions, dosage and angle can be provided with according to arts demand, no longer details in the present embodiment.
With reference to figure 6, to source, drain electrode 140 surperficial aerating oxygen plasmas, in the source, drain electrode 140 surfaces form barrier oxide layer 150.
In the present embodiment; To source, drain electrode 140 surperficial aerating oxygen plasmas; The silicon generation chemical reaction of the oxygen gas plasma that is fed in source, drain electrode 140 surfaces and Semiconductor substrate forms barrier oxide layer 150; The material of said barrier oxide layer 150 is a silicon dioxide, and said barrier oxide layer 150 is used for preventing that in the process of the dopant ion of subsequent anneal activation of source, drain electrode 140 dopant ion in source, the drain electrode 140 from leaving source, drain electrode 140 because of diffusion.
Because the material of side wall 130 is silicon nitrides, so in this step, side wall 130 surfaces can not form barrier oxide layer 150.In addition, the material on the surface of the isolation structure between the adjacent mos structure is a silicon dioxide, and the isolation structure surface can not form barrier oxide layer 150 yet.
The thickness that 150 1 benefits of barrier oxide layer that adopt the method for the aerating oxygen plasma that present embodiment provided to form are exactly formed barrier oxide layer 150 can be through the aerating oxygen plasma flow or/and the time control, thereby help removing barrier oxide layer 150 after the subsequent anneal technology.
In the present embodiment, the thickness range of said barrier oxide layer 150 is the 40-50 dust.The thickness of said barrier oxide layer 150 is excessive; Can increase the complexity of the technology of follow-up removal barrier oxide layer 150; Be unfavorable for improving process efficiency; The thickness of described barrier oxide layer 150 is too small, may be not enough to stop that the dopant ion of source, drain electrode 140 leaves source, drain electrode 140 because of diffusion.The inventor finds that through a large amount of experimental studies said barrier oxide layer 150 can stop that the dopant ion of source, drain electrode 140 leaves the scope of the minimum thickness of source, drain electrode 140 at the 40-50 dust because of diffusion.
Simultaneously; If formed barrier oxide layer 150 is in uneven thickness; In the process of follow-up removal barrier oxide layer 150, may produce residual, perhaps in order all to remove barrier oxide layer 150; And produce too much over etching amount in the subregion, and therefore cause the loss of Semiconductor substrate 100 surfacings.If produce residually, may increase conductive plunger and the source of follow-up formation, the resistance between the drain electrode, even open circuit; If cause the loss of Semiconductor substrate 100 surfacings, may produce leakage current.
For this reason, the inventor has carried out a large amount of experimental studies, and finds can obtain the uniform barrier oxide layer 150 of thickness through the adjusting process condition.And one group of process conditions that can form the uniform barrier oxide layer 150 of thickness is provided in an embodiment of the present invention: pressure is 8-16mtorr, and the flow of oxygen gas plasma is 80-120sccm, and voltage is the negative 230V of negative 200-, and sedimentation time is 25-40 second.
Preferably, the process conditions that form barrier oxide layer 150 are: pressure is 12mtorr, and the flow of oxygen gas plasma is 80sccm, and voltage is negative 215V, and sedimentation time is 35 seconds.
Fig. 7 adopts under one group of process conditions that embodiments of the invention provided, thickness of oxide layer that obtains in the surface of silicon growth and measuring position concern sketch map, the diameter of said silicon substrate is 200mm.The inventor has chosen A, B, C, D, E, F, G, H, I; Nine formed thickness of oxide layer of point measurement; Its mid point A is near the center of circle, and F, G, H, I point are near circumference, and B, C, D, E are between the center of circle and circumference; The thickness of oxide layer at some A, B, C, D, E, F, G, H, I place is respectively 2.7nm, 2.9nm, 2.9nm, 2.9nm, 2.9nm, 2.7nm, 2.7nm, 2.7nm, 2.9nm; Average thickness is 2.8nm, and error is 3.5%, so can think that formed oxide layer is uniform.
Please continue with reference to figure 6, form said barrier oxide layer 150 after, carry out annealing in process with activation of source, leak the dopant ion in 140.
The purpose of said annealing in process is the dopant ion of activation of source, drain electrode 140.The quick thermal annealing process that annealing in process described in the present embodiment adopts.Formed barrier oxide layer 150 can prevent that the dopant ion of source, drain electrode 140 is diffused into semiconductor and sinks to the bottom 100 surfaces in annealing in process.Because the technology that adopts annealing in process to activate dopant ion is well known to those skilled in the art, so be not described in detail in this.
With reference to figure 8, form the insulating medium layer 160 that covers said barrier oxide layer 150 and grid structure.
In this instance, the material of said insulating medium layer 160 is highly doped phosphorous silex glasss, and the ion of being mixed can be regulated as required.Highly doped phosphorous silex glass has than higher dry etching and selects ratio, so in the step of follow-up removal insulating medium layer 160, can not damage isolation structure and side wall 130 between the metal-oxide-semiconductor with respect to silicon dioxide and silicon nitride.
With reference to figure 9, form mask layer 170 on said insulating medium layer 160 surfaces with opening 200, the position of said opening 200 is corresponding with the position of source, drain electrode 140, and the width of said opening 200 is greater than the width of source, drain electrode 140.
In the present embodiment, said mask layer 170 be photoresist layer, in other embodiments, mask layer 170 also can be formed by other materials.
With reference to Figure 10, adopt dry etch process along the said insulating medium layer 160 of said opening 200 etchings, until exposing said barrier oxide layer 150 and part side wall 130.
In the present embodiment, the material of said insulating medium layer 160 is highly doped phosphorous silex glasss, and the material of side wall 130 is silicon dioxide or silicon nitride, perhaps the mixture of silicon dioxide and silicon nitride.Because said dry etch process is high to the etching selection ratio of insulating medium layer 160 and silicon dioxide, silicon nitride, so in this step etching, can not damage side wall 130.So shown in figure 10, the position of said opening 200 and source, drain electrode 140 and part side wall 130 over against situation under, said etching technics can stop at the surface of side wall 130 and barrier oxide layer 150.
With reference to Figure 11, remove the barrier oxide layer 150 that is exposed, form through hole 180.
As an embodiment, adopt etching technics to remove the barrier oxide layer 150 that is exposed.Such as selecting anisotropic dry etch process.
Shown in figure 11; In the present embodiment, formed through hole 180 meeting expose portion side walls, in this case; Because the thickness of barrier oxide layer is very little; Can ignore the influence that side wall 130 causes so remove the technology of barrier oxide layer, and because the thickness of the thickness of barrier oxide layer formed barrier oxide layer in the prior art, so can improve the efficient of removing barrier oxide layer simultaneously.
With reference to Figure 12, form the conductive plunger 190 of filling full said through hole 180.
Alternatively, the step that forms said conductive plunger 190 also is included in said through hole 180 bottoms and forms the metal silicide layer (not shown), and the metal material of said metal silicide layer is a titanium.Said metal silicide layer can reduce the resistance between conductive plunger and source, the drain electrode 140.
This step also comprises the mask layer of removing insulating medium layer 160 surfaces.
To sum up, technical scheme of the present invention is earlier to said source, drain surface aerating oxygen plasma, and said oxygen gas plasma and semiconductor substrate materials react; In the source, drain surface forms barrier oxide layer; The thickness of formed barrier oxide layer is little, thus in subsequent technique, remove easily, and be not easy to damage side wall; Therefore improved process efficiency through technical scheme of the present invention, and the performance that improves formed device;
Further; After forming barrier oxide layer, the anneal dopant ion of activation of source, drain electrode of technical scheme of the present invention; In annealing process, said barrier oxide layer stops that the dopant ion of source, drain electrode is diffused into semiconductor substrate surface, thereby makes that the resistance value of source, drain electrode is stable.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (7)
1. MOS device formation method, comprising: Semiconductor substrate is provided, and said semiconductor substrate surface is formed with grid structure, and said grid structure comprises side wall; With said grid structure is mask, injects dopant ion, formation source, drain electrode to the Semiconductor substrate of grid structure both sides; It is characterized in that, also comprise:
To source, drain surface aerating oxygen plasma, in the source, drain surface forms barrier oxide layer, carries out annealing in process then, the dopant ion in said annealing in process activation of source, drain region;
Form the insulating medium layer that covers said barrier oxide layer and grid structure;
Form the mask layer with opening at said dielectric laminar surface, the position of said opening is corresponding with the position of source, drain electrode;
Remove said insulating medium layer along said opening, until exposing said barrier oxide layer;
Remove the barrier oxide layer that is exposed, form the through hole of source of exposure, drain electrode, said through hole is the expose portion side wall also;
Form the conductive plunger of filling full said through hole.
2. according to the described MOS device of claim 1 formation method; It is characterized in that the process conditions that form said barrier oxide layer are: pressure is 8-16mtorr, the flow of oxygen gas plasma is 80-120sccm; Voltage is the negative 230V of negative 200-, and sedimentation time is 25-40 second.
3. according to the described MOS device of claim 1 formation method, it is characterized in that the thickness of formed barrier oxide layer is the 40-50 dust.
4. according to the described MOS device of claim 1 formation method, it is characterized in that, adopt the method for dry etching to remove said barrier oxide layer.
5. according to the described MOS device of claim 1 formation method, it is characterized in that the material of said insulating medium layer is highly doped phosphorous silex glass.
6. according to the described MOS device of claim 1 formation method, it is characterized in that said grid structure also comprises grid, and said side wall is formed on the grid both sides.
7. according to the described MOS device of claim 1 formation method, it is characterized in that the step that forms conductive plunger also is included in via bottoms and forms metal silicide layer, the metal material of said metal silicide layer is a titanium.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116435275A (en) * | 2023-06-09 | 2023-07-14 | 粤芯半导体技术股份有限公司 | Semiconductor structure and preparation method thereof |
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| US20040126946A1 (en) * | 2002-12-30 | 2004-07-01 | Kim Bong Soo | Method for forming transistor of semiconductor device |
| US20070063294A1 (en) * | 2004-03-24 | 2007-03-22 | Texas Instruments Incorporated | Semiconductor Device Having a Fully Silicided Gate Electrode and Method of Manufacture Therefor |
| CN101866850A (en) * | 2009-04-14 | 2010-10-20 | 中芯国际集成电路制造(北京)有限公司 | Structure of salicide area barrier film and preparation method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040126946A1 (en) * | 2002-12-30 | 2004-07-01 | Kim Bong Soo | Method for forming transistor of semiconductor device |
| US20070063294A1 (en) * | 2004-03-24 | 2007-03-22 | Texas Instruments Incorporated | Semiconductor Device Having a Fully Silicided Gate Electrode and Method of Manufacture Therefor |
| CN101866850A (en) * | 2009-04-14 | 2010-10-20 | 中芯国际集成电路制造(北京)有限公司 | Structure of salicide area barrier film and preparation method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116435275A (en) * | 2023-06-09 | 2023-07-14 | 粤芯半导体技术股份有限公司 | Semiconductor structure and preparation method thereof |
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