CN107369621B - Fin field effect transistor and forming method thereof - Google Patents

Fin field effect transistor and forming method thereof Download PDF

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Publication number
CN107369621B
CN107369621B CN201610318186.4A CN201610318186A CN107369621B CN 107369621 B CN107369621 B CN 107369621B CN 201610318186 A CN201610318186 A CN 201610318186A CN 107369621 B CN107369621 B CN 107369621B
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layer
forming
gate electrode
fin
dielectric layer
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CN107369621A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201610318186.4A priority Critical patent/CN107369621B/en
Priority to US15/473,726 priority patent/US10297595B2/en
Priority to EP17169813.7A priority patent/EP3244444A1/en
Publication of CN107369621A publication Critical patent/CN107369621A/en
Priority to US16/376,278 priority patent/US10734381B2/en
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Abstract

A fin field effect transistor and a forming method thereof are provided, wherein the method comprises the following steps: providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a fin part, and the fin part comprises an edge area and a central area; forming a pseudo gate structure crossing the fin part in the central region and a blocking structure crossing the fin part in the edge region, wherein the pseudo gate structure comprises a pseudo gate electrode layer positioned on the top and the side wall of the fin part; forming a source drain region in the fin part between the pseudo gate structure and the blocking structure; then forming a first interlayer dielectric layer covering the side wall of the pseudo gate structure and the side wall of the blocking structure on the semiconductor substrate and the fin part; removing the dummy gate electrode layer to form an opening; a metal gate electrode layer is formed in the opening. According to the method, the blocking structure is formed before the source-drain region is formed, the blocking structure is reserved when the pseudo gate electrode layer is removed, and the electrical performance of the fin field effect transistor is improved.

Description

Fin field effect transistor and forming method thereof
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a fin type field effect transistor and a forming method thereof.
Background
A MOS (metal-oxide-semiconductor) transistor, which is one of the most important components in modern integrated circuits, has a basic structure including: a semiconductor substrate; a gate structure located on a surface of a semiconductor substrate, the gate structure comprising: the gate electrode layer is positioned on the surface of the gate dielectric layer; and the source and drain regions are positioned in the semiconductor substrate at two sides of the grid structure.
With the development of semiconductor technology, the conventional planar MOS transistor has a weak ability to control channel current, resulting in a serious leakage current. A Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a Fin portion protruding from a surface of a semiconductor substrate, a gate structure covering a portion of a top surface and a sidewall of the Fin portion, and source and drain regions in the Fin portion located at both sides of the gate structure.
However, the electrical performance of the fin field effect transistor formed by the prior art is poor.
Disclosure of Invention
The invention provides a fin field effect transistor and a forming method thereof, and aims to improve the electrical performance of the fin field effect transistor.
In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, including: providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a fin part, and the fin part comprises an edge area and a central area; forming a pseudo gate structure crossing the fin part in the central region and a blocking structure crossing the fin part in the edge region, wherein the pseudo gate structure comprises a pseudo gate electrode layer positioned on the top and the side wall of the fin part; forming a source drain region in the fin part between the pseudo gate structure and the blocking structure; after a source drain region is formed, forming a first interlayer dielectric layer on the semiconductor substrate and the fin portion, wherein the first interlayer dielectric layer covers the side wall of the pseudo gate structure and the side wall of the blocking structure; after the first interlayer dielectric layer is formed, removing the pseudo gate electrode layer to form an opening; and forming a metal gate electrode layer in the opening.
Optionally, the blocking structure is formed at the same time as the dummy gate structure is formed.
Optionally, the blocking structure includes a blocking gate dielectric layer crossing the fin portion of the edge region and a blocking gate electrode layer located on the blocking gate dielectric layer.
Optionally, the barrier gate dielectric layer is made of silicon oxide or a high-K dielectric material; the material of the blocking gate electrode layer is polysilicon.
Optionally, the barrier structure has a conductivity below 3.0E-4S/m.
Optionally, the material of the blocking structure is monocrystalline silicon or polycrystalline silicon.
Optionally, the dummy gate structure includes a dummy gate dielectric layer crossing the fin portion in the central region and a dummy gate electrode layer located on the surface of the dummy gate dielectric layer; further comprising: after the first interlayer dielectric layer is formed, removing the pseudo gate electrode layer and the pseudo gate dielectric layer to form an opening; and forming a gate dielectric layer positioned at the bottom and the side wall of the opening and a metal gate electrode layer positioned on the gate dielectric layer in the opening.
Optionally, the method further includes: forming a second interlayer dielectric layer on the metal gate electrode layer, the barrier structure and the first interlayer dielectric layer; and forming a conductive plug penetrating through the first interlayer dielectric layer and the second interlayer dielectric layer on the source drain region.
Optionally, the method further includes: a first mask layer is formed on the top surfaces of the blocking structure and the dummy gate structure; after a source drain region is formed, forming a first interlayer dielectric layer on the semiconductor substrate and the fin portion, wherein the first interlayer dielectric layer covers the side wall of the pseudo gate structure, the side wall of the blocking structure and the side wall of the first mask layer; and removing the first mask layer on the top surface of the dummy gate structure in the process of forming the opening.
Optionally, the material of the first mask layer includes silicon nitride, silicon oxynitride, or silicon oxycarbonitride.
Optionally, the method for forming the first mask layer, the blocking structure and the dummy gate structure includes: forming a pseudo gate dielectric material layer, a pseudo gate electrode material layer positioned on the surface of the pseudo gate dielectric material layer and a first mask material layer positioned on the surface of the pseudo gate electrode material layer on the semiconductor substrate and on the fin parts of the edge region and the central region; and patterning the first mask material layer, the dummy gate electrode material layer and the dummy gate dielectric material layer to form a dummy gate structure crossing the fin part in the central region, a blocking structure crossing the fin part in the edge region and a first mask layer positioned on the top surfaces of the dummy gate structure and the blocking structure.
Optionally, the method for forming the opening includes: forming a second mask layer, wherein the second mask layer covers the first mask layer on the top surface of the blocking structure; removing the first mask layer on the top surface of the pseudo gate structure by taking the second mask layer as a mask; and removing the pseudo gate electrode layer by taking the first mask layer on the top surface of the barrier structure as a mask after removing the second mask layer, thereby forming an opening.
Optionally, the material of the second mask layer includes photoresist.
Optionally, the step of forming the source and drain regions includes: removing part of the fin part between the pseudo gate structure and the blocking structure to form a recess; and forming a source and drain region material layer in the recess so as to form a source and drain region.
The present invention also provides a fin field effect transistor, including: the semiconductor device comprises a semiconductor substrate, a first electrode and a second electrode, wherein the surface of the semiconductor substrate is provided with a fin part, and the fin part is provided with an edge region and a central region; the metal gate electrode layer is positioned on the top and the side wall of the fin part of the central region; the blocking structure spans the fin part of the edge region; the source drain region is positioned in the fin part between the metal gate electrode layer and the blocking structure; and the first interlayer dielectric layer is positioned on the semiconductor substrate and the fin part, and covers the side wall of the metal gate electrode layer and the side wall of the barrier structure.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the forming method of the fin field effect transistor, the blocking structure is formed before the source drain region is formed, so that the forming space of the source drain region can be limited by the blocking structure and the dummy gate structure together in the process of forming the source drain region, and collapse of a region close to the blocking structure in the source drain region relative to a region close to the dummy gate structure is avoided. And further, after the metal gate electrode layer is formed, the region, close to the blocking structure, in the source-drain region is prevented from collapsing relative to the region close to the metal gate electrode layer, so that the stress of the source-drain region between the blocking structure and the metal gate electrode layer on a corresponding channel is increased.
Secondly, the barrier structure is reserved while the dummy gate electrode layer is removed, so that the metal gate electrode layer does not replace the barrier structure. The barrier structure can be made of a material with better insulating property, so that after a conductive plug positioned between the barrier structure and the metal gate electrode layer is formed subsequently, the parasitic capacitance between the barrier structure and the conductive plug is smaller. Thereby reducing the parasitic capacitance of the finfet.
Further, the step of forming the source and drain regions includes: forming a recess after removing part of the fin part between the pseudo gate structure and the blocking structure; and forming a source and drain region material layer in the recess so as to form a source and drain region. Due to the fact that the blocking structures are formed, the two sides of the recess between the pseudo grid structure and the blocking structures are provided with recess side walls, and the fin portions are exposed out of the recess side walls. Because the fin parts can be exposed from the sunken side walls on the two sides of the recess, the fin parts exposed from the sunken side walls on the two sides of the recess can be used as seeds for growing the source drain region material layer in the process of forming the source drain region material layer, so that the growth rate of the source drain region material layer on one side close to the blocking structure is consistent with that of the source drain region material layer on one side close to the dummy gate structure, and collapse of the region close to the blocking structure in the source drain region relative to the region close to the dummy gate structure is avoided. And further, after the metal gate electrode layer is formed, the region, close to the blocking structure, in the source-drain region is prevented from collapsing relative to the region close to the metal gate electrode layer, so that the stress of the source-drain region between the blocking structure and the metal gate electrode layer on a corresponding channel is increased.
According to the fin type field effect transistor, the fin type field effect transistor is provided with the blocking structure crossing the fin part of the first region, the blocking structure can limit the forming space of the source drain region, and the situation that the region close to the blocking structure in the source drain region is collapsed relative to the region close to the metal gate electrode layer is avoided, so that the stress of the source drain region between the blocking structure and the metal gate electrode layer on a corresponding channel is increased.
Second, the metal gate electrode layer does not replace the location of the barrier structure. The blocking structure can be made of a material with good insulating property, so that the parasitic capacitance of the fin field effect transistor is reduced.
Drawings
Fig. 1 to 4 are schematic structural views of a finfet in one embodiment;
fig. 5-12 are schematic diagrams illustrating a finfet formation process according to an embodiment of the invention.
Detailed Description
As described in the background, the electrical performance of the finfet formed in the prior art is poor.
Fig. 1 to 4 are schematic structural diagrams illustrating a finfet formation process according to an embodiment.
Referring to fig. 1, a semiconductor substrate 100 is provided, the surface of the semiconductor substrate 100 has a fin 120, and the fin 120 includes an edge region I and a central region ii; a dummy gate structure 132 is formed across the center iifin 120 and an additional gate structure 131 is formed across the edge iifin.
The number of dummy gate structures 132 is 3 as an example.
Referring to fig. 2, source drain regions 140 are formed in the fin between adjacent dummy gate structures 132, between dummy gate structures 132 and additional gate structure 131; after forming the source/drain regions 140, a first interlayer dielectric layer 150 is formed on the semiconductor substrate 100 and the fin 120 to cover sidewalls of the dummy gate structure 132 and sidewalls of the additional gate structure 131.
The additional gate structure 131 is formed to function as: in the process of forming the source-drain regions 140 between the additional gate structure 131 and the adjacent dummy gate structures 132, the growth rate of the source-drain region material layer close to the additional gate structure 131 is prevented from being smaller than that of the source-drain region material layer close to the dummy gate structures 132, and the source-drain regions 140 between the additional gate structure 131 and the adjacent dummy gate structures 132 are prevented from collapsing, so that the stress of corresponding channels is prevented from being reduced.
Referring to fig. 3, after the first interlayer dielectric layer 150 is formed, the dummy gate structure 132 and the additional gate structure 131 are removed, and an opening 160 is formed.
Referring to fig. 4, a metal gate structure 170 is formed in the opening 160 (refer to fig. 3); forming a second interlayer dielectric layer 180 on the metal gate structure 170 and the first interlayer dielectric layer 150; a conductive plug 190 penetrating the first interlayer dielectric layer 150 and the second interlayer dielectric layer 180 is formed on the source drain region 140.
The electrical performance of the finfet in the above embodiments is found to be poor due to the following reasons:
since the dummy gate structure 132 is removed and the additional gate structure 131 is also removed, for convenience of description, the opening 160 formed after removing the additional gate structure 131 is referred to as a first opening, and the opening 160 formed after removing the dummy gate structure 132 is referred to as a second opening, so that the metal gate structure 170 is formed in the first opening while the metal gate structure 170 is formed in the second opening. Since the metal gate structure 170 is also formed in the first opening, and the metal gate electrode layer in the metal gate structure 170 is made of metal, the conductivity is relatively high, which easily causes a relatively large parasitic capacitance to be formed between the metal gate electrode layer in the first opening and the conductive plug 190, and significantly increases the parasitic capacitance of the fin field effect transistor.
It can be seen that in the above embodiments, the parasitic capacitance of the finfet is increased while avoiding the stress reduction of the source-drain regions 140 between the additional gate structure 131 and the adjacent metal gate structure 170 on the corresponding channel.
On the basis, the invention provides a method for forming a fin field effect transistor, which comprises the following steps: providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a fin part, and the fin part comprises an edge area and a central area; forming a pseudo gate structure crossing the fin part in the central region and a blocking structure crossing the fin part in the edge region, wherein the pseudo gate structure comprises a pseudo gate electrode layer positioned on the top and the side wall of the fin part; forming a source drain region in the fin part between the pseudo gate structure and the blocking structure; after a source drain region is formed, forming a first interlayer dielectric layer on the semiconductor substrate and the fin portion, wherein the first interlayer dielectric layer covers the side wall of the pseudo gate structure and the side wall of the blocking structure; after the first interlayer dielectric layer is formed, removing the pseudo gate electrode layer to form an opening; and forming a metal gate electrode layer in the opening. According to the method, the blocking structure is formed before the source-drain region is formed, and the blocking structure is reserved when the pseudo gate electrode layer is removed, so that the stress of the source-drain region between the blocking structure and the metal gate electrode layer on a corresponding channel is improved, the parasitic capacitance of the fin field effect transistor is reduced, and the electrical performance of the fin field effect transistor is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5-12 are schematic diagrams illustrating a finfet formation process according to an embodiment of the invention.
Referring to fig. 5, a semiconductor substrate 200 is provided, the surface of the semiconductor substrate 200 has a fin 220, and the fin 220 includes an edge region iii and a central region iv.
The semiconductor substrate 200 provides a process platform for subsequent formation of fin field effect transistors.
The semiconductor substrate 200 may be single crystal silicon, polycrystalline silicon, or amorphous silicon; the semiconductor substrate 200 may be a semiconductor material such as silicon, germanium, silicon germanium, or gallium arsenide. In this embodiment, the material of the semiconductor substrate 200 is silicon.
The semiconductor substrate 200 has a fin portion 220 on a surface thereof.
The fin portion 220 is formed by etching the semiconductor substrate 200; or the following steps: a fin material layer is formed on the semiconductor substrate 200 and then patterned to form the fin 220.
The fin 220 includes an edge region iii and a central region iv.
The edge regions iii are located at two ends of the fin portion 220, and the central region iv is located between the edge regions iii.
An isolation structure is further formed on the surface of the semiconductor substrate 200, the surface of the isolation structure is lower than the top surface of the fin portion 220, and the isolation structure is used for electrically isolating the fin portion 220. The isolation structure is made of silicon oxide or silicon oxynitride.
With continued reference to fig. 5, a dummy gate structure 232 is formed across the center region iv fin 220 and a barrier structure 231 is formed across the edge region iiifin 220, the dummy gate structure 232 including a dummy gate electrode layer 236 on the top and sidewalls of the fin 220.
The dummy gate structure 232 crosses over the fin 220 in the central region iv and covers the top surface and sidewalls of the fin 220 in a portion of the central region iv. The dummy gate structure 232 includes a dummy gate dielectric layer 235 spanning the central region iv fin 220 and a dummy gate electrode layer 236 on a surface of the dummy gate dielectric layer 235. The dummy gate dielectric layer 235 is located on the surface of the isolation structure, and covers the top surface and the sidewalls of the fin portion 220 in the central region iv.
The number of the dummy gate structures 232 may be one or more. In this embodiment, the number of the dummy gate structures 232 is 3 as an example.
The material of the dummy gate electrode layer 236 is polysilicon.
If the opening is formed by removing the dummy gate electrode layer 236, the dummy gate dielectric layer 235 forms a gate dielectric layer after the opening is formed, and therefore the material of the dummy gate dielectric layer 235 is required to be a high-K dielectric material (K is greater than 3.9). If an opening is formed by removing the dummy gate electrode layer 236 and the dummy gate dielectric layer 235, and after the opening is formed, a gate dielectric layer is formed at the bottom and the sidewall of the opening, the material of the dummy gate dielectric layer 235 is silicon oxide.
In this embodiment, an example in which the dummy gate electrode layer 236 and the dummy gate dielectric layer 235 are removed to form an opening is described.
The blocking structure 231 functions as: (1) in the subsequent process of forming a source-drain region between the barrier structure 231 and the adjacent dummy gate structure 232, the growth rate of one side of the source-drain region material layer close to the barrier structure 231 is prevented from being smaller than that of one side close to the dummy gate structure 232, and collapse of the source-drain region between the barrier structure 231 and the adjacent dummy gate structure 232 is prevented; (2) the blocking structure 231 can be made of a material with good insulation, so that after a conductive plug between the blocking structure and the metal gate electrode layer is formed subsequently, the parasitic capacitance between the blocking structure 231 and the conductive plug is small.
The barrier structure 231 has a conductivity of 3.0E-4S/m (siemens/meter) or less.
The conductivity of the barrier structure 231 is selected to be in the range of 3.0E-4S/m or less, taking into account the following factors: if the conductivity of the barrier structure 231 is too high, the insulation property of the barrier structure 231 is deteriorated, and a large parasitic capacitance is formed between the subsequent barrier structure 231 and the conductive plug at the side of the barrier structure 231. In this embodiment, the conductivity of the blocking structure 231 is selected to be less than 3.0E-4S/m, which can make the blocking structure 231 have weak conductivity or insulation, so that the parasitic capacitance between the subsequent blocking structure 231 and the adjacent conductive plug of the blocking structure 231 is small or even zero.
In this embodiment, the dummy gate structure 232 is formed and the blocking structure 231 is formed at the same time, so that the blocking structure 231 includes a blocking gate dielectric layer 233 blocking the fin portion 220 crossing the edge region iii and a blocking gate electrode layer 234 on the blocking gate dielectric layer 233. In other embodiments, the dummy gate structure and the blocking structure may be formed separately in different steps.
The barrier gate dielectric layer 233 is made of silicon oxide or a high-K dielectric material; the material of the blocking gate electrode layer 234 is polysilicon.
Specifically, the method for forming the dummy gate structure 232 and the blocking structure 231 includes: forming a dummy gate dielectric material layer (not shown) and a dummy gate electrode material layer on the surface of the dummy gate dielectric material layer (not shown) on the semiconductor substrate 200 and on the fin portions 220 of the edge region iii and the central region iv; and patterning the dummy gate electrode material layer and the dummy gate dielectric material layer to form a dummy gate structure 232 and a barrier structure 231.
The barrier gate dielectric layer 233 corresponds to the dummy gate dielectric material layer in the edge region iii, and the barrier gate electrode layer 234 corresponds to the dummy gate electrode material layer in the edge region iii; the dummy gate dielectric layer 235 corresponds to the dummy gate dielectric material layer of the central region iv, and the dummy gate electrode layer 236 corresponds to the dummy gate electrode material layer of the central region iv.
Since the barrier structure 231 is formed at the same time as the dummy gate structure 232, the process is simplified.
It should be noted that in other embodiments, the barrier structure may be a single layer material, and the conductivity of the barrier structure is required to be below 3.0E-4S/m.
When the barrier structure is a single-layer material, the material of the barrier structure may be polycrystalline silicon or monocrystalline silicon.
In this embodiment, the first mask layer 240 is formed on the top surfaces of the barrier structure 231 and the dummy gate structure 232.
The first mask layer 240 functions as: (1) the method is used as a hard mask layer in the process of patterning the pseudo gate electrode material layer and the pseudo gate dielectric material layer, so that the pattern distortion of the formed pseudo gate structure 232 and the barrier structure 231 is avoided; (2) in the subsequent process of forming the source and drain regions, the source and drain region material layer is prevented from growing on the top surfaces of the barrier structure 231 and the dummy gate structure 232; (3) the dummy gate structure 232 is then removed by using the first mask layer 240 on the top surface of the blocking structure 231 as a mask.
The first mask layer 240 is made of silicon nitride, silicon oxynitride, or silicon oxycarbonitride.
In this embodiment, the first mask layer 240 is formed at the same time as the barrier gate dielectric layer 233 and the dummy gate structure 232 are formed.
Specifically, after a dummy gate electrode material layer is formed, a first mask material layer is formed on the surface of the dummy gate electrode material layer; the first mask material layer is patterned while the dummy gate electrode material layer and the dummy gate dielectric material layer are patterned to form a dummy gate structure 232, a blocking structure 231, and a first mask layer 240 on the top surfaces of the dummy gate structure 232 and the blocking structure 231.
The first mask layer 240 corresponds to the first mask material layer.
Referring to fig. 6, source and drain regions 250 are formed in fin 220 between dummy gate structure 232 and barrier structure 231.
In this embodiment, since the number of the dummy gate structures 232 is plural, the source/drain regions 250 are also formed in the fin portion 220 between the adjacent dummy gate structures 232.
In this embodiment, the step of forming the source/drain region 250 includes: removing a part of the fin portion 220 between the adjacent dummy gate structures 232 and between the dummy gate structures 232 and the barrier structures 231 to form a recess (not shown); source and drain regions material layers are formed in the recess to form source and drain regions 250.
When the number of the dummy gate structures 232 is one, only a portion of the fin 220 between the dummy gate structures 232 and the blocking structure 231 needs to be removed to form a recess.
The initial source and drain region material layer can be epitaxially grown, and then the initial source and drain region material layer is subjected to ion implantation, so that the source and drain region material layer is formed; or doping ions in situ while growing the initial source and drain region material layer in an epitaxial manner, thereby forming a source and drain region material layer.
It should be noted that, due to the formation of the blocking structure 231, both sides of the recess between the dummy gate structure 232 and the blocking structure 231 have a recess sidewall, and the fin 220 is exposed by the recess sidewall. Because the fin portions 220 can be exposed from the recessed side walls on the two sides of the recess, in the process of forming the source and drain region material layers, the fin portions 220 exposed from the recessed side walls on the two sides of the recess can be used as seeds for growing the source and drain region material layers, so that the growth rate of the source and drain region material layers on one side close to the blocking structure 231 is consistent with that of the source and drain region material layers on one side close to the dummy gate structure 232, and the region close to the blocking structure 231 in the source and drain region 250 is prevented from collapsing relative to the region close to the dummy gate structure 232.
In this embodiment, sidewalls are formed on sidewalls of both sides of the dummy gate structure 232 and sidewalls of the blocking structure 231, and then a source/drain region 250 is formed in the fin portion 220 exposed by the adjacent sidewalls.
The side wall has the following functions: (1) the side walls of the two side walls of the dummy gate structure 232 define the distance between the dummy gate structure 232 and the source drain region 250; (2) in the process of forming the source-drain region 250, the sidewalls of the barrier structure 231 and the dummy gate structure 232 are protected, and a source-drain region material layer is prevented from growing on the sidewalls of the barrier structure 231 and the dummy gate structure 232.
In another embodiment, before forming the source and drain regions, spacers (not shown) are formed only on sidewalls of two sides of the dummy gate structure, and then the source and drain regions are formed in the spacers and the fins on two sides of the dummy gate structure.
Referring to fig. 7, after forming the source and drain regions 250, a first interlayer dielectric layer 260 is formed on the semiconductor substrate 200 and the fin portion 220, wherein the first interlayer dielectric layer 260 covers sidewalls of the dummy gate structures 232 and sidewalls of the blocking structures 231.
In this embodiment, since the first mask layer 240 is formed, the first interlayer dielectric layer 260 covers sidewalls of the dummy gate structures 232, sidewalls of the blocking structures 231, and sidewalls of the first mask layer 240.
The method for forming the first interlayer dielectric layer 260 comprises the following steps: forming a first interlayer dielectric material layer covering the dummy gate structure 232, the blocking structure 231, the first mask layer 240, the fin portion 220 and the semiconductor substrate 200, wherein the whole surface of the first interlayer dielectric material layer is higher than the top surface of the first mask layer 240; the first interlayer dielectric material layer is planarized until the top surface of the first mask layer 240 is exposed, forming a first interlayer dielectric layer 260.
It should be noted that, in this embodiment, after the first interlayer dielectric material layer is formed, the first interlayer dielectric material layer also covers the side wall; and after the first interlayer dielectric material layer is flattened, the formed first interlayer dielectric layer 260 covers the side wall of the side wall.
When the first mask layer is not formed, the entire surface of the first interlayer dielectric material layer is required to be higher than the top surfaces of the dummy gate structure and the blocking structure; and then flattening the first interlayer dielectric material layer until the top surface of the dummy gate structure is exposed, thereby forming a first interlayer dielectric layer.
The material of the first interlayer dielectric layer 260 includes silicon oxide, silicon oxynitride, or silicon oxycarbide.
Next, the dummy gate electrode layer 236 and the dummy gate dielectric layer 235 are removed, and the blocking structure 231 is remained to form an opening.
The steps of removing the dummy gate electrode layer 236 and the dummy gate dielectric layer 235 to form the opening are described in detail below with reference to fig. 8 to 11.
Referring to fig. 8, a second mask layer 270 is formed, wherein the second mask layer 270 covers the first mask layer 240 on the top surface of the blocking structure 231.
The material of the second mask layer 270 includes photoresist.
The second mask layer 270 covers the first mask layer 240 on the top surface of the blocking structure 231, and exposes the first mask layer 240 on the top surface of the dummy gate structure 232.
Referring to fig. 9, the first mask layer 240 on the top surface of the dummy gate structure 232 is removed by using the second mask layer 270 as a mask.
The process of removing the first mask layer 240 on the top surface of the dummy gate structure 232 is a wet etching process or a dry etching process.
Referring to fig. 10, the second mask layer 270 (refer to fig. 9) is removed.
Referring to fig. 11, after removing the second mask layer 270 (refer to fig. 9), the dummy gate electrode layer 236 (refer to fig. 9) and the dummy gate dielectric layer 235 (refer to fig. 9) are removed by using the first mask layer 240 on the top surface of the blocking structure 231 as a mask, so as to form an opening 280.
The first mask layer 240 on the top surface of the barrier structure 231 is used as a mask, and the process of removing the dummy gate electrode layer 236 and the dummy gate dielectric layer 235 is a dry etching process, a wet etching process or a combination of the dry etching process and the wet etching process.
When the dummy gate electrode layer 236 needs to be removed to form an opening, after the second mask layer 270 is removed, the dummy gate electrode layer 236 is removed by using the first mask layer 240 on the top surface of the barrier structure 231 as a mask, so as to form an opening 280.
If the first mask layer 240 is not formed, the dummy gate structure 232 needs to be removed using the second mask layer 270 as a mask. Since the top surface of the dummy gate structure 232 is easily oxidized to form an oxide layer on the top surface of the dummy gate structure 232, an anisotropic dry etching process is generally required to remove the dummy gate structure 232 with a partial thickness, the oxide layer is removed by using a bombardment effect in the anisotropic dry etching process for removing the dummy gate structure 232 with the partial thickness, and then a wet etching process is used to remove the remaining dummy gate structure 232 so as to reduce etching damage to the surface of the fin portion 220 at the bottom of the opening 280. When the second mask layer 270 is used as a mask to remove the dummy gate structure 232, if the second mask layer 270 covers a part of the dummy gate structure 232, the part of the oxide layer and the dummy gate structure 232 with the corresponding thickness at the bottom of the oxide layer cannot be removed in the anisotropic dry etching process for removing the dummy gate structure 232 with a part of the thickness; in the wet etching process for removing the remaining dummy gate structures 232, the second mask layer 270 and the oxide layer both block the removal of the dummy gate structures 232 at the bottom of the second mask layer 270, so that the dummy gate structures 232 are difficult to completely remove.
In this embodiment, the first mask layer 240 on the top surface of the dummy gate structure 232 is removed, and then the first mask layer 240 on the top surface of the blocking structure 231 is used as a mask to remove the dummy gate structure 232, so that the requirement on the position accuracy of the second mask layer 270 can be reduced.
Specifically, since the distance between the blocking structure 231 and the adjacent dummy gate structure 232 is smaller, which is 40nm to 70nm, and is influenced by the precision of the photolithography process, in the process of forming the second mask layer 270, the second mask layer 270 is easily caused to cover the top surface of the blocking structure 231 and also cover the first mask layer 240 and a part of the first mask layer 240 on the top surface of the dummy gate structure 232. Even in the case that the second mask layer 270 covers part of the first mask layer 240 on the top surface of the dummy gate structure 232, since the first mask layer 240 on the top surface of the dummy gate structure 232 has a smaller volume and is located on the dummy gate structure 232, it is easier to expose the first mask layer 240 on the top surface of the dummy gate structure 232 in a corresponding etching environment, and the first mask layer 240 on the top surface of the dummy gate structure 232 can be easily and completely removed. The second masking layer 270 is then removed. After the second mask layer 270 is removed, the dummy gate structure 232 is etched and removed by using the first mask layer 240 on the top surface of the blocking structure 231 as a mask. Since the first mask layer 240 on the top surface of the blocking structure 231 does not cover the dummy gate structure 232, the situation that the dummy gate structure 232 cannot be completely removed is avoided. That is, under the condition that the position accuracy of the second mask layer 270 is poor, the dummy gate structure 232 can be completely removed, so that the requirement on the position accuracy of the second mask layer 270 is reduced in the process.
Referring to fig. 12, a metal gate structure 237 is formed in the opening 280 (see fig. 11); forming a second interlayer dielectric layer 291 on the metal gate structure 237, the barrier structure 231 and the first interlayer dielectric layer 260; and forming a conductive plug 292 penetrating through the first interlayer dielectric layer 260 and the second interlayer dielectric layer 291 on the source drain region 250.
The metal gate structure 237 includes a gate dielectric layer 238 located at the bottom and on the sidewalls of the opening 280 and a metal gate electrode layer 239 located on the gate dielectric layer 238.
The gate dielectric layer 238 is made of a high-K dielectric material (K is greater than 3.9), such as HfO2、La2O3、HfSiON、HfAlO2、ZrO2、Al2O3Or HfSiO4(ii) a The metal gate electrode layer 239 is made of Al, Cu, Ag, Au, Ni, Ti, W, WN or WSi.
The material of the second interlayer dielectric layer 291 includes silicon oxide, silicon oxynitride, or silicon oxycarbide.
The process of forming the second interlayer dielectric layer 291 is a deposition process, such as a plasma chemical vapor deposition process, a low pressure chemical vapor deposition process, or a sub-atmospheric sub-chemical vapor deposition process.
In this embodiment, the second interlayer dielectric layer 291 further covers the first mask layer 240.
The conductive plug 292 is made of a metal, such as tungsten.
The forming process of the conductive plug 292 is as follows: forming a through hole (not shown) penetrating through the first interlayer dielectric layer 260 and the second interlayer dielectric layer 291 on the source drain region 250, wherein the through hole exposes the surface of the source drain region 250; a conductive plug 292 is formed in the via hole.
Under the condition that the dummy gate electrode layer is removed to form an opening, forming a gate dielectric layer by the dummy gate dielectric layer after the opening is formed; then forming a metal gate electrode layer in the opening, wherein the metal gate electrode layer and the gate dielectric layer form a metal gate structure; then forming a second interlayer dielectric layer on the metal grid structure, the blocking structure and the first interlayer dielectric layer; and forming a conductive plug penetrating through the first interlayer dielectric layer and the second interlayer dielectric layer on the source drain region.
Due to the fact that the region, close to the blocking structure 231, in the source-drain region 250 is prevented from collapsing relative to the region close to the dummy gate structure 232, after the metal gate electrode layer 239 is formed, the region, close to the blocking structure 231, in the source-drain region 250 is prevented from collapsing relative to the region close to the metal gate electrode layer 239, and stress of the source-drain region 250 between the blocking structure 231 and the metal gate electrode layer 239 to a corresponding channel is increased.
Second, since the barrier structure 231 is left while the dummy gate electrode layer 236 is removed, the metal gate electrode layer 239 does not replace the barrier structure 231. The blocking structure 231 can be made of a material with good insulation, so that the parasitic capacitance between the blocking structure 231 and the adjacent conductive plug 292 is small, and the parasitic capacitance of the fin field effect transistor is reduced.
Accordingly, an embodiment of the present invention further provides a fin field effect transistor formed by the above method, with reference to fig. 12, including:
the semiconductor device comprises a semiconductor substrate 200, wherein the surface of the semiconductor substrate 200 is provided with a fin part 220, and the fin part 220 is provided with an edge area III and a central area IV; a metal gate electrode layer 239 on the top and sidewalls of the fin 220 in the central region; a blocking structure 231 spanning the fin portion 220 of the edge region iii; source and drain regions 250 in fin 220 between metal gate structure 237 and barrier structure 231; and a first interlayer dielectric layer 260 located on the semiconductor substrate 200 and the fin portion 220, wherein the first interlayer dielectric layer 260 covers sidewalls of the metal gate electrode layer 239 and sidewalls of the barrier structure 231.
The fin field effect transistor further comprises a gate dielectric layer 238, the gate dielectric layer 238 crosses over the fin portion 220 of the central region IV, and the metal gate electrode layer 239 is located on the gate dielectric layer 238.
The gate dielectric layer 238 and the metal gate electrode layer 239 form a metal gate structure 237.
The number of the metal gate structures 237 is one or more. In this embodiment, the number of the metal gate structures 237 is 3 as an example.
The barrier structure 231 has a conductivity of 3.0E-4S/m or less.
In this embodiment, the blocking structure 231 includes a blocking gate dielectric layer 233 blocking the fin 220 crossing the edge region iii and a blocking gate electrode layer 234 on the blocking gate dielectric layer 233.
The barrier gate dielectric layer 233 is made of silicon oxide or a high-K dielectric material; the material of the blocking gate electrode layer 234 is polysilicon.
It should be noted that, in other embodiments, the barrier structure may be a single layer material, and the electrical conductivity of the barrier structure is below 3.0E-4S/m. When the barrier structure is a single-layer material, the material of the barrier structure may be polycrystalline silicon or monocrystalline silicon.
In this embodiment, a first mask layer 240 is formed on the top surface of the blocking structure 231.
The first mask layer 240 is made of silicon nitride, silicon oxynitride, or silicon oxycarbonitride.
The fin field effect transistor further includes: a second interlayer dielectric layer 291, wherein the second interlayer dielectric layer 291 is located on the metal gate structure 237, the barrier structure 231 and the first interlayer dielectric layer 260; and the conductive plug 292 is positioned on the source drain region 250, and the conductive plug 292 penetrates through the first interlayer dielectric layer 260 and the second interlayer dielectric layer 291.
Since the finfet has the first mask layer 240, the second interlayer dielectric layer 291 is located on the metal gate structure 237, the blocking structure 231, the first interlayer dielectric layer 260, and the first mask layer 240.
According to the fin type field effect transistor, the fin type field effect transistor is provided with the blocking structure crossing the fin part of the first region, the blocking structure can limit the forming space of the source drain region, and the situation that the region close to the blocking structure in the source drain region is collapsed relative to the region close to the metal gate electrode layer is avoided, so that the stress of the source drain region between the blocking structure and the metal gate electrode layer on a corresponding channel is increased.
Second, the metal gate electrode layer does not replace the location of the barrier structure. The blocking structure can be made of a material with good insulating property, so that the parasitic capacitance between the blocking structure and the adjacent conductive plug is small, and the parasitic capacitance of the fin field effect transistor is reduced.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (14)

1. A method for forming a fin field effect transistor (FinFET), comprising:
providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a fin part, and the fin part comprises an edge area and a central area;
forming a pseudo gate structure crossing the fin part in the central region and a blocking structure crossing the fin part in the edge region, wherein the pseudo gate structure comprises a pseudo gate electrode layer positioned on the top and the side wall of the fin part;
forming a source drain region in the fin part between the pseudo gate structure and the blocking structure;
after a source drain region is formed, forming a first interlayer dielectric layer on the semiconductor substrate and the fin portion, wherein the first interlayer dielectric layer covers the side wall of the pseudo gate structure and the side wall of the blocking structure;
after the first interlayer dielectric layer is formed, removing the pseudo gate electrode layer to form an opening;
forming a metal gate electrode layer in the opening;
the barrier structure has a conductivity of 3.0E-4S/m or less.
2. The method of claim 1, wherein the blocking structure is formed at the same time as the dummy gate structure.
3. The method of claim 2, wherein the blocking structure comprises a blocking gate dielectric layer spanning the edge region fin and a blocking gate electrode layer overlying the blocking gate dielectric layer.
4. The method of claim 3, wherein the barrier dielectric layer is made of silicon oxide or a high-K dielectric material; the material of the blocking gate electrode layer is polysilicon.
5. The method of claim 1, wherein the blocking structure is formed from monocrystalline silicon or polycrystalline silicon.
6. The method of claim 1, wherein the dummy gate structure comprises a dummy gate dielectric layer crossing the fin portion of the central region and a dummy gate electrode layer on a surface of the dummy gate dielectric layer;
further comprising: after the first interlayer dielectric layer is formed, removing the pseudo gate electrode layer and the pseudo gate dielectric layer to form an opening;
and forming a gate dielectric layer positioned at the bottom and the side wall of the opening and a metal gate electrode layer positioned on the gate dielectric layer in the opening.
7. The method of claim 1, further comprising: forming a second interlayer dielectric layer on the metal gate electrode layer, the barrier structure and the first interlayer dielectric layer; and forming a conductive plug penetrating through the first interlayer dielectric layer and the second interlayer dielectric layer on the source drain region.
8. The method of claim 1, further comprising: a first mask layer is formed on the top surfaces of the blocking structure and the dummy gate structure; after a source drain region is formed, forming a first interlayer dielectric layer on the semiconductor substrate and the fin portion, wherein the first interlayer dielectric layer covers the side wall of the pseudo gate structure, the side wall of the blocking structure and the side wall of the first mask layer; and removing the first mask layer on the top surface of the dummy gate structure in the process of forming the opening.
9. The method of claim 8, wherein the material of the first mask layer comprises silicon nitride, silicon oxynitride, or silicon oxycarbide.
10. The method of claim 8, wherein the method of forming the first mask layer, the blocking structure, and the dummy gate structure comprises:
forming a pseudo gate dielectric material layer, a pseudo gate electrode material layer positioned on the surface of the pseudo gate dielectric material layer and a first mask material layer positioned on the surface of the pseudo gate electrode material layer on the semiconductor substrate and on the fin parts of the edge region and the central region;
and patterning the first mask material layer, the dummy gate electrode material layer and the dummy gate dielectric material layer to form a dummy gate structure crossing the fin part in the central region, a blocking structure crossing the fin part in the edge region and a first mask layer positioned on the top surfaces of the dummy gate structure and the blocking structure.
11. The method of claim 8, wherein the method of forming the opening comprises:
forming a second mask layer, wherein the second mask layer covers the first mask layer on the top surface of the blocking structure;
removing the first mask layer on the top surface of the pseudo gate structure by taking the second mask layer as a mask;
and removing the pseudo gate electrode layer by taking the first mask layer on the top surface of the barrier structure as a mask after removing the second mask layer, thereby forming an opening.
12. The method of claim 11, wherein the material of the second mask layer comprises photoresist.
13. The method of claim 1, wherein the forming the source and drain regions comprises: removing part of the fin part between the pseudo gate structure and the blocking structure to form a recess; and forming a source and drain region material layer in the recess so as to form a source and drain region.
14. A fin field effect transistor formed by the method of any of claims 1 to 13, comprising:
the semiconductor device comprises a semiconductor substrate, a first electrode and a second electrode, wherein the surface of the semiconductor substrate is provided with a fin part, and the fin part is provided with an edge region and a central region;
the metal gate electrode layer is positioned on the top and the side wall of the fin part of the central region;
the barrier structure spans the fin part of the edge region, and the conductivity of the barrier structure is below 3.0E-4S/m;
the source drain region is positioned in the fin part between the metal gate electrode layer and the blocking structure;
and the first interlayer dielectric layer is positioned on the semiconductor substrate and the fin part, and covers the side wall of the metal gate electrode layer and the side wall of the barrier structure.
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