JP2008235925A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce unevenness of gate pattern density in a semiconductor device having a damascence-type or replacement-type gate and to prevent dishing from occurring in a CMP process for making an upper face of a dummy gate exposed. <P>SOLUTION: In a semiconductor device having a damascence-type or replacement-type gate, the unevenness of the gate pattern density is reduced by adding and arranging dummy gates 12a at a position 14 except a gate forming position. Alternatively, the uneveness of the gate pattern density is reduced by arranging an interface transistor or an electrode of capacitance for an analog circuit in place of the dummy gate 12a. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a damascene gate and a replacement gate.

  With the miniaturization of LSI, the gate insulating film has been made thinner, and the reduction in gate capacitance due to the depletion of the polycrystalline silicon gate electrode has become ignorable. In order to solve this, studies have been made to replace the gate electrode with a metal that is not depleted. (For example, see Patent Document 1)

Usually, the source / drain is formed after the formation of the gate electrode. However, metal is more likely to react with a silicon oxide film, a high dielectric film such as Al ₂ O ₃ , HfO _2, etc., as compared with polycrystalline silicon. A method of forming a gate electrode after forming a necessary source / drain has been proposed, which is called a damascene gate or a replace gate. (For example, see Non-Patent Documents 1 and 2)

JP 2001-102443 A A. Yagishita et al., IEDM Tech. Dig. (1998), pp.785-788, etc. A. Chatterjee et al., IEDM Tech. Dig. (1997), pp.821-824, etc.

44 to 54 are process explanatory views for explaining a conventional method of manufacturing a damascene gate and a replace gate in order.
First, as shown in FIG. 44, an element isolation 6a, a P-type well 8, and an N-type well 10 are formed on a semiconductor substrate 1, and a dummy gate oxide film 11 and a polycrystalline silicon film 12 are formed.

  Next, as shown in FIG. 45, a resist pattern 13 is formed by lithography, and dry etching is performed using the resist pattern 13 as a mask to form a dummy gate 12a.

  Next, as shown in FIG. 46, an NMOS low-concentration diffusion layer region (hereinafter referred to as extension) 15, an NMOS pocket ion implantation region (hereinafter referred to as Halo) 16, and a PMOS extension by lithography and ion implantation. 17 and PMOS Halo 18 are formed.

  Next, as shown in FIG. 47, a spacer 19 made of a silicon nitride film is formed. As shown in FIG. 48, an NMOS source / drain 20 and a PMOS source / drain 21 are formed by lithography and ion implantation.

  Next, as shown in FIG. 49, a contact etch stopper film 22 made of a silicon nitride film and an interlayer insulating film 23 made of a silicon oxide film are formed.

Next, as shown in FIG. 50, the interlayer insulating film 23 and the contact etch stopper film 22 are polished by chemical mechanical polishing (hereinafter referred to as CMP) to expose the upper surface of the dummy gate 12a.
Next, as shown in FIG. 51, the gate groove 25 is formed by removing the dummy gate 12a and the dummy gate oxide film 11 (see FIG. 50).

Next, as shown in FIG. 52, a high dielectric insulating film made of Al ₂ O ₃ , HfO ₂ , ZrO ₂ or the like, or SiO ₂ , SiN or the like so as to cover the inside of the gate groove 25 (see FIG. 51). A gate insulating film 26 is formed, and then a first metal film 27 made of TiN or the like is formed. The first metal film determines the threshold value of the MOSFET and the like, and is determined in consideration of the work function and the reactivity with the high dielectric film.

  Further, a second metal film 28 is deposited so as to fill the groove. The second metal is deposited to reduce the resistance of the electrode, and may be a material used for normal wiring, such as W, Al, and Cu.

  Next, as shown in FIG. 53, when a damascene gate is formed, the second metal film 28, the first metal film 27, and the gate insulation deposited outside the gate trench 25 (see FIG. 51). The damascene gate 29 is formed by removing the film 26 by CMP.

In the case of forming a replacement gate, a resist pattern (not shown) is formed by lithography as shown in FIG. 54 instead of the step of FIG. 53, and the second metal is formed by dry etching using this as a mask. The replacement gate 30 is formed by selectively etching the film 28, the first metal film 27, and the gate insulating film 26.
Although not shown in the drawings, an interlayer insulating film is deposited on the damascene gate or the replace gate, and contact formation / wiring formation is performed.

  FIG. 55 shows a cross-sectional view before CMP processing for exposing the upper surface of the dummy gate in a conventional damascene gate forming process. FIG. 56 shows a cross-sectional view after the CMP process for exposing the upper surface of the dummy gate (note that FIG. 55 corresponds to the step of FIG. 49 of the prior art, and FIG. It is a process corresponding to this process).

  In FIG. 55, 1 is a P-type silicon substrate, 7 is a region for forming an N-type channel transistor (hereinafter referred to as an Nch region), and 9 is a region for forming a P-type channel transistor (hereinafter referred to as a Pch region). , Dummy gates 12 a are formed in the Nch region 7 and the Pch region 9. Reference numeral 14 denotes a region where no dummy gate is formed. Reference numeral 8 denotes a P-type well, 10 denotes an N-type well, 6a denotes element isolation, 12a denotes a dummy gate, 22 denotes a contact etch stopper film, and 23 denotes an interlayer insulating film.

As shown in FIG. 56, when the upper surface of the dummy gate 12a is exposed by CMP, the polishing rate of the contact etch stopper film 22 and the interlayer insulating film 23 is different, so in the region 14 where the gate as a transistor is not formed, The film thickness of the interlayer insulating film after CMP is reduced by dishing, and a recess 35 is generated.
Thereafter, in the damascene gate, the dummy gate 12a and the dummy gate oxide film 11 formed thereunder are selectively removed to form a gate groove, and a gate insulating film and a metal film are formed so as to fill the gate groove. The portion formed outside the gate trench is removed again by CMP.

At this time, as shown in FIG. 57, the metal film 35a remains in the depression 35 (see FIG. 56), causing a wiring short circuit or changing the interlayer capacitance. Further, since the CMP pattern dependency due to the dummy gate occupation density occurs, it becomes difficult to control the polishing amount.
As shown in FIG. 58, even in the replacement gate, the metal film 35b remains in the recess 35 (see FIG. 56) in the step of selectively etching the metal film, and the same problem as in the case of the damascene gate is caused. It is thought to occur.

  As described above, according to the conventional technique, in the method for manufacturing a semiconductor device having a damascene gate or a replace gate, a metal film remains in a CMP dishing portion in a region where a dummy gate is not formed, thereby causing a wiring short circuit or the like. There was a problem of causing it.

  The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to obtain a semiconductor device that does not cause a wiring short-circuit in a semiconductor device having a damascene gate or a replace gate. It is another object of the present invention to provide a manufacturing method in which dishing by CMP does not occur on a substrate in a step of exposing a dummy gate of a semiconductor device having a damascene gate or a replace gate.

  The method of manufacturing a semiconductor device according to the present invention is different from the first position where the damascene or replace gate on the main surface of the semiconductor substrate is formed and the first position of the main surface of the semiconductor substrate in that the density of the gate is Forming a dummy gate at a second position that is sparser than the first position; forming an interlayer insulating film covering the dummy gate; and polishing the interlayer insulating film by chemical mechanical polishing. Exposing the upper surfaces of the dummy gates at the first and second positions; selectively removing the dummy gates formed at the first position to form gate grooves; and filling the gate grooves; An electrode film is formed so as to cover the dummy gate at the second position, and the electrode film is selectively removed so that the upper part of the dummy gate formed at the second position is exposed. Forming a gate electrode or forming a replacement gate electrode leaving an electrode wider than the gate groove, and forming an interlayer insulating film and wiring on the damascene or replacement gate electrode And a step of performing.

  Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a dummy gate at a first position for forming a damascene or replacement gate on the main surface of the semiconductor substrate, and a chemical on the main surface of the semiconductor substrate. A step of forming a mechanical polishing stopper film to a thickness close to the thickness of the dummy gate; and the chemical mechanical polishing stopper film by selectively etching the chemical mechanical polishing stopper film to a predetermined thickness. And a step of forming a dummy pattern by the left stopper film at a second position where the gate density is sparser than the first position, unlike the first position, A step of forming an interlayer insulating film on the stopper film and the dummy pattern, and polishing the interlayer insulating film and the stopper film by chemical mechanical polishing. A step of exposing the upper surface of the me gate and the upper surface of the dummy pattern; a step of selectively removing the dummy gate to form a gate groove; and filling the gate groove to form an upper surface of the dummy pattern at the second position. Forming a damascene gate electrode by selectively removing the electrode film so that the upper portion of the dummy pattern formed at the second position is exposed, or And a step of forming a replacement gate electrode leaving an electrode wider than the gate groove, and a step of forming an interlayer insulating film and a wiring on the damascene or replacement gate electrode. And Other features of the present invention are described in detail below.

  According to the present invention, in a method for manufacturing a semiconductor device having a damascene type gate or a replacement type gate, it is possible to obtain a favorable method for manufacturing a semiconductor device in which wiring short-circuit and interlayer capacitance change are suppressed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Embodiment 1 FIG.
1 to 16 are process explanatory views for explaining the semiconductor device manufacturing method according to the first embodiment of the present invention step by step in accordance with the cross section of the semiconductor device.

  In manufacturing a semiconductor device, a P-type silicon substrate or an N-type silicon substrate is generally used. Here, a P-type silicon substrate is used. As an element isolation formation method, after the element region is covered with a silicon nitride film, isolation may be performed by a so-called selective oxidation method (LOCOS) or by a shallow trench isolation method (STI). Here, an example of using STI is shown.

First, as shown in FIG. 1, a buffer thermal oxide film 2 is formed to 20 nm on the main surface of a P-type silicon substrate 1 by a vertical diffusion furnace, and a silicon nitride film 3 is formed to 150 nm on the buffer thermal oxide film 2 by LPCVD. Generate.
Next, although not shown, a resist pattern is formed on the silicon nitride film 3 by lithography, and the silicon nitride film 3 and the buffer thermal oxide film 2 are selectively etched using this as a mask.

  Next, as shown in FIG. 2, the trench 4 is formed in the P-type silicon substrate 1 at a depth of about 350 nm by reactive ion etching using the selectively etched silicon nitride film 3a and the buffer thermal oxide film 2a as a mask. To do. Next, in order to remove the plasma damage layer formed on the inner wall of the trench 4, the inner wall of the silicon is oxidized in a diluted oxygen atmosphere at 1100 ° C., and a liner oxide film 5 is formed with a film thickness of 20 nm by a vertical diffusion furnace.

  Next, as shown in FIG. 3, a buried oxide film 6 is formed with a thickness of 600 nm by high-density plasma CVD so as to fill the trench 4 (see FIG. 2). At this time, the trench 4, the selectively etched silicon nitride film 3a, and the buffer thermal oxide film 2a (see FIG. 2) are completely filled with the buried oxide film 6, and sufficient flatness is obtained by CMP in the next process. The film thickness is set as follows.

  Next, as shown in FIG. 4, the buried oxide film 6 is polished by CMP to expose the upper surface of the silicon nitride film 3a.

  Next, as shown in FIG. 5, the silicon nitride film 3a (see FIG. 4) is entirely removed with hot phosphoric acid, and the buffer thermal oxide film 2a (see FIG. 4) is further removed with a dilute hydrofluoric acid aqueous solution to separate the elements. 6a is formed.

Next, although not shown, a resist pattern is formed at a position other than the P-type well formation region by lithography, and ion implantation of P-type impurities is performed using this as a mask. In order to make the impurity concentration inside the well uniform, ion implantation is performed in three steps. First time, boron acceleration voltage 400 keV, carried out at a dose of 5 × ¹⁰ 12 ^{cm -2,} a second time, boron acceleration voltage 250 keV, carried out at a dose of 5 × ¹⁰ 12 ^{cm -2,} 3 th Is performed under conditions of an acceleration voltage of 40 keV and a dose of 5 × 10 ¹² cm ⁻² .

In order to adjust the threshold voltage of the Nch transistor, boron ion implantation is performed under the conditions of an acceleration voltage of 20 keV and a dose of 5 × 10 ¹² cm ⁻² , and a P-type well 8 is formed in the Nch region 7 as shown in FIG. Form.

Next, although not shown, a resist pattern is formed at a position other than the N-type well formation region by lithography, and N-type impurity ions are implanted using the resist pattern as a mask. In order to make the impurity concentration inside the well uniform, ion implantation is performed in three steps. The first time is phosphorous under conditions of acceleration voltage 600 keV and dose amount 5 × 10 ¹² cm ⁻² , and the second time is phosphorous under conditions of acceleration voltage 300 keV and dose amount 5 × 10 ¹² cm ⁻² Arsenic is performed under the conditions of an acceleration voltage of 150 keV and a dose of 5 × 10 ¹² cm ⁻² .

Further, for adjusting the threshold voltage of the Pch transistor, arsenic ion implantation is performed under conditions of an acceleration voltage of 100 keV and a dose of 2 × 10 ¹² cm ⁻² , and as shown in FIG. Form.

Next, a dummy gate oxide film 11 is formed with a film thickness of about 5 nm by a vertical diffusion furnace. Further, the polycrystalline silicon film 12 is formed with a film thickness of about 200 nm by LPCVD.
At this time, silicon germanium or the like may be used instead of the polycrystalline silicon film as the material of the dummy gate.

  Next, as shown in FIG. 7, a resist pattern 13 is formed at each gate formation position of the Nch region 7 and the Pch region 9 and a region 14 where a gate as a transistor is not formed by lithography. Etching is performed to form a dummy gate 12a in the Nch region 7, the Pch region 9, and the region 14 where a gate as a transistor is not formed.

  At this time, the dummy gate 12a is formed with the line width = 0.2 μm and the space width = 0.5 μm at the gate forming position of the Nch region 7 and the Pch region 9 and the position 14 where the gate as a transistor is not formed. Yes. Therefore, the pattern density of the dummy gate 12a is almost constant in any of the Nch region 7, the Pch region 9, and the region 14 where a gate as a transistor is not formed.

Next, although not shown, a resist pattern is formed by lithography at a position other than the Nch region 7.
Next, ion implantation of Nch extension and Nch Halo is performed. The ion implantation of the Nch extension is performed under the conditions of an acceleration voltage of 20 keV and a dose amount of 2 × 10 ¹⁴ cm ⁻² . In addition, Nch Halo ion implantation is performed under the conditions of an acceleration voltage of 25 keV, a dose amount of 1 × 10 ¹³ cm ⁻² , and an implantation angle of about 30 °, and as shown in FIG. 15, Nch Halo 16 is formed.

  Next, although not shown, a resist pattern is formed by lithography at positions other than the Pch region 9.

Next, Pch extension and Pch Halo ion implantation are performed. The ion implantation of the Pch extension is performed using boron difluoride under the conditions of an acceleration voltage of 15 keV and 3 × 10 ¹³ cm ⁻² . In addition, Pch Halo ion implantation is performed under the conditions of an arsenic acceleration voltage of 150 keV, a dose of 1 × 10 ¹³ cm ⁻² , and an implantation angle of about 30 °. As shown in FIG. 17. Form Pch Halo18.

  Next, as shown in FIG. 9, a silicon nitride film of about 100 nm is formed by LPCVD, and by reactive ion etching, the Nch region 7, the Pch region 9, and the dummy gate 12a in the region 14 where a gate as a transistor is not formed are formed. A spacer 19 made of a silicon nitride film is formed on the side wall.

  Next, although not shown, a resist pattern is formed by lithography at a position other than the Nch region 7. Using this resist pattern as a mask, ion implantation for source / drain formation is performed in the Nch region 7.

Nch source / drain ion implantation is performed under the conditions of an arsenic acceleration voltage of 50 keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² to form an Nch source / drain 20 in the Nch region 7 as shown in FIG.
At this time, since the high concentration region is not formed by the spacer 19 in the vicinity of the gate edge, it is possible to prevent deterioration of the MOS characteristics due to hot electrons in the vicinity of the drain.

  Next, although not shown, a resist pattern is formed by lithography at positions other than the Pch region 9. Using this resist pattern as a mask, ion implantation for source / drain formation is performed in the Pch region 9.

The ion implantation of the Pch source / drain is performed under the conditions of boron at an acceleration voltage of 10 keV and a dose of 5 × 10 ¹⁵ cm ⁻² to form a Pch source / drain 21 in the Pch region 9 as shown in FIG.
At this time, since the high concentration region is not formed in the vicinity of the gate edge by the spacer 19, it is possible to prevent the deterioration of the characteristics of the MOS due to hot electrons in the vicinity of the drain.

  Next, as shown in FIG. 11, a contact etch stopper film 22 made of a silicon nitride film is formed by LPCVD so as to cover the Nch region 7, the Pch region 9, and the entire region 14 where a gate as a transistor is not formed by LPCVD. Form. Further, an interlayer insulating film 23 made of a silicon oxide film is formed on the stopper film 22 for contact etching by about 300 to 500 nm by atmospheric pressure CVD.

Next, as shown in FIG. 12, the interlayer insulating film 23 and the contact etch stopper film 22 are polished by CMP, and the Nch region 7, the dummy gate 12 a of the Pch region 9, and the region 14 where the gate as a transistor is not formed are formed. The upper surface of the dummy gate 12a is exposed.
At this time, the heights of the dummy gates 12a in the Nch region 7 and the Pch region 9 and the dummy gate 12a in the region 14 where the gate as a transistor is not formed are substantially the same, and the dummy gate 12a on the P-type silicon substrate 1 Since the pattern density is almost constant everywhere, it has a flat shape without dishing by CMP.

  Next, as shown in FIG. 13, a resist pattern 24 is formed by lithography so as to cover the entire region 14 where a gate as a transistor is not formed. Using this as a mask, dummy gate 12a and dummy gate oxide film 11 (see FIG. 12) in Nch region 7 and Pch region 9 are selectively removed by reactive ion etching to form gate trench 25.

  Next, as shown in FIG. 14, a gate insulating film 26 made of a high-k film, a silicon nitride film, or the like is formed to have a thickness of 5 nm so as to cover the inside of the gate trench 25 (see FIG. 13). Next, a 5 nm thick first metal film 27 made of TiN is formed on the inner surface of the groove-like gate insulating film 26. At this time, the first metal film 27 also leaves a groove. Further, a second metal film 28 made of tungsten is formed to have a thickness of 300 nm so as to fill the groove of the first metal film 27 in order to reduce electric resistance.

  Next, as shown in FIG. 15, the second metal film 28, the first metal film 27, and the gate insulating film 26 formed outside the gate groove 25 (see FIG. 13) of the Nch region 7 and the Pch region 9. Is removed by CMP to form a damascene gate 29.

  In the step shown in FIG. 13, the resist pattern 24 is formed in the region 14 where the gate as a transistor is not formed. However, the dummy gate in the region 14 where the gate as a transistor is not formed without forming this resist pattern. You may make it form in a type | mold.

  Further, in place of the process of FIG. 15, as shown in FIG. 16, after forming the gate insulating film 26, the first metal film 27, and the second metal film 28, the gates of the Nch region 7 and the Pch region 9 are formed by lithography. A resist pattern (not shown) wider than the gate width is formed at the formation position, the second metal film 28, the first metal film 27, and the gate insulating film 26 are selectively etched by dry etching, and the replacement gate 30 is formed. You may make it form.

  Thereafter, in both cases of forming a damascene gate and a replacement gate, a second interlayer insulating film is deposited thereon to form a contact and a wiring. Since these steps are known in this field, description thereof will be omitted.

  As described above, in this embodiment, in the method of manufacturing a semiconductor device for forming a damascene gate or a replacement gate structure, a transistor other than a dummy gate for forming a damascene gate or a replacement gate is used. A dummy gate is additionally formed in the region where the gate is not formed. In this way, the density difference in the distribution of the patterns of the plurality of dummy gates is reduced in any part on the substrate, so that dishing that occurs in the CMP process that exposes the upper surface of the dummy gates is suppressed, and damascene It is possible to obtain a semiconductor device and a method of manufacturing the same capable of forming a good wiring without wiring short-circuiting or interlayer capacitance change in the mold gate forming process.

  In other words, a dummy pattern for forming a damascene gate electrode or a replacement electrode and a dummy pattern added to the dummy pattern in any part on the substrate, and the total occupation of the dummy pattern in each part. The areas are the same or substantially the same, thereby eliminating or improving the CMP pattern dependency.

As understood from the above description, the damascene gate electrode is a dummy gate oxide film and a dummy gate formed at the gate formation position, and substantially the same height as the dummy gate at a position other than the gate formation position. Forming a gate insulating film on the bottom and side walls of the recess at the gate forming position formed by removing the dummy gate and the dummy gate oxide film, and forming a groove formed by the gate insulating film Refers to an electrode having a structure embedded with an electrode film.
The replacement gate electrode is formed by forming a dummy gate oxide film and a dummy gate at a gate formation position, and forming an interlayer insulating film at a position substantially the same as the dummy gate at a position other than the gate formation position. A gate insulating film is formed on the bottom and side walls of the recess at the gate forming position formed by removing the gate and dummy dummy gate oxide film, and the groove formed by this gate insulating film is filled with the electrode film, and the gate insulating film And an electrode having a structure in which the electrode film is laminated in a lateral direction for a predetermined length in a state where the electrode film is connected to the upper part and the outside of the concave part at the gate formation position.

  Next, the semiconductor device manufactured according to this embodiment has a structure as shown in FIG. That is, the semiconductor device according to the present embodiment is a semiconductor device having a damascene gate electrode or a replace type electrode in which the gate electrode is formed of a metal material, and the position where the damascene type gate electrode or the replace type electrode is not formed. In this case, dummy pattern electrodes are formed.

  In other words, the damascene gate electrode or the replace-type electrode and the damascene-type gate electrode or the replace-type electrode are arranged in such a manner that the depression of the insulating film as shown in FIG. In the electrode distribution as a whole including the added dummy pattern electrodes, the density difference of the distribution is reduced.

Embodiment 2. FIG.
FIGS. 17-24 are process explanatory views for explaining the semiconductor device manufacturing method according to the second embodiment of the present invention step by step through the cross section of the semiconductor device.

  The element isolation is formed according to the manufacturing method of the first embodiment.

  Thereafter, as shown in FIG. 17, element isolation 6a is formed on the main surface of P-type silicon substrate 1, and P-type well 8 and N-type well 10 are formed in Nch region 7 and Pch region 9 by lithography and ion implantation, respectively. Form. Next, a dummy gate oxide film 11 and a dummy gate 12a are formed in the Nch region 7 and the Pch region 9, respectively. Reference numeral 5 denotes a liner oxide film.

  Next, an Nch extension 15 and an Nch Halo 16 are formed in the Nch region 7 by lithography and ion implantation, and a Pch extension 17 and a Pch Halo 18 are formed in the Pch region 9.

  Next, a silicon nitride film is formed to a thickness of 100 nm by LPCVD, and a spacer 19 made of a silicon nitride film is formed on the side walls of the dummy gate 12a in the Nch region 7 and the Pch region 9 by reactive ion etching.

Next, Nch source / drain 20 is formed in Nch region 7 and Pch source / drain 21 is formed in Pch region 9 by lithography and ion implantation.
At this time, no dummy pattern is formed in the region 14 where a gate as a transistor is not formed.

  Next, as shown in FIG. 18, a silicon nitride film 22 is formed with a thickness of about 200 nm by LPCVD. At this time, the film thickness of the silicon nitride film 22 is set to be slightly thinner than the total 205 nm of the film thickness of the dummy gate oxide film 11 and the film thickness of the dummy gate 12a of 200 nm.

  Next, as shown in FIG. 19, a resist pattern 13 is formed with a line width = about 0.2 μm and a space width = about 0.5 μm by lithography in a region 14 where a gate as a transistor is not formed. Next, using this as a mask, the silicon nitride film 22 is selectively etched to form a dummy pattern 22a made of a silicon nitride film in a region 14 where a gate as a transistor is not formed. At this time, the dummy patterns 22a are arranged with substantially the same density as the dummy gates 12a of the Nch region 7 and the Pch region 9.

  At this time, in the selective etching of the silicon nitride film 22, a predetermined thickness is etched so that the CMP stopper film remains in the Nch region 7 and the Pch region 9 to a certain thickness. Specifically, etching is performed by a predetermined film thickness so that only the film thickness of 30 nm of the CMP stopper film 22 used in the first embodiment remains.

  By performing this etching, a dummy pattern 22a made of a silicon nitride film is formed in the region 14 where a gate as a transistor is not formed. The height of the dummy pattern 22a is close to the height of the dummy gate 12a and is slightly lower. Further, since the silicon nitride film is left with a film thickness of about 30 nm at a position other than the position where the dummy pattern 22a is formed, it corresponds to the contact etch stopper film 22 of the first embodiment and serves as a CMP stopper film. Function.

  Next, as shown in FIG. 20, an Nch region 7, a Pch region 9, and a region 14 where a gate as a transistor is not formed, that is, an interlayer insulating film 23 made of a silicon oxide film is formed on the entire surface by an atmospheric pressure CVD to 300 to 500 nm. Form about.

  Next, as shown in FIG. 21, the interlayer insulating film 23 and the CMP stopper film 22 are polished by CMP to expose the upper surfaces of the dummy gates 12 a in the Nch region 7 and the Pch region 9.

  At this time, the height of the dummy pattern 22a in the region 14 where the gate as a transistor is not formed is approximately the same as or slightly lower than the height of the dummy gate 12a in the Nch region 7 and the Pch region 9, and as a transistor The total density of the dummy pattern 22a in the region 14 where no gate is formed and the dummy gate 12a in the Nch region 7 and the Pch region 9 is almost constant at any location on the P-type silicon substrate 1. It has a flat shape without dishing by CMP. Here, the upper surface of the dummy pattern 22a is not necessarily exposed.

  Next, as shown in FIG. 22, the dummy gate 12 a and the dummy gate oxide film 11 (see FIG. 21) in the Nch region 7 and the Pch region 9 are selectively removed by reactive ion etching to form a gate groove 25. .

  Next, as shown in FIG. 23, a gate insulating film 26 made of a high-k film, a silicon nitride film, or the like is formed to have a thickness of 5 nm so as to cover the inside of the gate trench 25 (see FIG. 22). Next, a 5 nm thick first metal film 27 made of TiN is formed on the inner surface of the groove-like gate insulating film 26. At this time, the first metal film 27 also leaves a groove. Further, a second metal film 28 made of tungsten is formed to have a thickness of 300 nm so as to fill the groove of the first metal film 27 in order to reduce electric resistance.

Next, as shown in FIG. 24, the second metal film 28, the first metal film 27, and the gate insulating film 26 formed outside the gate groove 25 (see FIG. 22) of the Nch region 7 and the Pch region 9. Is removed by CMP to form a damascene gate 29.
Although an example of a damascene gate is shown here, it may be formed by a replacement gate system as shown in the first embodiment.

As described above, in this embodiment, in the semiconductor device having a damascene gate or replace gate structure and its manufacturing method, a region where a gate as a transistor is not formed is also made of the same material as the CMP stopper film. A dummy pattern was added to form. In this way, the dummy pattern is arranged at the same density as the dummy gate at the position where the gate as the transistor is formed in the region where the gate as the transistor is not formed.
Accordingly, dishing can be suppressed in the CMP process that exposes the upper surface of the dummy gate, and a semiconductor device and a manufacturing method thereof can be obtained in which a good wiring can be formed without a wiring short-circuit and interlayer capacitance change in the damascene gate forming process.

Embodiment 3 FIG.
25 to 32 are process explanatory views for explaining the semiconductor device manufacturing method according to the third embodiment of the present invention step by step in accordance with the cross section of the semiconductor device.

  In FIG. 25, the same manufacturing method as in the first embodiment is used until the element isolation 6 a is formed on the main surface of the P-type silicon substrate 1.

Thereafter, as shown in FIG. 25, an area for forming an internal circuit (hereinafter referred to as an internal circuit area) 30 and an I / O circuit are formed on the main surface of the P-type silicon substrate 1 by lithography and ion implantation. A P-type well 8 and an N-type well 10 are formed in a region (hereinafter referred to as an I / O circuit region) 31 to be formed. The ion implantation for forming each well is performed under the same conditions as in the first embodiment.
Next, the gate oxide film 11 is formed with a thickness of 5 nm by a vertical diffusion furnace, and the polycrystalline silicon film 12 is formed with a thickness of 200 nm by LPCVD.

  Next, as shown in FIG. 26, a resist pattern 13 is formed in the internal circuit region 30 and the I / O circuit region 31 by lithography. Next, using this as a mask, dry etching is performed to form a dummy gate 12 a in the internal circuit region 30 and a gate 12 b in the I / O circuit region 31. At this time, the gate 12b of the I / O circuit is arranged in the I / O circuit region 31 so as to eliminate the density difference of the distribution of the dummy gate 12a on the entire P-type silicon substrate 1.

  Next, as shown in FIG. 27, an Nch extension 15 and a Pch extension 17 are formed in the internal circuit region 30 by lithography and ion implantation, and an Nch extension 15 and a Pch extension 17 are formed in the I / O circuit region 31. Form.

  Next, a silicon nitride film is formed to 100 nm by LPCVD, and reactive ion etching is performed, so that a spacer of the silicon nitride film is formed on the side wall of the dummy gate 12a in the internal circuit region 30 and the side wall of the gate 12b in the I / O circuit region 31. 19 is formed.

Next, the Nch source / drain 20 and the Pch source / drain 21 are formed in the internal circuit region 30 by lithography and ion implantation, and the Nch source / drain 20 and the Pch source / drain are formed in the I / O circuit region 31. 21 is formed.
At this time, the ion implantation for forming the extension and source / drain formed in the internal circuit region 30 and the I / O circuit region 31 is performed under the same conditions as in the first embodiment.

  Next, as shown in FIG. 28, a contact etch stopper film 22 made of a silicon nitride film is formed to about 30 nm by LPCVD. Further, an interlayer insulating film 23 made of a silicon oxide film is formed to about 300 to 500 nm by atmospheric pressure CVD.

  Next, as shown in FIG. 29, the interlayer insulating film 23 and the contact etch stopper film 22 are polished by CMP to expose the upper surfaces of the dummy gate 12a in the internal circuit region 30 and the gate 12b in the I / O circuit region 31. Let

  At this time, the height of the dummy gate 12a in the internal circuit region 30 and the gate 12b in the I / O circuit region 31 are substantially the same, and the dummy gate 12a in the internal circuit region 30 and the I / O circuit region 31 have the same height. Since the total density of the gates 12b is almost constant on the P-type silicon substrate 1, it has a flat shape without dishing by CMP.

  Next, as shown in FIG. 30, a resist pattern 24 is formed by lithography in a region other than the internal circuit region 30. Next, the dummy gate 12a and the gate oxide film 11 (see FIG. 29) in the internal circuit region 30 are selectively removed to form the gate trench 25.

  Next, as shown in FIG. 31, a gate insulating film 26 made of a high-k film, a silicon nitride film, or the like is formed to have a thickness of 5 nm so as to cover the inside of the gate trench 25 (see FIG. 30). Next, a 5 nm thick first metal film 27 made of TiN is formed on the inner surface of the groove-like gate insulating film 26. At this time, the first metal film 27 also leaves a groove. Further, a second metal film 28 made of tungsten is formed to have a thickness of 300 nm so as to fill the groove of the first metal film 27 in order to reduce electric resistance.

  Next, as shown in FIG. 32, the second metal film 28, the first metal film 27, and the gate insulating film 26 formed outside the gate groove 25 (see FIG. 30) in the internal circuit region 30 are formed by CMP. Then, a damascene gate 29 is formed in the internal circuit region 30 and an I / O circuit transistor 32 is formed in the I / O circuit region 31.

  Although an example of a damascene gate is shown here, the damascene gate in the internal circuit region 30 may be formed by a replace gate system as described in the first embodiment.

  According to the above manufacturing method, the number of processes is increased by forming the transistors of the I / O circuit by using the dummy gate forming process in the process of manufacturing the damascene transistor and the replacement transistor constituting the internal circuit. Without this, transistors of an I / O circuit having different internal circuits, gate insulating films, and threshold values (Vt) can be formed.

  Thereafter, as in the first embodiment, a second interlayer insulating film is deposited to form contacts and wirings.

As described above, in this embodiment, in a semiconductor device having a damascene gate or a replace gate structure and a manufacturing method thereof, a dummy gate is disposed at a position where a gate as a transistor in a region used as an internal circuit is formed. In a region not used as an internal circuit, a gate electrode used in an I / O circuit is arranged so that the pattern density is not biased.
In this way, it is possible to obtain a semiconductor device and a method for manufacturing the same, in which dishing is suppressed in the CMP process for exposing the upper surface of the dummy gate, and there is no wiring short-circuit and no change in interlayer capacitance. Further, since the damascene gate dummy pattern and the gate electrode used in the I / O circuit can be formed at the same time, the process can be simplified.

Embodiment 4 FIG.
33 to 43 are process explanatory views for explaining the semiconductor device manufacturing method according to the fourth embodiment of the present invention step by step in accordance with the cross section of the semiconductor device.

  The element isolation is formed according to the manufacturing method of the first embodiment.

  Thereafter, as shown in FIG. 33, element isolation 6a is formed on the main surface of P-type silicon substrate 1, and P-type well 8 and N-type well 10 are formed in Nch region 7 and Pch region 9 by lithography and ion implantation, respectively. Form. Next, the gate oxide film 11 is formed to 5 nm by a vertical diffusion furnace, and the polycrystalline silicon film 12 is formed to 200 nm by LPCVD.

  Next, as shown in FIG. 34, a resist pattern 13 is formed in each of the Nch region 7, the Pch region 9, and a region 33 for forming an analog circuit capacitor (hereinafter referred to as an analog circuit capacitor region). Using this as a mask, the dummy gate 12a is formed in the Nch region 7 and the Pch region 9 by dry etching, and the analog circuit capacitor gate electrode 12c is formed in the analog circuit capacitor region 33.

  Next, as shown in FIG. 35, an Nch extension 15 is formed in the Nch region 7 and a Pch extension 17 is formed in the Pch region 9 by lithography and ion implantation. Next, a silicon nitride film is formed to a thickness of about 100 nm by LPCVD, and a silicon nitride film is formed on the sidewalls of the dummy gate 12a in the Nch region 7 and the Pch region 9 and the capacitor gate electrode 12c in the analog circuit capacitor region 33 by reactive ion etching. A spacer 19 is formed.

  Next, an Nch source / drain 20 is formed in the Nch region 7 and a Pch source / drain 21 is formed in the Pch region 9 by lithography and ion implantation. At this time, the extension formed in each region and the ion implantation for forming the source / drain are performed under the same conditions as in the first embodiment.

  Next, as shown in FIG. 36, a contact etch stopper film 22 made of a silicon nitride film is formed to a thickness of about 30 nm by LPCVD so as to cover the Nch region 7, the Pch region 9, and the analog circuit capacitance region 33, that is, the whole. Further, an interlayer insulating film 23 made of a silicon oxide film is formed on the stopper film 22 for contact etching by about 300 to 500 nm by atmospheric pressure CVD.

  Next, as shown in FIG. 37, the interlayer insulating film 23 and the contact etch stopper film 22 (see FIG. 36) are polished by CMP, and the upper surface of the dummy gate 12a in the Nch region 7 and the Pch region 9 and the analog circuit capacitance The upper surface of the analog circuit capacitor electrode 12c in the region 33 is exposed.

  At this time, the height of the dummy gate 12a in the Nch region 7 and the Pch region 9 is substantially the same as that of the capacitor electrode 12c in the analog circuit capacitor region 33, and the capacitor electrode 12c is disposed in the analog circuit capacitor region 33. Since the density difference on the P-type silicon substrate 1 is relieved as compared with the case where there is no capacitor electrode, the dishing by CMP is suppressed and the shape is flat.

  Next, as shown in FIG. 38, a resist pattern 24 is formed so as to cover the upper surface of the analog circuit capacitance region 33 by lithography, and the dummy gate 12a and the gate oxide film 11 (in the Nch region 7 and the Pch region 9 are formed by dry etching. 37) is selectively removed to form a gate trench 25.

Next, as shown in FIG. 39, a resist pattern 24 is formed in the Nch region 7 and the Pch region 9 by lithography, and half the film thickness of the analog circuit capacitor electrode 12c, that is, about 100 nm is selectively formed by dry etching. Etching is performed to form a groove 12d of the capacitor electrode for analog circuits.
As shown in the first to third embodiments, in the case where a replacement gate electrode is formed in the Nch region 7 and the Pch region 9, a step of forming a groove for the analog circuit capacitor electrode in the analog circuit capacitor region 33 ( The step of FIG. 39 may be omitted.
Further, in this embodiment, the step of forming the gate groove shown in FIG. 38 is performed first, and then the step of forming the groove of the capacitor electrode for analog circuit shown in FIG. 39 is performed. You may form by changing process order.

  Next, as shown in FIG. 40, a high-k film, a silicon nitride film, or the like is formed so as to cover the inside of the gate groove 25 (see FIG. 38) and the analog circuit capacitor electrode groove 12d (see FIG. 39). A 5 nm thick gate insulating film 26 is formed. Next, a 5 nm thick first metal film 27 made of TiN is formed on the inner surface of the groove-like gate insulating film 26. At this time, the first metal film 27 also leaves a groove. Further, a second metal film 28 made of tungsten is formed to have a thickness of 300 nm so as to fill the groove of the first metal film 27 in order to reduce electric resistance.

  Next, as shown in FIG. 41, the second metal film 28 and the first metal film 27 formed outside the gate groove 25 (see FIG. 38) and the analog circuit capacitor electrode groove 12d (see FIG. 39). The gate insulating film 26 is removed by CMP, a damascene gate 29 is formed in the Nch region 7 and the Pch region 9, and an analog circuit capacitor 34 is formed in the analog circuit capacitor region 33.

  Although an example of a damascene gate is shown here, the gates of the Nch region 7 and the Pch region 9 may be formed by a replace gate method as described in the first embodiment. At this time, as described above, the step of forming the groove of the analog circuit capacitor electrode in the analog circuit capacitor region 33 can be omitted. In this case, the structure shown in FIG. In FIG. 42, 30 is a replacement type gate, and 34a is an analog circuit capacitor.

  According to the manufacturing method as described above, the analog circuit capacitor can be formed without increasing the number of processes by using the dummy gate transistor forming process in the process of manufacturing the damascene transistor or the replacement transistor.

  Thereafter, as in the first embodiment, a second interlayer insulating film is deposited to form contacts and wirings.

  In this embodiment, as shown in FIGS. 41 and 42, the analog circuit capacitor 34 or 34a is formed in the active region. However, as shown in FIG. You may make it form in 6a (field) area | region. As described above, by forming the analog circuit capacitor on the element isolation, it is possible to improve the noise resistance through the P-type silicon substrate 1.

As described above, according to this embodiment, in a semiconductor device having a damascene type gate or a replacement type gate structure, a dummy gate is arranged at a position where a gate as a transistor in a region used as an internal circuit is formed, Capacitance electrodes used in analog circuits are arranged in areas not used as circuits so that the pattern density is not biased.
In this way, dishing that occurs in the CMP process that exposes the upper surface of the dummy gate is suppressed, and a semiconductor device capable of forming a favorable wiring without wiring short-circuit and interlayer capacitance change in the damascene gate forming process and its manufacture A method can be provided.
In addition, since the damascene gate dummy pattern and the capacitor electrode used in the analog circuit can be formed at the same time, the process can be simplified. Further, by forming the analog circuit capacitor on the element isolation, it is possible to improve the noise resistance through the semiconductor substrate.

  In order to eliminate the density difference between the damascene type gate and the replacement type gate, the gate electrode used in the I / O circuit is arranged in the third embodiment, and the gate electrode of the capacitor for the analog circuit is arranged in the fourth embodiment. Arranged. However, the electrodes disposed to eliminate the density difference between the damascene gate and the replace gate are not limited to these, and electrodes of other circuit elements may be disposed.

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Sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 4 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 4 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 4 of this invention. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device. Sectional drawing which shows the manufacturing method of the conventional semiconductor device.

Explanation of symbols

  1 P-type silicon substrate, 2 buffer thermal oxide film, 3 silicon nitride film, 5 liner oxide film, 6a element isolation, 7 Nch region, 8 P-type well, 9 Pch region, 10 N-type well, 11 dummy gate oxide film or Gate oxide film, 12a dummy gate, 12b gate of I / O circuit, 12c gate electrode of capacitor for analog circuit, 12d groove of capacitor electrode for analog circuit, 14 region not forming gate as transistor, 19 spacer, 22 contact etch Stopper film or CMP stopper film 23 interlayer insulating film, 25 gate trench, 26 gate insulating film, 27 first metal film, 28 second metal film, 29 damascene gate, 30 replace gate, 32 I / O Circuit gate, 34 Analog circuit Capacity.

Claims (2)

Unlike the first position of the damascene or replacement gate on the main surface of the semiconductor substrate and the first position of the main surface of the semiconductor substrate, the density of the gate is sparser than the first position. Forming a dummy gate at each of the positions,
Forming an interlayer insulating film covering the dummy gate;
Polishing the interlayer insulating film by chemical mechanical polishing to expose the upper surfaces of the dummy gates at the first and second positions;
Selectively removing the dummy gate formed at the first position to form a gate groove;
An electrode film is formed so as to fill the gate groove and cover the dummy gate at the second position, and selectively expose the upper part of the dummy gate formed with the electrode film at the second position. Forming a damascene gate electrode by removing, or forming a replacement gate electrode leaving an electrode wider than the gate groove;
Forming an interlayer insulating film and wiring on the damascene or replacement gate electrode;
A method for manufacturing a semiconductor device, comprising: Forming a dummy gate at a first position for forming a damascene or replacement gate on the main surface of the semiconductor substrate;
Forming a chemical mechanical polishing stopper film on the semiconductor substrate main surface to a thickness close to the thickness of the dummy gate;
The chemical mechanical polishing stopper film is selectively etched to a predetermined thickness to leave the chemical mechanical polishing stopper film to a certain thickness, and the density of the gate is different from the first position. Forming a dummy pattern with the remaining stopper film at a second position that is sparser than the first position;
Forming an interlayer insulating film on the stopper film and the dummy pattern;
Polishing the interlayer insulating film and the stopper film by chemical mechanical polishing to expose the upper surface of the dummy gate and the upper surface of the dummy pattern;
Selectively removing the dummy gate to form a gate groove;
An electrode film is formed so as to fill the gate groove and cover the dummy pattern at the second position, and selectively expose the upper part of the dummy pattern formed at the second position. Forming a damascene gate electrode by removing, or forming a replacement gate electrode leaving an electrode wider than the gate groove;
Forming an interlayer insulating film and wiring on the damascene or replacement gate electrode;
A method for manufacturing a semiconductor device, comprising:

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