JP2002190592A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress generation of variations in film thicknesses and thereby reduce the number of fill-up processes. SOLUTION: A semiconductor device comprises a metal gate electrode 17 of an embedded structure. At the same time of formation of the gate electrode 17, contacts 18 are formed, and at the same time, dummy contacts 19 are formed on an element isolation region 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a process for processing a gate electrode of a damascene gate transistor.

[0002]

2. Description of the Related Art A transistor using a metal material for a gate electrode does not deteriorate transistor characteristics due to gate depletion or a voltage drop due to gate resistance, unlike a transistor using a polysilicon for a gate electrode. Promising as a next-generation transistor technology.

However, metal materials such as W, Al, and Cu cannot withstand a high-temperature heat process. Therefore, heat treatment for activating the source / drain layers cannot be performed after the gate electrode is processed as in the process of forming a normal transistor.

To solve this problem, Internationala
l Electron Devices Meeting Technical Digest 1998
Attention has been paid to the damascene metal gate or replacement gate transistor disclosed in the editions PP.777-780, pp.785-788 and the like. The damascene metal gate process will be described below.

[0005] First, as shown in FIG.
01, an element isolation region 102 for isolating an element region is selectively formed, and a dummy gate electrode 105 is selectively formed on the element region of the semiconductor substrate 101 via a dummy oxide film 106. Using the dummy gate electrode 105 as a mask, impurities are ion-implanted into the semiconductor substrate 101 to form the extension layer 107. Next, a sidewall insulating film 108 is formed on the side surface of the dummy gate electrode 105,
Ion implantation and heat treatment are performed using the sidewall insulating film 108 and the dummy gate electrode 105 as a mask to form a source / drain layer 109. Thereafter, an interlayer insulating film 110 is deposited on the entire surface, and the surface of the interlayer insulating film 110 is CM
It is flattened by P (Chemical Mechanical Polish) or the like.
Thereby, the surface of the dummy gate electrode 105 is exposed.

Next, as shown in FIG. 31, the dummy gate electrode 105 is removed, and a trench 111 for burying a gate is formed. Next, the dummy oxide film 106 formed first is removed, and the surface of the semiconductor substrate 101 is exposed. Thereafter, ion implantation is performed on the channel.

Next, as shown in FIG. 32, a gate insulating film 113 is formed on the bottom of the trench 111 for embedding the gate. Next, a metal electrode material is deposited on the entire surface, and the gate embedding groove 111 is buried with the metal electrode material. Next, the metal electrode material is flattened by CMP or the like until the surface of the interlayer insulating film 110 is exposed, and the gate electrode 117 is formed. Next, after an interlayer insulating film 120 is deposited on the entire surface, a contact 118 is formed in the logic, and a transistor is formed.

[0008]

In such a damascene process, as shown in FIG. 33, when a dense pattern area A and a sparse pattern area B exist, as shown in FIG.
The following problem occurs in the embedding process. That is, when the metal electrode material 116 is flattened by CMP, the polishing rate is high in the dense area A of the pattern, and the polishing rate is low in the thin area B of the pattern.
That is, in the region A where the pattern is dense, the gate electrode 117
And the interlayer insulating film 110 is processed. Due to such a thinning phenomenon, as shown in FIG. 34, a depression 140 is formed at the center of the dense area A of the pattern, and a variation in film thickness occurs.

Further, an SR using a damascene metal gate is used.
In a process incorporating an AM (Static random Access Memory), gate processing, local wiring (local interconnect) processing, and contact processing are required, and a metal embedding step is performed three times. Therefore, performing the embedding step, which is difficult to process, a plurality of times not only increases the difficulty of processing, but also causes a problem of an increase in manufacturing cost due to multiple steps.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to suppress the occurrence of film thickness variations and to reduce the number of embedding steps, and to manufacture the same. It is to provide a method.

[0011]

The present invention uses the following means to achieve the above object.

According to a first aspect of the present invention, there is provided a semiconductor device comprising: an element isolation region for isolating an element region of a semiconductor substrate; an insulating film formed on the semiconductor substrate; A gate electrode selectively formed via a film, a source / drain diffusion layer formed in the element region so as to sandwich the element region below the gate electrode,
A contact formed on the source / drain diffusion layer in the insulating film; and a dummy contact formed on the element isolation region in the insulating film.

According to a second aspect of the present invention, there is provided a semiconductor device, comprising: an element isolation region for isolating an element region of a semiconductor substrate; an insulating film formed on the semiconductor substrate; A gate electrode selectively formed via a film, a source / drain diffusion layer formed in the element region so as to sandwich the element region below the gate electrode,
The semiconductor device includes a dummy contact formed on the element isolation region in the insulating film, and a local wiring formed in the insulating film and connecting an element having the gate electrode.
The semiconductor device may further include a contact formed on the source / drain diffusion layer in the insulating film.

According to a method of manufacturing a semiconductor device of the present invention, a step of selectively forming an element isolation region for separating an element region in a semiconductor substrate; a step of selectively forming a dummy electrode on the element region; Forming a source / drain layer in the element region in a self-aligned manner with the dummy electrode, depositing an insulating film over the entire surface, and planarizing the insulating film until the surface of the dummy electrode is exposed; After removing the dummy electrode and forming a first groove in the insulating film, the first groove is formed.
Forming a gate insulating film on the bottom surface of the groove, forming a second groove on the source / drain layer in the insulating film, and forming a third groove on the element isolation region in the insulating film. Forming an electrode material on the entire surface, filling the first, second, and third grooves, and flattening the electrode material until the surface of the insulating film is exposed.
Forming a gate electrode in the first groove, a contact in the second groove, and a dummy contact in the third groove.

In the method of manufacturing a semiconductor device according to the present invention, a fourth groove is further formed in the insulating film in the step of forming the second and third grooves, and the electrode is formed in the fourth groove. By localizing after the material is embedded, a local wiring connecting the elements having the gate electrode may be formed.

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, since the contact and the dummy contact are formed simultaneously with the embedding of the electrode material for the gate electrode, the film thickness can be increased without increasing the number of steps. The occurrence of variation can be suppressed. Further, since a contact, a dummy contact, and a local wiring are formed simultaneously with the embedding of the electrode material for the gate electrode, the embedding process can be reduced.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. For this explanation,
Common parts are denoted by common reference symbols.

First Embodiment A first embodiment is a semiconductor device having a metal gate electrode having a buried structure, wherein a contact and a dummy contact are formed simultaneously with the formation of the gate electrode. .

FIG. 1 is a sectional view of a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, in the semiconductor device according to the first embodiment, an element isolation region 2 for isolating an element region of a semiconductor substrate 1 is formed, and an interlayer insulating film 10 is formed on the semiconductor substrate 1. . This interlayer insulating film 1
0, a gate electrode 17 is formed on the element region via a gate insulating film 13, a contact 18 is formed on the source / drain diffusion layer 9, and a dummy contact 19 is formed on the element isolation region 2. I have.

FIGS. 2 to 15 are sectional views showing the steps of manufacturing the semiconductor device according to the first embodiment of the present invention. Hereinafter, a method for manufacturing the semiconductor device according to the first embodiment will be described.

First, as shown in FIG. 2, an element isolation region 2 for isolating an element region is selectively formed in a semiconductor substrate 1 and, for example, 5 nm to 30 nm is formed on the element region of the semiconductor substrate 1.
An oxide film 3 having a thickness of about nm is formed. This oxide film 3
Is preferably a thermal oxide film.

Next, as shown in FIG. 3, a dummy electrode material 4 serving as a material for forming a dummy gate electrode is, for example, 200
Deposited on the order of nm. The dummy electrode material 4 only needs to be a material capable of obtaining an etching selectivity with respect to a surrounding material when a later-described gate embedding groove 11 is formed, and is made of, for example, a polysilicon layer.

Next, as shown in FIG. 4, a dummy gate electrode 5 is formed on the element region of the semiconductor substrate 1 by lithography and RIE (Reactive Ion Etching).

Next, as shown in FIG. 5, the oxide film 3 is removed by etching until the surface of the semiconductor substrate 1 is exposed, and a dummy oxide film 6 is formed. The dummy oxide film 6 is
It may be formed by etching and removing the oxide film 3 simultaneously with the processing step of the dummy gate electrode 5.

Next, as shown in FIG. 6, impurities are ion-implanted into the semiconductor substrate 1 using the dummy gate electrode 5 as a mask, and the extension layer 7 is formed in a self-aligned manner. At this time, an oxide film having a thickness of about 2 nm may be formed on the semiconductor substrate 1 as an oxide film for screening for ion implantation.

Next, as shown in FIG.
After an insulating film such as a silicon nitride film is formed on the entire surface by a D (Low Pressure Chemical Vapor Deposition) method, the insulating film is etched back by RIE, so that the side wall insulating film 8 is formed on the side surface of the dummy gate electrode 5. Is formed.

Next, as shown in FIG. 8, after the impurity is ion-implanted into the semiconductor substrate 1 using the dummy gate electrode 5 and the side wall insulating film 8 as a mask, the impurity is activated by a high-temperature treatment. Thereby, the source / drain layers 9 adjacent to the extension layers 7 are formed in a self-aligned manner.

Next, as shown in FIG. 9, an interlayer insulating film 10 is deposited on the entire surface, and the surface of the interlayer insulating film 10 is formed by CMP.
(Chemical Mechanical Polish) or the like. Thereby, the surface of the dummy gate electrode 5 is exposed.

Next, as shown in FIG. 10, the dummy gate electrode 5 is selectively removed to form a trench 11 for embedding a gate. Here, when the dummy gate electrode 5 is formed of polysilicon, CDE (Chemical Dry Etching) using an etching gas such as CF ₄ or hydrofluoric acid and H
By using wet etching using a mixed acid of NO ₃ , the dummy gate electrode 5 can be selectively removed. When a mixed acid is used, the selectivity between the oxide film and the polysilicon can be adjusted by controlling the ratio of hydrofluoric acid.

Next, as shown in FIG. 11, the dummy oxide film 6 formed first is removed, and the surface of the semiconductor substrate 1 is exposed.

Next, as shown in FIG. 12, an impurity is ion-implanted into the semiconductor substrate 1 from the trench 11 for burying the gate to form a channel impurity layer 12 for forming a channel. At this time, by adjusting the acceleration energy of the ion implantation, the impurity can be implanted only into a predetermined region below the gate burying groove 11. For example, when a buried channel of a damascene metal gate is formed,
The impurity for the punch-through stopper is ion-implanted deeply and the impurity for the buried layer is ion-implanted shallowly. In this step, an oxide film having a thickness of about 2 nm may be formed on the semiconductor substrate 1 as an oxide film for screening for ion implantation.

Next, as shown in FIG. 13, a gate insulating film 13 is formed on the bottom surface of the trench 11 for embedding the gate.

Next, as shown in FIG. 14, a contact groove 14 and a dummy contact groove 15 are simultaneously formed on the source / drain layer 9 and the element isolation region 2 by lithography and RIE.

Next, as shown in FIG. 15, an electrode material 16 in which, for example, TiN and W are laminated is deposited on the entire surface, and the electrode material 16 is used to form the gate embedding groove 11, the contact groove 14, and the dummy contact. The groove 15 is buried.

Next, as shown in FIG. 16, the electrode material 16 is planarized by CMP or the like until the surface of the interlayer insulating film 10 is exposed. As a result, in the trench 11 for embedding the gate, the trench 14 for the contact, and the trench 15 for the dummy contact,
The gate electrode 17, the contact 18, and the dummy contact 19 are respectively formed at the same time.

Finally, as shown in FIG.
After 0 is deposited, contact 1 is formed using known techniques.
The wiring 21 connected to 8 is formed, and a transistor is formed.

According to the first embodiment, as shown in FIG. 15, during the step of embedding the electrode material 16, the dummy contact groove 15 is provided in the same layer as the gate embedding groove 11. For this reason, the patterns are uniformly arranged on the semiconductor substrate 1, and there is no difference in the density of the patterns. Therefore, the thinning phenomenon in which the CMP is partially performed excessively due to the pattern having the density difference as shown in FIG. 34 can be suppressed, and the flatness after the CMP is improved. That is,
The problem of variations in film thickness can be avoided.

The formation of the dummy contact groove 15 is performed simultaneously with the formation of the contact groove 14, and the formation of the dummy contact 19 is performed simultaneously with the formation of the contact 18 and the gate electrode 17.
Is performed simultaneously with the formation of Therefore, in providing the dummy contact pattern, the number of processes does not increase, so that the manufacturing cost does not increase.

[Second Embodiment] In a second embodiment, the semiconductor device shown in FIG. 1 is formed by using a method different from the manufacturing method according to the first embodiment. The feature of the second embodiment is that the contact groove 14 and the dummy contact groove 15 are formed with the dummy gate electrode 5 left.

FIGS. 17 to 21 are sectional views showing the steps of manufacturing a semiconductor device according to the second embodiment of the present invention. Hereinafter, a method for manufacturing the semiconductor device according to the second embodiment will be described. In the method for manufacturing a semiconductor device according to the second embodiment, the same steps as those in the method for manufacturing a semiconductor device according to the first embodiment are not described, and only different steps will be described.

First, as shown in FIGS. 2 to 9, the dummy gate electrode 5 is connected to the interlayer insulating film 1 as in the first embodiment.
Padded with 0.

Next, as shown in FIG. 17, with the dummy gate electrode 5 remaining without being removed, a contact groove 14 and a dummy are formed on the source / drain layer 9 and the element isolation region 2 by lithography and RIE. Groove for contact 1
5 are simultaneously formed.

Next, as shown in FIG. 18, the dummy gate electrode 5 is selectively removed to form a trench 11 for burying a gate.

Next, as shown in FIG. 19, the dummy oxide film 6 formed first is removed, and the surface of the semiconductor substrate 1 is exposed.

Next, as shown in FIG. 20, an impurity is ion-implanted into the semiconductor substrate 1 from the trench 11 for burying the gate to form a channel impurity layer 12 for forming a channel.

Next, as shown in FIG. 21, a gate insulating film 13 is formed on the bottom surface of the trench 11 for embedding the gate.

Thereafter, as in the first embodiment, FIG.
5. As shown in FIG. 16, after an electrode material 16 in which, for example, TiN and W are laminated is deposited on the entire surface, the electrode material 16 is flattened. As a result, the gate electrode 17, the contact 18, and the dummy contact 19 are formed in the gate embedding groove 11, the contact groove 14, and the dummy contact groove 15.
Are simultaneously formed.

According to the second embodiment, as in the first embodiment, it is possible to suppress the occurrence of film thickness variations without increasing the number of steps.

However, in the method according to the second embodiment,
20 and 21, as shown in FIG.
On the other hand, a lithography step for selectively performing ion implantation and forming the gate insulating film 13 is required.

[Third Embodiment] A third embodiment is directed to an SRAM (Stat) having a metal gate electrode having a buried structure.
ic random access memory), a contact, a dummy contact, and a local interconnect (local interconnect) at the same time as the formation of the gate electrode.
Is formed.

FIG. 22 shows four NMOS transistors Q
FIG. 1 shows a circuit diagram of an SRAM including n1, Qn2, Qn3, and Qn4 and two PMOS transistors Qp1 and Qp2. FIG. 23 is a diagram illustrating an SR according to the third embodiment of the present invention.
FIG. 1 shows a schematic plan view of a semiconductor device in which AM is mounted. FIG.
Shows a schematic sectional view of the semiconductor device along the line 24-24 in FIG. In FIG. 23, the contacts Ca,
The wiring connecting Cb and Cc is omitted.

As shown in FIGS. 22 to 24, in the semiconductor device according to the third embodiment, an element isolation region 2 for isolating an element region of a semiconductor substrate 1 is formed, and an interlayer insulating film is formed on the semiconductor substrate 1. 10 are formed. This interlayer insulating film 1
0, gate electrodes 17a and 17b are formed on the element region via a gate insulating film 13, a contact 18 is formed on the source / drain diffusion layer 9, and the element isolation region 2 is formed.
A dummy contact 19 is formed thereon. And
Adjacent gate electrodes 17a, 17b in interlayer insulating film 10
The local interconnect 32 is disposed between them. The local interconnect 32 connects the drains of the adjacent transistors 33a and 33b.

FIGS. 25 to 29 are sectional views showing the steps of manufacturing a semiconductor device according to the third embodiment of the present invention. Hereinafter, a method for manufacturing the semiconductor device according to the third embodiment will be described. Note that in the third embodiment, the first
The description of the same manufacturing process as that of the embodiment is omitted,
Only different steps will be described.

First, through the steps shown in FIGS. 2 to 9 of the first embodiment, as shown in FIG. 25, first and second dummy gate electrodes 5a and 5b embedded in an interlayer insulating film 10 are formed.
Are formed adjacent to each other.

Next, as shown in FIG. 26, the first and second dummy gate electrodes 5a and 5b are selectively removed to form a trench 11 for burying a gate. Next, after the dummy oxide film 6 formed first is removed, a gate insulating film 13 is formed on the bottom surface of the trench 11 for embedding the gate.

Next, as shown in FIG. 27, by lithography and RIE, on the source / drain layer 9, on the element isolation region 2, and between the gate embedding grooves 11 from which the first and second dummy gate electrodes have been removed. , Contact groove 14,
The dummy contact groove 15 and the local interconnect groove 31 are simultaneously formed.

Next, as shown in FIG. 28, an electrode material 16 in which, for example, TiN and W are laminated is deposited on the entire surface, and the electrode material 16 is used to bury the gate embedding groove 11, the contact groove 14, and the dummy contact. The groove 15 and the local interconnect groove 31 are buried.

Next, as shown in FIG. 29, the electrode material 16 is planarized by CMP or the like until the surface of the interlayer insulating film 10 is exposed. As a result, the first and second gate electrodes 17a and 17b, the contact 18, the dummy contact 19, and the local interconnect 32 are provided in the trench 11 for embedding the gate, the trench 14 for the contact, the trench 15 for the dummy contact, and the trench 31 for the local interconnect. Each is formed simultaneously.

Finally, as shown in FIG. 24, after the interlayer insulating film 20 is deposited, the wiring 21 connected to the contact 18 is formed by using a known technique, and the transistor 33 is formed.
a, 33b are formed. Thus, by providing the local interconnect 32, the adjacent transistors 33a and 33b are connected.

According to the third embodiment, as in the first embodiment, it is possible to suppress the occurrence of film thickness variations without increasing the number of steps.

In the process of mounting the SRAM as in the third embodiment, since the local interconnect 32 is formed simultaneously with the embedding of the electrode material 16 for the gate electrodes 17a and 17b, the number of steps can be reduced. As described above, by reducing the embedding process which is difficult to process, it is possible to suppress an increase in the difficulty of the process and to prevent an increase in manufacturing cost due to multiple processes.

In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0063]

As described above, according to the present invention, it is possible to provide a semiconductor device and a method of manufacturing the same capable of suppressing the occurrence of film thickness variations and reducing the number of embedding processes.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 2;

FIG. 4 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 3;

FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 4;

FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 5;

FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 6;

FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 7;

FIG. 9 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 8;

FIG. 10 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 9;

FIG. 11 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 10;

FIG. 12 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 11;

FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 12;

FIG. 14 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 13;

FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 14;

FIG. 16 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 15;

FIG. 17 is a sectional view illustrating a manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 9;

FIG. 18 is a sectional view illustrating a manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 17;

FIG. 19 is a sectional view illustrating a manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 18;

FIG. 20 is a sectional view showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 19;

FIG. 21 is a sectional view illustrating a manufacturing step of the semiconductor device according to the second embodiment of the present invention, following FIG. 20;

FIG. 22 shows four NMs according to the third embodiment of the present invention.
FIG. 2 is a circuit diagram showing an SRAM including an OS transistor and two PMOS transistors.

FIG. 23 is a schematic plan view showing an SRAM-embedded semiconductor device according to a third embodiment of the present invention.

FIG. 24 is a schematic cross-sectional view showing a semiconductor device including an SRAM according to a third embodiment of the present invention.

FIG. 25 is a sectional view showing a manufacturing step of the semiconductor device according to the third embodiment of the present invention, following FIG. 8;

FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the third embodiment of the present invention, following FIG. 25;

FIG. 27 is a sectional view illustrating a manufacturing step of the semiconductor device according to the third embodiment of the present invention, following FIG. 26;

FIG. 28 is a sectional view illustrating a manufacturing step of the semiconductor device according to the third embodiment of the present invention, following FIG. 27;

FIG. 29 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the third embodiment of the present invention, following FIG. 28;

FIG. 30 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 31 is a sectional view showing a manufacturing step of a conventional semiconductor device, following FIG. 30;

FIG. 32 is a cross-sectional view showing a manufacturing step of the conventional semiconductor device, following FIG. 31;

FIG. 33 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 34 is a sectional view showing a manufacturing step of the semiconductor device according to the conventional technique, following FIG. 33;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation region, 3 ... Oxide film layer, 4 ... Dummy electrode material, 5, 5a, 5b ... Dummy gate electrode, 6 ... Dummy oxide film, 7 ... Extension layer, 8 ... Side wall insulating film, 9: source / drain layer, 10: first interlayer insulating film, 11: trench for burying gate, 12: channel impurity layer, 13: gate insulating film, 14: trench for contact, 15: trench for dummy contact, 16 ... Metal film, 17, 17a, 17b gate electrode, 18 contact, 19 dummy contact, 20 second interlayer insulating film, 21 wiring, 31 trench for local interconnect, 32 local interconnect, 33a, 33b Transistor.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/11 H01L 29/78 301G 29/43 F term (Reference) 4M104 BB30 CC01 CC05 DD03 DD16 FF18 FF22 FF40 GG09 GG10 GG14 GG16 HH12 5F040 DA00 DC01 EA08 EC01 EC04 EC12 EF02 FA02 FA07 FB02 FB05 FC00 FC10 5F048 AA09 AB01 AC03 BA01 BB01 BB04 BB09 BB12 BC06 BD04 BF07 BF16 BG01 BG13 DA27 5F083 BS03 BS01 BS27 BS27 BS39 BS27 BS01 BS27

Claims (5)

[Claims] An element isolation region for isolating an element region of a semiconductor substrate; an insulating film formed on the semiconductor substrate; and selectively formed on the element region in the insulating film via a gate insulating film. A gate electrode, a source / drain diffusion layer formed in the element region so as to sandwich the element region below the gate electrode, and a contact formed on the source / drain diffusion layer in the insulating film And a dummy contact formed on the element isolation region in the insulating film. 2. An element isolation region for isolating an element region of a semiconductor substrate; an insulating film formed on the semiconductor substrate; and selectively formed on the element region in the insulating film via a gate insulating film. A gate electrode, a source / drain diffusion layer formed in the device region so as to sandwich the device region below the gate electrode, and a dummy contact formed on the device isolation region in the insulating film. And a local wiring formed in the insulating film and connecting an element provided with the gate electrode. 3. The semiconductor device according to claim 2, further comprising a contact formed on said source / drain diffusion layer in said insulating film. 4. A step of selectively forming an element isolation region for separating an element region in a semiconductor substrate; a step of selectively forming a dummy electrode on the element region; and a source / drain in the element region. Forming a layer in a self-aligned manner with the dummy electrode; depositing an insulating film on the entire surface; planarizing the insulating film until the surface of the dummy electrode is exposed; removing the dummy electrode; Forming a first groove in the insulating film, forming a gate insulating film on the bottom surface of the first groove, forming a second groove on the source / drain layer in the insulating film; Forming a third groove on the element isolation region in the insulating film, depositing an electrode material on the entire surface and filling the first, second, and third grooves; Flattening until the surface of the insulating film is exposed. Ri, the first gate electrode in the groove, the second
Forming a contact in the groove, and forming a dummy contact in the third groove, respectively. 5. A step of forming the second and third grooves, further forming a fourth groove in the insulating film, and planarizing after the electrode material is embedded in the fourth groove. 5. The method according to claim 4, wherein a local wiring for connecting the element having the gate electrode is formed.