JP2011192744A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including a shared contact which prevents opening defect of a contact hole and an increase in contact resistance, and prevents degradation of yields caused by generation of a junction leak current. <P>SOLUTION: A source/drain region 106 is formed at both sides of a gate electrode 103 on a semiconductor substrate 100. The shared contact includes a lower level contact 113 that is connected to the source/drain region 106 and not connected to the gate electrode 103, and an upper level contact 118 connected to both the lower contact 113 and the gate electrode 103. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a shared contact connected to both a gate electrode and a source / drain region, and a method for manufacturing the same.

  In recent years, with the miniaturization of semiconductor device design rules, shared contacts have been adopted to narrow the pitch between contact holes. When the shared contact is used, the contact hole on the gate electrode and the contact hole on the source / drain region can be combined into one contact hole, so that the pitch between the contact holes can be reduced.

  9A to 9E are cross-sectional views showing respective steps of a conventional shared contact formation process. 9A to 9E, “1” is a silicon substrate, “2” is an element isolation region, “3” is a gate insulating film, “4” is a gate electrode, “5” is an extension region, and “6”. ”Is a sidewall insulating film,“ 7 ”is a sidewall spacer,“ 8 ”is a source / drain region,“ 9 ”is a stopper insulating film,“ 10 ”is an interlayer insulating film,“ 11 ”is a resist pattern,“ 12 "Is a shared contact hole, and" 13 "is a shared contact.

  First, as shown in FIG. 9A, after an element isolation region 2 is formed on a silicon substrate 1 by known STI (shallow trench isolation) or field element isolation, an element active surrounded by the element isolation region 2 is activated. A gate electrode 4 is formed on the silicon substrate 1 serving as a region via a gate insulating film 3, and then extension regions 5 are formed on both sides of the gate electrode 4 in the silicon substrate 1.

  Next, as shown in FIG. 9B, a sidewall insulating film 6 made of a silicon nitride film is deposited on the entire surface of the silicon substrate 1 including the gate electrode 4. Thereafter, as shown in FIG. 9C, the sidewall insulating film 6 is etched back to form sidewall spacers 7 on the side surfaces of the gate electrode 4, and then the gate electrode 4 in the silicon substrate 1 is formed. Source / drain regions 8 that are separated from the gate electrode 4 and connected to the extension region 5 are formed on both sides of the gate electrode 4.

  Next, as shown in FIG. 9D, a stopper insulating film 9 made of a silicon nitride film and an interlayer insulating film 10 are sequentially formed on the entire surface of the silicon substrate 1 including the gate electrode 4, and then known. A resist pattern 11 having an opening in the shared contact formation region is formed using a photolithography technique.

  Next, as shown in FIG. 9E, after the interlayer insulating film 10 located in the shared contact formation region is removed and the shared contact hole 12 is formed by anisotropic dry etching using the resist pattern 11 as a mask. The stopper insulating film 9 exposed at the bottom of the shared contact hole 12 is removed by dry etching. Thereafter, the resist pattern 11 is removed by ashing and cleaning, and then a conductive material is embedded in the shared contact hole 12 to form the shared contact 13.

  In the conventional structure provided with the shared contact described above, the shared contact hole 12 for providing the shared contact 13 is removed by removing the interlayer insulating film 10 by anisotropic dry etching as described above. After the hole 12 is formed, the stopper insulating film 9 exposed at the bottom of the shared contact hole 12 is removed by dry etching.

  However, in the step of removing the stopper insulating film 9, a portion of the sidewall spacer 7 exposed in the shared contact hole 12 is etched simultaneously with the stopper insulating film 9 made of the same silicon nitride film as the sidewall spacer 7. . For this reason, the side wall spacer 7 becomes smaller as the film is reduced. Accordingly, the sidewall spacer 7 in the shared contact hole 12 is almost completely removed depending on the height of the sidewall spacer 7 and the degree of process variation in the sidewall spacer 7 forming step shown in FIG. 9C. In some cases, the extension region (shallow impurity diffusion layer) 5 provided under the sidewall spacer 7 is exposed.

  If the conductive material is buried in the shared contact hole 12 with the extension region 5 exposed in this manner, the conductive material, that is, the shared contact 13 and the extension region 5 are in contact with each other, and thus a junction leakage current is generated in the contact region. This causes a problem that the yield decreases (see FIG. 9E).

  To solve this problem, there is provided means for increasing the process margin for reducing the thickness of the sidewall spacer 7 exposed in the shared contact hole 12 for forming the shared contact 13 (particularly, reducing the bottom width of the sidewall spacer 7). It can be solved by taking it.

  For example, in Patent Document 1, after removing the stopper insulating film (etching stopper film) at the bottom of the shared contact hole in the step shown in FIG. 9E, the silicon nitride film is deposited and etched again. A method for solving the above-described problem by re-forming the sidewall spacer in the shared contact hole is disclosed.

JP 2009-147161 A

  However, in the conventional technique disclosed in Patent Document 1, the following problems occur as the contact hole diameter becomes smaller as the miniaturization progresses. That is, the deposition of the silicon nitride film for re-forming the side wall spacer causes the shared contact hole to be completely buried, resulting in an opening defect, or the silicon nitride film remaining on the side wall of the shared contact hole. The contact resistance increases due to the reduction of the typical contact hole diameter, resulting in deterioration of device characteristics.

  In view of the above, the present invention provides a junction leakage current in a semiconductor device having a shared contact connected to both the gate electrode and the source / drain region while preventing a contact hole opening failure and an increase in contact resistance. The purpose is to prevent the resulting yield loss.

  In order to achieve the above object, a first semiconductor device according to the present invention includes a first gate electrode formed on a semiconductor substrate, and a sidewall insulating film formed on a side surface of the first gate electrode. A first source / drain region formed on both sides of the first gate electrode in the semiconductor substrate and spaced apart from the first gate electrode, the first gate electrode and the first source / drain An interlayer insulating film formed to cover the drain region; and a shared contact formed in the interlayer insulating film and connected to both the first gate electrode and the first source / drain region. The shared contact includes a first lower layer contact that is connected to the first source / drain region and is not connected to the first gate electrode, the first lower layer contact, and the front contact And a first upper contact connecting to both of the first gate electrode.

  According to the first semiconductor device of the present invention, the shared contact is connected to the first source / drain region and not connected to the first gate electrode, the first lower layer contact, A first upper layer contact connected to both of the first gate electrodes is formed separately. For this reason, the first lower layer contact connected to the first source / drain region can be formed sufficiently spaced from the first gate electrode. Therefore, it is possible to avoid the situation where the sidewall insulating film on the side surface of the first gate electrode is removed and the semiconductor substrate is exposed at the time of forming the hole in which the first lower layer contact is formed. A decrease in yield can be prevented. In addition, as described above, when the hole for the shared contact is formed, the side wall insulating film on the side surface of the first gate electrode is not removed, so that it is not necessary to re-form the side wall insulating film as in the prior art. Therefore, it is possible to prevent contact hole opening defects and contact resistance increase due to the re-formation.

  In the first semiconductor device according to the present invention, an upper barrier metal is provided on the bottom and sides of the first upper contact, and the upper surface of the first lower contact is in contact with the upper barrier metal. Good. In this case, a lower barrier metal is provided at the bottom and side of the first lower contact, and the thickness of the upper barrier metal and the thickness of the lower barrier metal may be substantially the same.

  In the first semiconductor device according to the present invention, a second gate electrode formed on the semiconductor substrate, and second source / drain regions formed on both sides of the second gate electrode in the semiconductor substrate A source / drain contact formed in the interlayer insulating film and connected to the second source / drain region and not connected to the second gate electrode. The source / drain contact is A second lower layer contact connected to the second source / drain region and a second upper layer contact connected to the second lower layer contact may be provided. In this case, the shape of the bottom surface of the first lower layer contact and the shape of the bottom surface of the second lower layer contact may be substantially the same. In addition, a gate contact formed in the interlayer insulating film and connected to the second gate electrode and not connected to the second source / drain region may be further provided. Here, the shape of the bottom surface of the second upper layer contact and the shape of the bottom surface of the gate contact may be substantially the same.

  In the first semiconductor device according to the present invention, the semiconductor substrate is formed below the side wall insulating film and shallower than the first source / drain region, and is connected to the first source / drain region. An extension region may be further provided, and the first lower layer contact may be formed apart from the extension region.

  In the first semiconductor device according to the present invention, a metal silicide layer may be formed on each surface portion of the first gate electrode and the first source / drain region. Here, the metal silicide layer may be, for example, a nickel silicide layer or a nickel platinum silicide layer.

  In the first semiconductor device according to the present invention, an etching stopper film may be formed between the first gate electrode and the first lower layer contact on the semiconductor substrate. Here, the etching stopper film may be, for example, a silicon nitride film or a silicon carbide film.

  In the first semiconductor device according to the present invention, each of the gate electrodes may be made of, for example, polysilicon, silicon compound, tungsten, titanium, or aluminum. The interlayer insulating film may be, for example, a silicon oxide film, a BPSG (boron-doped phospho-silicate glass) film, a PSG (phospho-silicate glass) film, or the like.

  A second semiconductor device according to the present invention is formed with a first gate electrode formed on a semiconductor substrate and on both sides of the first gate electrode in the semiconductor substrate, separated from the first gate electrode. A first source / drain region, an interlayer insulating film formed so as to cover the first gate electrode and the first source / drain region, and formed in the interlayer insulating film, and 1 and a shared contact connected to both of the first source / drain regions, a sidewall insulating film is not formed on a side surface of the first gate electrode, and the shared contact is A first lower layer contact that is connected to the first source / drain region and not connected to the first gate electrode; and the first lower layer contact and the first gate electrode And a first upper contact connecting towards.

  In this application, the side wall insulating film means a side wall spacer that covers the extension region (that is, formed after the extension region is formed), and is an offset formed on the side surface of the gate electrode before the extension region is formed. Spacers are not included.

  According to the second semiconductor device of the present invention, the shared contact is connected to the first source / drain region and not to the first gate electrode, the first lower layer contact, A first upper layer contact connected to both of the first gate electrodes is formed separately. For this reason, the first lower layer contact connected to the first source / drain region can be formed sufficiently spaced from the first gate electrode. Accordingly, it is possible to avoid a situation in which the semiconductor substrate is exposed by removing the insulating film (interlayer insulating film or etching stopper film) in the region adjacent to the first gate electrode when forming the hole in which the first lower layer contact is formed. Therefore, it is possible to prevent a decrease in yield due to the occurrence of junction leakage current. Further, as described above, when forming the hole for shared contact, the insulating film in the region adjacent to the first gate electrode is not removed, so that it is not necessary to re-form the side wall insulating film as in the prior art. Therefore, it is possible to prevent contact hole opening defects and contact resistance increase due to the re-formation.

  In the second semiconductor device according to the present invention, an upper layer barrier metal is provided on the bottom and sides of the first upper layer contact, and the upper surface of the first lower layer contact may be in contact with the upper layer barrier metal. Good. In this case, a lower barrier metal is provided at the bottom and side of the first lower contact, and the thickness of the upper barrier metal and the thickness of the lower barrier metal may be substantially the same.

  In the second semiconductor device according to the present invention, a second gate electrode formed on the semiconductor substrate, a second source / drain region formed on both sides of the second gate electrode in the semiconductor substrate, A source / drain contact formed in the interlayer insulating film and connected to the second source / drain region and not connected to the second gate electrode. The source / drain contact is A second lower layer contact connected to the second source / drain region and a second upper layer contact connected to the second lower layer contact may be provided. In this case, the shape of the bottom surface of the first lower layer contact and the shape of the bottom surface of the second lower layer contact may be substantially the same. In addition, a gate contact formed in the interlayer insulating film and connected to the second gate electrode and not connected to the second source / drain region may be further provided. Here, the shape of the bottom surface of the second upper layer contact and the shape of the bottom surface of the gate contact may be substantially the same.

  In the second semiconductor device according to the present invention, the first source / drain region is formed shallower than the first source / drain region in a region adjacent to the first gate electrode in the semiconductor substrate. The first lower layer contact may be formed apart from the extension region.

  In the second semiconductor device according to the present invention, a metal silicide layer may be formed on each surface portion of the first gate electrode and the first source / drain region. Here, the metal silicide layer may be, for example, a nickel silicide layer or a nickel platinum silicide layer.

  In the second semiconductor device according to the present invention, an etching stopper film may be formed between the first gate electrode and the first lower layer contact on the semiconductor substrate. Here, the etching stopper film may be, for example, a silicon nitride film or a silicon carbide film.

  In the second semiconductor device according to the present invention, a part of the interlayer insulating film may be formed between the first gate electrode and the first lower layer contact on the semiconductor substrate.

  In the second semiconductor device according to the present invention, each of the gate electrodes may be made of, for example, polysilicon, silicon compound, tungsten, titanium, or aluminum. The interlayer insulating film may be, for example, a silicon oxide film, a BPSG film, a PSG film, or the like.

  The method of manufacturing a semiconductor device according to the present invention includes a step (a) of forming a first gate electrode on a semiconductor substrate, and introducing impurities into the semiconductor substrate using the first gate electrode as a mask. A step (b) of forming an extension region, a step (c) of forming a sidewall insulating film on a side surface of the first gate electrode, and the semiconductor using the first gate electrode and the sidewall insulating film as a mask. A step (d) of forming a first source / drain region by introducing impurities into the substrate; and after the step (d), on the semiconductor substrate including the top of the first gate electrode. A step (e) of sequentially depositing an etching stopper film and a first insulating film; and etching the first insulating film and the etching stopper film to thereby form the first source / drain. A step (f) of forming a first lower layer contact hole connected to the first region, and a step (g) of forming a first lower layer contact having a lower layer barrier metal on the bottom and side portions in the first lower layer contact hole (g) And (h) forming a second insulating film on the first lower layer contact and on the first insulating film, and etching the second insulating film, thereby A step (i) of forming a first upper layer contact hole connected to each of the lower layer contact and the first gate electrode; and a first barrier layer having an upper barrier metal on the bottom and side portions of the first upper contact hole. And (j) forming an upper contact of one.

  According to the method for manufacturing a semiconductor device according to the present invention, the first lower layer contact hole connected to the first source / drain region, that is, the first lower layer contact, the first lower layer contact, and the first gate electrode, Since the first upper-layer contact hole to be connected, that is, the first upper-layer contact is formed separately, a shared contact composed of the first lower-layer contact and the first upper-layer contact can be formed. That is, according to the method for manufacturing a semiconductor device according to the present invention, the first semiconductor device according to the present invention can be manufactured. Thus, the same effect as the first semiconductor device according to the present invention can be obtained. be able to.

  The method for manufacturing a semiconductor device according to the present invention may further include a step of removing the sidewall insulating film between the step (d) and the step (e). In this way, the second semiconductor device according to the present invention described above can be manufactured, so that the same effect as that of the second semiconductor device according to the present invention described above can be obtained.

  In the method for manufacturing a semiconductor device according to the present invention, a step (k) of forming a second gate electrode on the semiconductor substrate, and second source / drain regions on both sides of the second gate electrode in the semiconductor substrate. The step (f) further includes the step of forming a second source / drain region connected to the second source / drain region by etching the first insulating film and the etching stopper film. A step of forming a lower layer contact hole, wherein the step (g) includes a step of forming a second lower layer contact in the second lower layer contact hole, and the step (i) includes the second insulating film. Forming a second upper layer contact hole that is connected to the second lower layer contact and not connected to the second gate electrode by etching Serial step (j) may include the step of forming the second upper layer contacts the second upper contact hole. In this case, the step (i) forms a gate contact hole that is connected to the second gate electrode and not connected to the second lower layer contact by etching the second insulating film. The step (j) may include a step of forming a gate contact in the gate contact hole.

  According to the present invention, in a semiconductor device having a shared contact connected to both the gate electrode and the source / drain region, the yield resulting from the occurrence of junction leakage current is prevented while preventing contact hole opening failure and increase in contact resistance. Can be prevented.

1A is a cross-sectional view showing the structure of the semiconductor device according to the embodiment, FIG. 1B is a top view showing the structure of the semiconductor device according to the embodiment, and FIG. FIG. 2 is an enlarged cross-sectional view of a connection portion between a lower layer contact and a source / drain region in the structure shown in FIG. 2A to 2C are cross-sectional views illustrating each step of the method of manufacturing a semiconductor device according to the embodiment. FIG. 3A and FIG. 3B are cross-sectional views showing each step of the method for manufacturing a semiconductor device according to the embodiment. 4A and 4B are cross-sectional views illustrating each step of the method of manufacturing a semiconductor device according to the embodiment. FIG. 5A and FIG. 5B are cross-sectional views showing respective steps of the method for manufacturing a semiconductor device according to the embodiment. FIG. 6 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the embodiment. FIG. 7 is a cross-sectional view showing a state in which a barrier metal that covers the bottom and wall surface of the shared contact hole is formed in the conventional shared contact formation process. FIG. 8 is a cross-sectional view illustrating a structure of a semiconductor device according to a modification of the embodiment. 9A to 9E are cross-sectional views showing respective steps of a conventional shared contact formation process.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1A is a cross-sectional view showing the structure of the semiconductor device according to this embodiment.

  As shown in FIG. 1A, a gate electrode 103 made of, for example, polysilicon is formed on a semiconductor substrate 100 made of, for example, silicon via a gate insulating film 102. Sidewall spacers 104 are formed on the side surfaces of the gate electrode 10. An extension region 105 is formed below the sidewall spacer 104 in the surface portion of the semiconductor substrate 100. The extension region 105 is, for example, a p-type shallow low-concentration impurity region. Further, on both sides of the gate electrode 103 on the surface portion of the semiconductor substrate 100, source / drain regions 106 that are separated from the gate electrode 103 and are connected to the extension region 105 are formed. The source / drain region 106 is, for example, a p-type deep high concentration impurity region. Metal silicide layers 107 are formed on the surface portions of the gate electrode 103 and the source / drain regions 106, respectively. An etching stopper film 108 is formed so as to cover the gate electrode 103, the sidewall spacer 104 and the source / drain region 106. On the etching stopper film 108, a first insulating film 109 and a second insulating film 114, which respectively serve as interlayer insulating films, are formed.

  The etching stopper film 108 and the first insulating film 109 have a lower contact hole 110 that reaches a predetermined portion of the source / drain region 106 (more precisely, the metal silicide layer 107 formed on the surface of the source / drain region 106). Is formed. A metal-containing film 112 is buried in the lower contact hole 110 via a lower barrier metal 111 that covers the bottom and side walls thereof, and a lower contact 113 is formed from the lower barrier metal 111 and the metal-containing film 112. That is, the lower layer contact 113 is connected to the source / drain region 106 and is not connected to the gate electrode 103. Further, a part of the etching stopper film 108 exists between the gate electrode 103 and the lower layer contact 113 on the semiconductor substrate 100.

  The upper contact hole 115 reaching the lower contact 113 and the gate electrode 103 (more precisely, the metal silicide layer 107 formed on the surface of the gate electrode 103) is formed in the upper portion of the first insulating film 109 and the second insulating film 114. Is formed. A metal-containing film 117 is buried in the upper contact hole 115 via an upper barrier metal 116 that covers the bottom and side walls of the upper contact hole 115, and an upper contact 118 is formed from the upper barrier metal 116 and the metal-containing film 117. That is, the upper layer contact 118 is connected to both the lower layer contact 113 and the gate electrode 103. Here, the upper surface of the lower layer contact 113 is in contact with the upper layer barrier metal 116 constituting the upper layer contact 118. The thickness of the upper barrier metal 116 and the thickness of the lower barrier metal 111 are approximately the same.

  As described above, in the present embodiment, a shared contact connected to both the gate electrode 103 and the source / drain region 106 is configured by the laminated structure of the lower layer contact 113 and the upper layer contact 118.

  FIG. 1B is a top view showing the structure of the semiconductor device according to this embodiment. 1A is a cross-sectional view taken along line BB in FIG. 1B. Further, in FIG. 1B, the gate electrode 103 and the lower layer contact 113 that are not actually seen from the upper surface are indicated by broken lines in order to clarify the positional relationship of each component.

  As shown in FIG. 1B, the upper surface of the upper contact 118 (that is, the upper surface of the shared contact) has, for example, a track shape having a major axis of 110 nm and a minor axis of 40 nm. One end in the direction overlaps with the gate electrode 103, and the other end in the major axis direction of the track shape overlaps with the lower layer contact 113. Thus, the gate electrode 103 and the lower layer contact 113 are electrically connected via the upper layer contact 118.

  FIG. 1C is an enlarged cross-sectional view of the connection portion between the lower layer contact 113 and the source / drain region 106 and the periphery thereof in the structure shown in FIG.

  As shown in FIG. 1C, in this embodiment, one end of the extension region 105 is located below the edge of the gate electrode 103, and the other end of the extension region 105 is below the edge of the sidewall spacer 104. For example, it is located at a location approaching 5 nm toward the gate electrode 103 side. The bottom surface of the lower layer contact 113 is, for example, a circle having a diameter of 0.04 μm, and the lower layer contact 113 is formed, for example, 10 nm away from the other end of the extension region 105.

  As described above, according to the present embodiment, the shared contact is connected to the lower layer contact 113 that is connected to the source / drain region 106 and not to the gate electrode 103, and to both the lower layer contact 113 and the gate electrode 103. The upper contact 118 is formed separately. Therefore, the lower layer contact 113 connected to the source / drain region 106 can be formed sufficiently away from the gate electrode 103. Accordingly, it is possible to avoid a situation where the sidewall spacer 104 on the side surface of the gate electrode 103 is removed and the semiconductor substrate 100 (specifically, the extension region 105) is exposed when the lower contact hole 110 where the lower contact 113 is formed is formed. Therefore, it is possible to prevent a decrease in yield due to the occurrence of junction leakage current. Further, as described above, when forming the hole for the shared contact, the sidewall spacer 104 on the side surface of the gate electrode 103 is not removed, so that it is not necessary to re-form the sidewall spacer as in the prior art. It is possible to prevent contact hole opening defects and contact resistance increase due to the re-formation.

  Hereinafter, a semiconductor device manufacturing method according to an embodiment of the present invention will be described with reference to the drawings.

  2 (a) to 2 (c), 3 (a), 3 (b), 4 (a), 4 (b), 5 (a), 5 (b), and 6 relate to the present embodiment. It is sectional drawing which shows each process of the manufacturing method of a semiconductor device.

  First, as shown in FIG. 2A, an element isolation region 101 is formed on a semiconductor substrate 100 made of, for example, silicon by, for example, STI, so that the element active region surrounded by the element isolation region 101 is activated. The area is divided into a shared part A, a non-shared part B, and a non-shared part C. Here, the width of the source / drain formation region in each of the shared part A and the non-shared part C (distance from the gate electrode to the element isolation region) is approximately the same, and the width of the source / drain formation region in the non-shared part B Is wider than the shared part A and the non-shared part C. Subsequently, in each of the shared portion A, the non-shared portion B, and the non-shared portion C, the thickness of, for example, 100 nm is formed on the semiconductor substrate 100 via the gate insulating films 102A, 102B, and 102C having a thickness of about 1.5 nm, for example. Gate electrodes 103A, 103B, and 103C having the same degree are formed.

  The formation method of the gate electrodes 103A, 103B, and 103C is, for example, as follows. First, after a polycrystalline silicon film having a thickness of about 100 nm is formed on the entire surface of the semiconductor substrate 100, a photoresist is applied on the polycrystalline silicon film, and then the photoresist is exposed and developed. A mask that covers the gate electrode formation region is formed. Subsequently, dry etching is performed on the polycrystalline silicon film using the mask to form the gate electrodes 103A, 103B, and 103C, and then the photoresist layer is removed by ashing and washing.

Next, as shown in FIG. 2B, in each of the shared part A, the non-shared part B, and the non-shared part C, the gate electrodes 103A, 103B, and 103C are used as masks on the semiconductor substrate 100, for example, boron (B ) And the like are ion-implanted with an implantation energy of 3 keV, for example, to form extension regions 105A, 105B, and 105C made of shallow p-type impurity regions with a depth of 20 nm, for example. The concentration of the p-type impurity contained in the extension regions 105A, 105B, and 105C is, for example, about 2 × 10 ¹⁴ cm ⁻³ . Thereafter, a sidewall insulating film 121 made of, for example, a silicon nitride film having a thickness of 40 nm is formed on the entire surface of the semiconductor substrate 100 including the gate electrodes 103A, 103B, and 103C. Note that offset spacers may be formed on the side surfaces of the gate electrodes 103A, 103B, and 103C before the extension regions 105A, 105B, and 105C are formed.

Next, as shown in FIG. 2C, anisotropic dry etching is performed on the sidewall insulating film 121 to form, for example, a silicon nitride film on each side surface of the gate electrodes 103A, 103B, and 103C. Side wall spacers 104A, 104B and 104C made of are formed. Thereafter, in each of the shared part A, the non-shared part B, and the non-shared part C, impurities such as boron (B), for example, 40 keV, for example, using the gate electrodes 103A, 103B, 103C and the sidewall spacers 104A, 104B, 104C as a mask. By implanting ions with an implantation energy of, for example, source / drain regions 106A, 106B, 106C made of deep p-type impurity regions having a depth of 45 nm, for example, are formed. The concentration of the p-type impurity contained in the source / drain regions 106A, 106B, 106C is, for example, about 2 × 10 ¹⁵ cm ⁻³ . Thereafter, a metal silicide layer 107A is formed on each surface portion of the gate electrode 103A and the source / drain region 106A, and a metal silicide layer 107B is formed on each surface portion of the gate electrode 103B and the source / drain region 106B. A metal silicide layer 107C is formed on the respective surface portions of 103C and source / drain regions 106C. Each of the metal silicide layers 107A, 107B, and 107C is made of, for example, nickel silicide or nickel platinum silicide.

  Next, as shown in FIG. 3A, after depositing an etching stopper film 108 made of, for example, a 30 nm-thickness silicon nitride film on the entire surface of the semiconductor substrate 100, the etching stopper film 108 has a thickness of, for example, A first insulating film 109 made of a silicon oxide film having a thickness of 500 nm is deposited. Here, as the silicon nitride film to be the etching stopper film 108, a film having the same composition as the silicon nitride films to be the sidewall spacers 104A, 104B, and 104C is used. Thereafter, the surface of the first insulating film 109 is planarized by, for example, CMP (chemical mechanical polishing). Here, the finished thickness of the first insulating film 109 after planarization is, for example, about 200 nm. Subsequently, after applying a photoresist on the first insulating film 109, the photoresist is exposed to light and developed to thereby form a lower layer contact in each of the shared part A, the non-shared part B, and the non-shared part C. A resist pattern 122 having openings 122a, 122b, and 122c is formed in a formation region (a lower layer contact that constitutes a shared contact (contact connected to a source / drain region)). Here, the respective widths of the openings 122a, 122b, 122c corresponding to the diameters of the lower layer contacts formed in the shared part A, the non-shared part B, and the non-shared part C are all the same D1.

  Next, as shown in FIG. 3B, anisotropic dry etching is selectively performed on the first insulating film 109 using the resist pattern 122 as a mask, so that a shared portion A and a non-shared portion B are formed. Then, after forming the lower contact holes 110A, 110B, 110C reaching the etching stopper film 108 in each of the non-shared portions C, dry etching is performed, so that the resist pattern 122 and the lower contact holes 110A, 110B, 110C are formed. The exposed etching stopper film 108 is removed. As a result, the lower layer contact hole 110A connected to the source / drain region 106A is formed in the shared portion A, the lower layer contact hole 110B connected to the source / drain region 106B is formed in the non-shared portion B, and the source in the non-shared portion C is formed. Lower layer contact hole 110C connected to / drain region 106C is formed.

  In the present embodiment, the depth, diameter (for example, diameter of the bottom surface of the hole), and aspect ratio of the lower layer contact holes 110A, 110B, and 110C provided in each of the shared portion A, the non-shared portion B, and the non-shared portion C are substantially equal. Is the same. Therefore, compared to a conventional process in which several types of contact holes having different aspect ratios such as a shared contact hole and a contact hole on a gate are formed at the same time, processing control can be performed more easily, thereby reducing variations in processing dimensions. be able to. Note that the distance from the gate electrode 103A to the lower contact hole 110A in the shared portion A and the distance from the gate electrode 103C to the lower contact hole 110C in the non-shared portion C are approximately the same, and the gate electrode 103B in the non-shared portion B The distance from the lower contact hole 110B to the lower contact hole 110B is longer than the shared part A and the non-shared part C.

  Next, as shown in FIG. 4A, lower barrier metals 111A, 111B made of a laminated film of, for example, a titanium film and a titanium nitride film so as to cover the bottom and side walls of the lower contact holes 110A, 110B, 110C. , 111C. Thereafter, the lower contact holes 110A, 110B, and 110C are filled with the metal-containing films 112A, 112B, and 112C made of tungsten, for example, and then protruded from the lower contact holes 110A, 110B, and 110C, for example, by CMP. The metal-containing films 112A, 112B, and 112C and the lower barrier metals 111A, 111B, and 111c are removed. As a result, a lower layer contact 113A composed of the lower layer barrier metal 111A and the metal-containing film 112A is formed in the lower layer contact hole 110A, and a lower layer contact 113B composed of the lower layer barrier metal 111B and the metal-containing film 112B is formed in the lower layer contact hole 110B. In the formed lower contact hole 110C, a lower contact 113C composed of the lower barrier metal 111C and the metal-containing film 112C is formed.

  In the present embodiment, at the time of CMP for forming the lower layer contacts 113A, 113B, and 113C, for example, by setting overpolishing to about 60 nm, the upper surfaces of the lower layer contacts 113A, 113B, and 113C and the first insulation after polishing are formed. The first insulating film 109 is thinned so that the upper surface of the film 109 and the surface of the etching stopper film 108 on the gate electrodes 103A, 103B, and 103C have substantially the same height. However, after the above-described CMP, the upper surface of the first insulating film 109 after polishing (that is, the upper surfaces of the lower layer contacts 113A, 113B, and 113C) and the surface of the etching stopper film 108 on the gate electrodes 103A, 103B, and 103C are the same. It does not have to be height. In other words, the first insulating film 109 may remain on the etching stopper film 108 on the gate electrodes 103A, 103B, and 103C after the above-described CMP.

  Further, as described above, in the present embodiment, the lower layer contact holes 110A, 110B, and 110C are set to have substantially the same depth and diameter (for example, the diameter of the bottom surface of the hole). , 110C also has substantially the same aspect ratio. Therefore, lower barrier metals 111A, 111B in lower contact holes 110A, 110B, 110C, respectively, as compared with a conventional process in which conductive films are simultaneously embedded in several types of contact holes having different aspect ratios such as shared contact holes and contact holes on gates. , 111C thickness uniformity and embeddability of the metal-containing films 112A, 112B, and 112C can be controlled more accurately, so that the yield can be improved. For example, the thickness of the lower barrier metal 111A on the bottom of the lower contact hole 110A, which is the lower part of the shared contact hole in the shared part A, and the lower contact holes 110B, 110C, which are the lower part of the non-shared contact holes in the non-shared parts B and C. The thicknesses of the lower barrier metals 111B and 111C on the bottom of each can be made substantially the same within the range of film formation variation.

  Next, as shown in FIG. 4B, on the lower contacts 113A, 113B, 113C and on the first insulating film 109 (when the surface of the etching stopper film 108 is exposed, the etching stopper film). 108), a second insulating film 114 made of, for example, a silicon oxide film having a thickness of about 200 nm is deposited. Thereafter, a resist pattern 123 is formed on the second insulating film 114. The resist pattern 123 has an opening 123a in the upper layer contact (contact connected to both the lower layer contact and the gate electrode) formation region of the shared portion A, and the opening 123b in the gate contact formation region of the non-shared portion B. And has an opening 123c in the region where the upper layer contact (connected to the lower layer contact and not connected to the gate electrode) is formed, and the upper layer contact (connected to the lower layer contact) of the non-shared portion C. And a contact not connected to the gate electrode) has an opening 123d. Here, the width of the opening 123b corresponding to the diameter of the gate contact formed in the non-shared portion B, and the openings 123c and 123d corresponding to the diameter of the lower layer contact formed in each of the non-shared portions B and C. Are all the same D2 (where D2 = D1).

  Next, as shown in FIG. 5A, anisotropic dry etching is selectively performed on the second insulating film 114 using the resist pattern 123 as a mask, and then the resist pattern 123 is removed. As a result, in the shared portion A, an upper contact hole 115A connected to both the lower contact 113A and the gate electrode 103A (more precisely, the metal silicide layer 107A formed on the surface of the gate electrode 103A) is formed. In the non-shared portion B, the gate contact hole 115B connected to the gate electrode 103B (more precisely, the metal silicide layer 107B formed on the surface of the gate electrode 103B) and the upper contact hole 115C connected to the lower layer contact 113B. Form. In the non-shared portion C, an upper contact hole 115D connected to the lower contact 113C is formed. Here, in the non-shared portion C, a gate contact hole connected to the gate electrode 103B is not formed.

  In the step shown in FIG. 5A, the upper portions of the gate electrodes 103A and 103B (more precisely, the metal silicide layers 107A and 107B) and the upper portions of the lower layer contacts 113A, 113B, and 113C may be removed.

  In the step shown in FIG. 5A, the tops of the lower layer contacts 113A, 113B, and 113C may protrude from the bottoms of the upper layer contact holes 115A, 115C, and 115D.

  Further, regarding the type of hole group (depth and diameter (for example, the diameter of the bottom surface of the hole)) formed in the step shown in FIG. 5A, the upper contact hole 115A that is the upper part of the shared contact hole of the shared portion A is used. It is the same except for this. In other words, the upper layer contact holes 115C and 115D which are the lower portions of the non-shared contact holes of the non-shared portions B and C and the gate contact hole 115B of the non-shared portion B all have substantially the same depth and diameter. Accordingly, the hole group formed in the process shown in FIG. 5A has only two types of aspect ratios. Therefore, compared to the conventional process in which several types of contact holes having different aspect ratios are formed at the same time, the processing control is further improved. Since it can be performed easily, variations in processing dimensions can be reduced.

  Next, as shown in FIG. 5B, for example, a laminated film of a titanium film and a titanium nitride film so as to cover the bottom and side walls of the upper contact hole 115A, the gate contact hole 115B, and the upper contact holes 115C and 115D. An upper layer barrier metal 116A, a barrier metal 116B, and upper layer barrier metals 116C and 116D are formed. Thereafter, the upper contact hole 115A, the gate contact hole 115B, and the upper contact holes 115C and 115D are filled with metal-containing films 117A, 117B, 117C, and 117D made of, for example, tungsten, and then the upper contact hole 115A is formed by, eg, CMP. Then, unnecessary metal-containing films 117A, 117B, 117C, and 117D protruding from the gate contact hole 115B and the upper contact holes 115C and 115D, and the upper-layer barrier metal 116A, the barrier metal 116B, and the upper-layer barrier metals 116C and 116D are removed. As a result, in the upper layer contact hole 115A of the shared portion A, an upper layer contact 118A made of the upper layer barrier metal 116A and the metal-containing film 117A and connected to both the lower layer contact 113A and the gate electrode 103A is formed. A shared contact composed of 113A and the upper layer contact 118A is formed. Further, in the gate contact hole 115B of the non-shared portion B, a gate contact 118B made of the upper layer barrier metal 116B and the metal-containing film 117B and connected to the gate electrode 103B but not to the lower layer contact 113B is formed. Further, in the upper contact hole 115C of the non-shared portion B, an upper contact 118C made of the upper barrier metal 116C and the metal-containing film 117C, connected to the lower contact 113B, and not connected to the gate electrode 103B is formed. A source / drain contact comprising a lower layer contact 113B and an upper layer contact 118C having substantially the same diameter is formed. Further, in the upper layer contact hole 115D of the non-shared portion C, an upper layer contact 118D made of the upper layer barrier metal 116D and the metal-containing film 117D and connected to the lower layer contact 113C but not to the gate electrode 103C is formed. A source / drain contact comprising a lower layer contact 113C and an upper layer contact 118D having substantially the same diameter is formed.

  As described above, in this embodiment, since the aspect ratio of the hole group formed in the process shown in FIG. 5A is only two types, there are several types having different aspect ratios such as a shared contact hole and a contact hole on the gate. Compared with the conventional process of simultaneously embedding a conductive film in each contact hole, upper barrier metal 116A, barrier metal 116B, and upper barrier metal 116C, 116D in upper contact hole 115A, gate contact hole 115B, and upper contact holes 115C and 115D, respectively. The film thickness uniformity and the embedding property of the metal-containing films 117A, 117B, 117C, and 117D can be controlled more accurately, so that the yield can be improved. Specifically, the thicknesses of the upper barrier metals 116A, 116C, and 116D and the thicknesses of the lower barrier metals 111A, 111B, and 111C can be made substantially the same within the range of film formation variation.

  Next, as shown in FIG. 6, on the second insulating film 114, the upper layer contact 118A (ie, shared contact) of the shared portion A, the gate contact 118B of the non-shared portion B, and the upper layer contact 118C (ie, source / drain). Contact) and the upper layer contact 118D (that is, the source / drain contact) of the non-shared portion C are formed. The wiring 119 is made of, for example, a metal material.

  Here, in the shared portion A, each of the gate electrode 103A and the source / drain region 106A and the wiring 119 are electrically connected by a shared contact having a laminated structure of the lower layer contact 113A and the upper layer contact 118A. In the non-shared portion B, the gate electrode 103A and the wiring 119 are electrically connected by the gate contact 118B, and the source / drain contact having a stacked structure of the lower layer contact 113B and the upper layer contact 118C The drain region 106B and the wiring 119 are electrically connected. In the non-shared portion C, the source / drain region 106C and the wiring 119 are electrically connected by the source / drain contact having a laminated structure of the lower layer contact 113C and the upper layer contact 118D, while the gate electrode 103C and the wiring are connected. It is not electrically connected to 119 (in other words, the wiring 119 is formed so as to pass above the gate electrode 103C).

  Through the steps described above, the manufacture of the semiconductor device having the shared contact according to the present embodiment is completed.

  By the way, in a conventional semiconductor device having a shared contact, the sidewall spacer formed on the side surface of the gate electrode is reduced due to over-etching at the time of contact hole etching and process variation, and as a result, the exposed extension There has been a problem that a junction leak current is generated due to contact between the region (shallow impurity region) and the contact.

  In contrast, in the present embodiment, the shared contact is connected to the source / drain region 106A and is not connected to the gate electrode 103A, and the upper contact 118A is connected to both the lower contact 113A and the gate electrode 103A. It is divided and formed. Therefore, the lower layer contact 113A connected to the source / drain region 106A can be formed sufficiently away from the gate electrode 103A. That is, since the margin for the film thickness reduction of the sidewall spacer 104A when forming the lower layer contact hole 110A in which the lower layer contact 113A is formed increases, the semiconductor substrate 100 (specifically, the extension region) located below the sidewall spacer 104A. Since the situation in which 105A) is exposed can be avoided, it is possible to prevent a decrease in yield due to the occurrence of junction leakage current.

  For example, in the conventional shared contact formation process shown in FIGS. 9A to 9E, as shown in FIG. 7, when the barrier metal 21 covering the bottom and the wall surface of the shared contact hole 12 is formed, the shared contact is formed. Due to the step in the contact hole 12, for example, a variation occurs between the thickness of the barrier metal 21 on the gate electrode 4 and the thickness of the barrier metal 21 on the source / drain region 8, resulting in a contact failure. Will occur and the yield will decrease.

  On the other hand, in the present embodiment, as described above, the lower layer contact holes 110A, 110B, and 110C can have substantially the same aspect ratio, and therefore, a conventional process of simultaneously embedding a conductive film in several types of contact holes having different aspect ratios. Compared to the above, it is possible to more accurately control the film thickness uniformity of the lower barrier metals 111A, 111B, and 111C and the filling properties of the metal-containing films 112A, 112B, and 112C in the lower contact holes 110A, 110B, and 110C, respectively. . Similarly, the upper layer contact hole 115A, the gate contact hole 115B, and the upper layer contact holes 115C, 115D can have only two types of aspect ratios, so that the conductive film is embedded in several types of contact holes having different aspect ratios at the same time as the conventional process. , Upper layer barrier metal 116A, barrier metal 116B, upper layer barrier metal 116C, 116D thickness uniformity and metal-containing films 117A, 117B, 117C in upper layer contact hole 115A, gate contact hole 115B, upper layer contact holes 115C, 115D, respectively. The embedding property of 117D can be controlled more accurately. Therefore, contact failure can be prevented and yield can be improved.

  In the present embodiment, the conductivity type of the semiconductor substrate 100 may be either p-type or n-type.

  In the present embodiment, the shared contact used for the static random access memory (SRAM) has been described as an example. However, if the shared contact connected to both the source / drain region and the gate electrode is provided, the element of the device can be used. The type is not particularly limited.

  In this embodiment, titanium and titanium nitride are used as the barrier metal material of each contact, and tungsten is used as the main body material of each contact. However, it goes without saying that any material is not particularly limited. For example, tantalum and tantalum nitride may be used as the barrier metal material of each contact, and copper may be used as the main body material of each contact.

  In the present embodiment, polysilicon is used as the material of each gate electrode, but it goes without saying that the material of each gate electrode is not particularly limited. For example, a silicon compound, tungsten, titanium, aluminum, or the like may be used as a material for each gate electrode.

  In this embodiment, the silicon oxide film is used as the first insulating film 109 in which the lower contact is formed and the second insulating film 114 in which the upper contact is formed. However, the material of each insulating film is Needless to say, there is no particular limitation. For example, BPSG, PSG, or the like may be used as the material for the insulating films 109 and 114. Further, different materials may be used for the insulating films 109 and 114 instead of the same material.

  In this embodiment, a silicon nitride film is used as the etching stopper film 108, but a silicon carbide film or the like may be used instead.

  In the present embodiment, the planar shape of the upper layer contact 118A is set to the track shape (see FIG. 1B), but it goes without saying that the planar shape of the upper layer contact 118A is not particularly limited. Further, although the planar shapes of the lower layer contacts 113A, 113B, and 113C are set to be circular, it goes without saying that the planar shapes of the lower layer contacts 113A, 113B, and 113C are not particularly limited. However, in order to improve the film thickness uniformity of the lower barrier metals 111A, 111B, and 111C, it is preferable that the planar shapes (for example, bottom shapes) of the lower contacts 113A, 113B, and 113C are substantially the same. Further, although the planar shapes of the gate contact 118B and the upper layer contacts 118C and 118D are set to be circular, it is needless to say that the planar shape of the gate contact 118B and the upper layer contacts 118C and 118D is not particularly limited. However, in order to improve the film thickness uniformity of the barrier metal 116B and the upper barrier metals 116C and 116D, the planar shape (for example, the bottom surface shape) of the gate contact 118B and the upper contact 118C and 118D is substantially the same. Is preferred.

  In the present embodiment, the semiconductor device having the gate structure having the sidewall spacer has been described as an example. Instead, for example, as shown in FIG. 8, the gate structure in which the sidewall spacer is removed. Even when a semiconductor device having a (disposable sidewall structure) is targeted, the same effect as that of the present embodiment can be obtained. FIG. 8 is a view corresponding to FIG. 6 which is a cross-sectional view showing the final process of the method for manufacturing the semiconductor device according to the first embodiment. In FIG. 8, the same components as those shown in FIG. The same reference numerals are attached.

  The disposable sidewall structure as shown in FIG. 8 is formed after the step of forming the source / drain regions 106A, 106B, and 106C and the step of forming the metal silicide layers 107A, 107B, and 107C shown in FIG. It can be obtained by removing the sidewall spacers 104A, 104B, and 104C on the side surfaces of the gate electrodes 103A, 103B, and 103C before performing the step of depositing the etching stopper film 108 shown in FIG. That is, the disposable sidewall structure shown in FIG. 8 is different from the semiconductor device according to the first embodiment shown in FIG. 6 in that sidewall spacers 104A, 104B, 104C is not formed.

  In the disposable sidewall structure shown in FIG. 8, offset spacers (spacers formed on the side surfaces of the gate electrode before forming the extension regions) may be formed on the side surfaces of the gate electrodes 103A, 103B, and 103C.

  Further, in the disposable sidewall structure shown in FIG. 8, the side wall spacers 104A, 104B, and 104C are not formed on the side surfaces of the gate electrodes 103A, 103B, and 103C. A part of the first insulating film 109 exists between the contact 113A, between the gate electrode 103B and the lower layer contact 113B, and between the gate electrode 103C and the lower layer contact 113C.

  As described above, the present invention is useful as a semiconductor device provided with a shared contact and a manufacturing method thereof.

100 Semiconductor substrate 101 Element isolation region 102, 102A, 102B, 102C Gate insulating film 103, 103A, 103B, 103C Gate electrode 104, 104A, 104B, 104C Side wall spacer 105, 105A, 105B, 105C Extension region 106, 106A, 106B 106C Source / drain regions 107, 107A, 107B, 107C Metal silicide layer 108 Etching stopper film 109 First insulating film 110, 110A, 110B, 110C Lower layer contact hole 111, 111A, 111B, 111C Lower layer barrier metal 112, 112A, 112B, 112C Metal-containing film 113, 113A, 113B, 113C Lower layer contact 114 Second insulating film 115, 115A, 115C, 15D Upper layer contact hole 115B Gate contact hole 116, 116A, 116C, 116D Upper layer barrier metal 116B Barrier metal 117, 117A, 117B, 117C, 117D Metal-containing film 118, 118A, 118C, 118D Upper layer contact 118B Gate contact 119 Wiring 121 Side wall Insulating film 122 resist pattern 122a, 122b, 122c opening 123 resist pattern 123a, 123b, 123c, 123d opening

Claims (25)

A first gate electrode formed on a semiconductor substrate;
A sidewall insulating film formed on a side surface of the first gate electrode;
A first source / drain region formed on both sides of the first gate electrode in the semiconductor substrate and spaced apart from the first gate electrode;
An interlayer insulating film formed to cover the first gate electrode and the first source / drain region;
A shared contact formed in the interlayer insulating film and connected to both the first gate electrode and the first source / drain region;
The shared contact includes a first lower layer contact connected to the first source / drain region and not connected to the first gate electrode, and both the first lower layer contact and the first gate electrode. And a first upper layer contact connected to the semiconductor device. The semiconductor device according to claim 1,
An upper barrier metal is provided on the bottom and sides of the first upper contact,
The semiconductor device according to claim 1, wherein an upper surface of the first lower layer contact is in contact with an upper barrier metal. The semiconductor device according to claim 2,
A bottom barrier metal is provided on the bottom and sides of the first bottom contact,
A thickness of the upper barrier metal and a thickness of the lower barrier metal are substantially the same. The semiconductor device according to any one of claims 1 to 3,
A second gate electrode formed on the semiconductor substrate;
A second source / drain region formed on both sides of the second gate electrode in the semiconductor substrate;
A source / drain contact formed in the interlayer insulating film and connected to the second source / drain region and not connected to the second gate electrode;
The semiconductor device, wherein the source / drain contact has a second lower layer contact connected to the second source / drain region and a second upper layer contact connected to the second lower layer contact. The semiconductor device according to claim 4,
The shape of the bottom surface of the first lower layer contact and the shape of the bottom surface of the second lower layer contact are substantially the same. The semiconductor device according to claim 4 or 5,
A semiconductor device, further comprising a gate contact formed in the interlayer insulating film and connected to the second gate electrode and not connected to the second source / drain region. The semiconductor device according to claim 6.
The shape of the bottom surface of the second upper layer contact and the shape of the bottom surface of the gate contact are substantially the same. In the semiconductor device according to claim 1,
The semiconductor substrate further includes an extension region formed below the side wall insulating film and shallower than the first source / drain region and connected to the first source / drain region,
The semiconductor device according to claim 1, wherein the first lower layer contact is formed apart from the extension region. The semiconductor device according to any one of claims 1 to 8,
A semiconductor device, wherein a metal silicide layer is formed on a surface portion of each of the first gate electrode and the first source / drain region. The semiconductor device according to any one of claims 1 to 9,
A semiconductor device, wherein an etching stopper film is formed between the first gate electrode and the first lower layer contact on the semiconductor substrate. A first gate electrode formed on a semiconductor substrate;
A first source / drain region formed on both sides of the first gate electrode in the semiconductor substrate and spaced apart from the first gate electrode;
An interlayer insulating film formed to cover the first gate electrode and the first source / drain region;
A shared contact formed in the interlayer insulating film and connected to both the first gate electrode and the first source / drain region;
A sidewall insulating film is not formed on the side surface of the first gate electrode,
The shared contact includes a first lower layer contact connected to the first source / drain region and not connected to the first gate electrode, and both the first lower layer contact and the first gate electrode. And a first upper layer contact connected to the semiconductor device. The semiconductor device according to claim 11,
An upper barrier metal is provided on the bottom and sides of the first upper contact,
The semiconductor device according to claim 1, wherein an upper surface of the first lower layer contact is in contact with an upper barrier metal. The semiconductor device according to claim 12,
A bottom barrier metal is provided on the bottom and sides of the first bottom contact,
A thickness of the upper barrier metal and a thickness of the lower barrier metal are substantially the same. The semiconductor device according to any one of claims 11 to 13,
A second gate electrode formed on the semiconductor substrate;
A second source / drain region formed on both sides of the second gate electrode in the semiconductor substrate;
A source / drain contact formed in the interlayer insulating film and connected to the second source / drain region and not connected to the second gate electrode;
The semiconductor device, wherein the source / drain contact has a second lower layer contact connected to the second source / drain region and a second upper layer contact connected to the second lower layer contact. The semiconductor device according to claim 14.
The shape of the bottom surface of the first lower layer contact and the shape of the bottom surface of the second lower layer contact are substantially the same. The semiconductor device according to claim 14 or 15,
A semiconductor device, further comprising a gate contact formed in the interlayer insulating film and connected to the second gate electrode and not connected to the second source / drain region. The semiconductor device according to claim 16, wherein
The shape of the bottom surface of the second upper layer contact and the shape of the bottom surface of the gate contact are substantially the same. The semiconductor device according to any one of claims 11 to 17,
The semiconductor substrate further comprising an extension region formed shallower than the first source / drain region and connected to the first source / drain region in a region adjacent to the first gate electrode;
The semiconductor device according to claim 1, wherein the first lower layer contact is formed apart from the extension region. The semiconductor device according to any one of claims 11 to 18,
A semiconductor device, wherein a metal silicide layer is formed on a surface portion of each of the first gate electrode and the first source / drain region. The semiconductor device according to any one of claims 11 to 19,
A semiconductor device, wherein an etching stopper film is formed between the first gate electrode and the first lower layer contact on the semiconductor substrate. 21. The semiconductor device according to claim 11, wherein:
A part of the interlayer insulating film is formed between the first gate electrode and the first lower layer contact on the semiconductor substrate. Forming a first gate electrode on the semiconductor substrate (a);
(B) forming an extension region by introducing impurities into the semiconductor substrate using the first gate electrode as a mask;
Forming a sidewall insulating film on a side surface of the first gate electrode;
(D) forming a first source / drain region by introducing impurities into the semiconductor substrate using the first gate electrode and the sidewall insulating film as a mask;
A step (e) of sequentially depositing an etching stopper film and a first insulating film on the semiconductor substrate including the top of the first gate electrode after the step (d);
(F) forming a first lower layer contact hole connected to the first source / drain region by etching the first insulating film and the etching stopper film;
Forming in the first lower layer contact hole a first lower layer contact having a lower layer barrier metal on the bottom and side (g);
Forming a second insulating film on the first lower layer contact and on the first insulating film (h);
(I) forming a first upper layer contact hole connected to each of the first lower layer contact and the first gate electrode by etching the second insulating film;
And a step (j) of forming a first upper layer contact having an upper barrier metal on the bottom and side portions in the first upper layer contact hole. In the manufacturing method of the semiconductor device according to claim 22,
A method of manufacturing a semiconductor device, further comprising a step of removing the sidewall insulating film between the step (d) and the step (e). In the manufacturing method of the semiconductor device of Claim 22 or 23,
Forming a second gate electrode on the semiconductor substrate (k);
And (1) forming a second source / drain region on both sides of the second gate electrode in the semiconductor substrate,
The step (f) includes a step of forming a second lower layer contact hole connected to the second source / drain region by etching the first insulating film and the etching stopper film,
The step (g) includes a step of forming a second lower layer contact in the second lower layer contact hole,
The step (i) is a step of etching the second insulating film to form a second upper layer contact hole that is connected to the second lower layer contact and not connected to the second gate electrode. Including
The method (j) includes a step of forming a second upper layer contact in the second upper layer contact hole. In the manufacturing method of the semiconductor device according to claim 24,
The step (i) includes a step of etching the second insulating film to form a gate contact hole that is connected to the second gate electrode and not connected to the second lower layer contact,
The method (j) includes a step of forming a gate contact in the gate contact hole.

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