KR101996710B1 - Gate contact structure over active gate and method to fabricate same - Google Patents

Abstract

Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, the semiconductor structure includes a substrate having an active region and an isolation region. The gate structure has a portion disposed over the active region of the substrate and a portion disposed over the isolation region. The source and drain regions are disposed in an active region of the substrate on either side of the gate structure portion disposed over the active region. The gate contact structure is disposed on a portion of the gate structure disposed over the active region of the substrate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate contact structure on an active gate,

Embodiments of the present invention are in the field of semiconductor device and processing, particularly gate contact structures disposed over active portions of gates and methods of forming such gate contact structures.

Over the past several decades, scaling of features in integrated circuits has been the driving force for the growing semiconductor industry. Scaling to smaller and smaller features makes it possible to increase the density of functional units on semiconductor chips of limited area. For example, it is possible to include an increased number of memory or logic devices on a chip by reducing transistor size, making it suitable for manufacturing increased capacity products. However, the need for increasing capacity is an issue. The need to optimize the performance of each device is becoming increasingly important.

In the manufacture of integrated circuit devices, multi-gate transistors such as tri-gate transistors have become more common as device dimensions continue to shrink. In conventional processes, tri-gate transistors are typically fabricated on one of a bulk silicon substrate or a silicon-on-insulator substrate. In some cases, bulk silicon substrates are desirable because they enable low cost and less complex tri-gate fabrication processes.

However, scaling of multi-gate transistors has had side effects. As the dimensions of such basic building blocks of the microelectronic circuit have decreased and the total number of basic building blocks made in a particular area has increased, constraints on the lithography processes used to pattern the building blocks have become irresistible. In particular, there may be a trade-off between the minimum dimension (critical dimension) of the patterned features in the semiconductor stack and the spacing between the features.

Figure 1A illustrates a top view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode.
Figure IB illustrates a cross-sectional view of a planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode.
Figure 1C illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode.
2A illustrates a plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode, in accordance with an embodiment of the invention.
Figure 2B illustrates a cross-sectional view of a planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode, in accordance with an embodiment of the present invention.
2C illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode, in accordance with an embodiment of the invention.
3A-3F illustrate cross-sectional views illustrating various operations in a method of fabricating a semiconductor structure having a gate contact structure disposed over an active portion of a gate, in accordance with an embodiment of the present invention;
Figure 3A illustrates a semiconductor structure after trench contact formation;
Figure 3b illustrates recessing the trench contacts and forming an insulating cap layer thereon in the spacers of the structure of Figure 3a;
FIG. 3C illustrates the step of forming and patterning an interlayer dielectric (ILD) and a hardmask stack on the structure of FIG. 3B; FIG.
FIG. 3D illustrates the step of forming via openings in an interlayer dielectric (ILD) extending from a metal (0) trench in the structure of FIG. 3C to one or more recessed trench contacts;
FIG. 3E illustrates forming via openings in an interlayer dielectric (ILD), extending from a metal (0) trench in the structure of FIG. 3D to one or more gate stack structures;
Figure 3F illustrates the step of forming a metal contact structure in the metal (0) trenches and via openings of the structure described with respect to Figure 3E.
Figure 4 illustrates a cross-sectional view of another non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode, in accordance with another embodiment of the present invention.
Figures 5A and 5B illustrate cross-sectional views illustrating various operations in a method of fabricating another semiconductor structure having a gate contact structure disposed over an active portion of a gate, according to another embodiment of the present invention.
Figure 6 illustrates a plan view of another semiconductor device having gate contact vias disposed over active portions of the gate, according to another embodiment of the present invention.
Figure 7 illustrates a top view of another semiconductor device having trench contact vias coupling a pair of trench contacts, in accordance with another embodiment of the present invention.
Figure 8 illustrates a computing device in accordance with an implementation of the present invention.

Gate contact structures disposed over the active portions of the gates and methods of forming such gate contact structures are described. In the following description, numerous specific details are set forth such as specific integration and material schemes in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without such specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order not to unnecessarily obscure embodiments of the present invention. In addition, the various embodiments shown in the figures are illustrative and not necessarily drawn to scale.

One or more embodiments of the present invention are directed to semiconductor structures or devices having one or more gate contact structures (e.g., gate contact vias) disposed over active portions of gate structures of semiconductor structures or devices . One or more embodiments of the present invention are directed to methods of fabricating semiconductor structures or devices having one or more gate contact structures formed over active portions of gate structures of semiconductor structures or devices. The approaches described in the present invention can be used to reduce the standard cell area by allowing gate contact formation over the active gate regions. In at least one embodiment, the gate contact structures fabricated to contact the gate electrodes are self aligned via structures.

In techniques where space and layout constraints are somewhat mitigated relative to current generation space and layout constraints, the contact to the gate structure may be fabricated by contacting a portion of the gate electrode disposed over the isolation region. By way of example, FIG. 1A illustrates a plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode.

1A, a semiconductor structure or device 100A includes a diffusion or active region 104 disposed in a substrate 102 within isolation region 106. As shown in FIG. One or more gate lines (also known as polylines), such as gate lines 108A, 108B, and 108C, are disposed over a portion of the isolation region 106 as well as over the diffusion or active region 104. [ Source or drain contacts (also known as trench contacts), such as contacts 110A and 110B, are disposed over the source and drain regions of the semiconductor structure or device 100A. Trench contact vias 112A and 112B provide contacts to trench contacts 110A and 110B, respectively. A separate gate contact 114 and an overlying gate contact via 116 provide contact to the gate line 108B. In contrast to the source or drain trench contacts 110A or 110B, the gate contact 114 is disposed over the isolation region 106 and not over the diffusion or active region 104 in plan view. Also, neither the gate contact 114 nor the gate contact via 116 is disposed between the source or drain trench contacts 110A or 110B.

Figure IB illustrates a cross-sectional view of a planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode. 1B, a planar version of a semiconductor structure or device 100B, e.g., device 100A of FIG. 1A, includes a planar diffusion or active region 104B disposed in a substrate 102 within isolation region 106, ). The gate line 108B is disposed on a portion of the isolation region 106 as well as above the planar diffusion or active region 104B. As shown, the gate line 108B includes a gate electrode 150 and a gate dielectric layer 152. A dielectric cap layer 154, for example a dielectric cap layer for protecting the metal gate electrode, may also be disposed on the gate electrode. Gate contact 114 and overlying gate contact vias 116 also appear in this regard with overlying metal interconnect 160, all of which are disposed in interlayer dielectric stacks or layers 170. Also shown in view of FIG. 1B is that gate contact 114 and gate contact via 116 are disposed over isolation region 106 but not over planar diffusion or active region 104B.

Figure 1C illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode. 1C, a non-planar version of the semiconductor structure or device 100C, e.g., the device 100A of FIG. 1A, may include a non-planar diffusion or active region (not shown) formed from the substrate 102 within isolation region 106 104C) (e.g., a fin structure). Gate line 108B is disposed over a portion of isolation region 106 as well as over non-planar diffusion or active region 104C. As shown, the gate line 108B, along with the dielectric cap layer 154, includes a gate electrode 150 and a gate dielectric layer 152. Gate contact 114 and overlying gate contact vias 116 also appear in this regard with overlying metal interconnect 160, all of which are disposed in interlayer dielectric stacks or layers 170. 1c, the gate contact 114 is disposed over the isolation region 106, but not over the non-planar diffusion or active region 104C.

1A-1C, the structure of the semiconductor structure or device 100A-100C each place a gate contact over the isolation regions. Such a configuration wastes layout space. However, placing the gate contacts over the active regions would require a significant stringent registration budget, or gate dimensions would need to be increased to provide sufficient space to form gate contacts. Also, historically, contacts to the gate over diffusion regions have been avoided due to the risk of perforating through conventional gate material (e.g., polysilicon) and contacting the underlying active region. One or more embodiments described in the present invention address the issues discussed above by providing feasible approaches and obtained structures for manufacturing contact structures that are in contact with portions of a gate electrode formed over a diffusion or active region.

By way of example, FIG. 2A illustrates a plan view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode, in accordance with an embodiment of the invention. Referring to FIG. 2A, a semiconductor structure or device 200A includes a diffusion or active region 204 disposed in a substrate 202 within an isolation region 206. FIG. One or more gate lines, such as gate lines 208A, 208B, and 208C, are disposed over a portion of isolation region 206 as well as over diffusion or active region 204. [ Source or drain trench contacts, such as trench contacts 210A and 210B, are disposed over the source and drain regions of the semiconductor structure or device 200A. Trench contact vias 212A and 212B provide contacts to trench contacts 210A and 210B, respectively. Without an intervening separate gate contact layer, the gate contact via 216 provides a contact to the gate line 208B. In contrast to FIG. 1A, a gate contact 216 is disposed over a diffusion or active region 204 and between source or drain contacts 210A and 210B in plan view.

Figure 2B illustrates a cross-sectional view of a planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode, in accordance with an embodiment of the present invention. 2B, a planar version of the semiconductor structure or device 200B, e.g., device 200A of FIG. 2A, includes a planar diffusion or active region 204B disposed in the substrate 202 within isolation region 206, . Gate line 208B is disposed over a portion of isolation region 206 as well as over planar diffusion or active region 204B. As shown, the gate line 208B includes a gate electrode 250 and a gate dielectric layer 252. [ A dielectric cap layer 254, for example a dielectric cap layer for protecting the metal gate electrode, may also be disposed on the gate electrode. Along with the overlying metal interconnects 260, the gate contact vias 216 also appear in this regard, both disposed in the interlayer dielectric stacks or layers 270. As also shown in FIG. 2B, gate contact vias 216 are disposed above the planar diffusion or active region 204B.

2C illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode, in accordance with an embodiment of the invention. 2C, a non-planar version of the semiconductor structure or device 200C, e.g., device 200A of FIG. 2A, includes a non-planar diffusion or active region 204C formed from the substrate 202 within isolation region 206, (E.g., a pin structure). Gate line 208B is disposed over a portion of isolation region 206 as well as over non-planar diffusion or active region 204C. As shown, gate line 208B includes gate electrode 250 and gate dielectric layer 252, along with dielectric cap layer 254. Along with the overlying metal interconnects 260, the gate contact vias 216 also appear in this regard, both disposed in the interlayer dielectric stacks or layers 270. 2c, gate contact vias 216 are disposed over the non-planar diffusion or active region 204C.

Thus, referring again to Figures 2A-2C, in one embodiment, the trench contact vias 212A, 212B and the gate contact vias 216 are formed in the same layer and are essentially coplanar. Compared to FIGS. 1A-1C, the contact for the gate line would comprise an additional gate contact layer, which may be perpendicular to the corresponding gate line, for example, unlike the above. However, in the structure (s) described in connection with Figures 2A-2C, the fabrication of structures 200A-200C may each be such that contacts are formed directly from the metal interconnect layer directly on the active gate portion As shown in FIG. In one embodiment, such a configuration increases the area reduction in the circuit layout by eliminating the need to extend the transistor gates on the isolation region, thereby forming a reliable contact. As used throughout this specification, in one embodiment, denoting the active portion of a gate refers to a gate line or structure portion (plan view perspective) disposed over the active or diffusive region of the underlying substrate. In one embodiment, denoting the inactive portion of the gate refers to a gate line or structure portion (plan view perspective) disposed over the isolation region of the underlying substrate.

In one embodiment, the semiconductor structure or device 200 is a planar device such as that shown in Figure 2B. In another embodiment, the semiconductor structure or device 200 is a non-planar device such as, but not limited to, a pin-FET or tri-gate device. In such an embodiment, the corresponding semiconductor channel region is constructed or formed with a three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines 208A-208C enclose at least the top surface and the pair of side walls of the three-dimensional body. In another embodiment, at least the channel region is fabricated to be a separate three-dimensional body, such as in a gate-all-around device. In one such embodiment, the gate electrode stacks of gate lines 208A-208C completely surround the channel region, respectively.

The substrate 202 may be constructed of a semiconductor material that is capable of withstanding the fabrication process and capable of transferring charge. In one embodiment, the substrate 202 may be formed of a charge carrier, such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof, to form the diffusion or active region 204 Doped, crystalline silicon, a silicon / germanium or germanium layer. In one embodiment, the silicon atom concentration of the bulk substrate 202 is greater than 97%. In another embodiment, the bulk substrate 202 is comprised of an epitaxial layer grown on top of a separate crystalline substrate, for example a silicon epitaxial layer grown on top of a boron-doped bulk silicon monocrystalline substrate. The bulk substrate 202 may alternatively be comprised of a Group III-V material. In one embodiment, the bulk substrate 202 may be formed of a material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, V materials such as indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate 202 is comprised of a III-V material and the charge-carrier dopant impurity atoms include, but are not limited to, carbon, silicon, germanium, oxygen ), Sulfur, selenium, or tellurium. In an alternative embodiment, the substrate 202 is a silicon- or semiconductor-on-insulator (SOI) substrate.

The isolation region 206 may isolate the active regions formed in the underlying bulk substrate, such as ultimately electrically isolating portions of the permanent gate structure from the underlying bulk substrate or contributing to their isolation, or isolating the pin active regions And may be made of a material suitable for the following. For example, in one embodiment, the isolation region 206 may include, but is not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and carbon-doped silicon nitride.

Gate lines 208A, 208B, and 208C may be comprised of gate electrode stacks, each of which includes a gate dielectric layer and a gate electrode layer (not shown here as separate layers). In one embodiment, the gate electrode of the gate electrode stack is comprised of a metal gate and the gate dielectric layer is comprised of a high permittivity material. For example, in one embodiment, the gate dielectric layer may include, but is not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, Zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide such as lead oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. In addition, a portion of the gate dielectric layer may comprise a native oxide layer formed from several upper layers of the substrate 202. In one embodiment, the gate dielectric layer is comprised of a high-permittivity top portion and a bottom portion comprised of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is comprised of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride.

In one embodiment, the gate electrode may be formed of a material selected from the group consisting of, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, a metal layer such as zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or a conductive metal oxide. . In a particular embodiment, the gate electrode is comprised of a non-work function setting fill material formed over the metal work function-setting layer.

The spacers associated with the gate electrode stacks may be composed of a material suitable for ultimately electrically isolating or contributing to the detachment of the permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are comprised of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

Any or all of the contacts 210A and 210B and the vias 212A, 212B, and 216 may be constructed of a conductive material. In one embodiment, any or all of these contacts or vias are comprised of metal species. The metal species may be pure metals such as tungsten, nickel or cobalt, or alloys such as metal-metal alloys or metal-semiconductor alloys (e.g., silicide materials).

More generally, one or more embodiments relate to approaches to forming gate contact vias directly above the active transistor gate and structures formed therefrom. Such approaches may make it unnecessary to extend the gate line on the isolation region for contact purposes. Such approaches may also eliminate the need for a separate gate contact (GCN) layer to conduct signals from the gate line or structure. In one embodiment, the removal of the features described above is accomplished by recessing the contact metals of the trench contact (TCN) and introducing additional dielectric material (e.g., TILA) in the process flow. The additional dielectric material is included as a trench contact dielectric cap layer having etch characteristics that differ from the gate dielectric material cap layer (e.g., GILA) already used for trench contact alignment in a gate aligned contact process (GAP) processing scheme.

3A-3F illustrate cross-sectional views illustrating various operations in a method of fabricating a semiconductor structure having a gate contact structure disposed over an active portion of a gate, in accordance with an embodiment of the present invention.

Referring to FIG. 3A, a semiconductor structure 300 is provided following trench contact (TCN) formation. It will be appreciated that the particular configuration of structure 300 is used for illustrative purposes only, and that various layouts possible from the embodiments of the invention described in this application may be advantageous. The semiconductor structure 300 includes one or more gate stack structures, such as gate stack structures 308A-308E, disposed on the substrate 302. The gate stack structures may include a gate dielectric layer and a gate electrode, as described above in connection with FIG. Contacts for the diffusion regions of the substrate 302, such as trench contacts, e.g., trench contacts 310A-310C, are also included in the structure 300 and are electrically connected to the gate stack structure 320 by dielectric spacers 320. [ 308A-308E. ≪ / RTI > As depicted in FIG. 3A, an insulating cap layer 322 may be disposed on the gate stack structures 308A-308E (e.g., GILA). As also depicted in FIG. 3A, contact blocking regions or "contact plugs ", such as regions 323 made of interlayer dielectric material, can be included in regions where contact formation is blocked.

The process used to provide the structure 300 is described in detail in U. S. Patent Application Serial No. 10 / 548,502, filed December 22, 2011, by Intel Corp., which is incorporated herein by reference, Which is described in International Patent Application No. PCT / US11 / 66989, entitled " Gate Aligned Contact and Method to Fabricate Same ". For example, self-aligned contacts 310A-310C may be formed using trench contact etch selectively performed on insulating cap layer 322. [

In one embodiment, providing the structure 300 involves the formation of a contact pattern that is essentially completely aligned with the existing gate pattern, while eliminating the need to use a lithography step with a significant stringent registration budget. In one such embodiment, this approach enables the use of a highly selective wet etch (e.g., compared to a dry or plasma etch that is conventionally implemented) to create contact openings. In one embodiment, the contact pattern is formed by using an existing gate pattern in combination with a contact plug lithography operation. In such an embodiment, the approach may be such that, as used in conventional approaches, the lithography process, which is otherwise crucial for generating the contact pattern, is not necessary. In one embodiment, the trench contact grid is not separately patterned and is formed between the poly (gate) lines. For example, in one such embodiment, a trench contact grid is formed after gate-patterning and before gate-gating cutting.

In addition, the gate stack structures 308A-308E may be fabricated by a replacement gate process. In such a configuration, a dummy gate material, such as a polysilicon or silicon nitride pillar material, may be removed and replaced with a permanent gate electrode material. In one such embodiment, as opposed to what was done through previous processing, a permanent gate dielectric layer is also formed in this process. In one embodiment, the dummy gates are removed by a dry etch or wet etch process. In one embodiment, the dummy gates consist of polycrystalline silicon or amorphous silicon and are removed by a dry etch process that includes SF ₆ . In another embodiment, the dummy gates are formed of polycrystalline silicon or amorphous silicon and are removed by a wet etch process comprising aqueous NH ₄ OH or tetramethylammonium hydroxide. In one embodiment, the dummy gates are composed of silicon nitride and are removed by wet etching that includes phosphoric acid.

In one embodiment, the one or more approaches described in the present invention essentially arrive at the structure 300 in consideration of the dummy and replacement gate processes in combination with the dummy and replacement contact processes. In one such embodiment, the replacement contact process is performed after the replacement gate process to enable high temperature annealing of at least a portion of the permanent gate stack. For example, in such specific embodiments, annealing at least a portion of the permanent gate structures, e.g., after the gate dielectric layer is formed, is performed at a temperature greater than about 600 ° C. The annealing is performed prior to the formation of the permanent contacts.

Referring to Figure 3B, the trench contacts 310A-310C of the structure 300 are recessed in the spacers 320 so that the spacers 320 and the insulating cap layer 322, To provide recessed trench contacts 311A-311C. An insulating cap layer 324 is then formed on the recessed trench contacts 311A-311C (e.g., TILA). The isolation cap layer 324 on the recessed trench contacts 311A-311C has different etch characteristics than the isolation cap layer 322 on the gate stack structures 308A-308E . As can be seen in subsequent processing steps, one of the 322/324 can be selectively etched from the other of the 322/324 using such a difference.

The trench contacts 310A-310C may be recessed by an optional process for the materials of the spacers 320 and the insulating cap layer 322. [ For example, in one embodiment, the trench contacts 310A-310C are recessed by an etch process, such as a wet etch process or a dry etch process. The insulating cap layer 324 may be formed by a process suitable to provide conformal and sealing layers over the exposed portions of the trench contacts 310A-310C. For example, in one embodiment, the insulating cap layer 324 is formed by a chemical vapor deposition (CVD) process as an conformal layer over the entire structure. The isotropic layer is then planarized, for example by CMP, to provide the isolation cap layer 324 material only over the trench contacts 310A-310C and the spacers 320 and the isolation cap layer 322 are again exposed .

In a suitable material combination for the insulating cap layer 322/324, in one embodiment, one of the pairs 322/324 is comprised of silicon oxide while the other is comprised of silicon nitride. In another embodiment, one of the pairs of 322/324 is comprised of silicon oxide while the other is comprised of carbon doped silicon nitride. In another embodiment, one of the pairs of 322/324 is comprised of silicon oxide while the other is comprised of silicon carbide. In another embodiment, one of the pairs 322/324 is comprised of silicon nitride while the other is comprised of carbon doped silicon nitride. In another embodiment, one of the pairs of 322/324 is comprised of silicon nitride while the other is comprised of silicon carbide. In another embodiment, one of the pairs of 322/324 is comprised of carbon doped silicon nitride while the other is comprised of silicon carbide.

3C, an interlayer dielectric (ILD) 330 and a hard mask 332 stack are formed and patterned to provide a patterned metal (0) trench 334, for example, over the structure of FIG. 3B.

The interlevel dielectric (ILD) 330 may be composed of a material suitable for electrically separating the metal features ultimately formed therein while maintaining a robust structure for the front end and back end processing. Also, in one embodiment, the composition of the ILD 330 may be adjusted to match the via etch selectivity for trench contact dielectric layer and gate dielectric cap layer patterning, as described in more detail below with respect to Figures 3D and 3E. Is selected. In one embodiment, ILD 330 is comprised of single or multiple layers of silicon oxide, or single or multiple layers of carbon doped oxide (CDO) material. However, in other embodiments, the ILD 330 may include a dual-layer structure having an upper portion constructed of a different material than the underlying portion underlying the ILD 330, as described in greater detail below with respect to FIG. Layer composition. The hardmask layer 332 may be composed of a material suitable to serve as a subsequent sacrificial layer. For example, in one embodiment, the hardmask layer 332 is substantially comprised of carbon and is configured, for example, as a cross-linked organic polymer layer. In other embodiments, a silicon nitride or carbon-doped silicon nitride layer is used as the hard mask 332. Interlayer dielectric (ILD) 330 and hard mask 332 stacks may be patterned by lithography and etching processes.

Referring to Figure 3D, the via openings 336 (e.g., VCT) extend from the metal (0) trench 334 to one or more recessed trench contacts 311A-311C to form an interlayer dielectric ILD < / RTI > For example, in Figure 3D, the via openings are formed to expose the recessed trench contacts 311A and 311C. The formation of the via openings 336 includes etching both portions of the interlayer dielectric (ILD) 330 and the corresponding insulating cap layer 324. In one such embodiment, a portion of the insulating cap layer 322 is exposed during patterning of the interlevel dielectric (ILD) 330 (e.g., the insulating cap layer 322 over the gate stack structures 308B and 308E) ) Is exposed). In that embodiment, the insulating cap layer 324 is etched to form via openings 336 selectively in the insulating cap layer 322 (i.e., without significant etching or impact).

The via openings 336 may be formed by first depositing a hard mask layer, an antireflective coating (ARC) layer and a photoresist layer. In one embodiment, the hard mask layer is comprised substantially of carbon, for example, as a crosslinked organic polymer layer. In one embodiment, the ARC layer is suitable for suppressing reflective interference during lithographic patterning of the photoresist layer. In one such embodiment, the ARC layer is a silicon ARC layer. The photoresist layer may be comprised of a material suitable for use in a lithographic process. In one embodiment, the photoresist layer is formed by first masking the blanket layer of the photoresist material and exposing it to a light source. The blanket photoresist layer can then be developed to form a patterned photoresist layer. In one embodiment, portions of the photoresist layer exposed to the light source are removed upon development of the photoresist layer. Thus, the patterned photoresist layer is comprised of a positive photoresist material. In one particular embodiment, the photoresist layer comprises at least one of a 248 nm resist, a 193 nm resist, a 157 nm resist, an extreme ultra violet (EUV) resist, an e-beam imprint layer or a diazonaphthoquinone sensitizer and a positive photoresist material such as a phenolic resin matrix using a sensitizer. In another embodiment, portions of the photoresist layer exposed to the light source are preserved upon development of the photoresist layer. Thus, the photoresist layer is composed of a negative photoresist material. In a particular embodiment, the photoresist layer is formed from a negative photoresist material such as, but not limited to, poly-cis-isoprene or poly-vinyl-cinnamate .

In accordance with one embodiment of the present invention, the pattern of photoresist layers (e.g., the pattern of via openings 336) is transferred to the hard mask layer by using a plasma etch process. The pattern is ultimately transferred to the interlayer dielectric (ILD) 330, for example, by different or the same dry etching process. In one embodiment, the pattern is then transferred to an insulating cap layer 324 (i.e., trench contact insulating cap layers) by an etch process that does not etch the insulating cap layer 322 (i.e., the gate insulating cap layers) do. The insulating cap layer 324 (TILA) may comprise any of a variety of metal oxides including silicon oxide, silicon nitride, silicon carbide, carbon doped silicon nitride, carbon doped silicon oxide, amorphous silicon, and zirconium oxide, hafnium oxide, lanthanum oxide, ≪ / RTI > and silicates, or combinations thereof. Layer may be deposited using any of the techniques including CVD, ALD, PECVD, PVD, HDP assisted CVD, and low temperature CVD. Corresponding plasma dry etching is performed as a combination of chemical and physical sputtering mechanisms. Coincident polymer deposition can be used to control material removal rates, etch profiles, and film selectivity. Dry etching is typically done using a gas mixture comprising NF ₃ , CHF ₃ , C ₄ F ₈ , HBr, and O ₂ at a pressure in the range of 30-100 mTorr and a plasma bias of 50-1000 Watts. The dry etch has a significant etch selectivity between cap layer 324 (TILA) and 322 (GILA) to minimize the loss of 322 (GILA) during dry etching of 324 (TILA) to form contacts for the source and drain regions of the transistor Dry etching may be performed to achieve the desired etching rate.

Referring to Figure 3E, one or more additional via openings 338 (e.g., VCG) extend from the metal (0) trench 334 to one or more gate stack structures 308A-308E to form an interlayer dielectric ILD < / RTI > For example, in Figure 3E, the via openings are formed to expose the gate stack structures 308C and 308D. Formation of the via openings 338 includes etching both portions of the interlayer dielectric (ILD) 330 and the corresponding insulating cap layer 322. In one such embodiment, a portion of the insulating cap layer 324 is exposed during patterning of the layered dielectric (ILD) 330 (e. G., A portion of the insulating cap layer 324 over the recessed trench contact 311B) Some are exposed). In that embodiment, the insulating cap layer 322 is etched to form via openings 338 selectively in the insulating cap layer 324 (i.e., without significant etching or influence).

Similar to forming the via openings 336, via openings 338 can be formed by first depositing a hard mask layer, an antireflective coating (ARC) layer and a photoresist layer. In accordance with one embodiment of the present invention, the pattern of photoresist layers (e.g., the pattern of via openings 338) is transferred to the hard mask layer by using a plasma etch process. The pattern is ultimately transferred to the interlayer dielectric (ILD) 330, for example, by different or the same dry etching process. In one embodiment, the pattern is then transferred to the insulating cap layer 322 (i.e., gate insulating cap layers) by an etching process that does not etch the insulating cap layer 324 (i.e., the trench contact insulating cap layers) do. The insulating cap layer 322 (GILA) may comprise any of a variety of metal oxides including silicon oxide, silicon nitride, silicon carbide, carbon doped silicon nitride, carbon doped silicon oxide, amorphous silicon, and zirconium oxide, hafnium oxide, lanthanum oxide, ≪ / RTI > and silicates, or combinations thereof. Layer may be deposited using any of the techniques including CVD, ALD, PECVD, PVD, HDP assisted CVD, and low temperature CVD. The insulating cap layer 322 (GILA), in one embodiment, is comprised of a different material for the cap layer 324 (TILA) to ensure a significant etch rate difference between the two capping layers. Corresponding plasma dry etching can be performed as a combination of chemical and physical sputtering mechanisms to achieve acceptable etch rate differences between GILA and TILA films. The conformal polymer deposition can be used to control the material removal rate, etch profile and film selectivity. Dry etching is typically performed using a gas mixture comprising NF ₃ , CHF ₃ , C ₄ F ₈ , HBr, and O ₂ at a pressure in the range of 30-100 mTorr and a plasma bias of 50-1000 Watts. The dry etch allows significant etch selectivity between the cap layer 322 (GILA) and 324 (TILA) layers to minimize the loss of 324 (TILA) during dry etching of 322 (GILA) to form gate contacts on the active areas of the transistor Can be performed.

3F, a metal contact structure 340 is formed in the metal trench 334 and the via openings 336 and 338 of the structure described with reference to FIG. 3E. The metal contact structure 340 may include trench contact vias (e.g., trench contact vias 341A and 341B for trench contacts 311A and 311C, respectively) and gate contact vias (e.g., (0) portion 350 with gate contact vias 342A and 342B for structures 308C and 308D.

In one embodiment, the metal contact structure is formed by metal deposition and subsequent chemical mechanical polishing operations. The metal deposition may first involve deposition of an adhesive layer followed by deposition of a fill metal layer. Accordingly, the metal structure 340 can be made of a conductive material. In one embodiment, the metal structure 340 is comprised of metal species. The metal species may be pure metals such as copper, tungsten, nickel or cobalt, or alloys such as metal-metal alloys or metal-semiconductor alloys (e.g., silicide materials).

As briefly described above in connection with FIG. 3C, ILD 330 may instead be a dual-layer structure. By way of example, FIG. 4 illustrates a cross-sectional view of another non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode, in accordance with another embodiment of the present invention. 4, a semiconductor structure or device 400, e.g., a non-planar device, is formed from a substrate 402 and includes a non-planar diffusion or active region 404 in the isolation region 406 (e.g., Structure). The gate electrode stack 408 is disposed on a portion of isolation region 406 as well as on non-planar diffusion or active region 404. As shown, the gate electrode stack 408, along with the dielectric cap layer 454, includes a gate electrode 450 and a gate dielectric layer 452. The gate electrode stack 408 is disposed in an interlayer dielectric layer 420, such as a silicon oxide layer. Gate contact vias 416 and overlying metal interconnect 460 are all disposed in interlevel dielectric (ILD) stacks or layers 470. In one embodiment, the structure 470 is a dual-layer interlevel dielectric stack, including a bottom layer 472 and an upper layer 474, as depicted in FIG.

In one embodiment, top layer 474 of ILD structure 470 is composed of a material optimized for low dielectric constant performance, e.g., to reduce capacitive coupling between metal lines formed therein. In one such embodiment, the top layer 474 of the ILD structure 470 is comprised of a material such as, but not limited to, a carbon-doped oxide (CDO) or a porous oxide film. In one embodiment, the lower layer 472 of the ILD structure 470 has compatibility with the via etch selectivity, e.g., an integrated system leveraging the etch selectivity between the trench contact cap layer and the gate cap layer. And is optimized for materials. In one such embodiment, the lower layer 472 of the ILD structure 470 is comprised of a material such as, but not limited to, silicon dioxide (SiO ₂ ) or a CDO film. In a particular embodiment, the top layer 474 of the ILD structure 470 is comprised of a CDO material and the bottom layer 472 of the ILD structure 470 is comprised of SiO ₂ .

3A-3C, the tops of the spacers 320 are exposed during formation of the via openings in the cap layers 324 and 322. If the material of the spacers 320 is different from the material of the cap layers 324 and 322, additional etch selectivity should also be considered to prevent the spacers from deteriorating undesirably during via opening formation. In another embodiment, the spacers may be recessed to be essentially flat with the gate structures. In one such embodiment, the gate cap layer may be formed to cover the spacers while preventing exposure of the spacers during via opening formation. By way of example, Figures 5A and 5B illustrate cross-sectional views illustrating various operations in a method for fabricating another semiconductor structure having a gate contact structure disposed over an active portion of a gate, according to another embodiment of the present invention.

Referring to FIG. 5A, there is provided a semiconductor structure 500 after forming a trench contact (TCN). It will be appreciated that the particular configuration of structure 500 is used for illustrative purposes only and that various layouts possible from the embodiments of the present invention described in this application may be advantageous. Semiconductor structure 500 includes one or more gate stack structures, such as gate stack structures 308A-308E, The gate stack structures may include a gate dielectric layer and a gate electrode, as described above in connection with FIG. Contacts for the diffusion regions of the substrate 302, such as trench contacts, e.g., trench contacts 310A-310C, are also included in the structure 500 and are electrically connected to the gate stack structure 520 by dielectric spacers 520. [ 308A-308E. ≪ / RTI > The insulating cap layer 522 is disposed on the gate stack structures 308A-308E (e.g., GILA), as also depicted in FIG. 5A. However, in contrast to the structure 300 described with respect to FIG. 3A, the spacers 520 have been recessed to approximately the same height as the gate stack structures 308A-308E. Thereby, corresponding insulating cap layers 522 cover the gate stack as well as the spacers 520 associated with each gate stack.

Referring to FIG. 5B, a metal contact structure 540 is formed in the metal trenches and via openings formed in the dielectric layer 330. Metal contact structure 540 includes a metal (0) portion 550 with trench contact vias (e.g., trench contact vias 341A and 341B for trench contacts 311A and 311C, respectively) . Metal contact structure 540 also includes gate contact vias (e.g., gate contact vias 542A and 542B for gate stack structures 308C and 308D, respectively). As compared to the structure described with respect to FIG. 3F, the spacers 522 are not exposed during etching formation of the via openings resulting in gate contact vias 542A and 542B and the coating of insulating cap layers 522 is extended The resulting structure of Figure 5b is slightly different.

Referring again to FIG. 5B, in one embodiment, trench contacts (including trench contacts labeled 311A and 311C in FIG. 5B) are connected to gate stack structures (including gate stack structures designated 308C and 308D in FIG. 5) Which is lower than the rest. In one such embodiment, for example, when the trench contacts are coplanar with the gate stack structures, the gate contact vias 542A and 542B and the trench contacts 311A and 311C, respectively, The trench contacts are recessed lower than the gate stack structures in order to prevent the possibility of a short circuit between the gate contact vias 542A and 542B and the trench contacts 311A and 311C, respectively.

Also, in other embodiments (not shown), the spacers are recessed to about the same height as the trench contacts. Corresponding trench isolation cap layers (TILA) cover the trench contacts as well as the spacers associated with each trench contact. In such an embodiment, the gate stack structures are recessed lower than the trench contacts to prevent the possibility of shorting between the trench contact vias and adjacent or near gate stack structures.

The approaches and structures described in the present invention may enable the formation of other structures or devices that are either impossible to manufacture or difficult to manufacture using conventional methodologies. In a first example, Figure 6 illustrates a top view of another semiconductor device having a gate contact via disposed over an active portion of a gate, according to another embodiment of the present invention. 6, a semiconductor structure or device 600 includes a plurality of interdigitated gate structures 608A-608C with a plurality of trench contacts 610A and 610B, (Not shown). A gate contact via 680 is formed on the active portion of the gate structure 608B. Gate contact vias 680 are additionally disposed on the active portion of gate structure 608C while coupling gate structures 608B and 608C. It will be appreciated that intervening trench contact 610B may be detached from contact 680 using a trench contact isolation cap layer (e.g., TILA). The contact configuration of Figure 6 strapping adjacent gate lines in the layout without the need to route straps through the top layers of the metallization to achieve a smaller cell area and / Lt; RTI ID = 0.0 > and / or < / RTI >

In a second example, Figure 7 illustrates a top view of another semiconductor device having trench contact vias coupling a pair of trench contacts, in accordance with another embodiment of the present invention. 7, a semiconductor structure or device 700 includes a plurality of gate structures 708A-708C engaged with a plurality of trench contacts 710A and 710B, the features being disposed over the active area of the substrate, Not shown). A trench contact via 790 is formed on the trench contact 710A. Trench contact vias 790 are additionally disposed on trench contact 710B while coupling trench contacts 710A and 710B. It will be appreciated that intervening gate structure 708B may be separated from trench contact via 790 (e.g., by a GILA process) by using a gate separation cap layer. The contact configuration of Figure 7 can be achieved by strapping adjacent trench contacts in a layout without the need to route the strap through the top layers of the metal cargo to provide an easier approach to enable smaller cell area and / .

It will be appreciated that not all aspects of the above-described processes need be implemented to fall within the spirit and scope of embodiments of the present invention. For example, in one embodiment, the dummy gates need not always be formed prior to making the gate contacts over the active portions of the gate stacks. The above-described gate stacks may actually be permanent gate stacks as initially formed. In addition, the processes described in the present invention can be used to fabricate one or more semiconductor devices. Semiconductor devices may be transistors or similar devices. For example, in one embodiment, the semiconductor devices are metal-oxide semiconductor (MOS) transistors or bipolar transistors for logic or memory. Further, in one embodiment, the semiconductor devices have a three-dimensional architecture such as a tri-gate device, an independently accessed dual gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at a technology node of 10 nm or less.

In general, one or more embodiments of the present invention (e. G., Additionally) prior to forming the gate contact structure (e. G., Via) in the active portion of the gate and in the same layer as the trench contact via Gate aligned trench contact process. Such a process can be implemented to form a trench contact structure for semiconductor structure fabrication, e.g., for integrated circuit fabrication. In one embodiment, the trench contact pattern is formed in alignment with an existing gate pattern. In contrast, conventional approaches typically involve additional lithography processes with strict registration of lithography contact patterns for existing gate patterns in combination with selective contact etches. For example, a conventional process may include patterning a poly (gate) grid while separately patterning the contact features.

FIG. 8 illustrates a computing device 800 in accordance with an implementation of the present invention. The computing device 800 accepts the board 802. The board 802 may include a number of components including, but not limited to, a processor 804 and at least one communication chip 806. The processor 804 is physically and electrically coupled to the board 802. In some implementations, the at least one communications chip 806 is also physically and electrically coupled to the board 802. In further implementations, the communications chip 806 is part of the processor 804.

Depending on the application, the computing device 800 may include other components that may or may not be physically and electrically coupled to the board 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, , A touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a GPS device, a compass, an accelerometer, a gyroscope, a speaker, a camera and a mass storage device (for example, a hard disk drive, ), A digital versatile disk (DVD), etc.).

The communication chip 806 enables wireless communication to and from the computing device 800 to transmit data. The terms "wireless" and its derivatives are intended to encompass all types of communication, such as circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data by using modulated electromagnetic radiation through a non- Can be used to illustrate. Although not in some embodiments, the term does not suggest that the associated devices do not contain any wires. The communication chip 806 may be any of a variety of communication technologies including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA + , Any of a number of wireless standards or protocols including GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives as well as any other wireless protocols designated 3G, 4G, 5G and above. The computing device 800 may include a plurality of communication chips 806. For example, the first communication chip 806 may be dedicated for short-range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip 806 may be dedicated to GPS, EDGE, GPRS, CDMA, WiMAX, LTE, And others. ≪ / RTI >

The processor 804 of the computing device 800 includes an integrated circuit die packaged within the processor 804. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors, constructed in accordance with implementations of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory and transforms the electronic data into other electronic data that may be stored in registers and / or memory.

The communication chip 806 also includes an integrated circuit die packaged within the communication chip 806. In accordance with another embodiment of the present invention, an integrated circuit die of a communications chip includes one or more devices, such as MOS-FET transistors, constructed in accordance with an implementation of the present invention.

In further implementations, other components contained within computing device 800 may include integrated circuit dies including one or more devices, such as MOS-FET transistors, constructed in accordance with implementations of the present invention.

In various implementations, the computing device 800 may be a computing device such as a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a PDA, an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, , A digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 800 may be any other electronic device that processes data.

Accordingly, embodiments of the present invention include gate contact structures disposed over active portions of gates and methods of forming such gate contact structures.

In one embodiment, the semiconductor structure includes a substrate having an active region and an isolation region. The gate structure has a portion disposed over the active region of the substrate and a portion disposed over the isolation region. The source and drain regions are disposed in the active region of the substrate and are disposed on either side of the gate structure portion disposed over the active region. The gate contact structure is disposed on a portion of the gate structure disposed over the active region of the substrate.

In one embodiment, the gate contact structure is a self-aligning via.

In one embodiment, the active region of the substrate is a three-dimensional semiconductor body.

In one embodiment, the substrate is a bulk silicon substrate.

In one embodiment, the semiconductor structure includes a substrate having an active region and an isolation region. A plurality of gate structures each having a portion disposed over the active region of the substrate and a portion disposed over the isolation region. A plurality of source or drain regions are disposed in the active portion of the substrate between portions of the gate structures disposed over the active region. And a plurality of trench contacts disposed on each of the source or drain regions. The gate contact vias are disposed on one of the gate structures on a portion of the gate structure disposed over the active region of the substrate. The trench contact vias are disposed on one of the trench contacts.

In one embodiment, the gate contact vias and trench contact vias are essentially co-planar with the same inter-level dielectric layer disposed over the substrate.

In one embodiment, the interlayer dielectric layer is a double-layer structure comprising an upper low dielectric constant dielectric layer and a bottom etch select layer.

In one embodiment, the gate contact vias and the trench contact vias are substantially coplanar with each other.

In one embodiment, each of the gate structures further comprises a pair of sidewall spacers, and the trench contacts are disposed immediately adjacent to the sidewall spacers of the corresponding gate structure.

In one embodiment, the top surface of the plurality of gate structures is substantially coplanar with the top surface of the plurality of trench contacts.

In one embodiment, the top surface of the plurality of gate structures and the top surface of the plurality of trench contacts are below the top surface of each of the pair of sidewall spacers.

In one embodiment, the plurality of gate structures each comprise a gate cap dielectric layer, or the remainder thereof, that is substantially coplanar with the pair of corresponding sidewall spacers on the top surface of the gate structure.

In one embodiment, the plurality of trench contacts each comprise, on the upper surface of the trench contact, a trench cap dielectric layer or a remainder thereof that is substantially coplanar with the pair of corresponding sidewall spacers.

In one embodiment, the gate cap dielectric layer and the trench cap dielectric layer have different etch selectivities with respect to each other.

In one embodiment, the top surface of the plurality of gate structures is approximately flush with the top surface of each of the pair of sidewall spacers.

In one embodiment, the gate contact vias are additionally disposed on a second of the gate structures disposed over the active area of the substrate, on a portion of the second gate structure. The gate contact vias couple one gate structure and the second gate structure.

In one embodiment, the trench contact vias are further disposed on the second of the trench contacts and couple one trench contact to the second trench contact.

In one embodiment, the gate contact via is a self-aligning via and the trench contact via is a self-aligning via.

In one embodiment, the active region of the substrate is a three-dimensional semiconductor body.

In one embodiment, the substrate is a bulk silicon substrate.

In one embodiment, the gate structure comprises a high-k gate dielectric layer and a metal gate electrode.

In one embodiment, a method of fabricating a semiconductor structure includes forming a plurality of gate structures over an active region of a substrate. The method also includes forming a plurality of source or drain regions in the active region of the substrate between the gate structures. The method also includes forming a plurality of trench contacts formed on each of the source or drain regions. The method also includes forming a gate cap dielectric layer over each of the gate structures. The method also includes forming a trench cap dielectric layer over each of the trench contacts. The method also includes forming gate contact vias on one of the gate structures, wherein the forming comprises selectively etching the corresponding gate cap dielectric layer with respect to the trench cap dielectric layer. The method also includes forming trench contact vias on one of the trench contacts, and the forming includes etching the trench trench dielectric layer selectively corresponding to the gate cap dielectric layer.

In one embodiment, forming the gate contact vias and the trench contact vias includes forming a conductive material for both with the same process operation.

In one embodiment, forming the plurality of gate structures includes replacing the dummy gate structures with the permanent gate structures.

In one embodiment, the step of forming a plurality of trench contacts includes replacing dummy gate trench contact structures with permanent trench contact structures.

In one embodiment, the method further comprises forming a three-dimensional body from active areas of the substrate prior to forming the plurality of gate structures.

In one embodiment, forming the three-dimensional body includes etching the fins in the bulk semiconductor substrate.

Claims (20)

1. A semiconductor structure comprising:
A gate electrode over the substrate, said gate electrode having a first portion over the monocrystalline region of the substrate and a second portion over the trench isolation layer of the substrate;
A source / drain region in the single crystal region of the substrate at a side of the gate electrode;
A first dielectric sidewall spacer laterally adjacent the side of the gate electrode;
A second dielectric sidewall spacer laterally adjacent a second side of the gate electrode, opposite the side of the gate electrode;
An insulating cap layer over the gate electrode;
A trench contact structure on said source / drain region transversely adjacent said first dielectric sidewall spacers; And
A conductive via structure over the trench contact structure and in contact with the trench contact structure, the conductive via structure overlying the first dielectric sidewall spacers, the conductive via structure overlying the gate electrode and in contact with the gate electrode, Wherein the opening exposes a portion of the gate electrode that is not all of the gate electrode and the conductive via structure has a non-planar bottom surface,
≪ / RTI > The semiconductor structure of claim 1, wherein the trench contact structure comprises tungsten. The semiconductor structure according to claim 2, wherein the conductive via structure comprises tungsten. The semiconductor structure according to claim 1, wherein the conductive via structure includes an adhesive layer and a filled metal layer. 2. The semiconductor structure of claim 1, wherein the insulating cap layer is over the second dielectric sidewall spacers. 2. The semiconductor structure of claim 1, wherein the first dielectric sidewall spacers and the second dielectric sidewall spacers comprise silicon nitride. The semiconductor structure of claim 1, wherein the insulating cap layer comprises silicon nitride. The semiconductor structure according to claim 1, wherein the single crystal region of the substrate is a silicon fin. The method according to claim 1,
Further comprising a trench cap dielectric layer on the top surface of the trench contact structure, wherein the trench cap dielectric layer comprises a material different from the material of the insulating cap layer. The method according to claim 1,
And a high-k dielectric layer between the gate electrode and the monocrystalline region of the substrate. A method of fabricating a semiconductor structure,
Forming a sacrificial gate electrode on the substrate, the sacrificial gate electrode having a first portion over the monocrystalline region of the substrate and a second portion over the trench isolation layer of the substrate;
Forming a dielectric sidewall spacer laterally adjacent the side of the sacrificial gate electrode;
Forming a source / drain region in the single crystal region of the substrate on the side of the sacrificial gate electrode;
Removing the sacrificial gate electrode;
Forming a permanent gate electrode having a first portion over the monocrystalline region of the substrate and a second portion over the trench isolation layer of the substrate;
Forming an insulating cap layer over the permanent gate electrode;
Forming a trench contact structure on the source / drain region transversely adjacent the dielectric sidewall spacers;
Forming an opening in the insulating cap layer to expose a portion of the permanent gate electrode that is not all of the permanent gate electrode; And
A portion of the gate electrode overlying the trench contact structure and overlying the trench contact structure and overlying the dielectric sidewall spacer and overlying the portion of the permanent gate electrode exposed by the opening and exposed by the opening Forming a conductive via structure to be contacted, the conductive via structure having a non-planar bottom surface,
≪ / RTI > 12. The method of claim 11, wherein the trench contact structure comprises tungsten. 13. The method of claim 12, wherein the conductive via structure comprises tungsten. 12. The method of claim 11, wherein the conductive via structure comprises an adhesive layer and a filled metal layer. 12. The method of claim 11,
Forming a second dielectric sidewall spacer laterally adjacent a second side of the sacrificial gate electrode, opposite the side of the sacrificial gate electrode, wherein the insulating cap layer is formed over the second dielectric sidewall spacer How to. 12. The method of claim 11, wherein the dielectric sidewall spacers comprise silicon nitride. 12. The method of claim 11, wherein the insulating cap layer comprises silicon nitride. 12. The method of claim 11, wherein the monocrystalline region of the substrate is a silicon fin. 12. The method of claim 11,
Further comprising forming a trench cap dielectric layer on the top surface of the trench contact structure, wherein the trench cap dielectric layer comprises a material that is different from the material of the insulating cap layer. 12. The method of claim 11,
Further comprising forming a high-k dielectric layer over the monocrystalline region of the substrate, wherein the permanent gate electrode is formed over the high-k dielectric layer.

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