TWI766949B - Advanced lithography and self-assembled devices - Google Patents

Abstract

Advanced lithography techniques including sub-10nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Description

Advanced lithography and self-polymerization device

Embodiments of the invention are in the field of semiconductor devices and processing, and in particular, sub-10 nm pitch patterning and self-polymerizing devices.

Scaling of features in integrated circuits has been the driving force behind the growing semiconductor industry over the past few decades. Scaling to smaller and smaller features enables an increased density of functional units on a limited surface of a semiconductor wafer. For example, shrinking transistor size allows an increased number of memory or logic devices to be incorporated on a chip, resulting in the manufacture of products with increased throughput. However, the desire for more and more capacity is not without problems. The need to optimize the performance of each device is becoming more and more important.

Variability in traditional and currently known fabrication procedures may limit the possibility of extending it further into the sub-10 nm range. Therefore, the fabrication of functional components required for future technology nodes may require introducing new methodologies or integrating new technologies into or replacing current manufacturing processes.

and

Advanced pitch patterning and self-polymerizing devices are described, particularly advanced pitch patterning techniques and self-polymerizing device fabrication methods for producing sub-10 nanometer (nm) devices and structures. In the following description, numerous specific details are set forth, such as specific integrations and material states, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, have not been described in detail so as not to unnecessarily obscure embodiments of the invention. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

The following detailed description is merely illustrative in nature and is not intended to limit the claimed subject matter embodiments or the application and uses of such embodiments. As used herein, the text "example" refers to "acting as a scope, instance, or illustration." Any implementation described herein as an example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief abstract or the following detailed description.

This specification includes references to "an embodiment" or "an embodiment." The appearances of the terms "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present invention.

the term. The following paragraphs provide definitions and/or background to terms found in this specification (including the appended claims):

"Contains." This term is open ended. As used in the appended claims, this term does not exclude additional structures or steps.

"Configured." Individual units or components may be described or requested to be "configured" to perform a job or jobs. In these contexts, "configured to" is used to imply structure by indicating that its unit/component includes the structure that performs those tasks during operation. As such, the unit/component can be said to be configured to perform the job even when the specified unit/component is not currently operating (eg, not on/active). To state that its unit/circuit/component is "configured" to perform one or more jobs is to expressly not refer to 35 U.S.C. §112 (sixth paragraph) for that unit/component.

"First," "Second," and so on. As used herein, these terms are used to designate the nouns that follow them, and do not imply any type of ordering (eg, spatial, temporal, logical, etc.). For example, a reference to a "first" solar cell does not necessarily imply that this solar cell is the first solar cell in a sequence; instead, the term "first" is used to distinguish this solar cell from other solar cells such as , "second" solar cells) are different.

"Coupled" - The following description refers to elements or nodes or features that are "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element/node/feature is directly or indirectly coupled to (or communicates directly or indirectly with) another element/node/feature , and not necessarily mechanically.

In addition, certain terms may also be used in the following description for reference purposes only and are therefore not intended to be limiting. For example, terms such as "higher", "lower", "above", and "below" refer to directions in the drawing to which the reference applies. Terms such as "front," "rear," "rear," "side," "outward," and "inward" describe the orientation and/or position of portions of components within a referenced constant (but arbitrary) frame , which is made apparent by reference to the text and associated graphics describing the components in question. This term may include the words expressly mentioned above, derivatives thereof, and words of similar import.

"Prohibited" - As used herein, prohibited is used to describe a reduction or reduction effect. When a component or feature is described as prohibiting an action, action, or condition, it can completely prevent an outcome or consequence or future state. In addition, "prohibited" may also mean that a reduction or mitigation of the consequences, properties, and/or effects that may otherwise occur. Thus, when a component, element, or feature is referred to as a prohibited result or condition, it need not completely prevent or remove that effect or condition.

Embodiments described herein may be directed to front end of line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication in which individual devices (eg, transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL generally covers all steps up to, but not including, the deposition of metal interconnect layers. Following the final FEOL operation, the result is typically a wafer with isolated transistors (eg, without any wiring).

Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second part of IC fabrication where individual devices (eg, transistors, capacitors, resistors, etc.) are interconnected with wiring (eg, metallization layers or layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In BEOL at the manufacturing stage, contacts (pads), interconnect wiring, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added to the BEOL. The embodiments described below can be applied to FEOL processes and structures, BEOL processes and structures, or both FEOL and BEOL processes and structures. In particular, although the example processing scheme may be illustrated using a FEOL processing context, these approaches may also be applied to BEOL processing. Likewise, while example processing schemes can be illustrated using a BEOL processing scenario, these approaches can also be applied to FEOL processing.

The pitch segmentation process and patterning scheme may be implemented to enable or may be included as part of the embodiments described herein. Pitch division patterning generally refers to pitch halving, pitch halving, and so on. The pitch segmentation scheme can be applied to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to print unidirectional lines (eg, strictly unidirectional or predominantly unidirectional) at a predefined pitch. The pitch division process is then implemented as a technique to increase line density.

In one embodiment, the term "grating structure" for metal lines, ILD lines, or hard mask lines is used herein to refer to a tight pitch grating structure. In this embodiment, tight pitch cannot be achieved directly by conventional lithography. For example, a pattern according to conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask, as is known in the art. Even, the original pitch can be reduced by a quarter by a second round of spacer mask patterning. Thus, the grating-like patterns described herein can have metal lines, ILD lines, or hard mask lines that are separated by a substantially constant pitch and have a substantially constant width. For example, in some embodiments, the pitch may vary within ten percent and the width may vary within ten percent, and in some embodiments, the pitch may vary within five percent and the width The variation can be within 5%. Patterns can be made by pitch halving or quarter pitch (or other pitch division). In one embodiment, the grating is not necessarily a single pitch.

In a first example, pitch halving can be implemented to double the line density of the resulting grating structure. 1A illustrates a cross-sectional view of the starting structure following deposition (but before patterning) of a layer of hard mask material formed on an interlayer dielectric (ILD) layer. FIG. 1B illustrates a cross-sectional view of the structure of FIG. 1A subsequent to patterning by a pitch halved hard mask layer.

Referring to FIG. 1A , the starting structure 100 has a hard mask material layer 104 formed on an interlayer dielectric (ILD) layer 102 . The patterned mask 106 is disposed over the hard mask material layer 104 . The patterned mask 106 has spacers 108 formed along the sidewalls of its features (lines) on the layer 104 of hard mask material.

Referring to FIG. 1B , the hard mask material layer 104 is patterned in a half pitch manner. Specifically, the patterned mask 106 is removed first. The resulting pattern of spacers 108 has twice the density of the mask 106, or half the pitch or features thereof. The pattern of spacers 108 is transferred to the layer of hard mask material 104, eg, by an etch process, to form a patterned hard mask 110, as shown in Figure IB. In one such embodiment, the patterned hardmask 110 is formed to have a grating pattern of unidirectional lines. The grating pattern of the patterned hardmask 110 may be a tight pitch grating structure. For example, tight pitch may not be achieved directly by conventional lithography techniques. Even, although not shown, the original pitch can be reduced by a quarter by a second round of spacer mask patterning. Thus, the raster-like pattern of the patterned hardmask 110 of FIG. 1B may have hardmask lines separated by a constant pitch and having a constant width from each other. The resulting dimensions may be much smaller than the critical dimensions of the lithography techniques that have been utilized.

Thus, for front-end-of-line (FEOL) or back-end-of-line (BEOL) (or both) integration schemes, the cap film may use lithography and etching processes (which may involve, for example, spacer-based double patterning (SBDP) Either the pitch is halved, or the spacer-based quadruple patterning (SBQP) or the pitch is halved) are patterned. It should be understood that other pitch divisions may also be implemented.

For example, FIG. 2 illustrates a cross-sectional view in a spacer-based six-fold patterning (SBSP) processing technique involving factor-of-six pitch divisions. Referring to FIG. 2, in operation (a), the sacrificial pattern X after the lithography, thinning and etching processes is shown. In operation (b), spacers A and B are shown after deposition and etching. In operation (c), the pattern of operation (b) after the spacer A is removed is shown. In operation (d), the pattern of operation (c) after spacer C deposition is shown. In operation (e), the pattern of operation (d) after spacer C is etched is shown. In operation (f), a pitch/6 pattern is obtained after the sacrificial pattern X is removed and the spacer B is removed.

In another example, FIG. 3 illustrates a cross-sectional view in a spacer-based ninefold patterning (SBNP) processing technique involving factor-of-nine pitch divisions. Referring to FIG. 3, in operation (a), the sacrificial pattern X after the lithography, thinning and etching processes is shown. In operation (b), spacers A and B are shown after deposition and etching. In operation (c), the pattern of operation (b) after the spacer A is removed is shown. In operation (d), the pattern of operation (c) after deposition and etching of spacers C and D is shown. In operation (e), a pitch/9 pattern is obtained after spacer C is removed.

In any event, in one embodiment, the grid layout can be fabricated by conventional or state-of-the-art lithography, such as 193 nm immersion lithography (193i). Pitch division can be implemented to increase the density of lines in a grid layout by a factor of n. Grid layout formation using 193i lithography plus pitch divisions by a factor of n may be designated as 193i+P/n pitch divisions. In one such embodiment, 193 nm immersion scaling can be extended over many generations with cost-effective pitch segmentation.

In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more common as device dimensions continue to shrink. In conventional processes, tri-gate transistors are usually fabricated on bulk silicon substrates or silicon insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-volume bulk silicon substrate facilities.

However, the shrinking of multi-gate transistors is not without consequences. As the size of these basic building blocks of microelectronic circuits decreases and as the total number of basic building blocks fabricated in a given area increases, limitations on the semiconductor process used to manufacture these building blocks become problematic.

In one embodiment, Directed Self-Aggregation (DSA) is implemented for hardmask differentiation (eg, to form hardmasks with different etch properties). In some embodiments, differentiated hardmasks may also be referred to as "colored" hardmasks, where hardmasks of the same color have the same or similar etch selectivity and hardmasks of different colors therein The masks have different etch selectivities. It should be noted that in practice, the term "color" does not refer to the actual color of the hardmask material. Hardmask differentiation (or coloring) can be used to pattern or selectively remove semiconductor fins from among a plurality of gridded semiconductor fins. One or more of the embodiments described herein relate to a procedure based on (and derived from) an aligned pitch quarter (or other) patterning approach (corrected for edge layout error (EPE)) and structure. One or more embodiments may be described as a differentiated or "colored" alternating hardmask approach for semiconductor fin patterning. Embodiments may include one or more of DSA, semiconductor material patterning, pitch division (such as pitch reduction by quarter), differentiated hardmask selectivity, self-alignment for fin patterning By. One or more embodiments are particularly suitable for non-planar semiconductor device fabrication.

In accordance with embodiments of the present invention, a doubling of edge layout errors that can be tolerated and a doubling of dicing size for dicing small features on tight pitches are implemented in very fine fin patterning. In one embodiment, all features (eg, fin lines) are transferred into the semiconductor substrate, with a single population of critical dimension (CD) variation. This approach is in contrast to current state-of-the-art approaches, which rely on spacer-based pitch reductions that typically have three discrete groups of line widths (eg, backbone or mandrel, complementary, and spacer dimensions) .

To provide context, it may be desirable to use bulk silicon on fin or tri-gate based semiconductor devices. In one embodiment, Directed Self-Aggregation (DSA) is implemented to complete every other feature's pitch segmentation and "paint" to the desired pattern. In one such embodiment, the patterning approach is particularly applicable to patterning silicon fins in a three-gate transition patterning process. In one example, advantages of the implementations described herein may include one or more of: (1) enabling a single population of feature widths, (2) doubling edge placement error requirements for feature cuts, (3) ) double the size of the hole or opening it needs to cut a single feature (eg, relax restrictions on the size of the opening), or (4) reduce the cost of the patterning process. Structural artifacts from the process include (in one embodiment) a single population of critical dimensions and are around the wafer as transitions from pitch to pitch and/or from grid to grid on the protective ring of the grain. Embodiments may enable cutting of tight pitch lines without scaling edge layout error requirements.

In an exemplary processing scheme, FIGS. 4A-4N illustrate cross-sectional views of various operations in a method of fabricating a non-planar semiconductor device, in accordance with an embodiment of the present invention.

FIG. 4A illustrates a bulk semiconductor substrate 402 with a first patterned hard mask 404 formed thereon. In one embodiment, the bulk semiconductor substrate 402 is a bulk monocrystalline silicon substrate having fins 402 etched therein. In one embodiment, the bulk semiconductor substrate 402 is undoped or lightly doped at this stage. For example, in certain embodiments, the bulk semiconductor substrate 402 has a concentration of boron dopant impurity atoms of less than about 1E17 atoms/cm ³ .

In one embodiment, the first patterned hardmask 404 includes features having a pitch 406 . In one such embodiment, the first patterned hard mask 404 represents one-half of the possible number of fins ultimately formed in the substrate 402 . That is, the pitch 406 is effectively relaxed to double the pitch of the final pattern of fins formed. In one embodiment, the first hard mask 404 is directly patterned using a lithography process. However, in other embodiments, pitch division is applied (eg, pitch halving) and is used to provide patterned hardmask 404 with pitch 406 . It should be understood that, in one embodiment, the first guide pattern may be formed using conventional patterning (lithography/etching), lithography only, spacer-based double patterning, or other pitch division methods. In one embodiment, the pilot pattern is separated from the DSA pattern through the use of two or more hard masks so that its CD is formed from a single population (eg, an etch).

FIG. 4B illustrates the structure of FIG. 4A following the formation of the second hard mask layer 408 between the first patterned hard masks 404 . In one embodiment, the second hard mask layer 408 is formed by forming an overlying hard mask layer over the substrate 402 and the first patterned hard mask 404 and then forming the overlying hard mask layer It is planarized to form the second hard mask layer 408, eg, by chemical mechanical planarization (CMP). In another embodiment, ALD or CVD techniques will follow the contours of the surface of the wafer; and since fin dicing is used as an example, the wafer is substantially flat at this point in the process.

In one embodiment, the second hard mask layer 408 has a different etch characteristic than that of the first patterned hard mask 404 . In one embodiment, one or both of the second hard mask layer 408 and the first patterned hard mask 404 are layers of nitrides of silicon (eg, silicon nitride) or oxides of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials, such as silicon carbide. In another embodiment, the hard mask material includes metals. For example, a hardmask or other overlying material may include a layer of titanium or other metal nitrides (eg, titanium nitride). Potentially smaller amounts of other materials, such as oxygen, may be included in one or more of these layers. The hard mask layer can be formed by CVD, PVD, or by other deposition methods.

FIG. 4C illustrates the structure of FIG. 4B, following the application of a layer 410 of selective brush material. The selective brush material 410 is a selective material (in some embodiments) that can be applied by a brush. It should be noted that "brush material" is often used as a technical term in DSA processes and does not imply that the selective material 410 is used as a brush. In one embodiment, the selective brush material layer 410 is only adhered to the first patterned hard mask 404, as shown in FIG. 4C. However, in another embodiment, a selective brush material is applied to the second hard mask layer 408 instead. In yet another embodiment, the selective brush material layer 410 is only adhered to the first patterned hard mask 404 , and a second, different selective brush material is formed on the second hard mask layer 408 .

In one embodiment, the selective brush material layer 410 includes a molecular species including a molecular species having a species selected from -SH, _-PO3H2 , _-CO2H , _-NRH , -NRR', and -Si(OR) ₃ The polystyrene of the head group of the formed group. In another embodiment, the selective brush material layer 410 includes a molecular species including a molecular species selected from -SH, _-PO3H2 , _-CO2H , _-NRH , -NRR', and -Si(OR) ₃ Polymethyl methacrylate of the head group of the group formed. In one embodiment, the selective brush material layer 410 is attracted to a component of a DSA block copolymer (eg, polystyrene or polymethyl methacrylate). Selective material layer 410 may include other suitable materials in other embodiments.

Figure 4D illustrates the structure of Figure 4C, following the coating of the direct self-polymerization (DSA) block copolymers 414/416 (A/B) and the polymer polymerization procedure. In one embodiment, the DSA block copolymer is coated on the surface and annealed to separate the polymer into a first polymer block 414 and a second polymer block 416 (identified as 416A and 416A in FIG. 4D ). 416B). In one embodiment, the polymer block 416 preferentially adheres to the selective brush material layer 410 during the annealing process. The polymer block 414 is adhered to the second hard mask layer 408 . However, in certain embodiments, the pitch of the aggregates is half the pitch of the first patterned hardmask 404 . In this case, the portion 416A of the polymer block 416 is adhered to the selective brush material layer 410 on the first hard mask 404 , and the portion 416B of the polymer block 416 is formed between the polymer blocks 414 on the second hard mask layer 408.

In one embodiment, block copolymer molecules 414/416 (A/B) are polymer molecules formed from chains of covalently joined monomers. In two-block copolymers, there are two different types of monomers, and these different types of monomers are primarily included in two different blocks or adjacent sequences of monomers. The block copolymer molecules shown include blocks of polymer 414 and blocks of polymer 416 (A/B). In one embodiment, the block of polymer 414 significantly includes chains of covalently linked monomer A (eg, A-A-A-A-A...), while the block of polymer 416 (A/B) significantly includes covalent chains The chain of monomer B that is knotted (eg, B-B-B-B-B...). Monomers A and B can represent any of the different types of monomers used in block copolymers known in the art. For example, monomer A can represent the monomer used to form polystyrene, and monomer B can represent the monomer used to form polymethyl methacrylate (PMMA), or vice versa, although the present invention The scope is not so limited. In other embodiments, there may be more than two blocks. Furthermore, in other embodiments, each of the blocks may include a different type of monomer (eg, each block may itself be a copolymer). In one embodiment, blocks of polymer 414 and blocks of polymer 416 (A/B) are covalently bonded together. The blocks of polymer 414 and the blocks of polymer 416 (A/B) may be approximately the same length, or one block may be significantly longer than the other.

Typically, blocks of block copolymers (eg, blocks of polymer 414 and blocks of polymer 416 (A/B)) can each have different chemistries. For example, one of the blocks can be relatively hydrophobic (eg, water repellent) and the other can be relatively relatively hydrophilic (water absorbent). At least conceptually, one of the blocks can be relatively oil-like and the other block can be relatively water-like. Such differences in chemical properties between different block polymers (whether hydrophilic-hydrophobic differences or otherwise) may cause the block copolymer molecules to self-polymerize. For example, self-polymerization can be based on microphase separation of polymer blocks. Conceptually, this can be analogous to the phase separation of oil and water, which are generally immiscible. Similarly, differences in hydrophilicity between polymer blocks (eg, one block is relatively hydrophobic and another block is relatively hydrophilic) may result in similar microphase separation, with different polymer blocks The blocks try to "separate" from each other because they don't like each other chemically.

However, in one embodiment, because the polymer blocks are covalently bonded to each other, they cannot be completely separated on a macroscopic scale. Conversely, polymer blocks of a given type tend to separate or aggregate in extremely small (eg, nano-sized) regions or phases from polymer blocks of other molecules of the same type. The particular size and shape of the domains or microphases generally depends, at least in part, on the relative lengths of the polymer blocks. In one embodiment, for example, in a two-block copolymer, if the blocks are approximately the same length, a grid-like pattern of alternating polymer 414 lines and polymer 416 (A/B) lines results .

In one embodiment, the polymer 414/polymer 416 (A/B) grating is first applied as part of the unpolymerized block copolymer layer, including, for example, by brushing or other coating process The block copolymer material. The unpolymerized form refers to the situation in which (at the time of deposition) the block copolymer has not yet substantially phase-separated and/or self-polymerized to form nanoparticles. In this unpolymerized form, the block polymer molecules are fairly highly randomized, with distinct polymer blocks oriented and positioned fairly highly randomly. The unpolymerized block copolymer layer portion can be applied in a number of different ways. For example, the block copolymer can be dissolved in a solvent and then spin coated onto a surface. Alternatively, the unpolymerized block copolymer may be sprayed, dipped, dipped, or otherwise coated or applied to the surface. Other ways of applying the block copolymer, as well as other ways known in the art for applying similar organic coatings, can potentially be used. The unpolymerized layer can then form portions of the polymerized block copolymer layer, eg, by microphase separation and/or self-polymerization of the unpolymerized block copolymer layer portion. Microphase separation and/or self-polymerization occurs through the reconfiguration and/or repositioning of the block copolymer molecules, and in particular the reconfiguration and/or repositioning of the different polymer blocks of the block copolymer molecules.

In this embodiment, an annealing treatment can be applied to the unpolymerized block copolymer to initiate, accelerate, increase, or improve the quality of microphase separation and/or self-polymerization. In certain embodiments, the annealing treatment may include a treatment operable to increase the temperature of the block copolymer. An example of such a treatment is baking the layer, heating the layer in an oven or over a heat lamp, applying infrared radiation to the layer, or applying heat to the layer or increasing the temperature of the layer. The desired temperature increase will generally be sufficient to significantly accelerate the microphase separation and/or self-polymerization of the block polymer without damaging the block copolymer or any other important materials or structures of the integrated circuit substrate. Typically, the heating range can be from about 50°C to about 300°C, or from 75°C to about 250°C, without exceeding the thermal degradation limits of the block copolymer or integrated circuit substrate. Heating or annealing can help provide energy to the block copolymer molecules to make them more mobile/elastic to increase the rate and/or quality of microphase separation. This microphase separation or reconfiguration/repositioning of block copolymer molecules can result in self-polymerization to form extremely small (eg, nanoscale) structures. Self-polymerization can occur under the influence of surface energy, molecular affinity, and other surface-related and chemical-related forces.

In any event, in certain embodiments, self-polymerization of block copolymers (whether by virtue of hydrophobic-hydrophilic differences or not) can be used to form extremely small periodic structures (eg, precisely spaced nanoscale structures or Wire). In some embodiments, it can be used to form nanoscale wires or other nanoscale structures that can ultimately be used to form semiconductor fin wires.

Figure 4E illustrates the structure of Figure 4D, following removal of one of the blocks of the two-block copolymer. In one embodiment, polymer portion 414 is selectively removed through a wet or dry etch process to leave portion 416 (A/B). The pitch of the remaining portions 416 (A/B) is about half of the pitch of the first patterned hard mask 404 .

Figure 4F illustrates the structure of Figure 4E following the transfer of the pattern of remaining polymer portions into the underlying fully crystalline semiconductor substrate. In one embodiment, the pattern of the remaining polymer portions 416 (A/B) (ie, the pattern of the first patterned hard mask 404 when the pitch is halved) is etched into the bulk semiconductor substrate 402 . The patterning operation patterns the second hard mask layer 408 to form a second patterned hard mask layer 424 corresponding to the polymer portion 416B. The first patterned hard mask 404 corresponds to the polymer portion 416A. In one embodiment, the plurality of fins 418 are formed directly on the bulk substrate 402 (which becomes the patterned substrate 420) and (as such) are formed in connection with the bulk substrate 402/420, at approx. on a flat surface 422.

Figure 4G illustrates the structure of Figure 4F following the removal of the remaining polymer layer and any brush layer. In one embodiment, the remaining polymer layer 416 (A/B) and brush layer 410 are removed to leave a plurality of alternating fins 418 with alternating "colored" first patterned hardmask 404 and The second patterned hard mask 424 is thereon. In one embodiment, the remaining polymer layer 416 (A/B) and brush layer 410 are removed using an ashing and cleaning process. The resulting pitch 426 of the fins is half the pitch 406 of the original first patterned hardmask 404 .

FIG. 4H illustrates the structure of FIG. 4G following the formation of an interlayer dielectric (ILD) layer 428 between the plurality of fins 418 . In one embodiment, the ILD layer 428 is composed of silicon dioxide, such as is used in shallow trench isolation processes. However, other dielectrics may be used instead, such as carbides and nitrides. The ILD layer 428 may be deposited by chemical vapor deposition (CVD) or other deposition processes (eg, ALD, PECVD, PVD, HDP, assisted CVD, low temperature CVD) and may be deposited by chemical mechanical polishing (CMP) techniques planarized to reveal the uppermost surfaces of hard mask layers 404 and 428 .

4I illustrates the structure of FIG. 4H following the formation and patterning of a photoresist material used to form a patterned mask 430. FIG. In one embodiment, the patterned mask 430 has openings 432 formed therein. The opening 432 exposes the target one of the plurality of fins 418 with the first patterned hard mask 404 thereon for final fin removal. Opening 432 has cut dimension 436 . In one embodiment, the constraints on the cut size 436 are relaxed, and even portions of adjacent fins with the second patterned hardmask 424 thereon may be exposed. In one embodiment, the patterning operation uses "painting" or hardmask material differentiation to prepare for cutting away unwanted features to allow the cut size to be twice the pitch 426 of the features 418 (ie, to cause original pitch 406). In one embodiment, the hard mask material allows for differences in wet etch selectivity through plasma or between the two hard mask materials. Again, edge placement error (EPE) 434 is half pitch. In contrast, in a standard patterning process (no coloring), the dicing size is 1X pitch and the edge layout error (EPE) is 1/4 pitch. Thus, in one embodiment, the process described herein doubles the edge layout error budget and doubles the size of the hole or opening required to cut a single feature.

In one embodiment, the patterned mask 430 is composed of a photoresist layer, as is known in the art, and can be patterned by conventional lithography and development processes. In certain embodiments, the portion of the photoresist layer exposed to the light source is removed when the photoresist layer is developed. Therefore, the patterned photoresist layer is composed of positive photoresist material. In a specific embodiment, the photoresist layer is composed of positive photoresist materials such as (but not limited to) 248nm resist, 193nm resist, 157nm resist, extreme ultraviolet (EUV) resist, e Beam resist, imprint layer, or phenolic resin matrix with diazonaphthoquinone sensitizer. In another specific embodiment, the portion of the photoresist layer exposed to the light source is retained when the photoresist layer is developed. Therefore, the photoresist layer is composed of negative photoresist material. In certain embodiments, the photoresist layer is composed of a negative photoresist material such as, but not limited to, including poly-cis-isoprene or poly-vinyl-cinnamate (poly-vinyl-cinnamate). In one embodiment, the lithography operation is performed using 193 nm immersion lithography (193i), EUV and/or electron beam direct writing (EBDW) lithography, or the like. Positive or negative tone resists can be used. In one embodiment, the patterned mask 430 is a three-layered mask composed of a topographic mask, an anti-reflection coating (ARC), and a photoresist layer. In a particular such embodiment, the topographic mask is a carbon hard mask (CHM) layer and the anti-reflective coating is a silicon-containing ARC layer. In one such embodiment, a spin-on glass material with additional chromophores is used to help suppress reflectivity. Chemically it is a (siloxane) silicon-carbon polymer. When annealed, it forms a mixture of silica and carbon polymer.

FIG. 4J illustrates the structure of FIG. 4I following etching of a selected one of the plurality of fins 418 and subsequent removal of the patterned mask 430 . In one embodiment, this process is referred to as a "fin dicing", or "feature selection" operation of the process. In one embodiment, one of the plurality of fins 418 is removed at location 438 to form a patterned plurality of fins 418' having a first pattern of interruptions. In one such embodiment, the exposed first patterned hardmask 404 is first removed using an etch process that is selective to any exposed second patterned hardmask 424 and to The ILD layer 428 is selective. In another embodiment, a "fin hold" approach is used, where the features are selected using opposite shades of photoresist and protected during the etch process, while the background or unprotected fins are remove. It is the opposite polarity of the lithography process (eg, negative versus positive tone imaging). It should be understood that any process can be used for this operation. The exposed fins are then removed at locations 438 using an etch process that is selective to the exposed second patterned hard mask 424 and selective to the ILD layer 428 . In the first embodiment, the fins are removed at location 438 to level 440 , leaving a protrusion 446 above the flat surface 422 . In the second embodiment, the fins are removed at location 438 to level 442 , which is approximately coplanar with flat surface 422 . In the third embodiment, the fins are removed at location 438 to level 444 , leaving recesses 448 below flat surface 422 .

4K illustrates the structure of FIG. 4J following the formation and patterning of a photoresist material used to form a patterned mask 450. FIG. In one embodiment, the patterned mask 450 has openings 452 formed therein. The opening 452 exposes the target second of the plurality of fins 418' with the second patterned hard mask 424 thereon for final fin removal. In one embodiment, the patterning operation uses "painting" or hard mask material differentiation to prepare for cutting away unwanted features to allow the cut size to be twice the pitch 426 of the features 418'. As described in relation to Figure 4I, the process described herein doubles the edge layout error budget and doubles the size of the holes or openings required to cut a single feature. In one embodiment, the patterned mask 450 is composed of materials such as those described in connection with FIG. 4I.

Figure 4L illustrates the structure of Figure 4K following etching of a selected second of the plurality of fins 418'. In one embodiment, the second of the plurality of fins 418' is removed at location 454 to form a patterned plurality of fins 418" having a second pattern of interruptions. In one such embodiment, the exposed first The second patterned hardmask 424 is first removed using an etch process that is selective to any exposed first patterned hardmask 104 and selective to the ILD layer 428. Exposed fins The sheet is then removed at location 454 using an etch process that is selective to the exposed first patterned hardmask 404 and selective to the ILD layer 428. In the first embodiment , the fins are removed at position 454 to level 456, leaving the protrusions above flat surface 422 at a height above surface 440 of protrusions 446. In the second embodiment, the fins are Removal at location 454 to level 458 leaves protrusion 464 above flat surface 422 and at approximately the same height as surface 440 of protrusion 446. In the third embodiment, the fins are removed At location 454 to level 460, approximately coplanar with flat surface 422. In the fourth embodiment, the fin is removed at location 454 to level 462, leaving recess 466 below flat surface 422 .

4M illustrates FIG. 4L following the removal of the patterned mask 450 and the formation of an interlayer dielectric (ILD) layer 468 over the plurality of fins 418" and in the locations 438 and 454 of the removed fins In one embodiment, the ILD layer 468 is composed of silicon dioxide, such as is used in shallow trench isolation processes. However, other dielectrics may be used instead, such as nitrides and carbides. The ILD layer 468 can be deposited by chemical vapor deposition (CVD) or other deposition processes such as ALD, PECVD, PVD, HDP assisted CVD, low temperature CVD. Spin-on materials are another common option for these films. Many low-k dielectric materials can be spin-coated on wafers and cured. These are commonly used in the industry.

FIG. 4N illustrates the structure of FIG. 4M following the planarization of the ILD layer 468 and the removal of the first and second patterned hard masks 404 and 424 . In one embodiment, a chemical mechanical polishing (CMP) technique is used to remove the first patterned hard mask 404 and the second hard mask 424 to individually recess the ILD layers 428 and 468 into the resulting planarization ILD layers 428' and 468', and the surfaces used to expose the plurality of fins 418". In one embodiment, the planarized ILD layer 428' is composed of substantially the same material as the planarized ILD layer 468'. In In one embodiment, the planarized ILD layer 428' is composed of a different material than the planarized ILD layer 468'. In either case, in one embodiment, a seam is formed between the ILD layer 468' and the ILD layer 428', for example, at locations 438 or 454. It should be understood that, in one embodiment, the exposed surfaces of the plurality of fins 418" may be used to form flat semiconductor devices.

According to another embodiment, FIG. 5 illustrates the structure of FIG. 4N following exposure of the upper portion of the plurality of fins 418". Referring to FIG. 5, the ILD layer 468' and the ILD layer 428' are recessed to expose the fins 418'. Protrudes portion 472 and provides recessed ILD layer 468" and recessed ILD layer 428" to recess height 476. Recess height 476 defines the location between upper fin portion 472 and lower fin portion 474. ILD layer 468' and ILD Recessing of layer 428' may be performed by plasma, vapor, or wet etching processes. In one embodiment, a dry etching process selective to silicon fins 418" is used that is based on Plasma generated by gases such as (but not limited to) NF ₃ , CHF ₃ , C ₄ F ₈ , HBr and O ₂ , at pressures typically in the range of 30-100 mTorr and plasma bias of 50-1000 Watts .

In an example embodiment, referring again to FIGS. 4J, 4L, and 5, a semiconductor structure includes a plurality of semiconductor fins 418" that protrude from a substantially flat surface 422 of a semiconductor substrate 420. The plurality of semiconductor fins 418" have a first The grating pattern interrupted by location 438 having a first fin portion 446 having a first height. The grating pattern of the semiconductor fins is further interrupted by a second location 454 having a second fin portion 464 having a second height. In one embodiment, the second height of the second fin portion 454 is different from the first height of the first fin portion 446 . In another embodiment, the second height of the second fin portion 454 is the same as the first height of the first fin portion 446 . In one embodiment, the grating pattern has a constant pitch 126 when viewed without these interruptions.

In an example embodiment, referring again to FIGS. 4J, 4L, and 5, a semiconductor structure includes a plurality of semiconductor fins 418" that protrude from a substantially flat surface 422 of a semiconductor substrate 420. The plurality of semiconductor fins 418" have a first The grating pattern interrupted by location 438, which has a first recess. In one embodiment, the grating pattern of the semiconductor fins is further interrupted by a second location 454 having a second recess, or one of the fin portions. In one embodiment, the grating pattern has a constant pitch 426 when viewed without these interruptions. In one embodiment, trench isolation layer 468" is disposed in and over the recess.

It should be understood that the above approach can be applied to fabricate other semiconductor geometries than semiconductor fins. For example, in one embodiment, the above-described approach is implemented to fabricate semiconductor nanowires or semiconductor nanoribbons. In one embodiment, the terms "semiconductor body" or "majority semiconductor body" generally refer to geometries such as fins, nanowires, and nanoribbons.

It should be understood that the resulting structures from the example processing schemes described above (eg, from Figures 4N and 5) can be used in the same or similar forms of subsequent processing operations to complete device fabrication, such as PMOS and NMOS device fabrication. As an example of a completed device, FIGS. 6A and 6B individually illustrate a cross-sectional view and a plan view (taken along the a-a' axis of the cross-sectional view) of a non-planar semiconductor device, in accordance with implementations of the present invention example.

6A, a semiconductor structure or device 600 includes a non-planar active region (eg, a fin structure including protruding fin portion 604 and sub-fin region 605) formed from substrate 602 (and within isolation region 606). The gate line 608 is disposed over the protruding portion 604 of the non-planar active region and over a portion of the isolation region 606 . As shown, gate line 608 includes gate electrode 650 and gate dielectric layer 652 . In one embodiment, the gate line 608 may also include a dielectric capping layer 654 . Gate contact 614 , and upper gate contact via 616 are also seen from this perspective view, along with upper metal interconnect 660 , which are configured in an interlevel dielectric stack or layer 670 . Also seen from the perspective view of FIG. 6A, gate contact 614 (in one embodiment) is disposed over isolation region 606, but not over the non-planar active region.

As also shown in FIG. 6A, in one embodiment, artifacts of the fin selection recesses remain in the final structure. For example, in the embodiment shown, residual protrusions 699 remain. In other embodiments, the recesses may remain, as described above.

As also shown in FIG. 6A , in one embodiment, an interface 680 exists between the protruding fin portion 604 and the sub-fin region 605 . Interface 680 may be a transition region between doped sub-fin region 605 and lightly or undoped upper fin portion 604 . In one such embodiment, each fin is about 10 nanometers wide or less, and the sub-fin dopant is supplied from an adjacent solid-state doped layer at the sub-fin location. In certain such embodiments, each fin is less than 10 nanometers wide.

Referring to FIG. 6B , gate line 608 is shown disposed over protruding fin portion 604 . The source and drain regions 604A and 604B of the protruding fin portion 604 can be seen from this perspective view. In one embodiment, the source and drain regions 604A and 604B are doped portions of the original material of the protruding fin portion 604 . In another embodiment, the material of the protruding fin portion 604 is removed and replaced with another semiconductor material, such as by epitaxial deposition. In either case, source and drain regions 604A and 604B may extend below the height of dielectric layer 606 , ie, into sub-fin region 605 . In accordance with embodiments of the invention, the more heavily doped sub-fin region (ie, the doped portion of the fin under interface 680) prevents source-to-drain leakage through this portion of the bulk semiconductor fin.

In one embodiment, the semiconductor structure or device 600 is a non-planar device, such as, but not limited to, a fin-FET or a tri-gate device. In this embodiment, the corresponding semiconductor channel regions consist of or are formed as three-dimensional bodies. In one such embodiment, the gate electrode stack of gate line 608 surrounds at least the top surface and a pair of sidewalls of the three-dimensional body.

Substrate 602 may be composed of a semiconductor material that can withstand fabrication processes and in which charges may migrate. In one embodiment, the substrate 602 is a bulk substrate formed by a layer of crystalline silicon, silicon/germanium, or germanium doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof. composition to form the active region 604 . In one embodiment, the concentration of silicon in the bulk substrate 602 is greater than 97%. In another embodiment, the bulk substrate 602 consists of an epitaxial layer grown on top of a separate crystalline substrate, eg, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate. The bulk substrate 602 may alternatively be composed of Group III-V materials. In one embodiment, bulk substrate 602 is composed of III-V materials such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium arsenide Gallium, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, bulk substrate 602 is composed of III-V materials, and charge carrier dopant impurity atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium and so on.

Isolation region 606 may be composed of a material suitable for ultimately electrically isolating (or helping to isolate) portions of the permanent gate structure from the underlying bulk substrate or active regions formed within the underlying bulk substrate , such as isolating the fin active area. For example, in one embodiment, isolation region 606 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

Gate line 608 may be composed of a gate electrode stack including gate dielectric layer 652 and gate electrode layer 650 . In one embodiment, the gate electrodes of the gate electrode stack are composed of metal gates, and the gate dielectric layer is composed of high-K materials. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide , barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Also, a portion of the gate dielectric layer may include a layer of native oxide formed from the top layers of substrate 602 . In one embodiment, the gate dielectric layer consists of a top high-k portion and a lower portion (composed of an oxide of semiconductor material). In one embodiment, the gate dielectric layer consists of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In certain embodiments, the portion of the gate dielectric is a "U"-shaped structure comprising a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.

In one embodiment, the gate electrode is composed of a metal layer such as, but not limited to, metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, Ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a particular embodiment, the gate electrode is composed of a non-work function setting fill material formed over the metal work function setting layer. The gate electrode layer may be composed of a P-type work function metal or an N-type work function metal, depending on the transistor, it will be a PMOS or NMOS transistor. In certain embodiments, the gate electrode layer may comprise a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode having a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide , tantalum carbide, and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may include a "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may only be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In further embodiments of the present invention, the gate electrode may include a U-shaped structure and a combination of planar and non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.

The spacer associated with the gate electrode stack may be composed of a material suitable for ultimately electrically isolating (or helping to isolate) the permanent gate structure from adjacent conductive contacts, such as self-aligned contacts . For example, in one embodiment, the spacer is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

The gate contact 614 and the upper gate contact via 616 may be composed of a conductive material. In one embodiment, one or more contacts or vias are composed of metal species. The metal species may be pure metals, such as tungsten, nickel, or cobalt; or may be alloys, such as metal metal alloys or metal semiconductor alloys (eg, such as silicide materials).

In one embodiment (although not shown), providing structure 600 involves forming a contact pattern that is perfectly aligned with an existing gate pattern while avoiding the use of a lithography operation with an extremely severe registration budget. . In one such embodiment, this approach enables the use of an inherently highly selective wet etch (eg, as opposed to conventionally performed dry or plasma etch) to create contact openings. In one embodiment, the contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, this approach enables the elimination of the need for other critical lithography operations (as used in conventional approaches) to create the contact pattern. In one embodiment, the trench contact grid is not patterned separately, but is formed between poly (gate) lines. For example, in one such embodiment, the trench contact grid is formed subsequent to gate grating patterning but before gate grating dicing.

Furthermore, the gate stack structure 608 can be fabricated by a replacement gate process. In this technique, dummy gate material such as polysilicon or silicon nitride pillar material can be removed and replaced with permanent gate electrode material. In one such embodiment, the permanent gate dielectric layer is also formed in this process, rather than being completed from an earlier process. In one embodiment, the dummy gate is removed by a dry etch or wet etch process. In one embodiment, the dummy gates are composed of polysilicon or amorphous silicon and are removed with a dry etch process including the use of _SF6 . In another embodiment, the dummy gates are composed of polysilicon or amorphous silicon and are removed with a wet etch process including the use of aqueous _NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gates are composed of silicon nitride and removed by a wet etch including aqueous phosphoric acid.

In one embodiment, one or more of the approaches described herein essentially consider a dummy and replacement gate process, combined with a dummy and replacement contact process, to obtain structure 600 . In one such embodiment, the replacement contact procedure is performed after the replacement gate procedure to allow high temperature annealing of at least a portion of the permanent gate stack. For example, in certain such embodiments, annealing of at least a portion of the permanent gate structure (eg, after the gate dielectric layer is formed) is performed at a temperature greater than about 600 degrees Celsius. Annealing is performed prior to the formation of permanent contacts.

Referring again to FIG. 6A, the configuration of the semiconductor structure or device 600 places the gate contact over the isolation region. This configuration can be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of a gate electrode formed over an active region. Typically, prior to (eg, in addition to) forming gate contact structures (such as vias) over the active portion of the gate and in the same layer as trench contact vias, one of the present inventions Or more embodiments include first using a gate-aligned trench contact process. Such a process can be implemented to form trench contact structures for semiconductor structure fabrication, eg, for integrated circuit fabrication. In one embodiment, the trench contact pattern is formed to align with the existing gate pattern. In contrast, conventional approaches typically involve an additional lithography process, with a lithography contact pattern closely aligned to the existing gate pattern, combined with selective contact etching. For example, conventional processes may include the patterning of a separately patterned poly (gate) grid with contact features.

It should be understood that not all forms of the above-described processes need to be implemented to fall within the spirit and scope of the embodiments of the present invention. For example, in one embodiment, the dummy gate need not have been formed prior to fabricating the gate contact over the active portion of the gate stack. The gate stacks described above may actually be permanent gate stacks, as originally formed. Also, the procedures described herein can be used to fabricate one or more semiconductor devices. The semiconductor device may be a transistor or the like. For example, in one embodiment, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Meanwhile, in one embodiment, the semiconductor device has a three-dimensional architecture, such as a triple-gate device, a dual-gate device with independent access, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at sub-ten nanometer (10 nm) technology nodes.

It should be understood that in the above-described example FEOL embodiments, in one embodiment, sub-10 nm processing is implemented directly in the fabrication scheme and resulting structure. In other embodiments, FEOL considerations may be driven by BEOL sub-10 nm processing requirements. For example, material selectivity and layout for FEOL layers and devices may need to accommodate BEOL sub-10 nm processing. In one such embodiment, the material selectivity and gate stack architecture are chosen to accommodate high density metallization of the BEOL layer, eg, to reduce fringing capacitance in the transistor structure formed in the FEOL layer but by are coupled together by high density metallization of the BEOL layers. As such, the FEOL structure and processing may be directly affected by the sub-10 nm processing or may be indirectly affected by the sub-10 nm processing of the BEOL layer.

Integrated circuit back end of line (BEOL) layers typically include conductive microelectronic structures (known in the art as vias) for electrically connecting metal lines or other interconnects above the vias to metal below the vias line or other interconnection. Vias are usually formed by a lithography process. Typically, a photoresist layer can be spin-coated over the dielectric layer, the photoresist layer can be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer can be developed to form The opening is in the photoresist layer. Next, the openings for the vias can be etched into the dielectric layer by using the openings in the photoresist layer as an etch mask. This opening is called a via opening. Finally, the via openings may be filled with one or more metals or other conductive materials to form vias.

The size and spacing of vias has decreased significantly in the past, and it is expected that the size and spacing of vias will continue to decrease significantly in the future for at least some types of integrated circuits (eg, advanced microprocessors, chipset components, graphics wafer, etc.). When patterning very small vias with very small pitches by such lithographic procedures, there are several challenges in themselves. One of these challenges is that the overlap between vias and upper interconnects, and between vias and lower positioned interconnects, typically needs to be controlled to a high tolerance on the order of a quarter of the via pitch. As via pitch dimensions get smaller, the overlap tolerance tends to shrink at a greater rate than their lithography equipment can keep up.

Another of these challenges is that the critical dimensions of via openings generally tend to shrink faster than the resolution capabilities of lithographic scanners. There are shrink technologies to reduce the critical dimensions of via openings. However, the amount of shrinkage tends to be limited by the minimum via pitch, and by the ability of the shrinkage process to be sufficiently optically approximated-corrected (OPC) neutral and unable to significantly compromise line width roughness (LWR) and/or criticality Dimensional Uniformity (CDU). Yet another of these challenges is that the LWR and/or CDU characteristics of the photoresist typically need to be improved as the critical dimension of the via opening decreases to maintain the same overall segment of the critical dimension budget. However, the LWR and/or CDU properties of most current photoresists have not improved as rapidly as the critical dimension reduction of via openings.

A further such challenge is that very small via pitches typically tend to be lower than even the resolution capabilities of extreme ultraviolet (EUV) lithography scanners. As a result, often several different lithography masks can be used, which tends to increase cost. At some point, if the pitch continues to decrease, it may be impossible (even with multiple masks) to print these very fine pitch via openings using an EUV scanner.

The above factors are also relevant to consider the layout and scaling of non-conductive spaces or interruptions between metal lines (called "plugs", "dielectric plugs", or "metal line ends") in back-end-of-line (BEOL) between the metal lines of the metal interconnect structure. The above factors also relate to conductive sheets, which (by definition) are conductive links between two conductive metal lines, such as between two parallel conductive lines. The conductive sheets are usually located in the same layer as the metal lines. Therefore, there is a need to improve the field of metallization manufacturing techniques used to manufacture metal lines, metal vias, conductive sheets, and dielectric plugs.

In certain embodiments described below, patterning and alignment of via features (or other BEOL features) is accomplished using several reticle and critical alignment strategies. In other embodiments, in contrast, the methods described herein enable the fabrication of self-aligned plugs and/or vias. In the latter embodiment, it may be the case that only one critical overlap step (Mx+1 grating) needs to be performed.

It should be understood that the underlying layers and materials described in connection with back end of line (BEOL) structures and processing are typically formed on or over underlying semiconductor substrates or structures, such as underlying device layers of integrated circuits. In one embodiment, the underlying semiconductor substrate represents a typical workpiece object used to fabricate integrated circuits. Semiconductor substrates often include wafers or other pieces of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, monocrystalline silicon, polycrystalline silicon, and silicon-on-insulator (SOI), and similar substrates formed from other semiconductor materials (such as substrates including germanium, carbon, or III-V materials). Semiconductor substrates (depending on the stage of manufacture) often include transistors, integrated circuits, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, the depicted structures can be fabricated on lower level interconnect layers below.

While the method of fabricating a metallization layer (or portion of a metallization layer) of a BEOL metallization layer is described in detail for select operations, it should be understood that additional or intermediate operations in its fabrication may include standard microelectronics fabrication procedures, such as microelectronics. shadowing, etching, thin film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, and/or related to microelectronic device fabrication any other action. Also, it should be understood that the process operations described with respect to the following process flow may be performed in alternate orders, not every operation needs to be performed and/or additional process operations may be performed.

In some cases, the resulting structure enables fabrication of vias that are directly focused on the underlying metal lines. The vias may be wider, narrower, or the same thickness as the underlying metal lines, eg, due to a non-perfect selective etch process. However, in one embodiment, the centers of the vias are aligned (matched) with the centers of the metal lines. As such, in one embodiment, variations due to conventional lithography/damascene patterning (which would otherwise be tolerated) do not factor into the resulting structure of one or more of the following process schemes.

It should be understood that certain interconnect fabrication schemes described below can be implemented to save many alignment/exposures, can be implemented to improve electrical contact (eg by reducing via resistance), or can be implemented to reduce overall process operations and processing time, compared to what is required to pattern these features using traditional methods. It should also be understood that in subsequent or additional fabrication operations beyond those shown, in some instances, a dielectric layer may be removed from the layer of metal lines to provide air gaps between the metal lines.

According to an embodiment of the present invention, a backbone approach is described. The backbone approach can involve most stages of atomic layer deposition (ALD). In one embodiment, tight pitch formation is achieved by iterative spacer formation, eg, using ALD processing.

To provide context, lithographic patterning of features for semiconductor fabrication is limited to the resolution of imaging tools, whether optical (eg, 193 nm), electron beam, or EUV. Process methods such as multi-pass patterning, pattern reduction, and spacer-based pitch segmentation can be used to extend the resolution by a factor of 2 to 4, or even possibly a factor of 8. However, these methods may be limited in that process variations in the original lithography steps remain at similar values in the final pattern. For example, a lithography operation can have a variation of +/- 3 nm. If the split-to-pitch process method is utilized to produce a final pitch of 8 nm (4 nm feature size), the resulting final pattern changes by 4 nm +/- 3 nm.

One or more embodiments described herein relate to the use of iterative spacer or thin film deposition to define all or substantially all of the last critical small features for a layer, such as a BEOL layer. The variation of these features can be better than +/- 1 nm, which is consistent with ALD technology. Most materials can be utilized to enable "coloring" of the pattern to enable addressing of alternate features (eg, vias, cuts, plugs, etc.) that have magnification tolerance for edge layout errors.

7A and 7B illustrate cross-sectional views of a target infrastructure for enabling a very tight pitch final pattern of semiconductor layers, in accordance with an embodiment of the present invention.

Referring to FIG. 7A , a target base layer 700 includes a patterned layer 702 over a hard mask layer 704 , over a transfer layer 706 , and over a substrate 708 . Patterned layer 702 includes backbone features 710 . Backbone features 710 are relatively wide features (eg, 6-12 nm) with an intermediate group 712 of relatively smaller features (eg, 6-100s of smaller features between adjacent backbone features 710 , where Smaller features are, for example, 4-6 nm wide).

In one embodiment, each of the middle groups 712 of relatively small features includes small features 716 of a first material type, small features 714 of a second material type different from the first material type, and small features 714 of a second material type different from the first material type. Small features 718 of a material type and a third material type of the second material type. Differences in material types may provide different etch characteristics or selectivity between the material types. In one embodiment, the material of the backbone features 710 is the same material as the third material type of the small features 718, as depicted in Figure 7A. In another embodiment, the material of the backbone features 710 is a different material than the third material type of the small features 718 , but has similar etch characteristics or selectivity as the third material type of the small features 718 .

Referring to FIG. 7B , target base layer 750 includes patterned layer 752 over hard mask layer 754 , over transfer layer 756 , and over substrate 758 . Patterned layer 752 includes backbone features 760 . Backbone features 760 are relatively wide features (eg, 6-12 nm) with an intermediate group 762 of relatively smaller features (eg, 6-100s of smaller features between adjacent backbone features 760 , where Smaller features are, for example, 4-6 nm wide).

In one embodiment, each of the middle groups 762 of relatively smaller features includes small features 764 of a first material type, small features 766 of a second material type different from the first material type, and small features 766 of a second material type different from the first material type. Small features 768 of a material type and a third material type of the second material type. Differences in material types may provide different etch characteristics or selectivity between the material types. In one embodiment, the material of the backbone features 760 is the same material as the second material type of the small features 766, as depicted in Figure 7B. In another embodiment, the material of the backbone features 760 is a different material than the second material type of the small features 766 , but has similar etch characteristics or selectivity as the third material type of the small features 766 .

Referring to both Figures 7A and 7B, in one embodiment, a structure 700 or 750 includes several iterative vertical layers of alternating materials that will ultimately define a semiconductor pattern (eg, metal, transistor, etc.) The last position of the feature. Occasionally larger features appear because they represent lithographically defined structures, which (in one embodiment) are larger (wider) due to their larger size variation. In one embodiment, six to hundreds of narrow features are between the wide features.

8A-8H illustrate cross-sectional views representing various operations in a method of fabricating a target base structure for enabling a very tight pitch final pattern of semiconductor layers, in accordance with an embodiment of the present invention. Overall, in one embodiment, an iterative thin film generation operation is utilized. For example, conformal thin film deposition is performed, followed by anisotropic etching (eg, spacer formation), selective growth, or directed self-polymerization (DSA). A patterning process such as the one described below can be implemented to provide a patterning process suitable for producing very fine pitch final patterns of semiconductor layers. In one embodiment, advantages of implementing such a process flow include enhanced dimensional control of close-pitch features, utilizing a built-in method for coloring alternating features to allow for self-aligned vias, plugs, and dicing formation .

Figure 8A illustrates a process operation involving high backbone formation. Backbone features 808 are formed over hardmask layer 806 , which is formed over transfer layer 804 , which is formed over substrate 802 . In one embodiment, the formation of the plurality of backbone features 808 involves the use of standard lithography operations (eg, 193 nm or EUV), followed by etch transfer into a hard mask (eg, SiN, SiO ₂ , SiC) and then removal of any remaining The remaining resist and/or anti-reflection layer (eg, by ashing or wet cleaning).

Figure 8B illustrates a process operation involving the formation of a first spacer (Spacer 1). A first set of small features 810 of a first material are formed along the sidewalls of each of the plurality of backbone features 808 . In one embodiment, the first set of small features 810 is formed using deposition (eg, ALD) and etching. In another embodiment, the first set of small features 810 are formed using selective growth.

Figure 8C illustrates a process operation involving the formation of a second spacer (spacer 2), a third spacer (spacer 3), and a fourth spacer (spacer 4), implemented using as shown as a possible example specific layer of the example. A second set of small features 812 of a second material composition is formed along the exposed sidewalls of each of the first set of small features 810 . A third set of small features 814 composed of a third material is formed along the exposed sidewalls of each of the two sets of small features 812 . A fourth set of small features 816 of the second material composition is formed along the exposed sidewalls of each of the third set of small features 814 . In one embodiment, the second set of small features 812 are first formed using deposition (eg, ALD) and etching or selective growth. A third set of small features 814 is then formed using another deposition (eg, ALD) and etching or selective growth. A fourth set of small features 816 is then formed using another deposition (eg, ALD) and etching or selective growth.

Figure 8D illustrates a process operation involving successive layer generation. Additional spacer layers 818 are formed sequentially, using a selection order of material types. The additional spacer layer 818 can be fabricated using deposition and etching methods, selective growth methods, or a combination thereof. It should be understood that more layers than shown may be added. For example, in one embodiment, an additional 20-200 sets of spacers are formed at this stage. The deposition of the spacers can be done before the merging of adjacent sidewall growths, eg, the spacer formation is stopped when the openings 820 remain. It should be understood that although deposition and etching approaches or selective growth approaches are described as options for Figures 8A-8D, directed self-aggregation (DSA) may be used in place of or as one of the options for spacer formation described herein. In one such example, a three-block based DSA is used. An example of a three-block-based DSA is described below in connection with Figures 12A-12K.

In one embodiment, referring collectively to Figures 8A-8D, iterative generation of thin layers of alternating material on the sides of the template features defined by the original lithography is performed. One potential method to achieve such a structure is through thin film deposition followed by anisotropic etching. In one embodiment, a single process tool is used to perform both deposition and etching to significantly improve the efficiency of this approach. Other methods of producing thin layers of well-controlled thickness include selective growth or DSA.

Figure 8E illustrates a process operation involving backbone removal. Backbone feature 808 is removed to leave opening 822 . In one embodiment, opening 822 has a width that is approximately the same as the width of opening 820, as depicted in Figure 8E. In one embodiment, each of the openings 820 and 822 has a spacer 824 as the sidewall, the spacer 824 of the first material composition. As shown, some of the spacers 824 are reassigned from the previously labeled spacers 810 . In one embodiment, the backbone features 808 are removed to provide more space for further small feature generation.

Figure 8F illustrates a process operation involving successive layer generation. Openings 820 and 822 are formed using continuous spacers to be eventually completely filled. In an example embodiment, spacers 826 are formed along the exposed sidewalls of spacers 824 . In one such embodiment, the spacer 826 is composed of a second material. In one embodiment, the last wide feature 828 is finally formed on the center of each of the openings 820 and 822, at a stage when further spacer formation is not desired or achievable. In one embodiment, the formation of the last wide feature 828 involves the merging of its growth of material formed along adjacent sidewalls of the spacer 826 . In one such embodiment, the merging of material growth provides last wide features 828 each having a seam approximately centered within the last wide features 828 . In one embodiment, the last wide feature 828 is of a third material composition.

Figure 8G illustrates a process operation involving planarization of the structure of Figure 8F. In one embodiment, planarization is performed using a chemical mechanical polishing (CMP) operation. In one embodiment, the planarization process provides a flat structure prior to plug/cut and via process operations. Locations 828 centered directly under the original lithography feature (which results in opening 822) and halfway isolated therebetween (which results in opening 820) can be targeted to be larger to accommodate larger size variations associated with lithography operations, Compared to a single thin film (plus etch) operation. In one embodiment, as shown, the structure of FIG. 8G is similar or identical to that described in connection with FIG. 7A.

Figure 8H illustrates a process operation involving the selective removal of all features of the first material composition, eg, spacers 810/824 (corresponding to small features 716 of the first material type from the structure of Figure 7A, as in Figure 8G shown). In one embodiment, the small features 716 of the first material type are removed using a selective etch process that does not remove (or only slightly removes) the remaining spacer material. In the example embodiment shown in FIG. 8H, after removal of the small features 716 of the first material type, metal line patterned features 830 are formed in openings after removal of all the small features of the first material type. Generated when feature 716. Portions of metal line patterned features 830 are associated with underlying via patterned features 832 . Although not depicted, selected ones of the small features 716 of the first material type may be retained (eg, through a light lithography blocking process that blocked those selected ones of the small features 716 of the first material type removed) to form Plug patterning features. In one embodiment, metal line patterned features 830, via patterned features 832, and any plug patterned features are finally patterned into hardmask layer 806 and transfer layer 804 for final patterning of underlying layers change. In another embodiment, as shown, metal line patterned features 830 , via patterned features 832 , and any plug patterned features actually represent metal lines, vias, and plugs formed in layer 834 ,as the picture shows. Either metal line patterned features 830 or actual metal lines, each may have an overlying hard mask cap layer 836 to protect those features during subsequent processing of layer 834, as shown in Figure 8H. Referring again to FIG. 8H, in one embodiment, by shifting only one spacer type, additional tolerance is provided for process variations in plug, via, and/or dicing patterning operations.

8H' and 8H" illustrate cross-sectional views of exemplary structures following patterning of vias and plugs, in accordance with embodiments of the present invention.

Figure 8H' illustrates a process operation involving selective removal of all materials from backbone feature 710 of Figure 8H and all small features 718 of the third material type. In one embodiment, the backbone features 710 and the small features 718 of the third material type are removed using a selective etch process that does not remove (or only removes only a small amount) the remaining Spacer material or replaced spacer material. In the example embodiment shown in FIG. 8H', after removal of backbone features 710 and small features 718 of the third material type, second metal line patterned features 838 are formed in most or all of the openings is produced when the backbone feature 710 and the small features 718 of the third material type are removed. In one embodiment, any remains of the openings created when the backbone features 710 and the small features 718 of the third material type are removed are filled with plug material 850 (eg, to provide material such as SiN or SiO _{2 )} . non-conductive material such as wire termination features), or are reserved as plug areas. Portions of the second metal line patterned features 838 are associated with the underlying second via patterned features 840 . In one embodiment, the second metal line patterned features 838, the second via patterned features 840, and any plug patterned features 850 are finally patterned into the hardmask layer 806 and transfer layer 804 for Final patterning of the underlying layers. In another embodiment, as shown, the second metal line patterned features 838, the second via patterned features 840, and any plug patterned features 850 actually represent metal lines, vias, and plugs individually. plug.

Either the metal line second patterned feature 838 or the actual metal line, or either the patterned plug feature 850 or the actual plug feature 850, each may have an overlying hard mask cap layer 842 to protect those features from subsequent processing During operation, as shown in Figure 8H'. In one embodiment, the overlying hardmask cap layer 842 has a different composition than the overlying hardmask capping layer 836 . Thus, in one embodiment, alternating features have different hardmask materials. This configuration preferably facilitates subsequent connection of vias, from subsequent layers formed above, with increased edge layout tolerance to prevent vias to wrong metal features.

It should be understood that because the metal lines 830 (or patterned features) and the second metal lines 838 (or patterned features) are formed in different processing operations, the compositions of the metal lines 830 and the second metal lines 838 may be different. In an example embodiment, Figure 8H" illustrates an example in which metal line 830' has a different composition than metal line 838. Thus, alternating features may be composed of different conductive materials.

It should be understood that some older forms of spacer-based pitch segmentation techniques can be used for high volume manufacturing. The above-described embodiments around the backbone approach can be implemented with spacer-based pitch divisions extending one or two passes up to a very high number of iterative spacer forming operations. One or more embodiments provide a means for density scaling of semiconductor wafers with high manufacturing throughput. One or more embodiments provide a method for fabricating tight interconnects, or even transistors (if applied to FEOL processing), with consistently well-formed feature sizes. It should be understood that reverse engineering of products fabricated using the backbone approach can reveal significantly tight pitch features (eg, sub-10 nm pitch features) with occasional wide one-dimensional (1D) features. Cross-sectional scanning electron microscopy (XSEM) can reveal "colored" (eg, differing from each other for properties such as etch selectivity) hardmasks on alternating features.

In accordance with embodiments of the present invention, pitch division is applied to provide a way to fabricate alternating metal lines in a BEOL fabrication scheme. One or more of the embodiments described herein relate to a pitch segmentation patterning process flow that increases overlap tolerance for vias, cuts, and plugs. Embodiments may enable continuous scaling of the pitch of metal layers beyond the resolution capabilities of state-of-the-art lithography equipment. In one embodiment, the spacing between the metal lines is constant and can be controlled to Angstrom level accuracy using ALD. In one embodiment, the process flow is designed such that its "replacement ILD" flow is possible. That is, the ILD can be deposited after the patterning and metallization are completed. The patterning process typically damages the ILD through an etch/clean step; however, in this process, the ILD can be deposited last and thus avoid damage during patterning.

To provide context, edge placement errors for via, dicing, and plug patterning are problematic when feature size and pitch are scaled. State-of-the-art solutions to these problems involve trying to tighten edge layout errors by increasing scanner overlap and improving critical dimension (CD) control or trying to use super self-aligned integration approaches. In contrast, the embodiments described herein relate to the implementation of a process that can achieve similar improvements in edge layout error margins without the need for lithography tools or super self-alignment improvements.

According to embodiments of the present invention, metal lines are fabricated in two separate sequences of operations to double the amount of overlap tolerance for dicing/plugging and via patterning. In the first part of the example process flow, a pitch division method is used to pattern metal lines, plugs, and then vias into the interlayer dielectric material. In the second part of the example process flow, the trench/via openings are filled with metal (eg, dual damascene metallization) and then polished. The sacrificial hard mask layer is then removed between the metal lines. The metal lines are then coated with a sacrificial dielectric material using, for example, atomic layer deposition (ALD). In the third part of the example process flow, an isotropic spacer etch is performed to expose the bottom of the trench. Using a plug patterning process, dielectric material is added where metal line ends should occur, and via etch is done on complementary metal lines. The metal system from the first metal line acts as an etch stop to prevent etching in these locations. In the fourth part of the example process flow, the trenches are filled with metal and polished to expose the metal. After polishing, the sacrificial hard mask material is removed and, optionally, replaced with a dielectric material and then polished again to complete the metallization process. Air gaps can also be inserted through the deposition of tuning dielectric materials. Furthermore, embodiments may involve the use of sacrificial hard mask materials (instead of metals). The sacrificial hardmask can be removed and replaced with metal during a "second" metallization operation.

In an example processing scheme, FIGS. 9A-9L illustrate oblique cross-sectional views of a portion of an integrated circuit layer representing a pitch division patterning involving increased overlap tolerance for back end of line (BEOL) interconnect fabrication Each operation in the method is according to an embodiment of the present invention.

Referring to Figure 9A, a starting point structure 900 is provided as a starting point for fabricating a new metallization layer. The starting point structure 900 includes a hard mask layer 902 disposed on a sacrificial layer 904 disposed on an interlayer dielectric (ILD) layer 906 . The ILD layer may be disposed over the substrate and (in one embodiment) over the underlying metallization layer. In one embodiment, the hard mask layer 902 is a silicon nitride (SiN) or titanium nitride hard mask layer. In one embodiment, the sacrificial layer is a silicon layer, such as a polysilicon layer or an amorphous silicon layer.

Referring to FIG. 9B, the hard mask layer 902 and the sacrificial layer 904 of the structure of FIG. 9B are patterned. Hard mask layer 902 and sacrificial layer 904 are patterned to form patterned hard mask layer 908 and patterned sacrificial layer 910, respectively. The patterned hard mask layer 908 and the patterned sacrificial layer 910 include a pattern of first line openings 912 and line end regions 914 . In one embodiment, the sacrificial silicon layer is suitable for patterning into fine features using an anisotropic plasma etch process. In one embodiment, a lithographic resist mask exposure and etch process is used to form patterned hard mask layer 908 and patterned sacrificial layer 910, with subsequent removal of the resist layer or stack. In one embodiment, the first line openings 912 have a grating type pattern, as depicted in Figure 9B. In one embodiment, a pitch division patterning scheme is used to form the pattern of the first line openings 912 . Examples of suitable pitch partitioning schemes are described in more detail below. Subsequent line "dicing" or plug-preserving lithography processes may then be used to define line termination regions 914 .

Figure 9C illustrates the structure of Figure 9B following patterning of the underlying via locations. Via openings 916 may be formed in selected locations of the ILD layer 906 to form a patterned ILD layer 918 . In one embodiment, the vias are patterned using a self-aligned via process. Selected locations are formed in regions of the ILD layer 906 exposed by the first line openings 912 . In one embodiment, separate lithography and etching processes are used to form via openings 916 after the lithography patterning process used to form first line openings 912 .

Figure 9D illustrates the structure of Figure 9C following the first metallization process. In one embodiment, a dual damascene metallization process is used in which vias and metal lines are filled simultaneously. Interconnect lines 920 and conductive vias 920 are formed in the first line openings and via openings 916 . In one embodiment, a metal fill process is performed to provide interconnect lines 920 and conductive vias 920 . In one embodiment, the metal filling process is performed using metal deposition and subsequent planarization processing schemes, such as a chemical mechanical planarization (CMP) process. In the case where the patterned sacrificial hardmask layer 910 consists essentially of silicon, a liner material can be deposited prior to forming the conductive fill layer to prevent silicidation of the patterned sacrificial hardmask layer 910 .

FIG. 9E illustrates the structure of FIG. 9D following the exposure of interconnect 920. FIG. Patterned hard mask layer 908 and patterned sacrificial layer 910 are removed to leave interconnect lines 920 exposed, with underlying conductive vias in patterned ILD layer 918 . Wire end openings 924 are exposed. Line end openings 924 provide breaks in the grating pattern of interconnect lines 920 . In one embodiment, the patterned hard mask layer 908 and the patterned sacrificial layer 910 are removed using a selective wet etch process.

Figure 9F illustrates the structure of Figure 9E following the formation of a conformally patterned layer. A layer of spacer material 926 is formed over and conformal to the grating pattern of interconnect lines 920 . In one embodiment, Atomic Layer Deposition (ALD) is used due to the fact that it is highly conformal and extremely accurate (eg, controlling the da Angstrom level). It should be understood that the line end openings 924 are (in one embodiment) too short to effectively disrupt the general grating pattern of the interconnect lines 920 for the formation of the layer 926 of conformal spacer material. In one such embodiment, the line end openings 924 are filled with a layer of spacer material 926 without disrupting the general grating pattern of the interconnect lines 920 . In one embodiment, the spacer material layer 926 is deposited using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. In one embodiment, the spacer material layer 926 is a silicon layer, such as a polysilicon layer or an amorphous silicon layer. In certain such embodiments, a liner material is deposited on the interconnect lines 920 prior to forming the silicon spacer material layer to prevent silicidation of the spacer material layer 926. In one embodiment, the wire end cut (plug) is less than or equal to 2 times the spacer thickness so that it is completely filled with the conformal dielectric material. If it is greater than 2 times the thickness, seams may form and the metal may short the wires together during subsequent processing.

9G illustrates the structure of FIG. 9F following the formation of spacer lines from the layer of spacer material. In one embodiment, the spacers 928 are formed along the sidewalls of the interconnect lines 920 using an anisotropic plasma etching process. In one embodiment, the layer of spacer material 926 remains in the line end openings 924 to form line end placeholders 930 for interconnect lines 920 .

Figure 9H illustrates the structure of Figure 9G following the formation of a plug placeholder layer. Plug placeholder layers 932 are formed between spacers 928 of adjacent interconnect lines 920 . The plug placeholder layer 932 is initially formed in the locations where the second set of interconnect lines will be finally formed. In one embodiment, plug placeholder layer 932 is formed using a deposition and planarization process that confines plug placeholder layer 932 between spacers 928 .

Figure 9I illustrates the structure of Figure 9H following patterning of the plug placeholder layer. The plug placeholder layer 932 is patterned to retain the plug placeholders 934 in selected locations where the wire ends are finally formed. In one embodiment, a lithographic resist mask exposure and etch process is used to form plug placeholders 934, with subsequent removal of the resist layer or stack.

Figure 9J illustrates the structure of Figure 9I following a second metallization process. Interconnect lines 936 are formed in openings (second line openings) formed during the patterning of the plug placeholder layer 932 used to form the plug placeholders 934 . Furthermore, although the patterning omits separate processing operations, via openings (and ultimately conductive vias 938 ) may be formed in selected locations under conductive lines 936 . This process results in double patterning (two different via patterning operations) of the ILD layer 940, as depicted in Figure 9J.

In one embodiment, a metal fill process is performed to provide interconnect lines 936 and conductive vias 938 . In one embodiment, the metal filling process is performed using metal deposition and subsequent planarization processing schemes, such as a chemical mechanical planarization (CMP) process. In the case where the spacers 928 consist essentially of silicon, a liner material may be deposited prior to forming the conductive fill layer to prevent silicidation of the spacers 928.

It should be understood that in one embodiment, because interconnect 936 (and corresponding conductive via 938 ) is formed in a later process than the process used to fabricate interconnect 920 (and corresponding conductive via 922 ) , so the interconnect 936 may be fabricated using a different material than that used to fabricate the conductive lines 920 . In one such embodiment, the metallization layer ultimately includes alternating conductive interconnects of different first and second compositions.

FIG. 9K illustrates the structure of FIG. 9J following the exposure of the two sets of interconnect lines 920 and 936 . Spacers 928 , line end placeholders 930 , and plug placeholders 934 are removed to leave exposed interconnect lines 920 and 936 , respectively, with underlying conductive vias 922 and 938 in patterned ILD layer 940 . Wire end openings 942 are exposed. Line end openings 942 provide breaks in the grating pattern of interconnect lines 920 and in the grating pattern of interconnect lines 936 . In one embodiment, the spacers 928, the line end placeholders 930, and the plug placeholders 934 are removed using a selective wet etch process.

In one embodiment, the structure of FIG. 9K represents the final metallization structure with an air gap structure. That is, the air gap structure is enabled because interconnect lines 920 and 936 are ultimately exposed to the processes described herein. In another embodiment, because the interconnects 920 and 936 are exposed at this stage in the process, there is an opportunity to remove the sidewall portions of the diffusion barrier layers of the interconnects. For example, in one embodiment, removal of such a diffusion barrier layer physically thins the conductive features of interconnect lines 920 and 936 . In another embodiment, the resistance values of interconnect lines 920 and 936 are reduced upon removal of the sidewall portion of this diffusion barrier layer. As indicated in Figure 9K, feature sidewall portions 960 of interconnect lines 920 and 936 are exposed, while portions 962 below the lines are not. As such, in one embodiment, the diffusion barrier layers of interconnects 920 and 936 are removed from sidewalls 960 of interconnects 920 and 936 but not from region 962 of interconnects 920 and 936 . In certain embodiments, the removal of the sidewall portion of such a diffusion barrier layer involves removal of Ta and/or TaN layers.

Thus, with reference to operations 9A-9K, in one embodiment, a method of fabricating a back end of line (BEOL) metallization layer includes forming a plurality of conductive lines 920/936 in a sacrificial material 928 formed over a substrate. Each of the plurality of conductive lines 920/936 includes a barrier layer formed along the bottom and sidewalls of the conductive fill layer. The sacrificial material 928 is then removed. The barrier layer is removed from the sidewall of the conductive fill layer (eg, at location 960). In one embodiment, removing the barrier layer from the sidewalls of the conductive fill layer includes removing the barrier layer from a material selected from the group consisting of Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au The tantalum nitride or tantalum layer is removed from the sidewall of the conductive fill layer of the group of materials consisting of its alloys.

Figure 9L illustrates the structure of Figure 9K following the formation of the permanent ILD layer. Interlayer dielectric (ILD) layers 946 / 948 are formed between interconnect lines 920 and 936 . ILD layers 946/948 include portion 946 between interconnect lines 920 and 936. The ILD layers 946/948 also include a wire end (or dielectric plug) portion 948 between the locations where the wires of the interconnect wires 920 and 936 break.

Referring again to FIG. 9L, in one embodiment, semiconductor structure 999 includes a substrate (under which ILD layer 940 is shown). A plurality of alternating first 920 and second 936 conductive line types are arranged along the same direction of their back end of line (BEOL) metallization layers arranged over the substrate. In one embodiment, the overall composition of the first conductive line type 920 is different from the overall composition of the second conductive line type 936, as described in connection with FIG. 9K. In certain such embodiments, the overall composition of the first conductive line type 920 is substantially composed of copper, and the overall composition of the second conductive line type 936 is substantially composed of a group consisting of Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au and alloys of the group of materials, and vice versa. However, in another embodiment, the overall composition of the first conductive line type 920 is the same as the overall composition of the second conductive line type 936 .

In one embodiment, the lines of the first conductive line type 920 are separated by a pitch, and the lines of the second conductive line type 936 are separated by the same pitch. In one embodiment, a plurality of alternating first and second conductive line types are configured in interlayer dielectric (ILD) layers 946/948. However, in another embodiment, the lines of the plurality of alternating first and second conductive line types 920/936 are separated by an air gap, as described in connection with FIG. 9K.

In one embodiment, the plurality of alternating lines of first and second conductive line types 920/936 each include a barrier layer disposed along the bottom and sidewalls of the line. However, in another embodiment, the lines of the plurality of alternating first and second conductive line types 920/936 each include a barrier layer disposed along the bottom 962 of the line and not along the sidewalls 960 of the line, As described in the embodiment of Figure 9K. In one embodiment, one or more of the plurality of alternating lines of the first and second conductive line types 920/936 are connected to underlying vias 922/938, which are connected to the underlying metallization layer of the semiconductor structure. In one embodiment, one or more of the lines of the plurality of alternating first and second conductive line types 920 / 936 are interrupted by dielectric plugs 948 .

The resulting structure 999 such as described in connection with Figure 9L (or the air gap structure of Figure 9K) can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure 999 of FIG. 9L (or the structure of FIG. 9K ) may represent the last metal interconnect layer in the integrated circuit. It should be understood that the above-described process operations may be performed in alternate orders, not every operation needs to be performed and/or additional process operations may be performed. It should also be understood that the above examples have focused on metal wire and plug or wire end formation. However, in other embodiments, a similar approach may be used to form via openings in the ILD layer.

In accordance with one or more embodiments of the present invention, the self-aligned DSA double block or selective growth is described in a bottom-up manner. One or more embodiments described herein relate to self-aligned via and plug patterning. The self-aligned aspect of the procedures described herein may be based on a directed self-aggregation (DSA) mechanism, as described in more detail below. However, it should be understood that its selective growth mechanism can be exploited in a DSA-based manner. In one embodiment, the procedures described herein enable the realization of self-aligned metallization for back-end-of-process feature fabrication. More specifically, one or more embodiments relate to an approach that utilizes the underlying metal as a template to create conductive vias and non-conductive spaces or interruptions (referred to as "plugs") between the metals.

10A-10M illustrate portions of integrated circuit layers that represent various operations in a method of self-aligned vias and metal patterning, in accordance with embodiments of the present invention. In each illustration of the described operations, the plan view is shown on the left hand side and the corresponding cross-sectional view is shown on the right hand side. These views will be referred to herein as the corresponding cross-sectional and plan views.

10A illustrates a plan view and corresponding cross-sectional view for a selection of front-level metallization structures, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view option (a), the starting structure 1000 includes a pattern of metal lines 1002 and interlayer dielectric lines (ILD) 1004 . The starting structure 1000 can be patterned as a grating-like pattern with metal lines spaced at a constant pitch and of constant width (eg, for DSA embodiments, but not necessarily required for directional selective growth embodiments), as in Figure 10A depicted. Patterns, for example, can be fabricated by halving the pitch or reducing the pitch by a quarter. Certain lines may be associated with underlying vias, such as line 1002' shown in one example of the cross-sectional view.

Referring again to FIG. 10A, alternative options (b)-(f) are discussed in which an additional film (eg, deposited, grown, or leaving artifacts as left over from the previous patterning process). In example (b), an additional film 1006 is disposed on the interlayer dielectric line 1004 . In example (c), the additional film 1008 is disposed on the metal line 1002 . In example (d), the additional film 1006 is disposed on the interlayer dielectric line 1004 , and the additional film 1008 is disposed on the metal line 1002 . Furthermore, although the metal lines 1002 and the interlayer dielectric lines 1004 are described as coplanar in (a), in other embodiments, they may be non-coplanar. For example, in (e), the metal line 1002 protrudes above the interlayer dielectric line 1004. In example (f), the metal line 1002 is recessed under the interlayer dielectric line 1004 .

Referring again to examples (b)-(d), additional layers (eg, layers 1006 or 1008) may be used as hard masks (HM) or protective layers or to enable selective growth as described below in connection with subsequent processing operations and/or self-aggregation. These additional layers can also be used to protect the ILD from further processing. Furthermore, selectively depositing another material over the metal lines may be advantageous for similar reasons. Referring again to examples (e) and (f), ILD lines or metal lines can also be recessed by any combination of protective/HM materials on either or both surfaces. In summary, there are several options at this stage to prepare the final underlying surface for selective or directional self-polymerization processes.

10B illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 10A following formation of interlayer dielectric (ILD) lines 1010 over the structure of FIG. 10A, in accordance with an embodiment of the present invention. With reference to plan views and corresponding cross-sectional views (a) and (c), respectively, taken along axes a-a' and c-c', ILD lines 1010 are formed as grating structures in a direction perpendicular to underlying lines 1004 middle. In one embodiment, a cover film of the material of line 1010 is deposited by chemical vapor deposition or similar techniques. In one embodiment, the capping film is then patterned using lithography and etching processes, which may involve, for example, spacer-based quadruple patterning (SBQP) or quarter pitch. It should be understood that the grating pattern of lines 1010 can be fabricated by several methods, including EUV and/or EBDW lithography, directional self-polymerization, and the like. As will be described in more detail below, subsequent metal layers will therefore be patterned in an orthogonal direction relative to the previous metal layers, since the grating of lines 1010 is orthogonal to the direction of the underlying structure. In one embodiment, a single 193nm lithography mask is used to align/align to the previous metal layer 1002 (eg, the grating of lines 1010 is aligned in X to the previous layer "plug" pattern and in Y to previous metal grating). Referring to the cross-sectional structures (b) and (d), the hard mask 1012 may be formed on the dielectric line 1010 , or may be left after patterning of the dielectric line 1010 . The hard mask 1012 can be used to protect the lines 1010 during subsequent patterning steps. As described in more detail below, the formation of lines 1010 in a grating pattern exposes regions of previous metal lines 1002 and previous ILD lines 1004 (or corresponding hard mask layers on 1002/1004). The exposed regions correspond to all possible future via locations where metal is exposed. In one embodiment, previous metal layers (eg, lines 1002) are protected, marked, brushed, etc., at this point in the process flow.

10C illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 10B following selective differentiation of all potential via locations from all plug locations, in accordance with an embodiment of the present invention. Reference plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a', bb', c-c' and d-d', respectively, continue on ILD line 1010 After formation, a surface modification layer 1014 is formed on the exposed regions of the underlying ILD lines 1004 . In one embodiment, the surface modification layer 1014 is a dielectric layer. In one embodiment, the surface modification layer 1014 is formed by selective bottom-up growth. In one such embodiment, the bottom-up growth approach involves a directional self-polymerization (DSA) brush coating with a coating that preferentially collects on the underlying ILD line 1004 or (alternatively) on the metal line 1002 (or on the sacrificial line 1002). layer, the sacrificial layer is disposed on or grown on the underlying metal or ILD material) of the polymer composition.

10D illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 10C following its addition to the differential polymer of the exposed portions of the underlying metal and ILD lines of FIG. 10C, in accordance with an embodiment of the present invention. Reference plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a', b-b', c-c' and d-d', respectively, under metal/ILD Directed Self-Aggregation (DSA) or selective growth on exposed portions of the 1002/1004 grating is used to form intermediate lines 1016 with alternating polymer or alternating polymer compositions between ILD lines 1010. For example, as shown, polymer 1016A (or polymer composition 1016A) is formed on or over exposed portions of interlayer dielectric (ILD) lines 1004 of Figure 10C, while polymer 1016B (or polymer composition 1016B) is formed on or over the exposed portion of the metal line 1002 of Figure 10C. Although polymer 1016A is formed on or over surface modification layer 1014 as described in connection with FIG. 10C (see cross-sectional views (b) and (d) of FIG. 10D ), it should be understood that in other embodiments, the surface modification Layer 1014 may be omitted or alternate polymers or alternate polymer compositions may instead be formed directly in the structure described in connection with FIG. 10B.

Referring again to FIG. 10D , in one embodiment, once the surface of the underlying structure (eg, structure 1000 of FIG. 10A ) has been prepared (eg, such as the structure of FIG. 10B or the structure of FIG. 10C ) or used directly, a A 50-50 diblock copolymer, such as polystyrene-polymethylmethacrylate (PS-PMMA), is coated on a substrate and annealed to drive self-polymerization, resulting in polymer 1016A of Figure 10D /Polymer 1016B Layer 1016. In this embodiment, with appropriate surface energy conditions, the block copolymers are separated according to the underlying material exposed between the ILD lines 1010. For example, in one particular embodiment, polystyrene is selectively aligned to exposed portions of the underlying wire 1002 (or corresponding wire capping or hardmask material). At the same time, the polymethyl methacrylate is selectively aligned to the exposed portions of the ILD lines 1004 (or corresponding metal line capping or hard mask material).

Thus, in one embodiment, the underlying metal and ILD grids (eg, those exposed between ILD lines 1010) are regenerated in block copolymer (BCP, ie, polymer 1016A/polymer 1016B). This may especially be the case if the BCP pitch is comparable to the underlying grating pitch. The polymer grid (Polymer 1016A/Polymer 1016B), in one embodiment, is robust to some small deviation from a properly aligned grid. For example, a properly aligned polymer 1016A/polymer 1016B grid can still be achieved if the small plug is effectively provided with a material such as oxide (where a properly aligned grid would have metal). However, since the ILD line grating (in one embodiment) is an idealized grating structure with no metal breakage of the ILD backbone, it may be desirable to neutralize the ILD surface since the two types of polymers (1016A and 1016B) will In this example) is exposed to the ILD type material and only one type is exposed to the metal.

In one embodiment, the thickness of the coated polymer (polymer 1016A/1016B) is approximately the same (or slightly thicker) than the final thickness of the ILD that is ultimately formed in its place. In one embodiment, as described in more detail below, the polymer grid is not formed as an etch resist, but as a scaffold around which to eventually grow a permanent ILD layer. As such, the thickness of polymer 1016 (polymer 1016A/polymer 1016B) may be important as it can be used to define the final thickness of the subsequently formed permanent ILD layer. That is, in one embodiment, the polymer grating shown in FIG. 10D is eventually replaced with an ILD grating of approximately the same thickness.

In one embodiment, as described above, the polymer 1016A/polymer 1016B grid of FIG. 10D is a block copolymer. In this embodiment, the block copolymer molecules are polymer molecules formed from chains of covalently joined monomers. In block copolymers, there are at least two different types of monomers, and these different types of monomers are primarily included in different blocks or adjacent sequences of monomers. The block copolymer molecules shown include blocks of polymer 1016A and blocks of polymer 1016B. In one embodiment, the blocks of polymer 1016A primarily include chains of covalently linked monomer A (eg, A-A-A-A-A...), while the blocks of polymer 1016B primarily include covalently linked chains of monomer B chain (eg, B-B-B-B-B...). Monomers A and B can represent any of the different types of monomers used in block copolymers known in the art. For example, monomer A may represent the monomer used to form polystyrene, and monomer B may represent the monomer used to form polymethyl methacrylate (PMMA), although the scope of the invention is not so limited. In other embodiments, there may be more than two blocks. Furthermore, in other embodiments, each of the blocks may include a different type of monomer (eg, each block may itself be a copolymer). In one embodiment, blocks of polymer 1016A and blocks of polymer 1016B are covalently bonded together. The blocks of polymer 1016A and the blocks of polymer 1016B can be about the same length, or one block can be significantly longer than the other.

Typically, blocks of block copolymers (eg, blocks of polymer 1016A and blocks of polymer 1016B) can each have different chemistries. For example, one of the blocks can be relatively hydrophobic (eg, water repellent) and the other can be relatively relatively hydrophilic (water absorbent). At least conceptually, one of the blocks can be relatively oil-like and the other block can be relatively water-like. Such differences in chemical properties between different block polymers (whether hydrophilic-hydrophobic differences or otherwise) may cause the block copolymer molecules to self-polymerize. For example, self-polymerization can be based on microphase separation of polymer blocks. Conceptually, this can be analogous to the phase separation of oil and water, which are generally immiscible. Similarly, differences in hydrophilicity between polymer blocks (eg, one block is relatively hydrophobic and another block is relatively hydrophilic) may result in roughly similar microphase separation, where different polymers Blocks try to "separate" from each other because they don't like each other chemically.

However, in one embodiment, because the polymer blocks are covalently bonded to each other, they cannot be completely separated on a macroscopic scale. Conversely, polymer blocks of a given type tend to separate or aggregate in extremely small (eg, nanoscale) regions or phases from polymer blocks of other molecules of the same type. The particular size and shape of the domains or microphases generally depends, at least in part, on the relative lengths of the polymer blocks. In one embodiment, by way of example (as shown in Figure 10D ), in two block copolymers, alternating grids of polymer 1016A lines and polymer 1016B lines are produced if the blocks are approximately the same length. Grid pattern. In another embodiment (not shown), in a two-block copolymer, a columnar structure can be formed if one of the blocks is longer than the other, but not by much longer than the other. In a columnar structure, the block copolymer molecules can be microphase separated into their shorter polymer blocks inside the columns and their longer polymer blocks extending away from and around the columns. For example, if the blocks of polymer 1016A are longer (but not too much longer) than the blocks of polymer 1016B, a columnar structure can be formed with many blocks of copolymer molecules paired with their shorter blocks of polymer 1016B standard, forming a columnar structure surrounded by phases with longer blocks of polymer 1016A. When this occurs in an area of sufficient size, then a two-dimensional array of generally hexagonally packaged columnar structures can be formed.

In one embodiment, the Polymer 1016A/Polymer 1016B grating is first applied as part of an unpolymerized block copolymer layer including block copolymer applied, for example, by brushing or other coating process Material. The unpolymerized form refers to a situation in which (at the time of deposition) the block copolymer has not yet substantially phase separated and/or self-polymerized to form nanometers. In this unpolymerized form, the block polymer molecules are fairly highly randomized, with distinct polymer blocks oriented and positioned relatively highly randomly, as opposed to the aggregate blocks discussed in conjunction with the resulting structure of Figure 10D Part of the copolymer layer. The unpolymerized block copolymer layer portion can be applied in a number of different ways. For example, the block copolymer can be dissolved in a solvent and then spin coated onto a surface. Alternatively, the unpolymerized block copolymer may be sprayed, dipped, dipped, or otherwise coated or applied to the surface. Other ways of applying the block copolymer, as well as other ways known in the art for applying similar organic coatings, can potentially be used. The unpolymerized layer can then form portions of the polymerized block copolymer layer, eg, by microphase separation and/or self-polymerization of the unpolymerized block copolymer layer portion. Microphase separation and/or self-polymerization occurs through the reconfiguration and/or repositioning of the block copolymer molecules, and in particular the reconfiguration and/or repositioning of the different polymer blocks of the block copolymer molecules.

In this embodiment, an annealing treatment can be applied to the unpolymerized block copolymer to initiate, accelerate, increase, or improve the quality of microphase separation and/or self-polymerization. In certain embodiments, the annealing treatment may include a treatment operable to increase the temperature of the block copolymer. An example of such a treatment is baking the layer, heating the layer in an oven or over a heat lamp, applying infrared radiation to the layer, or applying heat to the layer or increasing the temperature of the layer. The desired temperature increase will generally be sufficient to significantly accelerate the microphase separation and/or self-polymerization of the block polymer without damaging the block copolymer or any other important materials or structures of the integrated circuit substrate. Typically, the heating range can be from about 50°C to about 300°C, or from 75°C to about 250°C, without exceeding the thermal degradation limits of the block copolymer or integrated circuit substrate. Heating or annealing can help provide energy to the block copolymer molecules to make them more mobile/elastic to increase the rate and/or quality of microphase separation. This microphase separation or reconfiguration/repositioning of block copolymer molecules can result in self-polymerization to form extremely small (eg, nanoscale) structures. Self-polymerization can occur under the influence of surface energy, molecular affinity, and other surface-related and chemical-related forces.

In any event, in certain embodiments, self-polymerization of block copolymers (whether by virtue of hydrophobic-hydrophilic differences or not) can be used to form extremely small periodic structures (eg, precisely spaced nanoscale structures or Wire). In some embodiments, it can be used to form nanoscale lines or other nanoscale structures that can ultimately be used to form vias and openings. In certain embodiments, directional self-polymerization of block copolymers can be used to form vias that are self-aligned with interconnects, as described in more detail below.

Referring again to FIG. 10D, in one embodiment, for the DSA process, the growth process may be affected by the sidewalls of the material of the ILD line 1010, except from the direction from the underlying ILD/metal 1004/1002 surface. As such, in one embodiment, DSA is controlled by graphic epitaxy (from the sidewalls of lines 1010) and chemical epitaxy (from below to expose surface features). Physically and chemically confining the DSA process can significantly assist the process, from a defectivity standpoint. The resulting polymer 1016A/1016B has fewer degrees of freedom and is completely localized in all directions by chemical (eg, underlying ILD or metal lines, or surface modifications made to it by, for example, brushing) and Physical (eg, from trenches formed between ILD lines 1010).

In an alternative embodiment, a selective growth process is used instead of DSA. 10E illustrates a cross-sectional view of the structure of FIG. 10B following selection of exposed portions of the underlying metal and ILD lines, in accordance with another embodiment of the present invention. Referring to FIG. 10E , a first material type 1090 is grown over exposed portions of the underlying ILD lines 1004 . A second (different) material type 1092 is grown over exposed portions of the underlying metal lines 1002. In one embodiment, selective growth is achieved by a dep-etch-dep-etch approach to each of the first and second materials, resulting in each of the materials Plural layers of the original, as depicted in Figure 10E. This approach may be ideal relative to conventional selective growth techniques which can form "mushroom top"-like membranes. Mushroom top film growth propensity can be reduced by an alternating deposition/etch/deposition (dep-etch-dep-etch) approach. In another embodiment, a film is selectively deposited over the metal, followed by a different film selectively deposited over the ILD (or vice versa), and repeated several times to create a sandwich-like stack. In another embodiment, the two materials are grown simultaneously in a reaction chamber (eg, by a CVD-style process) selectively grown on exposed regions of the underlying substrate.

10F illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 10D following removal of a polymer, in accordance with an embodiment of the present invention. Reference plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a', bb', c-c' and d-d', respectively, polymer or polymer Portion 1016A is removed to re-expose ILD line 1004 (or a hard mask or cap layer formed on ILD line 1004 ), while polymer or polymer portion 1016B is left over metal line 1002 . In one embodiment, a deep ultraviolet (DUV) bulk exposure followed by wet etching or selective dry etching is used to selectively remove polymer 1016A. It should be understood that instead of the first removal of polymer from the ILD line 1004 (as shown), the removal from the metal line 1002 may instead be performed first. Alternatively, a dielectric film is selectively grown over this region, and the hybrid scaffold is not used.

10G illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 10F following formation of the ILD material in a position opened upon removal of a polymer, in accordance with an embodiment of the present invention. Reference plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a', bb', c-c', and d-d', respectively, below ILD line 1004 The exposed regions are filled with a permanent interlayer dielectric (ILD) layer 1018 . As such, the open space between all possible via locations is filled with the ILD layer 1018, which includes the hardmask layer 1020 disposed thereon, such as the plan view and cross-sectional view of 1OG (b) and those depicted in (d). It should be understood that the material of the ILD layer 1018 need not be the same material as the ILD line 1010 . In one embodiment, the ILD layer 1018 is formed by deposition and polishing processes. In cases where the ILD layer 1018 is formed with an accompanying hard mask layer 1020, special ILD fill materials may be used (eg, polymer-encapsulated nanoparticles of the ILD that fill the holes/trenches). In this case, polishing operations may not be required.

Referring again to FIG. 10G , in one embodiment, the resulting structure includes a uniform ILD structure (ILD line 1010 + ILD layer 1018 ), while all possible plug locations are covered by hardmask 1020 and all possible vias are located in polymer 1016B in the area. In this embodiment, the ILD line 1010 and the ILD layer 1018 are composed of the same material. In another such embodiment, the ILD line 1010 and the ILD layer 1018 are composed of different ILD materials. In either case, in a particular embodiment, differences such as seams between the materials of the ILD wire 1010 and the ILD layer 1018 may be observed in the final structure. An example seam 1099 is shown in FIG. 10G for illustrative purposes.

10H illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 10G subsequent to via patterning, in accordance with an embodiment of the present invention. With reference to plan views and corresponding cross-sectional views (a)-(d), taken along axes a-a', bb', c-c', and d-d', respectively, via locations 1022A, 1022B and 1022C are opened by removal of polymer 1016B in selected locations. In one embodiment, selective via location formation is accomplished using lithography techniques. In one such embodiment, polymer 1016B is removed in its entirety with ash and refilled with photoresist. Photoresists can be highly sensitive and have large acid diffusion and aggressive deprotection or crosslinking (depending on resist hue) because the latent image is formed by the ILD (eg, by the ILD line 1010 and the ILD layer 1018 ) limited to two directions. The resist acts as a digital switch that can be turned "on" or "off" depending on whether vias are required in specific locations. Ideally, photoresist can be used to fill only the holes without spillage. In one embodiment, via locations 1022A, 1022B, and 1022C are completely confined to the process so that their line edge or width roughness (LWR) and line collapse and/or reflections are mitigated (if not eliminated). In one embodiment, low doses are used with EUV/EBDW and significantly increase the operating rate. In one embodiment, an additional advantage of utilizing EBDW is that there is only one shot type/size that increases the run rate by significantly reducing the number of apertures required and reducing the dose it needs to be delivered. In the case where it uses 193nm immersion lithography, in one embodiment, the process flow restricts the via locations to two directions so that the size of the vias that are actually patterned is the size of the actual vias on the wafer. twice the size (eg assuming a 1:1 line/space pattern). Alternatively, via locations can be chosen to be inverse tones, where vias that need to be preserved are protected with photoresist and the remaining locations are removed and later filled with ILD. This approach allows a single metal fill/polish process at the end of the patterning process rather than two separate metal deposition steps.

10I illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 10H subsequent to via formation, in accordance with an embodiment of the present invention. With reference to plan views and corresponding cross-sectional views (a)-(d), taken along axes a-a', bb', c-c', and d-d', respectively, via locations 1022A, 1022B and 1022C are individually filled with metal to form vias 1024A, 1024B and 1024C. In one embodiment, via locations 1022A, 1022B, and 1022C are filled with excess metal, and subsequent polishing operations are performed. However, in another embodiment, via locations 1022A, 1022B, and 1022C are filled without metal overfill and the polishing operation is omitted. It should be understood that the via filling shown in FIG. 10I can be skipped in the reverse tone via selection mode.

10J illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 10I following removal of the second polymer and replacement with ILD material, in accordance with an embodiment of the present invention. Reference plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a', bb', c-c' and d-d', respectively, the remaining polymer Or the polymer portion 1016B (eg, where the via location has not been selected) is removed to re-expose the metal line 1002 . Thereafter, an ILD layer 1026 is formed in the location where the remaining polymer or polymer portion 1016B was removed, as depicted in Figure 10J.

Referring again to FIG. 10J , in one embodiment, the resulting structure includes a uniform ILD structure (ILD line 1010 + ILD layer 1018 + ILD layer 1026 ), and all possible plug locations are covered with a hard mask 1020 . In this embodiment, ILD line 1010, ILD layer 1018, and ILD layer 1026 are composed of the same material. In another such embodiment, two of the ILD line 1010, the ILD layer 1018, and the ILD layer 1026 are composed of the same material and the third is composed of a different ILD material. In yet another embodiment, the ILD line 1010, the ILD layer 1018, and the ILD layer 1026 are all composed of different ILD materials from each other. In either case, in a particular embodiment, differences such as seams between the materials of the ILD wire 1010 and the ILD layer 1026 may be observed in the final structure. An example seam 1097 is shown in Figure 10J for illustrative purposes. Similarly, differences such as a seam between the materials of ILD layer 1018 and ILD layer 1026 may be observed in the final structure. An example seam 1098 is shown in FIG. 10J for illustrative purposes.

10K illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 10J following patterning of the resist or mask in selected plug locations, in accordance with an embodiment of the present invention. Referring to the respective plan views and corresponding cross-sectional views (a) and (b) taken along axes a-a' and bb', plug locations 1028A, 1028B, and 1028C are created by forming a mask or resist A layer of etchant remains over those locations. This retention patterning may be referred to as metal end-to-end lithography patterning, where the plug locations are determined as required for breaks in subsequently formed metal lines. It should be understood that plugging can occur over previous layer ILD lines 1004 because plug locations can only be in those locations where the ILD layer 1018/hardmask 1020 is placed. In one embodiment, patterning is achieved by using a lithographic operation (eg, EUV, EBDW, or immersion 193 nm). In one embodiment, the process shown in FIG. 10K shows the use of a positive tone patterning process in which the spaces between the metals are preserved where the spaces need to occur. It should be understood that in another embodiment, it is also possible to open the holes and reverse the color tone of the process instead.

10L illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 10K following hardmask removal and recessing of the ILD layer, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a' and bb', respectively, with hard mask 1020 removed and ILD layer 1018 and ILD layer 1026 Recessed to individually form recessed ILD layer 1018' and recessed ILD layer 1026', by etching these layers below their original uppermost surfaces. It should be understood that the recessing of the ILD layer 1018 and the ILD layer 1026 is performed without etching or recessing the ILD line 1010 . Selectivity can be achieved by using a hard mask layer 1012 on the ILD line (as depicted in cross-sectional views (a) and (b)). Alternatively, where the ILD line 1010 is composed of an ILD material different from that of the ILD layer 1018 and the ILD layer 1026, a selective etch can be used even in the absence of the hard mask 1012. The recesses in ILD layer 1018 and ILD layer 1026 are used to provide locations for second level metal lines, as isolated by ILD lines 1010, as described below. The degree or depth of the recess (in one embodiment) is selected according to the desired final thickness of the metal lines formed thereon. It should be understood that the ILD layer 1018 in the plug locations 1028A, 1028B and 1028C is not recessed.

10M illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 10L following metal line formation, in accordance with an embodiment of the present invention. Reference plan view and corresponding cross-sectional views (a), (b) and (c), taken along axes a-a', bb' and bb', respectively, for forming metal interconnects The metal of the lines is conformally formed over the structure of Figure 10L. The metal is then planarized (eg, by CMP) to provide metal lines 1030, which are confined to locations over recessed ILD layer 1018' and recessed ILD layer 1026'. Metal line 1030 is coupled to underlying metal line 1002 through predetermined via locations 1024A, 1024B, and 1024C (1024B is shown in cross-sectional view (c); note: for illustrative purposes, in cross-sectional view ( Another via 1032 in b) is depicted as directly adjoining plug 1028B, even though this is inconsistent with the previous figure). Metal lines 1030 are isolated from each other by ILD lines 1010 and interrupted or separated by remaining plugs 1028A, 1028B and 1028C. Any hard masks remaining on the plug locations and/or on the ILD lines 1010 can be removed at this portion of the process flow, as depicted in Figure 10M. The metal (eg, copper and associated barrier and seed layers) deposition and planarization processes used to form the metal lines 1030 may be those typically used for standard back end of line (BEOL) single or dual damascene processors. In one embodiment, in subsequent fabrication operations, the ILD lines 1010 may be removed to provide air gaps between the resulting metal lines 1030 .

The structure of Figure 10M can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of FIG. 10M may represent the final metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations may be performed in alternate sequences, not every operation needs to be performed and/or additional process operations may be performed. Furthermore, while the above process flow is focused on the application of Directed Self-Aggregation (DSA), the selective growth process may alternatively be used at one or more locations in the process flow. In any case, the resulting structure enables the fabrication of vias which are directly focused on the underlying metal lines. That is, the vias may be wider, narrower, or the same thickness as the underlying metal lines, eg, due to a non-perfect selective etch process. However, in one embodiment, the centers of the vias are directly aligned (matched) with the centers of the metal lines. As such, in one embodiment, variations due to conventional lithography/damascene patterning (which would otherwise be tolerated) do not factor into the resulting structures described herein.

One or more embodiments described herein relate to front layer self-aligned via and plug patterning. The self-aligned aspect of the procedures described herein may be based on a directed self-aggregation (DSA) mechanism, as described in more detail below. It should be understood, however, that selective growth mechanisms can be utilized in substitution (or in conjunction with) DSA-based approaches. In one embodiment, the procedures described herein enable the realization of self-aligned metallization for back-end-of-process feature fabrication.

11A-11M illustrate portions of integrated circuit layers that represent various operations in a method of self-aligned vias and metal patterning, in accordance with embodiments of the present invention. In each illustration of the described operations, the plan view is shown on the left hand side and the corresponding cross-sectional view is shown on the right hand side. These views will be referred to herein as the corresponding cross-sectional and plan views.

11A illustrates a plan view and corresponding cross-sectional view for a selection of front-level metallization structures, in accordance with an embodiment of the present invention. Referring to plan view and corresponding cross-sectional view option (a), starting structure 1100 includes a pattern of metal lines 1102 and interlayer dielectric lines (ILD) 1104 . The starting structure 1100 can be patterned into a grating-like pattern, with metal lines spaced at a constant pitch and of constant width, as depicted in FIG. 11A, if a self-polymerizing material is to be used. If a directional selective growth technique is used, the underlying pattern need not be of a single pitch or width. Patterns, for example, can be fabricated by halving the pitch or reducing the pitch by a quarter. Certain lines may be associated with underlying vias, such as line 1102' shown in one example of the cross-sectional view.

Referring again to FIG. 11A, alternative options (b)-(f) are discussed in which an additional film (eg, deposited, grown, or leaving artifacts as left over from the previous patterning process). In example (b), the additional film 1106 is disposed on the interlayer dielectric line 1104 . In example (c), the additional film 1108 is disposed on the metal line 1102 . In example (d), the additional film 1106 is disposed on the interlayer dielectric line 1104 , and the additional film 1108 is disposed on the metal line 1102 . Furthermore, although the metal lines 1102 and the interlayer dielectric lines 1104 are described as coplanar in (a), in other embodiments, they may be non-coplanar. For example, in (e), the metal lines 1102 protrude above the interlayer dielectric lines 1104 . In example (f), the metal line 1102 is recessed under the interlayer dielectric line 1104 .

Referring again to examples (b)-(d), additional layers (eg, layers 1106 or 1108) may be used as hard masks (HM) or protective layers or to enable selective growth as described below in connection with subsequent processing operations and/or self-aggregation. These additional layers can also be used to protect the ILD from further processing. Furthermore, selectively depositing another material over the metal lines may be advantageous for similar reasons. Referring again to examples (e) and (f), ILD lines or metal lines can also be recessed by any combination of protective/HM materials on either or both surfaces. In summary, there are several options at this stage to prepare the final underlying surface for selective or directional self-polymerization processes.

11B illustrates a selected plan view and corresponding cross-sectional view for directed self-aggregation (DSA) growth on an underlying metal/ILD grating (eg, on a structure such as that shown in FIG. 11A ), in accordance with an implementation of the present invention example. Referring to the plan view, structure 1110 includes a layer having alternating polymers or alternating polymer compositions. For example, as shown, polymer A (or polymer component A) is formed on or over interlayer dielectric (ILD) lines 1104 of FIG. 11A , while polymer B (or polymer component B) is formed on FIG. 11A on or above the metal line 1102. Referring to the cross-sectional view, in (a), polymer A (or polymer component A) is formed on ILD wire 1104 , and polymer B (or polymer component B) is formed on metal wire 1102 . In (b), polymer A (or polymer component A) is formed on the additional film 1106 formed on the ILD wire 1104 , and polymer B (or polymer component B) is formed on the metal wire 1102 . In (c), polymer A (or polymer component A) is formed on the ILD wire 1104 and polymer B (or polymer component B) is formed on the additional film 1108 formed on the metal wire 1102 . In (d), polymer A (or polymer component A) is formed on the additional film 1106 formed on the ILD wire 1104, and polymer B (or polymer component B) is formed on the metal wire 1102. on the additional film 1108 formed.

Referring again to FIG. 11B, in one embodiment, once the surface of the underlying structure (eg, structure 1100 of FIG. 11A) has been prepared, a 50-50 two-block copolymer, such as polystyrene-polymethylmethacrylate Ester (PS-PMMA), was coated on the substrate and annealed to drive self-polymerization, resulting in the polymer A/polymer B layers of structure 1110 of Figure 11B. In this embodiment, with appropriate surface energy conditions, the block copolymers are separated from the underlying material of the structure 1100. For example, in one particular embodiment, polystyrene is selectively aligned to the underlying wire 1102 (or corresponding wire capping or hardmask material). At the same time, the polymethyl methacrylate is selectively aligned to the ILD line 1104 (or corresponding wire capping or hard mask material).

Thus, in one embodiment, the underlying metal and ILD grids are regenerated in block copolymer (BCP, ie, polymer A/polymer B). This may especially be the case if the BCP pitch is comparable to the underlying grating pitch. The polymer grid (Polymer A/Polymer B), in one embodiment, is robust to some small deviation from a very properly aligned grid. For example, a very properly aligned Polymer A/Polymer B grid can still be achieved if the small plugs are effectively provided with materials such as oxides (where a very properly aligned grid would have metal). However, since the ILD line grating (in one embodiment) is an idealized grating structure with no metal breakage of the ILD backbone, it may be desirable to neutralize the ILD surface since the two types of polymers (A and B) will In this example) is exposed to the ILD type material and only one type is exposed to the metal.

In one embodiment, the thickness of the coated polymer (A/B) is about the same (or slightly thicker) as the final thickness of the ILD that is ultimately formed in its place. In one embodiment, as described in more detail below, the polymer grid is not formed as an etch resist, but as a scaffold around which to eventually grow a permanent ILD layer. As such, the thickness of the polymer (A/B) may be important as it can be used to define the final thickness of the subsequently formed permanent ILD layer. That is, in one embodiment, the polymer grating shown in FIG. 11B is eventually replaced with an ILD grating of approximately the same thickness.

In one embodiment, as described above, the polymer A/polymer B grid of FIG. 2 is a block copolymer. In one such embodiment, the block copolymer molecule is one such as that described above in connection with Figure 10D. In one embodiment, via a first example (shown in FIG. 11B ), in a two-block copolymer, if the blocks are approximately the same length, alternating polymer A lines and polymer B lines are produced. Grid-like pattern. In another embodiment, via a second example (not shown), in a two-block copolymer, a vertical columnar structure can be formed if one of the blocks is longer than the other, but not by much . In a columnar structure, the block copolymer molecules can be microphase separated into their shorter polymer blocks inside the columns and their longer polymer blocks extending away from and around the columns. For example, if a block of polymer A is longer (but not too long) than a block of polymer B, a columnar structure can be formed with many block copolymer molecules aligned with its shorter block of polymer B , forming a columnar structure surrounded by phases with longer blocks of polymer A. When this occurs in an area of sufficient size, then a two-dimensional array of pillar-like structures, typically hexagonally packaged, can be formed.

In one embodiment, the Polymer A/Polymer B grating is first coated as part of an unpolymerized block copolymer layer, including, for example, block copolymer applied by brushing or other coating process Materials, as described above in connection with Figure 10D. In this embodiment, an annealing treatment may be applied to the unpolymerized block copolymer to initiate, accelerate, increase its quality, or enhance microphase separation and/or self-polymerization, as described above in connection with Figure 10D.

11C illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 11B following removal of a polymer, in accordance with an embodiment of the present invention. Referring to FIG. 11C , polymer B is removed to re-expose metal lines 1102 (or a hard mask or capping layer formed on metal lines 1102 ), while polymer A is retained in ILD lines 1104 to form structures 1112 . In one embodiment, deep ultraviolet (DUV) bulk exposure followed by wet etching or selective dry etching is used to selectively remove polymer B. It will be appreciated that, instead of the first removal of polymer from the metal line 1102 (as shown), the removal from the ILD line may instead be performed first.

11D illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 11C after formation of a layer of sacrificial material over metal lines 1102, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (b), structure 1114 includes a sacrificial B layer formed on or over metal lines 1102 and between polymer A over or over ILD lines 1104 . In one embodiment, referring to cross-sectional view (a), low temperature deposition fills the trenches between the polymer A-lines, eg, with oxides (eg, _TiOx ) or other sacrificial materials as conformal Layer 1116. The conformal layer 1116 is then confined to the area over the metal line 1102 by a dry etch or chemical mechanical planarization (CMP) process. The resulting layer is referred to herein as sacrificial B because, in some embodiments, its material is ultimately replaced with permanent ILD material. However, in other embodiments, it should be understood that the permanent ILD material may alternatively be formed at this stage. Where sacrificial materials are used, in one embodiment, the sacrificial materials have the necessary deposition properties, thermal stability, and etch selectivity to other materials used in the process.

11E illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 11D following the replacement of polymer A with a permanent interlayer dielectric (ILD) material, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (c), structure 1118 includes permanent interlayer dielectric (ILD) lines 1120 on or over ILD lines 1104 and between sacrificial B-material lines. In one embodiment, the polymer A lines are removed as depicted in cross-sectional view (a). Next, referring to cross-sectional view (b), a layer 1119 of ILD material is conformally formed over the resulting structure. The conformal layer 1119 is then confined to the area over the ILD line 1104 by a dry etch or chemical mechanical planarization (CMP) process. In one embodiment, structure 1118 effectively replaces the polymer (A/B) grating of FIG. 11B with a grating of extremely thick material (eg, permanent ILD 1120 and sacrificial B), the grating of extremely thick material and the underlying metal grating Compatible and aligned with the lower grating. Two different materials can be used to ultimately define possible locations for plugs and vias, as described in more detail below.

11F illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 11E after selective hardmask formation on the permanent ILD line, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (c), structure 1122 includes a hard mask layer 1124 formed over permanent interlayer dielectric (ILD) lines 1120 . In one embodiment, referring to cross-sectional view (c), a selective growth process is used to form hard mask layer 1124 limited to the surface of permanent ILD lines 1120 . In another embodiment, a layer of conformal material 1123 is first formed (cross-sectional view (a)) on a structure with recessed permanent ILD lines 1120. Conformal layer 1123 is then subjected to a timed etch and/or CMP process to form hard mask layer 1124 (cross-sectional view (b)). In the latter case, the ILD lines 1120 are recessed relative to the sacrificial B material, and then a non-conformal (planarized) hardmask 1123 is deposited on the resulting grating. The material 1123 is thinner on the sacrificial B line than on the recessed ILD line 1120 so that a timed etch or polish operation of the hardmask selectively removes the material 1123 from the sacrificial B material.

11G illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 11F following removal of the sacrificial B line and replacement with a permanent ILD line 1128, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (c), structure 1126 includes permanent ILD line 1128 in place of the sacrificial B line of FIG. 11F , ie, over and aligned with metal line 1102 . In one embodiment, the sacrificial B material is removed (cross-sectional view (a)) and replaced with permanent ILD lines 1128 (cross-sectional view (c)), eg, by deposition of a conformal layer and subsequent Timed etching or CMP treatment (cross-sectional view (b)). In one embodiment, the resulting structure 1126 includes a uniform ILD material (permanent ILD line 1120 + permanent ILD line 1128) with all possible plug locations covered with hardmask 1124 and all possible vias on exposed permanent ILD lines in the area of 1128. In this embodiment, permanent ILD wire 1120 and permanent ILD wire 1128 are composed of the same material. In another such embodiment, permanent ILD wire 1120 and permanent ILD wire 1128 are composed of different ILD materials. In either case, in a particular embodiment, differences such as a seam between the materials of permanent ILD wire 1120 and permanent ILD wire 1128 may be observed in final structure 1126 . An example seam 1199 is shown in FIG. 11F for illustrative purposes.

11H illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 11G following trench formation (eg, grating definition), in accordance with an embodiment of the present invention. Reference plan views and corresponding cross-sectional views (a)-(d), taken along axes a-a', bb', c-c', and d-d', respectively, are shown in Figure 11G Trenches 1132 are formed in the structure to define a grating in structure 1130 (perpendicular to the grating of Figure 11G) to ultimately define the regions between the patterns of metal lines. In one embodiment, trenches 1132 are formed by patterning and etching a grating pattern into sacrificial gratings of earlier structures. In one embodiment, a grid is formed, effectively simultaneously defining all the spaces between the resulting metal lines as well as the locations of all plugs and vias. In one embodiment, trench 1132 exposes the location of underlying ILD line 1104 and metal line 1102 .

11I illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 11H following the formation of a grating of sacrificial material in the trench of FIG. 11H, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a)-(d), taken along axes a-a', bb', c-c', and d-d', respectively, material layer 1134 (which An interlayer dielectric layer or sacrificial layer) is formed in the trenches 1132 of the structure of FIG. 11H. In one embodiment, material layer 1134 is formed by conformal deposition with a permanent ILD material or sacrificial layer followed by a timed etch or CMP (eg, which can be removed later if an air gap is to be fabricated) . In the former case, the material layer 1134 eventually becomes the ILD material between the parallel metal lines formed subsequently on the same metal layer. In the latter case, the material may be referred to as a sacrificial C material, as shown. In one embodiment, material layer 1134 has high etch selectivity to other ILD materials and to hard mask layer 1128 .

11J illustrates a plan view and a corresponding cross-sectional view of the structure of FIG. 11I following formation and patterning of the mask and subsequent etching of via locations, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b), taken along axes a-a' and b-b', respectively, a mask 1136 is formed over the structure of Figure 11I. The mask is patterned, eg, by a lithography process, to have openings 1137 formed therein. In one embodiment, the openings are determined according to the desired pattern of the vias. That is, at this stage, all possible vias and plugs (eg, as placeholders) have been patterned and self-aligned to the final metal layers above and below. Here, a subset of via and plug locations are selected for reservation, such as locations where metal lines are etched. In one embodiment, ArF or EUV or e-beam resist is used to cut or select vias to be etched, ie, at the locations of exposed portions of metal lines 1102 . It should be understood that the hard mask 1124 and the material layer 1134 act as the actual etch mask that determines the shape and location of the vias. The mask 1136 only acts to block the remaining vias from being etched. In this way, the tolerance for the size of opening 1137 is relaxed because the selected via location (ie, the portion of opening 1137 that is directly above the exposed portion of metal line 1102 ) is surrounded by material (eg, hardmask 1124 and Material layer 1134) resists the etch process used to remove ILD lines 1128 over selected portions of metal lines 1102 for final via fabrication. In one embodiment, the mask 1136 is composed of a topographic mask portion 1136C, an anti-reflective coating (ARC) layer 1136B, and a photoresist layer 1136A. In a particular such embodiment, topographic mask 136C is a carbon hard mask (CHM) layer and anti-reflective coating 136B is a silicon ARC layer.

11K illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 11J following mask and hardmask removal and subsequent plug patterning and etching, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b), taken along axes a-a' and bb', respectively, the mask 1136 shown in FIG. 11J is patterned at the via locations was later removed. Afterwards, a second mask 1138 is formed and patterned to cover the selected plug locations. Specifically, in one embodiment, and as depicted in FIG. 11K , portions of hardmask 1124 are left in the position where the plug will be formed last. That is, at this stage, there are all possible plugs in the form of hardmask plugs. The patterning operation of FIG. 11K acts to remove all portions of hardmask 1124 except those selected for plug retention. The patterning effectively exposes substantially upper portions of ILD lines 1120 and 1128, eg, as a unified dielectric layer.

11L illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 11K subsequent to mask removal and metal line trench etching, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b), taken along axes a-a' and bb', respectively, the mask 1138 shown in FIG. 11K is patterned at the via locations was later removed. Thereafter, partial etching of the exposed portions of ILD lines 1120 and 1128 is performed to provide recessed ILD lines 1120' and 1128'. The degree of recessing can be based on the timing of the etching process, such as the depth for the desired metal line thickness. The portion of ILD line 1120 protected by the remaining portion of hardmask 1124 is not recessed by etching, as shown in FIG. 11L. In addition, material layer 1134, which may be a sacrificial material or permanent ILD material, is also not etched or recessed. It should be understood that the process shown in FIG. 11L does not require a lithography operation because the via locations (on the exposed portions of the metal lines 1102) have been etched and plugged (on the locations where the hard mask 1124 was left).

11M illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 11L subsequent to metal line deposition and polishing, in accordance with an embodiment of the present invention. With reference to plan views and corresponding cross-sectional views (a) and (b), taken along axes a-a' and bb', respectively, the metal used to form the metal interconnects is conformally formed in the Above the structure of Figure 11L. The metal is then planarized (eg, by CMP) to provide metal lines 1140 . The metal lines are coupled to the underlying metal lines through predetermined via locations and isolated by the remaining plugs 1142 and 1144 . Metal (eg, copper and associated barrier and seed layers) deposition and planarization processes may be those of standard BEOL dual damascene processing. It should be understood that in subsequent fabrication operations, the material layer lines 1134 may be removed to provide air gaps between the resulting metal lines 1140 .

The structure of FIG. 11M can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of FIG. 11M may represent the final metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations may be performed in alternate orders, not every operation needs to be performed and/or additional process operations may be performed. Furthermore, while the above process flow is focused on the application of Directed Self-Aggregation (DSA), the selective growth process may alternatively be used at one or more locations in the process flow. In any case, the resulting structure enables the fabrication of vias which are directly focused on the underlying metal lines. That is, the vias may be wider, narrower, or the same thickness as the underlying metal lines, eg, due to a non-perfect selective etch process. However, in one embodiment, the centers of the vias are directly aligned (matched) with the centers of the metal lines. As such, in one embodiment, variations due to conventional lithography/damascene patterning (which would otherwise be tolerated) do not factor into the resulting structures described herein.

According to an embodiment of the present invention, the three-block self-aligned DSA is described in a bottom-up manner. One or more of the embodiments described herein relate to triblock copolymers of self-aligned vias or contacts. By using more advanced block copolymers and directed self-polymerization strategies, alignment for the underlying tight metal layer can be achieved. The embodiments described herein can be implemented to improve cost, scalability, pattern layout errors, and variability.

In general, one or more of the embodiments described herein relate to the use of three phases of a three-block copolymer material to achieve phase separation as a "self-aligned light barrel", eg, to generate aligned light The use of barrel self-aligned triblock copolymers is described. Additional embodiments for the manufacture and use of light barrels are described in more detail below, in embodiments beyond the current embodiment of FIGS. 12A-12K. However, it should also be understood that embodiments are not limited to the concept of a light barrel, but have broad application to structures having pre-formed features fabricated using bottom-up and/or directed self-aggregation (DSA) approaches.

FIGS. 12A-12C illustrate oblique cross-sectional views representing various operations in a method of using triblock copolymers to form self-aligned vias or contacts for back end of line (BEOL) interconnects, in accordance with the present invention. Example.

Referring to FIG. 12A , a semiconductor structure layer 1200 has a grating pattern of alternating metal lines 1202 and interlayer dielectric (ILD) lines 1204 . The structure 1200 can be handled with a first molecular brushing operation (i) of the first molecular species 1206 . Structure 1200 may also be disposed of with a second molecular brush operation (ii) of second molecular species 1208 . It should be understood that the order of operations (i) and (ii) may be reversed, or may even be performed at substantially the same time.

Referring to FIG. 12B , a molecular brushing operation may be performed to modify or provide a derived surface to alternating metal lines 1202 and ILD lines 1204 . For example, the surface of the metal line 1202 can be treated to have an A/B surface 1210 on the metal line 1202. The surface of the ILD line 1204 can be treated to have a C-surface 1212 on the ILD line 1204 .

Referring to Figure 12C, the structure of Figure 12B may be processed in a processing operation (iii) involving the application of a three-block block copolymer (three-block BCP) 1214, and possibly subsequent separation processing, to form a separate structure 1220 . The split structure 1220 includes a first region 1222 over the ILD line 1204 that splits the three-block BCP. Alternating second regions 1224 and third regions 1226 separating the three-block BCP are located above metal line 1202 . The final configuration of the three blocks of the triblock 1214 is according to chemical epitaxy, since only the underlying pattern (and not the coplanar pattern, as used in Figure Epitaxy) is used to orient the polymerization of the triblock 1214 to form the separation structure 1220 .

Referring collectively to Figures 12A-12C, in one embodiment, a structure 1220 for directional self-polymerization of back end of line (BEOL) semiconductor structure metallization layers includes a substrate (not shown, but described below, and should be understood to be low on ILD line 1204 and metal line 1202). The lower metallization layer includes its alternating metal lines 1202 and dielectric lines 1204 disposed over the substrate. A three-block copolymer layer 1214 is disposed over the lower metallization layer. The three-block copolymer layer includes its first discrete block components 1222 disposed over the dielectric lines 1204 of the lower metallization layer. The three-block copolymer layer includes its alternating second 1224 and third 1226 separate block components disposed over the dielectric lines 1202 of the lower metallization layer.

In one embodiment, the third discrete block 1226 component of the three-block copolymer layer 1214 is light sensitive. In one embodiment, the three-block copolymer layer 1214 is formed to a thickness in the range of about 5-100 nanometers. In one embodiment, the triblock copolymer layer 1214 includes a triblock copolymer species selected from the group consisting of any three of the following: polystyrene and other polyvinyl arylenes, polyisoprene and other polyolefins, polymethacrylates and other polyesters, polydimethylsiloxane (PDMS) and related silicon-based polymers, polyferrocene silane, polyethylene oxide (PEO) and related Polyether and polyvinylpyridine. In one embodiment, the alternating second 1224 and third 1226 separate block components have a ratio of about 1:1, as depicted in Figure 21C (and as described below in connection with Figure 12H). In another embodiment, the alternating second 1224 and third 1226 split block elements have a ratio of X:1, the second split block element 1224 relative to the third split block element 1226, where X is greater than 1, and The third separation block element 1226 has a columnar structure surrounded by the second separation block element, as described below in connection with FIG. 12I . In another embodiment, the three-block copolymer layer 1214 is a blend of homopolymers of A, B, and/or C or two-block BCP of A-B, B-C, or A-C components to obtain the desired morphology.

In one embodiment, the structure 1220 further includes its first molecular brush layer 1212 disposed on the dielectric lines 1204 of the lower metallization layer. In this embodiment, the first separation block component 1222 is disposed on the first molecular brush layer. In one embodiment, the structure 1220 also includes its second (different) molecular brush layer 1210 disposed on the metal lines 102 of the lower metallization layer. Alternating second 1224 and third 1226 separate block components are disposed on the second molecular brush layer 1210 . In one embodiment, the first molecular brush layer 1212 includes a molecular species 1208 including a molecular species 1208 selected from the group consisting of -SH, _-PO3H2 , _-CO2H , _-NRH , -NRR', and -Si(OR) ₃ and the second molecular brush layer 1210 includes molecular species 1206 comprising molecules having a group selected from the group consisting of -SH, _-PO3H2 , _-CO2H , _-NRH , -NRR ', and the polymethyl methacrylate of the head group of the group consisting of -Si(OR) ₃ .

In one embodiment, the alternating metal lines 1202 and dielectric lines 1204 of the lower metallization layer have a grating pattern that includes a constant pitch. In one embodiment, the third discrete block element 1226 of the three-block copolymer layer 1214 defines all possible via locations for the metallization layer above the lower metallization layer. In one embodiment, the third discrete block component 1226 of the three-block copolymer layer 1214 is photosensitive to extreme ultraviolet (EUV) sources or electron beam sources.

12D illustrates an oblique cross-sectional view representing operation in a method of using triblock copolymers to form self-aligned vias or contacts for back end of line (BEOL) interconnects, in accordance with an embodiment of the present invention.

Referring to Figure 12D, all portions of the third split block element 1226 of the structure 1220 of Figure 12C are removed. In one such embodiment, removal of all portions of the third split block assembly 1226 opens up all possible via locations where it can be formed over the underlying metallization layer. The openings can be filled with a photoresist layer to ultimately allow selection of only those via location requirements for a particular design. It should be understood that in the case of FIG. 12D, the third split block element 1226 of the structure 1220 may be (but need not be) light sensitive, as the third split block element 1226 of the structure 1220 of FIG. 12C may be individually selected by Etching is performed selectively (eg, selectively for the first split block element 1222 and for the second split block element 1224). In one such embodiment, selective etching may be performed using selective dry etching or selective wet etching (or both).

12E illustrates an oblique cross-sectional view showing operation in another method of using triblock copolymers to form self-aligned vias or contacts for back end of line (BEOL) interconnects, according to another aspect of the present invention Example.

Referring to Figure 12E, only selected portions of the third split block element 1226 of the structure 1220 of Figure 12C are removed. In one such embodiment, removal of only selected portions of the third split block assembly 1226 opens only those via locations above the underlying metallization layer required for a particular design. It should be understood that in the case of FIG. 2E, the third discrete block element 1226 of the structure 1220 is photosensitive, and location selection is performed using a localized, but highly tolerant, lithographic exposure. This exposure can be described as resistant because adjacent materials 1222 and 1224 adjacent location 1226 (in one embodiment) are not photosensitive to the lithography used to select locations for the removed portion of component 1226.

12F illustrates a triblock copolymer used to form self-aligned vias or contacts for back end of line (BEOL) interconnects, in accordance with an embodiment of the present invention.

Referring to FIG. 12F , the split three-block BCP 1250 may be divided into sections 1222 , 1224 , 1226 along axis 1252 . It should be understood that other split configurations may be possible, such as asymmetrical configurations. In one embodiment, there is an etch selectivity between components 1222, 1224, and 1226, which may be as large as a 10:1 etch selectivity for one component relative to the other two. In one embodiment, the use of three-block BCP 1250 may improve pattern fidelity and reduce critical dimension (CD) variation. In one embodiment, a split three-block BCP 1250 may be implemented to enable a self-alignment strategy that complements a 193 nm immersion lithography (193i) or extreme ultraviolet lithography (EUVL) process.

It should be understood that in general, the blocks of the triblock copolymer can each have different chemical properties. For example, one of the blocks can be relatively hydrophobic (eg, water repellent) and the other two blocks can be relatively hydrophilic (water absorbent), or vice versa. At least conceptually, one of the blocks can be relatively oil-like and the other two blocks can be relatively water-like, or vice versa. Such differences in chemical properties between different block polymers (whether hydrophilic-hydrophobic differences or otherwise) may cause the block copolymer molecules to self-polymerize. For example, self-polymerization can be based on microphase separation of polymer blocks. Conceptually, this can be analogous to the phase separation of oil and water, which are generally immiscible.

Similarly, differences in hydrophilicity between polymer blocks can result in roughly similar microphase separations, where different polymer blocks try to "separate" from each other because they don't like each other chemically. However, in one embodiment, because the polymer blocks are covalently bonded to each other, they cannot be completely separated on a macroscopic scale. Conversely, a polymer block of a given type may tend to separate or aggregate in extremely small (eg, nanoscale) regions or phases from polymer blocks of other molecules of the same type. The particular size and shape of the domains or microphases generally depends, at least in part, on the relative lengths of the polymer blocks. In one embodiment, Figures 12C, 12H, and 12I depict possible polymerization schemes for triblock copolymers, for example.

It should be understood that the pattern used to open the pre-formed via or plug locations can be formed to be relatively small, enabling an increase in the overlap tolerance of the lithography process. The pattern features can be made of uniform size, which can reduce the scan time of the direct-write electron beam and/or the complexity of Optical Proximity Correction (OPC) using optical lithography. Pattern features can also be formed shallow, which can improve patterning resolution. The etching process performed subsequently may be an isotropic chemical selective etching. Such an etch process alleviates the otherwise associated profile and critical dimensions, and alleviates anisotropy problems typically associated with dry etch methods. This etch process is also relatively much cheaper (from an equipment and yield point of view) compared to other selective removal methods.

The following describes portions of integrated circuit layers that represent various operations in a method of self-aligned vias and metal patterning. In particular, Figures 12G and 12H illustrate plan views and corresponding cross-sectional views representing each of a method of using triblock copolymers to form self-aligned vias or contacts for back end of line (BEOL) interconnects operation, in accordance with embodiments of the present invention.

12G illustrates a plan view and a corresponding cross-sectional view taken along the a-a' axis for a selection of front-level metallization structures, in accordance with an embodiment of the present invention. Referring to plan view and corresponding cross-sectional view option (a), starting structure 1260 includes a pattern of metal lines 1262 and interlayer dielectric lines (ILD) 1264 . The starting structures 1260 may be patterned into a grating-like pattern, with metal lines spaced at a constant pitch and of constant width, as depicted in Figure 12G, with the self-polymerizing material being finally formed. In the case of cross-sectional view (a), metal lines 1262 and interlayer dielectric (ILD) lines 1264 are coplanar with each other. Certain lines may be associated with underlying vias, such as line 1262' shown in one example of the cross-sectional view.

Referring again to FIG. 12G, alternative options (b)-(f) are discussed in which an additional film (eg, deposited, grown, or leaving artifacts as left over from the previous patterning process). In example (b), an additional film 1266 is disposed on the interlayer dielectric line 1264 . In example (c), the additional film 1268 is disposed on the metal line 1262 . In example (d), the additional film 1266 is disposed on the interlayer dielectric line 1264 , and the additional film 1268 is disposed on the metal line 1262 . Also, although the metal lines 1262 and the interlayer dielectric lines 1264 are described as coplanar in (a), in other embodiments, they may be non-coplanar. For example, in (e), the metal lines 1262 protrude over the interlayer dielectric lines 1264 . In example (f), the metal lines 1262 are recessed under the interlayer dielectric lines 1264 .

Referring again to examples (b)-(d), additional layers (eg, layers 1266 or 1268) may be used as hard masks (HM) or protective layers or to enable self-polymerization as described below in connection with subsequent processing operations. These additional layers can also be used to protect the ILD from further processing. Furthermore, selectively depositing another material over the metal lines may be advantageous for similar reasons. Referring again to examples (e) and (f), ILD lines or metal lines can also be recessed by any combination of protective/HM materials on either or both surfaces. In summary, there are several options at this stage to prepare the final underlying surface for the directional self-polymerization process.

Referring to Figure 12H, a triblock copolymer layer 1270 is formed on the structure of Figure 12G (eg, plan view of cross-sectional structure (a)). The triblock copolymer layer 1270 is separated to have regions 1272 formed over the ILD lines 1264 , and to have alternating second and third regions 1274 and 1276 formed over the metal lines 1262 .

Referring to the cross-sectional view along the b-b' axis of FIG. Also shown between the first region 1272 and the ILD line 1264 is a layer 1280, which may be the remainder of the molecular brush layer, according to one embodiment. However, it should be understood that layer 1280 may not be present. According to one embodiment, the third region 1276 is shown formed directly on the metal line 1262 . However, it should be understood that the residue of the molecular brush layer may be between the third region 1276 and the metal line 1262 .

Referring to the cross-sectional view along the c-c' axis of FIG. Also shown between the first region 1272 and the ILD line 1264 is a layer 1280, which may be the remainder of the molecular brush layer, according to one embodiment. However, it should be understood that layer 1280 may not be present. Also shown between the second region 1274 and the metal line 1262 is a layer 1282, which may be the remainder of the molecular brush layer, according to one embodiment. However, it should be understood that layer 1282 may not be present. It should also be understood that region 1276 may be formed to be light sensitive or may be replaced with a light sensitive material.

Thus, in one embodiment, the underlying metal and ILD grids are regenerated in block copolymer (BCP). This may especially be the case if the BCP pitch is comparable to the underlying grating pitch. The polymer grid, in one embodiment, is robust to some small deviation from a very properly aligned grid. For example, a substantially well-aligned block copolymer grid can still be achieved if the small plugs are effectively provided with materials such as oxides (where a well-aligned grid would have metal).

In one embodiment, referring again to Figure 12H, the thickness of the coated triblock copolymer layer 1270 is approximately the same (or slightly thicker) than the final thickness of the ILD that is ultimately formed in its place. In one embodiment, as described in more detail below, the polymer grid is not formed as an etch resist, but as a scaffold around which to eventually grow a permanent ILD layer. As such, the thickness of the three-block copolymer layer 1270 may be important as it may be used to define the final thickness of the subsequently formed permanent ILD layer. That is, in one embodiment, the polymer grating shown in Figure 12H is eventually replaced with an ILD/wire grating of approximately the same thickness.

In one embodiment, the three-block copolymer layer 1270 molecules are polymer molecules formed from chains of covalently bonded monomers. In a three-block copolymer, there are three different types of monomers, and these different types of monomers are mainly included in two different blocks or adjacent sequences of monomers. In one embodiment, the three-block copolymer layer 1270 is first applied as part of an unpolymerized block copolymer layer comprising block copolymer material applied, for example, by brushing or other coating process . The unpolymerized form refers to where (at the time of deposition) the block copolymer has not substantially phase-separated and/or self-polymerized to form nanostructures. In this unpolymerized form, the block polymer molecules are rather highly randomized, with distinct polymer blocks oriented and positioned relatively highly randomly, as opposed to the aggregated tri-blocks discussed in conjunction with the resulting structure of Figure 12H Block copolymer layer 1270. The unpolymerized block copolymer layer portion can be applied in a number of different ways. For example, the block copolymer can be dissolved in a solvent and then spin coated onto a surface. Alternatively, the unpolymerized block copolymer may be sprayed, dipped, dipped, or otherwise coated or applied to the surface. Other ways of applying the block copolymer, as well as other ways known in the art for applying similar organic coatings, can potentially be used. The unpolymerized layer can then form portions of the polymerized block copolymer layer, eg, by microphase separation and/or self-polymerization of the unpolymerized block copolymer layer portion. Microphase separation and/or self-polymerization occurs through the reconfiguration and/or repositioning of the block copolymer molecules, and in particular the reconfiguration and/or repositioning of the different polymer blocks of the block copolymer molecules to A three-block copolymer layer 1270 is formed.

In this embodiment, an annealing treatment may be applied to the unpolymerized block copolymer to initiate, accelerate, increase, or enhance the quality of microphase separation and/or self-polymerization to form the three-block copolymer layer 1270 . In certain embodiments, the annealing treatment may include a treatment operable to increase the temperature of the block copolymer. An example of such a treatment is baking the layer, heating the layer in an oven or over a heat lamp, applying infrared radiation to the layer, or applying heat to the layer or increasing the temperature of the layer. The desired temperature increase will generally be sufficient to significantly accelerate the microphase separation and/or self-polymerization of the block polymer without damaging the block copolymer or any other important materials or structures of the integrated circuit substrate. Typically, the heating range can be from about 50°C to about 300°C, or from 75°C to about 250°C, without exceeding the thermal degradation limits of the block copolymer or integrated circuit substrate. Heating or annealing can help provide energy to the block copolymer molecules to make them more mobile/elastic to increase the rate and/or quality of microphase separation. This microphase separation or reconfiguration/repositioning of block copolymer molecules can result in self-polymerization to form extremely small (eg, nanoscale) structures. Self-polymerization can occur under the influence of forces such as surface tension, molecular likes and dislikes, and other surface-related and chemical-related forces.

In any event, in certain embodiments, self-polymerization of block copolymers (whether by virtue of hydrophobic-hydrophilic differences or not) can be used to form extremely small periodic structures (eg, precisely spaced nanoscale structures or line), in the form of a three-block copolymer layer 12720. In some embodiments, it can be used to form nanoscale wires or other nanoscale structures that can ultimately be used to form via openings. In certain embodiments, directional self-polymerization of block copolymers can be used to form vias that are self-aligned with interconnects, as described in more detail below.

It should be understood that the two components of the triblock copolymer structure which are formed over the metal lines need not have a 1:1 ratio (the 1:1 ratio is shown in Figures 12C and 12H). For example, the third separation block assembly may be present in a smaller amount than the second assembly and may have a columnar structure surrounded by the second separation block assembly. Figures 12I-12L illustrate plan views and corresponding cross-sectional views representing various operations in a method of using triblock copolymers to form self-aligned vias or contacts for back end of line (BEOL) interconnects, according to Embodiments of the present invention.

Referring to FIG. 12I , the plan view and corresponding cross-sectional view taken along the d-d' axis show a smaller amount of the third component 1276 than the second component 1274. The third separation block assembly 1276 has a columnar structure surrounded by the second separation block assembly 1274 .

Referring to Figure 12J, a plan view shows that lithography 1290 selections of some 1292 of the third split block components 1276 are performed to ultimately provide via locations for the upper metallization structures.

It should be understood that Figure 12I effectively illustrates the unexposed light-sensitive DSA structure, while Figure 12J illustrates the exposed light-sensitive DSA structure. In contrast to Figure 12H, Figures 12I and 12J show examples of columnar structures that can be formed when many blocks of copolymer molecules and polymers form a shorter block of one of the columnar structures (which is formed by having another polymer when the phase of the longer block surrounds) is aligned. In accordance with embodiments of the present invention, the photoactivatable properties of DSA structures provide the ability to effectively "insert" or "cut" one type of DSA polymer region using, for example, electron beam or EUV exposure.

Referring to Figure 12K, a plan view shows an exposed/chemically enlarged region 1294 in the exposed zone. For selectivity, the only effective modification is to the material of the exposed portion of the third split block assembly 1276. It should be understood that although shown as cleared in Figure 12K, the selected area may not have been cleared.

Referring to Figure 12L, a plan view and corresponding cross-sectional view taken along the e-e' axis are shown to provide cleared regions 1294 after lithographic development. The cleared area 1294 may ultimately be used for via formation.

The resulting patterned DSA structure of Figure 12L (or Figures 12C, 12D, 12E, or 12H) described above can ultimately be used as a scaffold from which the permanent layer is ultimately formed. That is, it may be the case that no DSA material is present in the final structure, but is used to direct the fabrication of the final interconnect structure. In one such embodiment, the permanent ILD replaces one or more regions of DSA material, and subsequent processing, such as wire fabrication, is completed. That is, it is possible that all DSA components are finally removed for final self-aligned via and plug formation. In other embodiments, at least some of the DSA material may remain in the final structure.

Referring again to FIGS. 12A-12C, 12G, 12H, and 12I-12L, in one embodiment, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer having alternating metal and dielectric lines on the base. A three-block copolymer layer is formed over the lower metallization layer. The three-block copolymer layers are separated to form first discrete block elements over the dielectric lines of the lower metallization layer, and to form alternating second and third discrete block elements disposed over the metal lines of the lower metallization layer . The third separation block assembly is light sensitive. The method also includes irradiating and developing selected locations of the third discrete block components to provide via openings over the metal lines of the lower metallization layer.

In one embodiment, the alternating second and third split block components have a ratio of about 1:1, as described in connection with Figures 12C and 12H. In another embodiment, the alternating second and third split block elements have a ratio of about X:1, the second split block element relative to the third split block element, wherein X is greater than one. In this embodiment, the third split block element has a columnar structure surrounded by the second split block element, as described in connection with Figure 12I.

In one embodiment, the method further includes: using the resulting patterned three-block copolymer layer as a scaffold to form a second stage subsequent to irradiating and developing selected locations of the third split block components to provide through-hole openings The alternating metal and dielectric lines are above, coupled to, and orthogonal to the first order of alternating metal and dielectric lines. In one embodiment, one or more components of the three-block copolymer layer are retained in the final structure. However, in other embodiments, all components of the three-block copolymer layer are ultimately sacrificial, since none of this material remains in the final product. An example embodiment of an implementation of the latter embodiment is described below in conjunction with FIG. 13 .

In one embodiment, the method further includes (before forming the triblock copolymer layer) forming a first molecular brush layer on the dielectric lines of the lower metallization layer, and forming a second (different) molecular brush layer on the lower metal layer 12A-12C, an exemplary embodiment of which is described above in conjunction with the metal lines of the ionization layer. In one embodiment, irradiating and developing selected locations of the third separation block element includes exposing the selected location of the third separation block element to an extreme ultraviolet (EUV) source or an electron beam source.

Provided only as an example of the final structure it can ultimately be obtained, FIG. 13 illustrates a plan view and corresponding cross-sectional view of the self-aligned via structure following the formation of metal lines, vias, and plugs, according to the present Examples of inventions. Referring to the plan view and corresponding cross-sectional views (a) and (b), taken along axes f-f' and g-g', respectively, upper level metal lines 1302 are provided with a dielectric frame (eg, on a dielectric layer 1304 and adjacent to dielectric line 1314). Metal line 1302 is coupled to underlying metal line 1262 through predetermined via locations (example 1306 of which is shown in cross-sectional view (a)) and is isolated by plugs (examples of which include plugs 1308 and 1310) . Lower lines 1262 and 1264 may be described above in connection with FIG. 12G , as formed to be normal to the direction of metal line 1302 . It should be understood that in subsequent fabrication operations, the dielectric lines 1314 may be removed to provide air gaps between the resulting metal lines 1302 .

The resulting structures, such as those described in connection with Figure 13, can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 13 may represent the final metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations may be performed in alternate orders, not every operation needs to be performed and/or additional process operations may be performed. In any case, the resulting structure enables the fabrication of vias which are directly focused on the underlying metal lines. That is, the vias may be wider, narrower, or the same thickness as the underlying metal lines, eg, due to a non-perfect selective etch process. However, in one embodiment, the centers of the vias are directly aligned (matched) with the centers of the metal lines. As such, in one embodiment, variations due to conventional lithography/damascene patterning (which would otherwise be tolerated) do not factor into the resulting structures described herein. It should be understood that the above examples have focused on via/contact formation. However, in other embodiments, a similar approach may be used to retain or form regions for wire terminations (plugs) within the metal line layers.

It should be understood that the processes described herein may be described as being primarily DSA-based (such as several of the process schemes described above), while others may be primarily etch-based. According to an embodiment of the present invention, a deep subtraction method is implemented in BEOL processing. One or more embodiments described herein relate to a subtractive approach for self-aligned via and plug patterning, and the resulting structures. In one embodiment, the procedures described herein enable the realization of self-aligned metallization for back-end-of-process feature fabrication. Overlap issues anticipated for the next generation of via and plug patterning may be addressed in one or more of the ways described herein. In general, one or more of the embodiments described herein involve using a subtractive method to preform each via and plug using etched trenches. An additional operation is then used to select which vias and plugs to keep.

14A-14N illustrate portions of integrated circuit layers that represent operations in a method of subtracting self-aligned vias and plugs patterning, in accordance with embodiments of the present invention. In each illustration describing the operation, an oblique three-dimensional cross-sectional view is provided.

FIG. 14A illustrates a starting point structure 1400 for a reduced via and plug process following deep metal line fabrication, in accordance with an embodiment of the present invention. Referring to FIG. 14A , structure 1400 includes metal lines 1402 with interlayer dielectric (ILD) lines 1404 . The ILD line 1404 includes a plug cap layer 1406 . In one embodiment, as described in more detail below in conjunction with FIG. 14E, the plug capping layer 1406 is later patterned to finally define all possible locations for subsequent plug formation.

In one embodiment, the grating structure formed by the metal lines 1402 is a close-pitch grating structure. In this embodiment, tight pitch cannot be achieved directly by conventional lithography. For example, a pattern according to conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask. Even, the original pitch can be reduced by a quarter by a second round of spacer mask patterning. Thus, the grating-like pattern of FIG. 14A may have metal lines of constant width separated by a constant pitch. Patterns can be made by halving the pitch or reducing the pitch by a quarter. It should also be understood that certain lines 1402 may be associated with underlying vias for coupling to previous interconnect layers.

In one embodiment, metal lines 1402 are formed by patterning trenches into an ILD material (eg, the ILD material of lines 1404 ) with plug capping layer 1406 formed thereon. The trenches are then filled with metal and, if necessary, planarized to the plug cap layer 1406 . In one embodiment, the metal trench and fill process involves high aspect ratio features. For example, in one embodiment, the aspect ratio of the metal line height (h) to the metal line width (w) is in the range of about 5-10.

14B illustrates the structure of FIG. 14A following the recess of the metal line, in accordance with an embodiment of the present invention. Referring to FIG. 14B , metal lines 1402 are selectively recessed to provide first-level metal lines 1408 . The recessing is selectively performed to the ILD line 1404 and the plug capping layer 1406 . The recessing can be performed by etching through dry etching, wet etching, or a combination thereof. The degree of recessing can be determined by the target thickness (th) of the first level metal lines 1408 for use as appropriate conductive interconnects within a back end of line (BEOL) interconnect structure.

FIG. 14C illustrates the structure of FIG. 14B after hardmask filling in the recessed area following the recessed metal line, in accordance with an embodiment of the present invention. Referring to FIG. 14C , a hard mask layer 1410 is formed in the region formed during recessing to form the first level metal lines 1408 . The hard mask layer 1410 may be formed to the level of the plug cap layer 1406 by material deposition and chemical mechanical planarization (CMP) processes, or by a controlled bottom-up-only growth process. In a particular embodiment, the hard mask layer 1410 is composed of a carbon-rich material.

14D illustrates the structure of FIG. 14C following deposition and patterning of a hard mask layer, in accordance with an embodiment of the present invention. Referring to FIG. 14D , a second hard mask layer 1412 is formed on or over the hard mask layer 1410 and the plug cap layer 1406 . In this embodiment, the second hard mask layer 1412 is formed with a grating pattern orthogonal to the grating pattern of the first order metal lines 1408/ILD lines 1404, as shown in FIG. 14D. In a specific embodiment, the second hard mask layer 1412 is composed of a silicon-based anti-reflective coating material. In one embodiment, the grating structure formed by the second metal lines 1412 is a tight-pitch grating structure. In this embodiment, tight pitch cannot be achieved directly by conventional lithography. For example, a pattern according to conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask, as is known in the art. Even, the original pitch can be reduced by a quarter by a second round of spacer mask patterning. Thus, the grating-like pattern of the second hard mask layer 1412 of FIG. 14D may have hard mask lines of constant width separated by a constant pitch.

14E illustrates the structure of FIG. 14D following the formation of trenches defined using the pattern of the hardmask of FIG. 14D, in accordance with an embodiment of the present invention. Referring to FIG. 14E , exposed regions of hard mask layer 1410 and plug cap layer 1406 (ie, those not protected by 1412 ) are etched to form trenches 1414 . The etch stops on (and thus exposes) the top surfaces of the first level metal lines 1408 and ILD lines 1404 .

14F illustrates the structure of FIG. 14E following ILD formation in the trenches of FIG. 14E and removal of the second hard mask, in accordance with an embodiment of the present invention. Referring to Figure 14F, a second ILD line 1416 is formed in the trench 1414 of Figure 14E. In one embodiment, flowable ILD material is used to fill the trenches 1414 . In one embodiment, the trenches 1414 are filled and the fill material is then planarized. Planarization can further be used to remove the second hard mask layer 1412, re-exposing the hard mask layer 1410 and the plug cap layer 1406, as shown in Figure 14F.

Referring again to FIG. 14F, in one embodiment, the resulting structure includes a uniform ILD structure (ILD line 1404+ILD line 1416). All possible plug locations are occupied by the remainder of the plug cap layer 1406 , and all possible via locations are occupied by the remainder of the hard mask layer 1410 . In this embodiment, ILD line 1404 and ILD line 1416 are composed of the same material. In another such embodiment, ILD line 1404 and ILD line 1416 are composed of different ILD materials. In either case, in a particular embodiment, differences such as a seam between the materials of ILD wire 1404 and ILD wire 1416 may be observed in the final structure. Furthermore, in one embodiment, there is no distinct etch stop layer where ILD lines 1404 meet ILD lines 1416, unlike conventional single or dual damascene patterning.

14G illustrates the structure of FIG. 14F following removal of the remainder of the hard mask layer that occupies all possible via locations, in accordance with an embodiment of the present invention. Referring to Figure 14G, the remainder of the hard mask layer 1410 is selectively removed to form openings 1418 for all possible via locations. In this embodiment, the hard mask layer 1410 consists essentially of carbon and is selectively removed by an ash process.

In general, one or more of the embodiments described herein involve using a subtractive method to preform each via and plug using etched trenches. An additional operation is then used to select which vias and plugs to keep. These operations can be illustrated using "light barrels", although a more traditional resist exposure and ILD backfill approach can also be used to perform the selection process. It should also be understood that embodiments are not limited to the concept of light barrels, but have broad application to structures having pre-formed features fabricated using bottom-up and/or directed self-aggregation (DSA) approaches. Additional embodiments for the manufacture and use of light barrels are described in more detail below, in embodiments beyond the current embodiments of FIGS. 14A-14N and 15A-15D.

Figure 14H illustrates the structure of Figure 14G following the formation of photobarrels in all possible via locations, in accordance with an embodiment of the present invention. Referring to Figure 14H, photo barrels 1420 are formed in all possible via locations over exposed portions of the first level metal lines 1408. In one embodiment, the openings 1418 of Figure 14G are filled with ultra-high speed photoresist or e-beam resist or other photosensitive material. In this embodiment, thermal backfill of polymer into openings 1418 is used following spin-on application. In one embodiment, fast photoresists are fabricated by removing inhibitors from existing photoresist materials. In another embodiment, the photo barrel 1420 is formed by an etch-back process and/or a lithography/reduction/etch process. It should be understood that the photobucket need not be filled with actual photoresist, so long as the material acts as a photoswitch.

Figure 14I illustrates the structure of Figure 14H following via location selection, in accordance with an embodiment of the present invention. Referring to FIG. 14I, the light barrel 1420 from FIG. 14H is removed when the via location is selected. In locations where the vias are not selected to be formed, the light barrel 1420 is retained, converted to permanent ILD material, or replaced with permanent ILD material. For example, FIG. 14I illustrates via locations 1422 with corresponding photo barrels 1420 removed to expose a portion of one of the first level metal lines 1408 . The other location previously occupied by light barrel 1420 is now shown as area 1424 in Figure 14I. Location 1424 was not selected for via formation and instead forms part of the final ILD structure. In one embodiment, the light barrel 1420 material is retained in location 1424 as the final ILD material. In another embodiment, the material of the photobarrel 1420 is modified (eg, by cross-linking) in location 1424 to form the final ILD material. In yet another embodiment, the material of the light barrel 1420 in position 1424 is replaced with the final ILD material.

Referring again to FIG. 14I, to form the via locations 1422, lithography is used to expose the corresponding photo barrels 1420. However, lithography constraints can be relaxed and misalignment tolerances can be high because the photobarrel 1420 is surrounded by non-photolyzable material. Also, in one embodiment, instead of exposing at, eg, 30 mJ/cm ² , such a photobarrel can be exposed at, eg, 3 mJ/cm ² . Typically this will result in very poor CD control and roughness. But in this example, the CD and roughness control will be defined by the light barrel 1420, which can be well controlled and defined. Therefore, the photobucket approach can be used to prevent imaging/dose tradeoffs that limit the throughput of next-generation lithography processes.

Referring again to Figure 14I, in one embodiment, the resulting structure includes a uniform ILD structure (ILD 1424+ILD line 1404+ILD line 1416). In this embodiment, both or all of ILD 1424, ILD line 1404, and ILD line 1416 are composed of the same material. In another such embodiment, ILD 1424, ILD line 1404, and ILD line 1416 are composed of different ILD materials. In either case, in a particular embodiment, a seam (eg, seam 1497) between the materials of the ILD 1424 and the ILD wire 1404 and/or between the ILD 1424 and the ILD wire 1404 is observed in the final structure. Seams (eg, seams 1498 ) etc. are distinguished between the materials of the ILD wire 1416 .

14J illustrates the structure of FIG. 14I following hardmask filling in the opening of FIG. 14I, in accordance with an embodiment of the present invention. Referring to FIG. 14J , a hard mask layer 1426 is formed in via locations 1422 and over ILD locations 1424 . The hard mask layer 1426 may be formed by deposition and subsequent chemical mechanical planarization.

14K illustrates the structure of FIG. 14J following removal of the plug cap layer and formation of a second plurality of photo barrels, in accordance with an embodiment of the present invention. Referring to Figure 14K, the plug cap layer 1406 is removed, eg, by a selective etch process. Photo barrels 1428 are then formed in all possible plug locations over exposed portions of the ILD lines 1404 . In one embodiment, the openings formed upon removal of the plug cap layer 1406 are filled with ultra-high-speed photoresist or e-beam resist or other photosensitive material. In this embodiment, thermal backfill of the polymer into the opening is used subsequent to spin-on application. In one embodiment, fast photoresists are fabricated by removing inhibitors from existing photoresist materials. In another embodiment, the photo barrel 1428 is formed by an etch back process and/or a lithography/reduction/etch process. It should be understood that the photobucket need not be filled with actual photoresist, so long as the material acts as a photoswitch.

14L illustrates the structure of FIG. 14K following plug location selection, in accordance with an embodiment of the present invention. Referring to Figure 14L, the light barrel 1428 from Figure 14K is removed not in the select plug position. In the position where the plug is selected to be formed, the light barrel 1428 is retained, converted to permanent ILD material, or replaced with permanent ILD material. For example, FIG. 14L illustrates a non-plug position 1430 with the corresponding photobarrel 1428 removed to expose a portion of the ILD line 1404 . The other location previously occupied by light barrel 1428 is now shown as area 1432 in Figure 14L. Region 1432 is selected where the plug is formed and forms part of the final ILD structure. In one embodiment, the material of the corresponding photobarrel 1428 is retained in region 1432 as the final ILD material. In another embodiment, the material of photobarrel 1428 is modified (eg, by cross-linking) in region 1432 to form the final ILD material. In yet another embodiment, the material of the light barrel 1428 in region 1432 is replaced with the final ILD material. In any event, region 1432 may also be referred to as plug 1432.

Referring again to FIG. 14L, to form openings 1430, lithography is used to expose corresponding photo barrels 1428. However, lithography constraints can be relaxed and misalignment tolerances can be high because the photobarrel 1428 is surrounded by non-photolyzable material. Also, in one embodiment, instead of exposing at, eg, 30 mJ/cm ² , such photobarrels can be exposed at, eg, 3 mJ/cm ² . Typically this will result in very poor CD control and roughness. But in this example, the CD and roughness control would be defined by the light barrel 1428, which can be well controlled and defined. Therefore, the photobucket approach can be used to prevent imaging/dose tradeoffs that limit the throughput of next-generation lithography processes.

Referring again to FIG. 14L, in one embodiment, the resulting structure includes a uniform ILD structure (plug 1432+ILD 1424+ILD line 1404+ILD line 1416). In this embodiment, two or more of plug 1432, ILD 1424, ILD line 1404, and ILD line 1416 are composed of the same material. In another such embodiment, plug 1432, ILD 1424, ILD line 1404, and ILD line 1416 are composed of different ILD materials. In either case, in a particular embodiment, a seam such as a seam (eg, seam 1499 ) between the material of the plug 1432 and the ILD wire 1404 and/or between the plug is observed in the final structure The seam (eg, seam 1496) etc. is distinguished between the material of 1432 and ILD wire 1416.

14M illustrates the structure of FIG. 14L following the removal of the hard mask of FIG. 14L, in accordance with an embodiment of the present invention. Referring to FIG. 14M , hard mask layer 1426 is selectively removed to form metal lines and via openings 1434 . In this embodiment, the hard mask layer 1426 consists essentially of carbon and is selectively removed by an ash process.

14N illustrates the structure of FIG. 14M following the formation of metal lines and vias, in accordance with an embodiment of the present invention. Referring to Figure 14N, metal lines 1434 and vias (shown as one of 1438) are formed on the metal fill of opening 1434 of Figure 14M. Metal lines 1436 are coupled to underlying metal lines 1408 by vias 1438 and interrupted by plugs 1432. In one embodiment, openings 1434 are filled in a damascene manner, wherein metal is used to overfill the openings and then planarized back to provide the structure shown in Figure 14N. Thus, the metal (eg, copper and associated barrier and seed layers) deposition and planarization processes used to form the metal lines and vias in the manner described above may be typically used for standard back-end-of-line (BEOL) single or dual damascene processor. In one embodiment, in subsequent fabrication operations, the ILD lines 1416 may be removed to provide air gaps between the resulting metal lines 1436 .

The structure of Figure 14N can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 14N may represent the last metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations may be performed in alternate orders, not every operation needs to be performed and/or additional process operations may be performed. In any case, the resulting structure enables the fabrication of vias which are directly focused on the underlying metal lines. That is, the vias may be wider, narrower, or the same thickness as the underlying metal lines, eg, due to a non-perfect selective etch process. However, in one embodiment, the centers of the vias are directly aligned (matched) with the centers of the metal lines. Furthermore, the ILD used to select which plugs and vias will likely be very different from the main ILD and will be highly self-aligned in both directions. As such, in one embodiment, deviations due to conventional lithography/damascene patterning (which would otherwise be tolerated) do not factor into the resulting structures described herein. Referring again to Figure 14N, this stage can then be completed by means of subtractive self-aligned fabrication. Fabricating the next layer in a similar manner may involve performing the above process again. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

The process flow described above involves the use of deep trench etching. In another form, a shallower approach involves plug-only self-aligned subtractive processing techniques. For example, FIGS. 15A-15D illustrate portions of an integrated circuit layer that represent operations in a method of subtracting self-aligned plug patterning, in accordance with another embodiment of the present invention. In each illustration of each of the described operations, the plan view is shown at the top and the corresponding cross-sectional view is shown at the bottom. These views will be referred to herein as the corresponding cross-sectional and plan views.

15A illustrates a plan view and a corresponding cross-sectional view for an initial plug grid, in accordance with an embodiment of the present invention. Referring to plan views and corresponding cross-sectional views (a) and (b) taken along axes a-a' and bb', respectively, starting plug grid structure 1500 includes an ILD layer 1502 having a first hard The mask layer 1504 is disposed thereon. The second hard mask layer 1508 is disposed on the first hard mask layer 1504 and is patterned to have a grating structure. The third hard mask layer 1506 is disposed on the second hard mask layer 1508 and on the first hard mask layer 1504 . In addition, openings 1510 remain between the grating structures of the second hard mask layer 1508 and the third hard mask layer 1506 .

15B illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 15A subsequent to photobarrel filling, exposure, and development, in accordance with an embodiment of the present invention. With reference to plan views and corresponding cross-sectional views (a) and (b) taken along axes a-a' and b-b', respectively, a light barrel 1512 is formed in opening 1510 of Figure 15A. Afterwards, selected photo barrels are exposed and removed to provide selected plug locations 1514, as shown in Figure 15B.

15C illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 15B subsequent to plug formation, in accordance with an embodiment of the present invention. With reference to plan views and corresponding cross-sectional views (a) and (b) taken along axes a-a' and b-b', respectively, plugs 1516 are formed in openings 1514 of Figure 15B. In one embodiment, the plugs 1516 are formed by spin-on methods and/or deposition and etch-back methods.

15D illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 15C following removal of the hardmask layer and remaining photobucket, in accordance with an embodiment of the present invention. Referring to the plan views and corresponding cross-sectional views (a) and (b) taken along axes a-a' and bb', respectively, the third hard mask layer 1506 is removed, leaving the second hard mask layer Mask layer 1508 and plug 1516. The resulting pattern (second hard mask layer 1508 and plugs 1516 ) can then be used to pattern hard mask layer 1504 for final patterning of ILD layer 1502 . In one embodiment, the third hard mask layer 1506 consists essentially of carbon and is removed by performing an ash process.

Thus, the structure of Figure 15D can then be used as the basis for forming the ILD lines and plug patterns. It should be understood that the above-described process operations may be performed in alternate orders, not every operation needs to be performed and/or additional process operations may be performed. In any event, the resulting structure enables the fabrication of self-aligned plugs. As such, in one embodiment, variations due to conventional lithography/damascene patterning (which would otherwise be tolerated) do not factor into the resulting structures described herein.

In accordance with embodiments of the present invention, a dielectric helmet-based approach and/or a hardmask selectivity-based approach (and the resulting structure) for back-end-of-line (BEOL) are described. One or more embodiments described herein relate to methods of using a dielectric helmet for the fabrication of directed self-polymerization (DSA) or selective growth to enable self-aligned interconnects. Embodiments may explore or implement one or more of the use of dielectric helmets, directed self-polymerization, selective deposition, self-alignment, or close-pitch patterned interconnects. Embodiments may be implemented to provide improved via short tolerance by utilizing self-alignment by "coloring" through selective deposition, and subsequent directional self-polymerization (eg, for sub-10 nm technology nodes).

To provide context, current solutions to improve short circuit tolerance may include: (1) using metal recesses to fill alternating metal trenches with different hardmasks, (2) using different "color" metal caps to serve as Directed Self-Aggregation (DSA) or selectively grown templates, or (3) recessing the metal or ILD to "steer" the via towards the associated line. In general, typical process flows to improve via shorting tolerance require metal recesses. However, recessed metal with acceptable uniformity has proven to be a challenge in many of these processing schemes.

In accordance with embodiments of the present invention, one or more of the above-mentioned problems are solved by implementing a method of depositing a non-conformal dielectric cap over half the population of interconnects. Non-conformal dielectric caps are used as templates for selective growth or directed self-polymerization. In one such embodiment, this approach can be applied to any interconnect metal layer and (possibly) to the gate contacts. In certain embodiments, the need for metal undercuts as seen in the state-of-the-art approach is effectively eliminated from the processing schemes described herein.

As a general overview of the concepts involved in the text, FIGS. 16A-16D illustrate cross-sectional views of portions of integrated circuit layers representing a method involved in the formation of dielectric helmets for back-end-of-line (BEOL) interconnect fabrication. The respective operations are in accordance with the embodiments of the present invention.

Referring to Figure 16A, a starting point structure 1600 is provided as a starting point for fabricating a new metallization layer. The starting point structure 1600 includes a hard mask layer 1602 disposed on an interlayer dielectric (ILD) layer 1602 . As described below, the ILD layer may be disposed over the substrate and (in one embodiment) over the underlying metallization layer. Openings are formed in hard mask layer 1604 (which correspond to trenches formed in ILD layer 1602). A space between the trenches is filled with a conductive layer to provide a first metal line 1606 (and, in some cases, a corresponding conductive via 1607). The remaining trenches are left unfilled, which provides open trenches 1608 . In one embodiment, the starting structure 1600 is fabricated by patterning the hardmask and ILD layers and then metallizing half the total number of metal trenches (eg, one spaced between the trenches), leaving The other half of the total is open. In one embodiment, the trenches in the ILD are patterned using a pitch division patterning process flow. It should be understood that the following process operations described below may or may not involve pitch segmentation first. In either case, but especially when pitch segmentation is also used, embodiments may enable continuous scaling of the pitch of the metal layers beyond the resolution capabilities of state-of-the-art lithography equipment.

16B illustrates the structure of FIG. 16A following deposition of a non-conformal dielectric cap layer 1610 over structure 1600. The non-conformal dielectric cap layer 1610 includes a first portion 1600A that covers the exposed surfaces of the hard mask layer 1604 and the metal lines 1606 . The non-conformal dielectric cap layer 1610 includes a second portion 1610B connected to the first portion 1610A. A second portion 1610B of the non-conformal dielectric cap layer 1610 is formed in the open trench 1608 , along the sidewalls 1608A and the bottom 1608B of the open trench 1608 . In one embodiment, the second portion 1610B of the non-conformal dielectric cap layer 1610 is substantially thinner than the first portion 1610A, as depicted in Figure 16B. In other embodiments, portion 1610B is absent or discontinuous. In this manner, the deposition of the non-conformal dielectric cap layer 1610 is considered a non-conformal deposition because the thickness of the non-conformal dielectric cap layer 1610 is not the same in all locations. The resulting geometry may be referred to as a helmet shape for the non-conformal dielectric cap layer 1610 because the uppermost portion of the ILD layer 1602 has the thickest portion of the non-conformal dielectric cap layer 1610 thereon, and is thus protected to more than the other regions. to a large extent. In one embodiment, the non-conformal dielectric cap layer 1610 is a dielectric material such as, but not limited to, silicon nitride or silicon oxynitride. In one embodiment, the non-conformal dielectric cap layer 1610 is formed using a plasma enhanced chemical vapor deposition (PECVD) process or (in another embodiment) physical vapor deposition (PVD).

16C illustrates the structure of FIG. 16B after via patterning, metallization, and planarization following the second half of the metal lines. In one embodiment, a metal filling process is performed to provide the second metal lines 1612 . However, in one embodiment, via locations are first selected and opened prior to metal filling. Next, upon metal filling, vias 1613 are formed in association with some of the second metal lines 1612 . In one such embodiment, the via opening is formed by extending one of the trenches 1608 open, by etching through the non-conformal dielectric cap layer 1610 on the bottom of the selected trench 1608 and then extending The trench passes through the dielectric layer 1602 . The result is an interruption of the continuity of the non-conformal dielectric cap layer 1610 at the location of the via hole of the second metal line 1612, as depicted in Figure 16C.

In one embodiment, the metal filling process used to form the second metal lines 1612 and conductive vias 1613 is performed using metal deposition and subsequent planarization processing schemes, such as a chemical mechanical planarization (CMP) process. The planarization process exposes (but does not remove) the non-conformal dielectric cap layer 1610, as depicted in Figure 16C. It should be understood that in one embodiment, because the second metal line 1612 (and corresponding conductive via 1613 ) is formed later in the process than the process used to fabricate the first metal line 1606 (and corresponding conductive via 1607 ) Therefore, the second metal line 1612 may be fabricated using a different material than that used to fabricate the first metal line 1606. In one such embodiment, the metallization layer ultimately includes alternating conductive interconnects of different first and second compositions. However, in another embodiment, the metal lines 1612 and 1606 are fabricated from substantially the same material.

In one embodiment, the first metal lines 1606 are isolated by a pitch, and the second metal lines 1612 are isolated by the same pitch. In other embodiments, the lines are not necessarily separated by a pitch. However, by including the non-conformal dielectric cap layer 1610 (or dielectric helmet), only the surface of the second metal line 1612 is exposed. Therefore, the pitch between adjacent first and second metal lines to which they would otherwise be exposed is relaxed to the pitch of only the second metal line. Thus, the exposed dielectric surfaces of the alternating non-conformal dielectric cap layers 1610 and the exposed surfaces of the second metal lines 1612 provide distinct surfaces on the pitch of the second metal lines 1612 .

16D illustrates the structure of FIG. 16C following a directional self-polymerization or selective deposition approach to ultimately form two distinct (alternating) first and second hard mask layers 1614 and 1616 individually. In one embodiment, the materials of hard mask layers 1614 and 1616 exhibit different etch selectivities from each other. The first hard mask layer 1614 is aligned with the exposed regions of the non-conformal dielectric cap layer 1610 . The second hard mask layer 1616 is aligned with the exposed areas of the second metal lines 1612 . As described in more detail below, directed self-polymerization or selective growth may be used to selectively individually align the first and second hard mask layers 1614 and 1616 to the dielectric and metal surfaces.

In the first general embodiment, to finally form the first and second hard mask layers 1614 and 1616, directed self-polymerization (DSA) block copolymer deposition and polymer polymerization processes are performed. In one embodiment, the DSA block copolymer is coated on the surface and annealed to separate the polymer into first and second blocks. In one embodiment, the first polymer block preferentially adheres to the non-conformal dielectric cap layer 1610 . The second polymer block is adhered to the second metal line 1612 . In one embodiment, the block copolymer molecule is a polymer molecule formed from chains of covalently joined monomers, examples of which are described above.

Referring again to FIG. 16D, in the case of the DSA process, in the first embodiment, the first and second hard mask layers 1614 and 1616 are respectively the first and second block polymers. However, in the second embodiment, the first and second block polymers are replaced with the materials of the first and second hard mask layers 1614 and 1616, respectively. In one such embodiment, selective etching and deposition processes are used to replace the first and second blocks of polymer with the materials of the first and second hard mask layers 1614 and 1616, respectively.

In the second general embodiment, in order to finally form the first and second hard mask layers 1614 and 1616, a selective growth process is used instead of the DSA method. In one such embodiment, the material of the first hard mask layer 1614 is grown over the exposed portions of the underlying non-conformal dielectric cap layer 1610 . A second (different) material of the second hard mask layer 1616 is grown over the exposed portions of the underlying second metal lines 1612. In one embodiment, selective growth is achieved by a dep-etch-dep-etch approach to each of the first and second materials, resulting in each of the materials plural layers of the person. This approach may be ideal relative to conventional selective growth techniques which can form "mushroom top"-like membranes. Mushroom top film growth propensity can be reduced by an alternating deposition/etch/deposition (dep-etch-dep-etch) approach. In another embodiment, a film is selectively deposited over the metal, followed by a different film selectively deposited over the ILD (or vice versa), and repeated several times to create a sandwich-like stack. In another embodiment, the two materials are grown simultaneously in a reaction chamber (eg, by a CVD-style process) selectively grown on exposed regions of the underlying substrate.

As described in more detail below, in one embodiment, the resulting structure of Figure 16D enables improved via shorting tolerance when fabricating later via layers on the structure of Figure 16D. In one embodiment, improved short circuit tolerance is achieved because fabricating structures with alternating "color" hard masks reduces the risk of vias shorting to the wrong metal lines. In one embodiment, self-alignment is achieved because the alternating color hardmask is self-aligned to the underlying metal trenches. In one embodiment, the need for metal recesses is removed from the processing scheme because it reduces process variation.

In a first more detailed example process flow, FIGS. 16E-16P illustrate cross-sectional views of a portion of an integrated circuit layer representing another method involving the formation of dielectric helmets for back-end-of-line (BEOL) interconnect fabrication. The respective operations are in accordance with the embodiments of the present invention.

Referring to Figure 16E, a starting point structure 1630 is provided (following the first metallization through processing) as a starting point for fabricating a new metallization layer. The starting point structure 1630 includes a hard mask layer 1634 (eg, silicon nitride) disposed on the interlayer dielectric (ILD) layer 1632 . As described below, the ILD layer may be disposed over the substrate and (in one embodiment) over the underlying metallization layer. First metal lines 1636 (and, in some cases, corresponding conductive vias 1637 ) are formed in ILD layer 1632 . The protruding portion 1636A of the metal line 1636 has an adjacent dielectric spacer 1638 . A sacrificial hard mask layer 1640 (eg, amorphous silicon) is included between adjacent dielectric spacers 1638 . Although not depicted, in one embodiment, the metal lines 1636 are formed by first removing the second sacrificial hardmask material between the dielectric spacers 1638 and then etching the hardmask layer 1634 and the ILD layer 1632 ( It will be formed from the filled trenches during the metallization process.

FIG. 16F illustrates the structure of FIG. 16E following the second pass metal treatment until including trench etching. Referring to FIG. 16F , sacrificial hard mask layer 1640 is removed to expose hard mask layer 1634 . Exposed portions of hard mask layer 1634 are removed and trenches 1642 are formed in ILD layer 1632.

Figure 16G illustrates the structure of Figure 16F following the filling of the sacrificial material. Sacrificial material 1644 is formed in trenches 1642 and over spacers 1638 and metal lines 1636 . In one embodiment, the sacrificial material 1644 is formed in a spin-on process, leaving a substantially flat layer, as depicted in Figure 16G.

16H illustrates the structure of FIG. 16G following a planarization process to re-expose hard mask layer 1634, to remove dielectric spacers 1638, and to remove protrusions 1636A of metal lines 1636. FIG. In addition, the planarization process confines the sacrificial material 1644 to the trenches 1642 formed in the dielectric layer 1632. In one embodiment, the planarization process is performed using a chemical mechanical polishing (CMP) process.

Figure 16I illustrates the structure of Figure 16H following removal of the sacrificial material. In one embodiment, sacrificial material 1644 is removed from trench 1642 using a wet etch or dry etch process.

Figure 16J illustrates the structure of Figure 16I following the deposition of a non-conformal dielectric cap layer 1646 (which may be referred to as a dielectric helmet). In one embodiment, the non-conformal dielectric cap layer 1646 is formed using a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process, such as a plasma enhanced CVD (PECVD) process. The non-conformal dielectric cap layer 1646 may be as described above in association with the non-conformal dielectric cap layer 1610 .

Figure 16K illustrates the structure of Figure 16J following deposition of a sacrificial cap layer. A sacrificial cap layer 1648 is formed on the upper surface of the non-conformal dielectric cap layer 1646 and can be implemented to protect the non-conformal dielectric cap layer 1646 during subsequent etching or CMP processes. In one embodiment, the sacrificial cap layer 1648 is a titanium nitride (TiN) layer formed by, for example, PVD or CVD processing.

Figure 16L illustrates the structure of Figure 16K following the via lithography and etch process. Selected ones of trenches 1638 are exposed and subjected to an etch process that breaks non-conformal dielectric cap layer 1646 at locations 1650 and extends the trenches to provide via locations 1652, as described above.

Figure 16M illustrates the structure of Figure 16L following the fabrication of the second metal line. In one embodiment, the second metal lines 1654 (and in some cases, the associated conductive vias 1656 ) are formed by performing a metal fill and polish process. The polishing process may be a CMP process, which further removes the sacrificial cap layer 1648 .

FIG. 16N illustrates a diagram following directed self-polymerization (DSA) or selective growth, for example, to provide first and second alternating placeholder materials 1658 and 1660 (or may be permanent materials, as described in conjunction with FIG. 16D ) 16M structure.

16O illustrates the structure of FIG. 16N following the replacement of first and second alternating placeholder materials 1658 and 1660 with permanent first and second hard mask layers 1662 and 1664, respectively. The processing of Figures 16N and 16O may be described in conjunction with Figure 16D.

Figure 16P illustrates the structure of Figure 16O following patterning of the next layer of vias. An upper ILD layer 1666 is formed over the first and second hard mask layers 1662 and 1664 . Openings 1668 are formed in the upper ILD layer 1666 . In one embodiment, the openings 1668 are formed wider than the via feature size. A selected one of the exposed first and second hard mask layer 1662 and 1664 locations is selected for selective removal, eg, by a selective etch process. In this case, the first hard mask 1662 region is removed, which is selective to the exposed portion of the second hard mask layer 1664. Conductive vias 1670 are then formed in openings 1668 and in the areas where the first hard mask 1662 area has been removed. The conductive via 1670 contacts one of the first metal lines 1636 . In one embodiment, the conductive via 1670 contacts one of the first metal lines 1636 without shorting to an adjacent one of the second metal lines 1654 . In certain embodiments, portions 1672 of conductive vias 1670 are disposed over portions of second hard mask layer 1664 without contacting underlying second metal lines 1654, as depicted in Figure 16P. Next, in one embodiment, improved short circuit tolerance is achieved.

In one embodiment, the first hard mask 1662 area is removed for via 1670 fabrication as described in the above embodiments. In this case, forming the opening upon removal of the selected first hardmask 1662 region further requires etching through the uppermost portion of the non-conformal dielectric cap layer 1646. However, in another embodiment, the second hard mask 1664 area is removed for via 1670 fabrication. In this case, forming the opening upon removal of a selected second hard mask 1664 region directly exposes the metal line 1654 to which the via 1670 is connected.

In a second, more detailed example process flow, which involves the first method of via etching, FIGS. 17A-17J illustrate cross-sectional views of portions of integrated circuit layers that represent another method involved in back-end-of-line (BEOL) interconnection. Various operations in the method of forming a dielectric helmet of manufacture are in accordance with embodiments of the present invention.

Referring to Figure 17A, a starting point structure 1700 is provided (following the first metallization through processing) as a starting point for fabricating a new metallization layer. The starting point structure 1700 includes a hard mask layer 1704 (eg, silicon nitride) disposed on an interlayer dielectric (ILD) layer 1702 . As described below, the ILD layer may be disposed over the substrate and (in one embodiment) over the underlying metallization layer. First metal lines 1706 (and, in some cases, corresponding conductive vias 1707 ) are formed in the ILD layer 1702 . The protruding portion 1706A of the metal line 1706 has an adjacent dielectric spacer 1708 . A sacrificial hard mask layer 1710 (eg, amorphous silicon) is included between adjacent dielectric spacers 1708 . Although not depicted, in one embodiment, the metal lines 1706 are formed by first removing the second sacrificial hardmask material between the dielectric spacers 1708 and then etching the hardmask layer 1704 and the ILD layer 1702 ( It will be formed from the filled trenches during the metallization process.

FIG. 17B illustrates the structure of FIG. 17A following the second etch through metallization until the locations including trenches and vias are etched. Referring to FIG. 17B , the sacrificial hard mask layer 1710 is removed to expose the hard mask layer 1704 . Exposed portions of hard mask layer 1704 are removed and trenches 1712 are formed in ILD layer 1702 . Furthermore, in one embodiment, via locations 1722 are formed in selected locations using via lithography and etching processes, as depicted in Figure 17B.

Figure 17C illustrates the structure of Figure 17B following the filling of the sacrificial material. Sacrificial material 1714 is formed in trenches 1712 and over spacers 1708 and metal lines 1706 . In one embodiment, the sacrificial material 1714 is formed in a spin-on process, leaving a substantially flat layer, as depicted in Figure 17C.

17D illustrates the structure of FIG. 17C following a planarization process to re-expose the hard mask layer 1704, to remove the dielectric spacers 1708, and to remove the protrusions 1706A of the metal lines 1706. In addition, the planarization process confines the sacrificial material 1714 to the trenches 1712 formed in the dielectric layer 1702 . In one embodiment, the planarization process is performed using a chemical mechanical polishing (CMP) process.

17E illustrates the structure of FIG. 17D following partial removal of sacrificial material 1714 to provide recessed sacrificial material 1715. FIG. In one embodiment, the sacrificial material 1714 is recessed within the trenches 1712 using a wet etch or dry etch process. Recessed sacrificial material 1715 may be left at this point to protect the metal layer below via location 1722.

17F illustrates the structure of FIG. 17E following the deposition of a non-conformal dielectric cap layer 1716 (which may be referred to as a dielectric helmet). In one embodiment, the non-conformal dielectric cap layer 1716 is formed using a physical vapor deposition (PVD), selective growth process, or a chemical vapor deposition (CVD) process such as a plasma enhanced CVD (PECVD) process. form. The non-conformal dielectric cap layer 1716 may be as described above in association with the non-conformal dielectric cap layer 1710 . Alternatively, the non-conformal dielectric capping layer 1716 may include only the upper portion 1716A substantially free of the portion of the non-conformal dielectric capping layer 1716 formed in the trench 1712, as depicted in Figure 17F.

Figure 17G illustrates the structure of Figure 17F following the fabrication of the second metal line. In one embodiment, the second metal lines 1724 (and in some cases, the associated conductive vias 1726 ) are formed by performing a metal fill and polish process (followed by the removal of the recessed sacrificial material 1715 ) . The polishing process may be a CMP process.

FIG. 17H illustrates a diagram following directed self-polymerization (DSA) or selective growth, for example, to provide first and second alternating placeholder materials 1728 and 1730 (or may be permanent materials, as described in conjunction with FIG. 16D ) 17G structure.

17I illustrates the structure of FIG. 17H following the replacement of first and second alternating placeholder materials 1728 and 1730 with permanent first and second hard mask layers 1732 and 1734, respectively. The processing of Figures 17H and 3I may be described in conjunction with Figure 16D.

Figure 17J illustrates the structure of Figure 17I following patterning of the next layer of vias. An upper ILD layer 1736 is formed over the first and second hard mask layers 1732 and 1734 . Openings 1738 are formed in the upper ILD layer 1736 . In one embodiment, the openings 1738 are formed wider than the via feature size. A selected one of the exposed first and second hard mask layer 1732 and 1734 locations is selected for selective removal, eg, by a selective etch process. In this case, the region of the first hard mask 1732 is removed, which is selective to the exposed portion of the second hard mask layer 1734 . Conductive vias 1740 are then formed in openings 1738 and in the areas where the first hard mask 1732 area has been removed. The conductive via 1740 contacts one of the first metal lines 1706 . In one embodiment, the conductive via 1740 contacts one of the first metal lines 1706 without shorting to one of the adjacent second metal lines 1724 . In certain embodiments, portions 1742 of conductive vias 1740 are disposed over portions of second hard mask layer 1734 without contacting underlying second metal lines 1724, as depicted in Figure 17J. Next, in one embodiment, improved short circuit tolerance is achieved.

In one embodiment, the first hard mask 1732 area is removed for via 1740 fabrication, as described in the above embodiments. In this case, forming the opening upon removal of the selected first hardmask 1732 region further requires etching through the uppermost portion of the non-conformal dielectric cap layer 1716. However, in another embodiment, the second hard mask 1734 area is removed for through-hole 1740 fabrication. In this case, forming openings upon removal of a selected second hard mask 1734 region directly exposes the metal lines 1724 to which the vias 1740 are connected.

Referring again to Figures 16P and 17J, by cross-sectional analysis, the dielectric helmet can be viewed over half of the total metal population. In addition, hard masks of different materials are self-aligned to the dielectric helmet. Such structures may include one or more of conductive vias with improved short circuit tolerance, the presence of alternating hard mask materials, dielectric helmets. The resulting structures, such as those described in connection with Figures 16P or 17J, can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structures of Figures 16P or 17J may represent the last metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations may be performed in alternate orders, not every operation needs to be performed and/or additional process operations may be performed.

In accordance with embodiments of the present invention, pattern buildup layers for vias and plugs are described. One or more of the embodiments described herein relate to process solutions for via critical dimension (CD) control. Embodiments may include improvements related to via CD control, via CD uniformity, edge layout error (EPE), via self-alignment. Embodiments can improve edge layout error (EPE) in semiconductor patterning of vias and enable self-alignment of most via lithography passes. In one embodiment, all via edges are defined with gratings instead of standard resist edges. The sacrificial grating is created under the via resist, in the same direction as the metal vias sit. The vias are patterned using standard photoresists. However, during subsequent etching of gratings (eg, two cross gratings) through sacrificial gratings and self-aligned via (SAV) metal gratings, all via edges are defined by these gratings. In one embodiment, no variability from via resist edges is transferred into the substrate, and the resulting process capability enables better control of via CD and improved throughput and process capability.

To provide context for the following embodiments, currently known solutions involve the use of resist edges to define via edges, which determine short circuit tolerance to the underlying metal. However, standard via resist patterning is known to have much higher edge layout errors than grating patterning. In contrast, according to the embodiments described herein, the use of sacrificial gratings to define the edges of the vias provides improved control over the edges of the vias, and the risk of shorting to the wrong metal is significantly improved.

In accordance with embodiments described herein, a pattern accumulation flow is described for a post-etched majority via pattern with sacrificial gratings in a stack to define via edges. The "screen" stack is created by applying a hard mask over the patterned upper metal (M1) interlayer dielectric layer (where the plugs already exist). The hard mask flattens the wafer for subsequent processing. The next layer formed can be used as an etch stop, followed by the formation of a buildup layer. At this stage, the grating can be produced at twice the pitch of the underlying lower metal (M0) layer and in the same direction as the M0 grating. This grating effectively blocks the underlying M0 line at every interval and ultimately defines the critical dimension (CD) of the via post etch. In one embodiment, since the grating is twice the pitch of the underlying M0, a substantial mass (+/- 20nm) of the hardmask between the vias is included to allow the edges of the overlying resist features Layout Error (EPE).

Next, most of the via mask patterns are accumulated through the grating and in the accumulation layer. After accumulation, the grating is inverted without additional lithography operations to expose the other lower metal (M0) lines and protect the vias they have created. Liners are added between the gratings to ensure that vias on adjacent M0 lines do not merge. The spacing between the vias can be adjusted to the thickness of the liner.

Finally, via patterns from one to several via masks can be accumulated through the inverted grating to complete the patterning in the accumulation of all the depicted vias. The grating is then removed and the accumulated via pattern in the accumulation layer is etched down through the upper metal (Ml) hard mask grating into the interlayer dielectric under the Ml line and to the underlying M0. The stack above the M1 grating and the overlying hardmask layer are removed. Afterwards, the trenches and vias are metallized and then polished. The result is very good CD control of the formed vias in both directions, and self-alignment of all vias with respect to each other.

Next, in one form, one or more of the embodiments described herein relate to an approach that utilizes an underlying metal grating structure (or an orthogonal portion of such a structure) for creating overlying conductive vias template. In an example processing scheme, Figures 18A-18W illustrate plan views (upper portion of the pattern) and corresponding oblique (middle portion of the pattern) and cross-sectional views (lower portion of the pattern), which represent a method for back-end-of-process ( Various operations in a metal via processing scheme for BEOL) interconnects, in accordance with embodiments of the present invention.

Referring to Figure 18A, a starting point structure 1800 is provided as a starting point for fabricating a new metallization layer. The starting point structure 1800 includes an array of alternating metal lines 1802 and dielectric lines 1804 . Metal line 1802 has an upper surface that is approximately coplanar with the upper surface of dielectric line 1804 . An etch stop layer 1806 is then formed on the starting structure 1800, as depicted in Figure 18B.

Referring to Figure 18C, an interlayer dielectric layer 1808 is formed on the structure of Figure 18B. A patterned hard mask 1810 is then formed over the structure of FIG. 18C, and the pattern of the patterned hard mask 1810 is partially transferred into the interlayer dielectric layer 1808 to form a patterned interlayer dielectric layer 1812 (with metal line regions 1814) formed therein), as depicted in Figure 18D. In one embodiment, the patterned hardmask 1810 has a grating type pattern, as depicted in the figure. In certain embodiments, the patterned hard mask 1810 is composed of titanium nitride (TiN).

Referring to Figure 18E, a hard mask layer 1816 is formed on the structure of Figure 18D. In one embodiment, the bottom surface of the hard mask layer 1816 is conformal to the topography of the structure of FIG. 18D , and the top surface of the hard mask layer 1816 is planarized. In certain embodiments, the hard mask layer 1816 is a carbon hard mask (CHM) layer. An etch stop layer 1818 is then formed over the structure of Figure 18E, as depicted in Figure 18F. In certain embodiments, the etch stop layer 1818 is composed of silicon oxide (SiOx or _SiO2 ).

Referring to Figure 18G, a pattern accumulation layer 1820 is then formed on the structure of Figure 18F. In one embodiment, the pattern accumulation layer 1820 is a layer in which more than one pattern will eventually be accumulated, eg, for via last patterning. In certain embodiments, the pattern accumulation cap 1820 is composed of amorphous silicon (a-Si). A patterned hardmask 1822 is then formed on the structure of Figure 18G, as depicted in Figure 18H. In one embodiment, the patterned hardmask 1822 has a grating type pattern, as depicted in the figure. In one such embodiment, the grating type pattern is orthogonal to the grating of patterned hardmask 1810 and parallel to the grating of metal lines 1802 . However, in one embodiment, from a top-down perspective, the patterned hardmask 1822 only exposes every spaced metal line 1802 (eg, metal line 1802(A)) and blocks alternate metal lines 1802 (eg, Metal line 1802(B)), as depicted in Figure 18H. In certain embodiments, the patterned hard mask 1822 is composed of silicon nitride (SiN).

Referring to Figure 18I, a hard mask 1824 is then formed over the structure of Figure 18H. In certain embodiments, hard mask 1824 is a carbon hard mask (CHM). The hard mask 1824 is then patterned (eg, by a lithography process using a single or multi-layer resist structure) and the pattern is transferred into the portion of the pattern build-up layer 1820 that is exposed by the patterned hard mask 1822 to A patterned memory layer 1826 is formed once, as depicted in Figure 18J. In one embodiment, the pattern is transferred into the portion of the pattern accumulation layer 1820 by an etch process that uses the etch stop layer 1818 as a termination point. In one embodiment, after forming the patterned memory layer 1826 once, the hard mask 1824 is removed, as also depicted in Figure 18J. It should be understood that this process can be repeated for several different masking operations.

Referring to Figure 18K, barrier lines 1828 are then formed by filling the openings in the patterned hardmask 1822 of the structure of Figure 18J with a layer of barrier material. In certain embodiments, the barrier material layer is a flowable silicon oxide material. In other embodiments, the barrier material layer is any of several other suitable materials. The patterned hard mask 1822 is then removed from the structure of FIG. 18K so that the barrier lines 1828 remain, as depicted in FIG. 18L.

Referring to FIG. 18M , a layer of insulating spacer-forming material 1830 is then formed over the structure of FIG. 18L , which is conformal to barrier lines 1828 . In one embodiment, the insulating spacer forming material layer 1830 is composed of a dielectric material. In one embodiment, the spacer forming material layer 1830 is composed of silicon oxide (SiOx or _SiO2 ). A layer of spacer-forming material 1830 is then patterned to form spacers 1832 adjoining the sidewalls of the barrier lines 1828, as depicted in Figure 18N. In one embodiment, the spacer-forming material layer 1830 is patterned to form the spacers 1832 using an anisotropic dry etch process.

Referring to FIG. 18O, the collective pattern of barrier lines 1828, spacers 1832, and protected areas of the patterned mask formed after the spacers 1832 are formed is then transferred into the primary patterned memory layer 1826 to form a secondary patterned memory layer 1834. In one embodiment, the pattern is transferred into the primary patterned memory layer 1826 by an etch process that uses the etch stop layer 1818 as a termination point. Barrier lines 1828, spacers 1832, and any additional masking material for the structure of Figure 18O are then removed to expose the secondary patterned memory layer 1834, as depicted in Figure 18P.

Referring to FIG. 18Q, the pattern of the secondary patterned memory layer 1834 of the structure of FIG. 18P is then transferred to the etch stop layer 1818 to form a patterned etch stop layer 1836 and expose portions of the hard mask layer 1816. In one embodiment, the pattern of the secondary patterned memory layer 1834 is transferred to the etch stop layer 1818 using a dry etch process. The secondary patterned memory layer 1834 of the structure of Figure 18Q is then removed, as depicted in Figure 18R.

Referring to FIG. 18S , the pattern of the patterned etch stop layer 1836 of the structure of FIG. 18R is then transferred into the hard mask layer 1816 to form a patterned hard mask layer 1838 . The patterned hard mask layer 1838 exposes portions of the line regions 1814 of the patterned interlayer dielectric layer 1812 and portions of the patterned hard mask 1810 . That is, although the patterned hardmask layer 1838 exposes a wider area than the line regions 1814 of the patterned interlayer dielectric layer 1812 , the patterned hardmask 1810 protects the patterned interlayer dielectric layer 1812 outside the line regions 1814 . "Exposed" area. The pattern of the patterned hardmask layer 1838 of the structure of Figure 18S is then transferred to the patterned interlayer dielectric layer 1812 to form a secondary patterned interlayer dielectric layer 1840 and expose the etch stop layer 1806, as depicted in Figure 18T. However, in one embodiment, the patterned hardmask 1810 inhibits the overall transfer pattern, as also depicted in Figure 18T. In one embodiment, the pattern of the patterned hard mask layer 1838 is transferred to the patterned interlayer dielectric layer 1812 by an etch process using the etch stop layer 1806 as a termination point.

Referring to FIG. 18U, the exposed portion of the etch stop layer 1806 of the structure of FIG. 18T is removed to form a patterned etch stop layer 1842 and expose the via locations 1844 of the metal lines 1802. The patterned etch stop layer 1836, the patterned hard mask layer 1838, and the patterned hard mask 1810 of the structure of Figure 18U are then removed, as depicted in Figure 18V. The removal exposes the secondary patterned interlayer dielectric layer 1840 and via locations 1844 of the metal lines 1802, and the locations 1846 of the upper metal lines. In one embodiment, the patterned etch stop layer 1836, the patterned hard mask layer 1838, and the patterned hard mask 1810 are removed using a selective wet etch process.

Referring to FIG. 18W, an upper metallization layer is formed on the structure of FIG. 18V. In particular, a metal fill process is performed to provide metal vias 1848 and metal lines 1850 . In one embodiment, the metal filling process is performed using metal deposition and subsequent planarization processing schemes, such as a chemical mechanical planarization (CMP) process. In one embodiment, the surface of the forming structure of FIG. 18W is substantially the same as the surface of the starting structure 1800 of FIG. 18A (although orthogonal thereto). Thus, in one embodiment, the process described in conjunction with FIGS. 18B-18W may be repeated on the structure of FIG. 18W to form the next metallization layer, and so on.

The resulting structures, such as those described in connection with Figure 18W, can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 18W may represent the last metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations may be performed in alternate orders, not every operation needs to be performed and/or additional process operations may be performed. It should also be understood that the above examples have focused on via/contact formation. However, in other embodiments, a similar approach may be used to retain or form regions for wire terminations (plugs) within the metal line layers.

In accordance with embodiments of the present invention, grid-based via and plug patterning is described. One or more of the embodiments described herein relate to grid self-aligned and super self-aligned metal via processing schemes. Embodiments described herein can be implemented to provide self-aligned methods for metal/via layers. Almost all plug and via geometries are possible by implementing the methods described herein. In addition, the final via critical dimension (CD) can be independent of the lithography performed for patterning. Furthermore, the approaches described herein can provide a "loop flow" in that the end of the process flow has the same or substantially the same layer stack-up and layout as the beginning of the process flow. Thus, once each operation in the process flow is completed, the process flow can be repeated as many times as desired to add as many metal/via layers as desired. In one or more embodiments, the overlap between vertical grids is used to define the layout of vias and metal lines. The size of the via can be determined by the overlapping area between the two grids.

To provide context for the embodiments described below, the approaches described herein may provide nearly any plug and via layout available, as compared to currently known approaches for via self-alignment. The approach described herein may require less selective etching. The approach described herein can provide final plugs and vias CD which are independent of the lithography utilized. Next, in one form, one or more of the embodiments described herein relate to an approach that utilizes the underlying metal grating structure as a template for creating overlying conductive vias. It should be understood that a similar approach can be implemented to create non-conductive spaces or breaks between metals (plugs).

In an example processing scheme, Figures 19A-19L illustrate plan views (upper portion of the graph) and corresponding oblique cross-sectional views (lower portion of the graph) representing a grid for back-end-of-line (BEOL) interconnects Various operations in the SAM processing scheme are in accordance with embodiments of the present invention. It should be understood that the different metallization layers are shown separated (top and bottom) in an oblique cross-sectional view for clarity, although this is not the case in practice.

Referring to Figure 19A, a starting point structure 1900 is provided as a starting point for fabricating a new metallization layer. The starting point structure 1900 includes an array of alternating metal lines 1902 and dielectric lines 1904. Metal lines 1902 are recessed under dielectric lines 1904 . Hard mask layers 1906 are disposed over metal lines 1902 and alternate with dielectric lines 1904 . In one embodiment, the dielectric lines 1904 are composed of silicon nitride (SiN), and the hard mask layer 1906 is composed of silicon carbide (SiC) or silicon oxide (SiO ₂ ). The next patterned layer 1908 is then fabricated over the starting point structure 1900, as depicted in Figure 19B. In one embodiment, the next patterned layer 1908 includes an etch stop layer 1910 , a dielectric layer 1912 , and a grating structure 1914 . In one embodiment, the etch stop layer 1910 is composed of silicon oxide (SiO), the dielectric layer 1912 is composed of silicon nitride (SiN), and the grating structure 1914 is composed of silicon oxide (SiO). In one embodiment, the grating structure 1914 is formed using a pitch halving or quartering scheme (eg, by spacer patterning).

Referring to FIG. 19C , the pattern of the grating structure 1914 is transferred to the dielectric layer 1912 to form a patterned dielectric layer 1916 . In one embodiment, the pattern of grating structure 1914 is transferred to dielectric layer 1912 using an etch process that utilizes etch stop layer 1910 as the end point of the etch process. A through etch is then performed to remove exposed portions of etch stop layer 1910 to form patterned etch stop layer 1918, as depicted in Figure 19D. In one embodiment, the through-etch exposes all possible via locations 1920 that could potentially be formed into structure 1900.

Referring to FIG. 19E, plug patterning is then performed by forming a patterned hardmask 1922 on the structure of FIG. 19D (in the position where the plugs would be retained). The combined pattern of patterned hardmask 1922 and grating structure 1914 is then transferred into structure 1900 to form structure 1900' having regions 1924 for metal line formation within structure 1900, as depicted in Figure 19F. In one embodiment, the combined pattern of patterned hardmask 1922 and grating structure 1914 is transferred into structure 1900 using an etch process. This etch process can etch both layers 1904 and 1906 at substantially the same rate (or can be performed as several etch operations) and can be followed by a clean process to remove patterned hardmask 1922, as also shown in FIG. Depicted in 19F.

Referring to Figure 19G, via patterning is then performed on the structure of Figure 19F by forming a patterned lithography mask 1926 that exposes the locations where the vias are to be formed ( For example, via selection process). The combined pattern of patterned lithography mask 1926 and grating structure 1914 is then transferred into structure 1900' to form structure 1900" with regions 1928 for metal via formation within structure 1900', as depicted in Figure 19H In one embodiment, the combined pattern of patterned lithographic mask 1926 and grating structure 1914 is transferred into structure 1900' using an etch process. This etch process can etch layer 1906 selectively to layer 1904, and A cleaning process to remove the patterned lithography mask 1926 may be followed, as also depicted in Figure 19H.

Referring to FIG. 19I, a metal fill process is performed on the structure of FIG. 19I to provide the underlying structure 1930. A metal fill process forms metal vias 1932 and metal lines 1934 in structure 1930 . The metal fill process can also fill the region between the grating structure 1914 and the metal line 1936, as depicted in Figure 19I. In one embodiment, the metal filling process is performed using a metal deposition and subsequent planarization process scheme. The structure of Figure 19I may then be reduced in thickness to remove grating structure 1914 to expose patterned dielectric 1916 and provide metal lines 1938 on top, which are reduced in thickness from metal lines 1936, as depicted in Figure 19J. In one embodiment, the structure of Figure 19I may then be reduced in thickness using a planarization process, such as a chemical mechanical planarization (CMP) process.

Referring to FIG. 19K, metal lines 1938 are removed from the structure of FIG. 19J to leave a patterned dielectric layer 1916 and a patterned etch stop layer 1918. Metal line 1938 may be removed by a selective etch process that removes metal line 1938 and also ensures that no metal remains above the height of material layers 1904 and 1906 (ie, causes It has no metal remaining over the plug region of structure 1930). A hard mask layer 1940 is then formed over the structure of Figure 19K, between the lines of patterned dielectric layer 1916, as depicted in Figure 19L. In one embodiment, the hard mask layer 1940 is composed of silicon carbide (SiC) or silicon oxide (SiO ₂ ) and is formed using a deposition and planarization process scheme. In one embodiment, hard mask layer 1940 is composed of the same material as hard mask layer 1906 . In one embodiment, the surface of the structure formed from patterned dielectric layer 1916 and hard mask layer 1940 is substantially the same as (although orthogonal to) the surface of starting structure 1900 of Figure 19A. Thus, in one embodiment, the process described in conjunction with FIGS. 19B-19L may be repeated on the structure of FIG. 19L to form the next metallization layer, and so on.

It should be understood that the process described in conjunction with FIGS. 19B-19L (eg, repeated on the structure of FIG. 19L to form the next metallization layer) can be referred to as a cyclic process, since the end of the process flow has the same value as the beginning of the process flow or substantially the same layer stacking and layout. In one embodiment, forming additional metallization layers includes using such a cyclic process. However, it should also be understood that a cyclic or repeated process may only be implemented for selected metallization layers. Other metallization layers in the resulting stack (eg, layers above or below or between layers fabricated using the processing schemes of Figures 19B-19L) can be fabricated using conventional dual damascene or other means.

The resulting structure, such as 1931 described in connection with Figure 19L, can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure 1931 of Figure 19L may represent the last metal interconnect layer in an integrated circuit. It should also be understood that in subsequent fabrication operations, the dielectric lines may be removed to provide air gaps between the resulting metal lines. It should be understood that the above examples have focused on via/contact formation. However, in other embodiments, a similar approach may be used to retain or form regions for wire terminations (plugs) within the metal line layers.

In accordance with embodiments of the present invention, grating-based via and plug patterning is described. One or more embodiments described herein relate to grating-based plug and cut for feature end formation. Embodiments may involve one or more of lithographic patterning, associated line-end CD generation, and spacer-based patterning. Embodiments utilize methods to generate plugs and cuts with layout control and uniformity of one-dimensional (1D) features. It should be understood that there is a trade-off between better control over the wire termination (plug) or via layout, implying that vias and wire terminations are placed in more restricted locations.

To provide context for the embodiments described herein, grating and plugs or grating and dicing are applied to more layers in order to enable patterning of tighter pitch features in semiconductor fabrication. As feature sizes continue to shrink, the ability to robustly pattern dicing and plugging may limit scaling and yield. Cut and plug features are typically defined directly by a lithography operation with predominantly two-dimensional (2D) features. These 2D features have much higher variation and non-uniformity than one-dimensional (1D) features.

20A-20G described below, in one embodiment, an overview of a simplified patterning process for producing grating-defined plugs is presented. The sacrificial 1D pattern is created orthogonal to the principal direction of the layer in which it is patterned. The selection mask is then used to cut or save the portion of the 1D pattern which will ultimately be used to cut or save the portion of the main raster. The final edge of the cut/save on the main pattern is thus defined by the edges of the 1D sacrificial grating, with much better control and uniformity. 20A-20G illustrate plan views (top) and corresponding cross-sectional views (middle and bottom) showing a method of fabricating grating-based plugs and dicing for feature end formation for back-end-of-line (BEOL) interconnects Each of the operations is in accordance with the embodiments of the present invention.

Referring to Figure 20A, a starting point structure 2000 is provided as a starting point for fabricating a new metallization layer. The starting point structure 2000 includes an interlayer dielectric (ILD) material layer 2002 having a first hard mask layer 2004 formed thereon. The second hard mask layer 2006 is formed on the first hard mask layer 2004 . The second hard mask layer 2006 has a grating pattern, which can be regarded as a predominantly one-dimensional (1D) grating pattern. In one embodiment, the grating pattern of the second hard mask 2006 is ultimately used to define the 1D positions of the last layer it will be patterned but ends that do not yet have feature positions patterned therein. The first hard mask layer 2004 and/or the second hard mask layer 2006 may be fabricated from a material such as, but not limited to, silicon nitride (SiN), silicon oxide (SiO ₂ ), titanium nitride (TiN) ), or silicon (Si). In one embodiment, the first hard mask layer 2004 and the second hard mask layer 2006 are fabricated from different materials from each other.

Referring to FIG. 20B, a third hard mask layer 2008 is formed on the structure of FIG. 20A. In one embodiment, the third hard mask layer 2008 has a grating pattern, which can be viewed as a predominantly one-dimensional (1D) grating pattern, orthogonal to the ID grating pattern of the second hard mask layer 2006 . The third hard mask layer 2008 may be fabricated from a material such as, but not limited to, silicon nitride (SiN), silicon oxide ( _SiO2 ), titanium nitride (TiN), or silicon (Si). In one embodiment, the third hard mask layer 2008 is fabricated from a different material than that of the first hard mask layer 2004 and the second hard mask layer 2006 . It should be understood that any of the above-described hard mask layers may actually include a plurality of sub-layers, eg, to provide enhanced etch selectivity.

In one embodiment, the grating pattern of the third hard mask layer 2008 and the grating pattern of the second hard mask layer 2006 together define all allowed line end positions for the metal line metallization layers. In one such embodiment, the grating pattern of the third hard mask layer 2008 and the grating pattern of the second hard mask layer 2006 together define line end locations at locations where the lines of the grating patterns overlap. In another such embodiment, the grating pattern of the third hard mask layer 2008 and the grating pattern of the second hard mask layer 2006 together define lines in which spaces are exposed at locations between the lines of the grating patterns end position.

Referring to FIG. 20C, regions of lithography-patterned mask 2010 are formed on the structure of FIG. 20B. The regions of the lithographically patterned mask 2010 can be formed from photoresist layers or layers, or similar lithographically patterned masks. In one embodiment, areas of the lithographically patterned mask 2010 provide a pattern of cut/save areas on the sacrificial gratings formed from the second hard mask layer 2006 and the third hard mask layer 2008. Next, in one embodiment, a lithography process is used to select (cut or save) portions of the sacrificial grating that will ultimately define the end positions of the main pattern of metal lines. In one such embodiment, 193 nm or EUV lithography is used, along with etching of the resist pattern to transfer into the underlying layers, before etching the sacrificial grating pattern. In one embodiment, the lithography process involves multiple exposures or repeated deposition/etching/deposition processes of the resist layer. It should be understood that masked regions may be referred to as cut or save locations, where orthogonal grating overlap regions or spaces between gratings are used to define plug (or possibly via) locations.

Referring to FIG. 20D , the area of the lithography patterned mask 2010 using the structure of FIG. 20C is a mask, and the third hard mask layer 2008 is selectively etched to form the patterned hard mask layer 2012 . That is, a portion of the sacrificial grating is etched to occupy a portion of the pattern in the area of the lithography-patterned mask 2010, which protects part of the third hard mask layer 2008 from the etch process. In one embodiment, the portion of the third hard mask layer 2008 that is removed during the etch process is not part of the final target design. In one embodiment, the regions of the lithographically patterned mask 2010 are removed after forming the patterned hard mask layer 2012, as depicted in Figure 20D.

Referring to FIG. 20E, the combined pattern formed by the second hard mask layer 2006 and the patterned hard mask layer 2012 of the structure of FIG. 20D is transferred into the first hard mask layer 2004 and into the ILD material layer 2002, eg, by selective etching. The patterning forms a patterned ILD layer 2014 and a patterned hard mask layer 2016 .

Referring to FIG. 20F, the patterned hard mask layer 2012 and the second hard mask layer 2006 (ie, the sacrificial grating) of the structure of FIG. 20E are then removed. The patterned hardmask layer 2016 may be left at this stage, as depicted in Figure 20F, or may be removed. Selective wet or dry processing techniques can be utilized for the removal of the patterned hard mask layer 2012 and the second hard mask layer 2006 (and, possibly, the patterned hard mask layer 2016). It should be understood that the resulting structure of FIG. 20F can subsequently be used as a starting point for metal fill, with the option of removing the remaining patterned hard mask layer 2016 first. The end locations (line ends) of which will be metal features are defined by the edges of the 1D sacrificial gratings which are transferred into the ILD material layer 2002 and are therefore well controlled.

Referring to FIG. 20G , a metal fill process is performed on the structure of FIG. 20F to form metal lines 2018 in the openings of the patterned ILD layer 2014 . The metal lines have line ends formed by discontinuities in the continuity formed in the patterned ILD layer 2014 . In one embodiment, the metal filling process is performed by depositing and then planarizing one or more metal layers over the patterned ILD layer 2014 . The patterned hard mask layer 2016 may be retained during the metal deposition process and then removed during the planarization process, as depicted in Figures 20F and 20G. However, in other embodiments, the patterned hard mask layer 2016 is removed before the metal fill process. In yet other embodiments, the patterned hard mask layer 2016 is left in the final structure. Referring again to FIG. 20G, it should be understood that metal lines 2018 may be formed over underlying features, such as conductive vias 2020 shown by way of example.

The resulting structures, such as those described in connection with Figure 20G, can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of FIG. 20G may represent the final metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations may be performed in alternate orders, not every operation needs to be performed and/or additional process operations may be performed. In one embodiment, variations due to conventional lithography/damascene patterning (which would otherwise be tolerated) do not factor into the resulting structures described herein. It should be understood that the above examples have focused on wire end/plug/cut formation or retention. However, in other embodiments, a similar approach can be used to form vias/contacts above or below the metal line layer. It should also be understood that in subsequent fabrication operations, the dielectric lines may be removed to provide air gaps between the resulting metal lines.

Referring again to Figures 20A-20G, in one embodiment, a patterning process for creating grating-defining plugs has been described. Advantages of such an embodiment may include better dimensional control of end-to-end features, which reduces the chance of end-to-end shorts (production failures) otherwise observed under worst-case process variation conditions. Improved dimensional control of end-to-end features provides more area under worst-case process variation (for via seating and coverage). Thus, in one embodiment, improved electrical connections can be achieved from layer to layer with increased throughput and product performance. Improved dimensional control of end-to-end features may enable smaller end-to-end widths, and thus, better product density (cost per function) may be achieved.

In one embodiment, an advantage of embodiments of the present invention is that all line end positions are defined by a single lithography operation. For example, when the plug/cut pitch becomes extremely small, a common solution is to use multi-pass lithography with additional processing to produce composite plug/cut patterns. Conversely, in the embodiments described herein, feature end position is a function of the majority of lithography operations and, therefore, has a greater advantage than when a single lithography operation is used to define the feature ends (as is the case with the embodiments described herein) greater changes.

According to an embodiment of the present invention, the wire end cutting method is described. One or more of the embodiments described herein relate to techniques for patterning metal line terminations. Embodiments may include the form of one or more of contact fabrication, damascene processing, dual damascene processing, interconnect fabrication, and metal line trench patterning.

To provide context, in advanced nodes of semiconductor fabrication, low-level interconnects are created by separate patterning processes of wire gratings, wire terminations, and vias. The fidelity of composite patterns tends to decrease with via encroachment on the line ends, and vice versa. The embodiments described herein provide an end-of-line process, also known as a plug process, that eliminates the associated approximation rules. Embodiments may allow vias to be placed on the wire ends and large vias to wrap around the wire ends.

To provide further context, Figure 21A illustrates a plan view of a metallization layer of a conventional semiconductor device and a corresponding cross-sectional view taken along the a-a' axis of the plan view. 21B illustrates a cross-sectional view of a wire end or plug fabricated using currently known processing schemes. Figure 21C illustrates another cross-sectional view of a wire end or plug fabricated using currently known processing schemes.

Referring to FIG. 21A , metallization layer 2100 includes metal lines 2102 formed in dielectric layer 2104 . Metal lines 2102 may be coupled to lower vias 2103 . Dielectric layer 2104 may include line termination or plug regions 2105 . Referring to FIG. 21B , conventional terminal or plug regions 2105 of the dielectric layer 2104 may be fabricated by patterning the hard mask layer 2110 on the dielectric layer 2104 and then etching the exposed portions of the dielectric layer 2104 . Exposed portions of dielectric layer 2104 may be etched to a depth suitable for forming line trenches 2106 or further etched to a depth suitable for forming via trenches 2108 . Referring to FIG. 21C, two vias adjacent opposite sidewalls of the terminal or plug 2105 can be fabricated in a single large exposure 2116 to finally form the line trench 2112 and the via trench 2114.

However, referring again to Figures 21A-21C, fidelity issues and/or hard mask erosion issues may result in imperfect patterned states. Rather, one or more of the embodiments described herein include an implementation of a process flow involving the construction of line-terminated dielectrics (plugs) after trench and via patterning processes. In an example processing scheme, Figures 21D-21J illustrate cross-sectional views representing various operations in a process for patterning metal line terminals of a back end of line (BEOL) interconnect, in accordance with embodiments of the present invention.

Referring to FIG. 21D, a method of fabricating a metallization layer for an interconnect structure of a semiconductor die includes forming line trenches 2128 in an upper portion of an interlayer dielectric (ILD) material layer 2126 formed over the underlying metallization layer 2120 (above lower section 2130). The lower metallization layer 2120 includes metal lines 2122 disposed in the dielectric layer 2124 .

21E, via trenches 2132A and 2132B are formed in the lower portion 2130 of the ILD material layer 2126 to form a patterned lower portion 2130' of the ILD material layer 2126. As an example embodiment, via trench 2132A exposes two metal lines 2122 of the underlying metallization layer 2120 , while via trench 2132B exposes one metal line 2122 of the underlying metallization layer 2120 .

Referring to Figure 21F, a sacrificial material 2134, such as a matrix material, is formed over the layer of ILD material (portion 2130' shown in Figure 21F) and in line trenches 2128 and via trenches 2132A and 2132B. In one embodiment, a patterned hard mask layer 2136 is formed on the sacrificial material 2134, as depicted in Figure 21F.

Referring to FIG. 21G, sacrificial material 2134 is patterned to form openings (left-hand opening of FIG. 21G) that expose between the two metal lines 2122 of the underlying metallization layer 2120 associated with the via trenches 2132A of FIG. 21E Portion of lower metallization layer 2120. In the example embodiment shown, the sacrificial material 2134 is further patterned to form openings (the right-hand side opening of FIG. 21G ) that expose the patterned lower portion 2130 of the ILD material layer adjacent to the via trench 2132B of FIG. 2E 'part. In one embodiment, the sacrificial material 2134 is patterned by transferring the pattern of the patterned hardmask 2136 to the sacrificial material 2134 (by an etch process).

Referring to FIG. 21H, the openings of sacrificial material 2134 (now shown patterned and filled with sacrificial material 2134') are filled with dielectric material 2138. In one embodiment, the openings of sacrificial material 2134 are filled with dielectric material 2138 using a deposition process selected from the group consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD). In one embodiment, the openings of the sacrificial material 2134 are filled with a dielectric material 2138 consisting of a first dielectric material. In one such embodiment, the ILD material layer 2126 includes a second dielectric material composed of a different material than the first dielectric material. However, in another such embodiment, the ILD material layer 2126 is composed of a first dielectric material.

Referring to Figure 21I, filled sacrificial material 2134' is removed to provide dielectric plugs 2140A and 2140B. In the example embodiment shown, the dielectric plug 2140A is disposed on the portion of the lower metallization layer 2120 between the two metal lines 2122 of the lower metallization layer 2120 . Dielectric plug 2140A is adjacent to via trench 2132A and line trench 2128', and (in the case shown in FIG. 21I) between substantially symmetrical via trench 2132A and line trench 2128' . Dielectric plugs 2140B are disposed over portions of the patterned lower portion 2130' of the layer 2126 of ILD material. Dielectric plug 2140 is adjacent to via trench 2142B and the corresponding line trench (the right hand side of dielectric plug 2140B). In one embodiment, the structure of Figure 21H is subjected to a planarization process that is used to remove overloaded regions of dielectric material 2138 (regions on and over the surface on either side of the trench) for The patterned hard mask 2136 is removed, along with the portion of the dielectric material 2138 used to reduce the height of the sacrificial material 2134'. The sacrificial material 2134' is then removed by using selective wet or dry process etching techniques.

Referring to Figure 21J, line trenches 2128' and via trenches 2132A and 2132B are filled with conductive material. In one embodiment, line trenches 2128' and via trenches 2132A and 2132B are filled with conductive material to form metal lines 2142 and conductive vias 2144 in patterned dielectric layer 2130'. In an exemplary embodiment, referring to plug 2140A, first metal line 2142 and first conductive via 2144 are directly adjacent to the left-hand sidewall of dielectric plug 2140A. The second metal line 2142 and the second conductive via 2144 are directly adjacent to the right-hand sidewall of the dielectric plug 2140A. Referring to the plug 2140B, the first metal line 2142 is directly adjacent to the right hand sidewall of the dielectric plug 2140B, and the lower portion of the patterned lower portion 2130' of the ILD layer is directly adjacent to the first conductive via 2144 . However, on the left-hand side of dielectric plug 2140B, only metal lines 2142 (and not the associated conductive vias) are associated with dielectric plug 2140B. In one embodiment, the metal filling process is performed by depositing and then planarizing one or more metal layers over the structure of FIG. 2I.

Referring again to FIG. 21J, several different embodiments may be shown using the diagram. For example, in one embodiment, the structure of Figure 21J represents the final metallization layer structure. In another embodiment, dielectric plugs 2140A and 2140B are removed to provide air gap structures. In another embodiment, the dielectric plugs 2140A and 2140B are replaced with another dielectric material. In another embodiment, the dielectric plugs 2140A and 2140B may be sacrificial patterns that are ultimately transferred to another underlying interlayer dielectric material layer.

In an exemplary embodiment, referring again to FIG. 21J (and previous processing operations), the metallization layers used for the interconnect structure of the semiconductor die include metal lines 2142 disposed in trenches of the interlayer dielectric (ILD) material layer 2126 in slot 2128'. The ILD material layer 2126 is composed of a first dielectric material. Conductive vias 2144 are disposed in the ILD 2126 material layer below and electrically connected to the metal lines 2142 . Dielectric plug 2140A (or 2140B) is directly adjacent to metal line 2142 and conductive via 2144 . The second metal lines 2142 and conductive vias 2144 may also be directly adjacent to a dielectric plug (eg, dielectric plug 2140A). In one embodiment, the dielectric plug 2140A (or 2140B) is composed of a second dielectric material different from the first dielectric material.

It will be appreciated that filling the openings of the sacrificial material 2134 with dielectric material can result in the formation of seams in the dielectric material approximately in the center of the resulting dielectric plug. For example, FIG. 21K illustrates a cross-sectional view of a metallization layer of an interconnect structure of a semiconductor die that includes a dielectric line end or plug having a seam therein, in accordance with an embodiment of the present invention.

Referring to Figure 21K, the metallization layer of the interconnect structure of the semiconductor die includes metal lines 2140 disposed in trenches (lower portion 2130' shown) in a layer of interlayer dielectric (ILD) material. Conductive vias 2144 are disposed in the ILD material layer 2130' below and electrically connected to the metal lines 2142. Dielectric plugs 2152A and 2152B are directly adjacent to metal lines 2142 and conductive vias 2144 . Dielectric plugs 2152A and 2152B each include a seam 2150 approximately in the center of the dielectric plug, which may facilitate deposition of the dielectric plug by chemical vapor deposition (CVD) or atomic layer deposition (ALD), for example.

It should be understood that a wire end or plug may be associated with a metal line that does not have a via immediately below the dielectric plug. For example, FIG. 21L illustrates a cross-sectional view of a metallization layer of an interconnect structure of a semiconductor die that includes dielectric lines or plugs that are not immediately adjacent conductive vias, in accordance with embodiments of the present invention. Referring to Figure 21L, the dielectric plug 2152 is associated with a metal line 2142 that does not have a via (such as via 2144) immediately below the dielectric plug 2152 (and above the associated patterned dielectric layer 2154').

The resulting structures, such as those described in connection with Figures 21J, 21K, or 21L, can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structures of Figure 21J, Figure 21K, or Figure 21L may represent the last metal interconnect layer in an integrated circuit. In one embodiment, the bias due to conventional lithography/damascene patterning (which would otherwise be tolerated) is mitigated for the resulting structures described herein. It should also be understood that in subsequent fabrication operations, the dielectric layer may be removed to provide air gaps between the resulting metal lines.

In accordance with embodiments of the present invention, self-aligned etching of pre-formed vias and plugs is described. One or more embodiments described herein relate to self-aligned via and plug patterning. The self-aligned aspect of the procedures described herein may be based on a directed self-aggregation (DSA) mechanism, as described in more detail below. However, it should be understood that its selective growth mechanism can be exploited in a DSA-based manner. In one embodiment, the procedures described herein enable the realization of self-aligned metallization for back-end-of-process feature fabrication.

Embodiments described herein may relate to self-aligned isotropic etch processes for pre-forming vias or plugs (or both). For example, the processing scheme may involve the pre-formation of every possible via and plug in a metallization layer, such as a back-end-of-process metallization layer of a semiconductor structure. Lithography is then utilized to select specific via and/or plug locations to open/close (eg, save/remove). Implementations of the embodiments described herein may involve the use of such an etch scheme to form all vias/plugs in a photobarrel configuration for each respective via/metal layer in the metallization stack. As will be understood: vias may be formed in a different layer than the layer in which the plugs are formed (eg, the latter are formed in metal line layers perpendicular to the via layers), or the plugs and vias can be formed in the same layer.

One or more of the embodiments described herein provide a more efficient way to pattern by maximizing overlapping process windows, minimizing the size and shape of the desired pattern, and increasing the number of holes or plugs used to pattern the efficiency of the lithography process. In more specific embodiments, the patterns used to open pre-formed via or plug locations can be formed to be relatively small, enabling increased overlap tolerance for the lithography process. The pattern features can be made of uniform size, which can reduce the scan time of the direct-write electron beam and/or the complexity of Optical Proximity Correction (OPC) using optical lithography. Pattern features can also be formed shallow, which can improve patterning resolution. The etching process performed subsequently may be an isotropic chemical selective etching. Such an etch process alleviates the otherwise associated profile and critical dimensions, and alleviates anisotropy problems typically associated with dry etch methods. This etch process is also relatively much cheaper (from an equipment and yield point of view) compared to other selective removal methods.

As an example general processing scheme, FIGS. 22A-22G illustrate portions of integrated circuit layers that represent various operations in a method involving self-aligned isotropic etching of pre-formed vias or plug locations, in accordance with the present invention. Example. In each illustration of the described operations, the plan view is shown on the left hand side and the corresponding cross-sectional view is shown on the right hand side. These views will be referred to herein as the corresponding cross-sectional and plan views.

22A illustrates a plan view and corresponding cross-sectional view (taken along the a-a' axis) of the starting structure after pre-patterning of holes/trenches 2204 in substrate or layer 2202. In one embodiment, the substrate or layer 2202 is an interlayer dielectric (ILD) material layer.

Although not depicted for simplicity, it is understood that the holes/trenches 2204 may expose underlying features, such as underlying metal lines. Also, in one embodiment, the starting structure may be patterned in a grating-like pattern with holes/trenches 2204 of constant width spaced at a constant pitch. Patterns, for example, can be fabricated by halving the pitch or reducing the pitch by a quarter, and so on. With their via layers fabricated, some of the holes/trenches 2204 may be associated with lower level metallization lines below.

22B illustrates a plan view and corresponding cross-sectional view (taken along the b-b' axis) of the structure of FIG. 22A subsequent to filling of holes/trenches 2204 with sacrificial or permanent placeholder material 2206. ILD material may be used to fill holes/trenches 2204 in the case where it uses permanent placeholder material. In the case of its use of sacrificial placeholder materials, more flexibility in design choices can be provided. For example, in one embodiment, a material that would not otherwise be suitable for retention in the final structure may be used, such as a structurally weak polymer or a soft photoresist. As depicted in the cross-sectional view of Figure 22B, the formation of a small amount of recesses 2208 of sacrificial or permanent placeholder material 2206 in the holes/trenches 2204 may be included to assist in subsequent processing. In one embodiment, the sacrificial or permanent placeholder material 2206 is a spin-on dielectric material.

22C illustrates a plan view and corresponding cross-sectional view (taken along the c-c' axis) of the structure of FIG. 22B following the formation of patterned layer 2210. In one embodiment, the patterned layer 2210 is a photosensitive material, such as a positive tone photoresist layer. In another embodiment, the patterned layer 2210 is an anti-reflection coating material. In one embodiment, the patterned layer 2210 includes a stack of material layers, including one or more layers of photosensitive material and/or one or more layers of anti-reflective coating material.

22D illustrates a plan view and corresponding cross-sectional view (taken along the d-d' axis) of the structure of FIG. 22C following patterning of patterned layer 2210 to form openings 2212 in patterned layer 2210. Referring to FIG. 22D , openings 2212 expose an underlying portion of sacrificial or permanent placeholder material 2206 . In particular, opening 2212 exposes the lower portion of sacrificial or permanent placeholder material 2206 only over hole/trench 2204 where vias or plugs are selected to be formed. In one embodiment, the openings 2212 in the patterned layer 2210 are substantially smaller than the exposed holes/trenches 2204. As briefly described above, the formation of openings 2212, which are relatively smaller than exposed holes/trenches 2204, provides significantly increased tolerance for misalignment issues. In one embodiment, the patterned layer 2210 is a photosensitive material, and the openings 2212 are formed by a lithography process, such as a positive tone lithography process.

22E illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 22D following removal of sacrificial or permanent placeholder material 2206 in locations exposed by openings 2212 to form re-exposed holes/trenches 2214 (along the taken along the e-e' axis). In one embodiment, the sacrificial or permanent placeholder material 2206 is removed by an isotropic etch process. In one such embodiment, the isotropic etch process involves the application of a wet etchant. The wet etchant accesses and etches the sacrificial or permanent placeholder material 2206 through the opening 2212 . The etch process is isotropic in that material not exposed by (but accessible through) openings 2212 can be etched into selectively formed re-exposed holes/trenches 2214 for vias or The plug is formed in the desired position. In one embodiment, the wet etch process etches the sacrificial or permanent placeholder material 2206 without etching (or not substantially etching) the patterned layer 2210 .

In one embodiment, the sacrificial or permanent placeholder material 2206 is a spin-on carbon hardmask material, and the etch process is a TMAH-based etch process. In another embodiment, the sacrificial or permanent placeholder material 2206 is a spin-on bottom anti-reflective coating (BARC) material, and the etch process is a TMAH-based etch process. In another embodiment, the sacrificial or permanent placeholder material 2206 is a spin-on bottom glass material, and the etching process is a wet etching process based on organic solvents, acids or bases. In another embodiment, the sacrificial or permanent placeholder material 2206 is a spin-on metal oxide material and the etch process is a wet etch process according to commercially available cleaning chemistries. In another embodiment, the sacrificial or permanent placeholder material 2206 is a CVD carbon material and the etch process is an etch process based on oxygen plasma ash.

22F illustrates a plan view and corresponding cross-sectional view (taken along the f-f' axis) of the structure of FIG. 22E following removal of patterned layer 2210. In one embodiment, the patterned layer 2210 is a photoresist layer, and the photoresist layer is removed by a wet removal or plasma ashing process. Removal of patterned layer 2210 fully exposes the re-exposure hole/trench 2214.

22G illustrates a plan view and corresponding cross-sectional view (taken along the g-g' axis) of the structure of FIG. 22F subsequent to filling of re-exposed holes/trenches 2214 with material layer 2216 and subsequent planarization. In one embodiment, the material layer 2216 is used to form the plug and is a permanent ILD material. In another embodiment, the material layer 116 is used to form conductive vias and is a metal filling layer. In one such embodiment, the metal fill layer is a single layer of material, or is formed from several layers, including a conductive liner layer and a fill layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, can be used to form such a metal fill layer. In one embodiment, the metal filling layer is composed of conductive materials such as (but not limited to) Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au or its alloys. With its material layer 116 planarized (following deposition), a chemical mechanical polishing process can be used.

In one embodiment, the material layer 2216 is a material suitable for forming conductive vias. In one such embodiment, the sacrificial or permanent placeholder material 2206 is a permanent placeholder material, such as a permanent ILD material. In another such embodiment, the sacrificial or permanent placeholder material 2206 is a sacrificial placeholder material that is subsequently removed and replaced with a material, such as a permanent ILD material. In another embodiment, the material layer 2216 is a material suitable for forming a dielectric plug. In one such embodiment, the sacrificial or permanent placeholder material 2206 is a sacrificial placeholder material that is subsequently removed or partially removed to enable metal line formation.

It should be understood that the resulting structure of Figure 22G can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 22G may represent the final metal interconnect layer in an integrated circuit. Furthermore, it should be understood that the above examples do not include an etch stop or metal capping layer in the pattern, which may otherwise be required for patterning. However, for clarity, these layers are not included in the figure as they do not affect the overall concept.

In another form, embodiments relate to a process flow for performing isotropic dry etching (along with a hole reduction process). In one such embodiment, one patterning scheme provides pinhole patterning in the mask layer, subsequent to filling all via locations with an organic polymer. As an example processing scheme, Figures 22H-22J illustrate oblique cross-sectional views showing portions of integrated circuit layers representing various operations in a method involving self-aligned isotropic etching of preformed via locations, According to an embodiment of the present invention.

Figure 22H illustrates starting the structure after filling all possible via locations with placeholder material. Referring to Figure 22H, a metallization layer 2252, such as an ILD layer of metallization layer, is formed over a substrate (not shown) and includes a plurality of metal lines 2254 therein. ILD material, which can be two or more different ILD materials 2256 and 2258, surrounds locations where vias may be formed. The sacrificial placeholder material 2260 occupies the locations where all possible vias can be formed over the metal lines 2252. A mask layer 2262, such as a thin low temperature oxide mask layer, is formed on the underlying structure. It should be understood that the sacrificial placeholder material 2260 does not appear over adjacent features, which can be accomplished by deposition and planarization or recessing processes.

22I illustrates the structure of FIG. 22H following patterning of mask layer 2262 to form openings 2264 in mask layer 2262. Referring to FIG. 22I , openings 2264 expose lower portions of sacrificial placeholder material 2260 . In particular, openings 2264 expose the underlying portions of sacrificial placeholder material 2260 only at locations where vias are selected to be formed. In one embodiment, the openings 2264 in the mask layer 2262 are substantially smaller than the exposed sacrificial placeholder material 2260 . As briefly described above, the formation of openings 2264 that are relatively smaller than the exposed sacrificial placeholder material 2260 provides significantly increased tolerance for misalignment issues. This process effectively "shrinks" the via location to the size of a "pinhole" for actual via location selection and patterning. In one embodiment, mask layer 2262 is patterned with openings 2262 by first forming and patterning the photosensitive material on mask layer 2262 by a lithography process, such as a positive tone lithography process, and The mask layer 2262 is then patterned by an etching process.

22J illustrates the structure of FIG. 22I following removal of sacrificial placeholder material 2260 in the locations exposed by openings 2264 to form exposed via locations 2266. FIG. In one embodiment, the sacrificial placeholder material 2260 is removed over the via locations 2266 by an isotropic etch process. In one such embodiment, the sacrificial placeholder material 2260 is an organic polymer, and the isotropic etching process is an isotropic plasma gray (oxygen plasma) or wet cleaning process.

Referring again to Figure 22J, it should be understood that subsequent processing may involve removing mask layer 2262 and filling holes/trenches 2266 with conductive via material. At the same time, the remaining sacrificial placeholder material 2260 that is not exposed by the openings 2264 (ie, not selected as via locations) can be replaced with permanent ILD material. The resulting structure can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the resulting structure may represent the final metal interconnect layer in an integrated circuit.

In accordance with one or more embodiments of the present invention, as described above, the approach described herein may build on the use of so-called "light barrels", where each possible feature (eg, via or plug) is pre-patterned into the base. Next, photoresist is filled into the patterned features and a lithography operation is used only to select selected vias for via opening formation. The light-barrel approach can tolerate larger critical dimension (CD) and/or overlap errors while preserving the ability to select vias or plugs of interest. The lithography method used to select a particular light barrel may include, but may not be limited to, 193 nm immersion lithography (i193), extreme ultraviolet (EUV) and/or electron beam direct writing (EBDW) lithography.

In summary, in accordance with one or more embodiments of the present invention, a DSA approach or a subtractive approach is produced to be photosensitive. In one view, a form of photobucket is achieved in which lithography constraints can be relaxed and misalignment tolerances can be high because the photobucket is surrounded by non-photolyzable material. Also, in one embodiment, instead of exposing at, eg, 30 mJ/cm ² , such a photobarrel can be exposed at, eg, 3 mJ/cm ² . Typically this will result in very poor CD control and roughness. But in this case, the CD and roughness control will be defined by the light barrel geometry, which can be well controlled and defined. Therefore, this photobucket approach can be used to prevent imaging/dose tradeoffs that limit the throughput of next-generation lithography processes. In one embodiment, the light barrel material that is not selected for removal is ultimately retained as a permanent ILD portion in the semiconductor structure. In another embodiment, the light barrel material, which is not selected for removal, is finally exchanged for the permanent ILD portion in the semiconductor structure.

In one embodiment, the optical barrel "ILD" composition is generally very different from standard ILDs, and (in one embodiment) is highly self-aligned in both directions. More generally, in one embodiment, the term photobucket as used herein refers to the use of ultrafast photoresists or e-beam resists or other photosensitive materials, such as those formed in etched openings. In this embodiment, thermal backfill of the polymer into the opening is used subsequent to spin-on application. In one embodiment, fast photoresists are fabricated by removing inhibitors from existing photoresist materials. In another embodiment, the photobarrel is formed by an etch-back process and/or a lithography/reduction/etch process. It should be understood that the photobucket need not be filled with actual photoresist, so long as the material acts as a photoswitch. In one embodiment, lithography is used to expose the respective photo barrels that are selected for removal. However, lithography constraints can be relaxed and misalignment tolerances can be high because the photobucket is surrounded by non-photolyzable material. In one embodiment, the photobarrel receives exposure to extreme ultraviolet (EUV) light to expose the photobarrel, wherein in particular embodiments, EUV is in the range of 5-15 nm. While many of the embodiments described herein relate to photobarrel materials according to polymers, in other embodiments, photobarrel materials according to nanoparticles are similarly implemented.

According to an embodiment of the present invention, a light barrel method is described. One or more embodiments described herein relate to a subtractive approach for self-aligned via and plug patterning, and the resulting structures. In one embodiment, the procedures described herein enable the realization of self-aligned metallization for back-end-of-process feature fabrication. Overlap issues anticipated for the next generation of via and plug patterning may be addressed in one or more of the ways described herein. More specifically, one or more of the embodiments described herein relate to using a subtractive method to preform each via and plug using etched trenches. An additional operation is then used to select which vias and plugs to keep. These operations can be illustrated using photobuckets, although a more traditional resist exposure and ILD backfill approach can also be used to perform the selection process.

In the first form, the first through hole and the second plug form are used. As an example, FIGS. 23A-23L illustrate portions of an integrated circuit layer that represent operations in a method of subtracting self-aligned vias and plugs patterning, in accordance with embodiments of the present invention. In each illustration of each of the described operations, cross-sectional and/or oblique views are shown. These views will be referred to herein as the corresponding cross-sectional and oblique views.

23A illustrates a cross-sectional view of the starting structure 2300 after deposition (but before patterning) of the first hard mask material layer 2304 formed on the interlayer dielectric (ILD) layer 2302, in accordance with an embodiment of the present invention . Referring to FIG. 23A, the patterned mask 2306 has spacers 2308 formed on or over the first layer of hard mask material 2304 (along its sidewalls).

23B illustrates the structure of FIG. 23A following patterning of the first hard mask layer by pitch doubling, in accordance with an embodiment of the present invention. Referring to FIG. 23B , the patterned mask 2306 is removed and the resulting pattern of spacers 2308 is transferred (eg, by an etch process) to the first layer of hard mask material 2304 to form a first patterned hard mask 2310 . In one such embodiment, the first patterned hardmask 2310 is formed in a grating pattern, as depicted in Figure 23B. In one embodiment, the grating structure of the first patterned hard mask 2310 is a close-pitch grating structure. In a particular such embodiment, tight pitch cannot be achieved directly by conventional lithography. For example, a pattern according to conventional lithography can be formed first (mask 2306), but the pitch can be halved by using spacer mask patterning, as depicted in Figures 23A and 23B. Even, although not shown, the original pitch can be reduced by a quarter by a second round of spacer mask patterning. Thus, the raster-like pattern of the first patterned hard mask 2310 of FIG. 23B can have hard mask lines of constant width separated by a constant pitch.

23C illustrates the structure of FIG. 23B following the formation of the second patterned hard mask, in accordance with an embodiment of the present invention. Referring to FIG. 23C , the second patterned hard mask 2312 is formed to be interleaved with the first patterned hard mask 2310 . In one such embodiment, the second patterned hardmask 2312 is formed by deposition of a second layer of hardmask material (having a different composition than the first layer of hardmask material 2304). The second layer of hard mask material is then planarized (eg, by chemical mechanical polishing (CMP)) to provide a second patterned hard mask 2312 .

23D illustrates the structure of FIG. 23C following deposition of a hard mask cap layer, in accordance with an embodiment of the present invention. Referring to FIG. 23D , a hard mask cap layer 2314 is formed on the first patterned hard mask 2310 and the first patterned hard mask 2312 . In one such embodiment, the material composition and etch selectivity of the hard mask capping layer 2314 are different from the first patterned hard mask 2310 and the first patterned hard mask 2312.

Figure 23E illustrates the structure of Figure 23D following deposition of a hard mask cap layer, in accordance with an embodiment of the present invention. Referring to FIG. 23E , a patterned hard mask capping layer 2314 is formed on the first patterned hard mask 2310 and the first patterned hard mask 2312 . In one such embodiment, the patterned hardmask cap layer 2314 is formed with a grating pattern orthogonal to the grating patterns of the first patterned hardmask 2310 and the first patterned hardmask 2312, as shown in FIG. shown in 23E. In one embodiment, the grating structure formed by the patterned hard mask cap layer 2314 is a close pitch grating structure. In this embodiment, tight pitch cannot be achieved directly by conventional lithography. For example, a pattern according to conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask. Even, the original pitch can be reduced by a quarter by a second round of spacer mask patterning. Thus, the raster-like pattern of the patterned hard mask cap layer 2314 of FIG. 23E can have hard mask lines of constant width separated by a constant pitch.

23F illustrates the structure of FIG. 23E following further patterning of the first patterned hardmask and subsequent formation of multiple photobuckets, in accordance with an embodiment of the present invention. Referring to FIG. 23F , using the patterned hard mask cap layer 2314 as a mask, the first patterned hard mask 2310 is further patterned to form the first patterned hard mask 2316 . The second patterned hard mask 2312 is not further patterned in this process. Afterwards, the patterned hard mask cap layer 2314 is removed, and photobuckets 2318 are formed in the resulting openings over the ILD layer 2302. Light barrels 2318 (at this stage) represent all possible via locations in the resulting metallization layer.

23G illustrates the structure of FIG. 23F following photobarrel exposure and development to leave selected via locations, and subsequent via openings etched into the underlying ILD, in accordance with an embodiment of the present invention. Referring to FIG. 23G , selected photo barrels 2318 are exposed and removed to provide selected via locations 2320 . Via locations 2320 are subjected to a selective etch process, such as a selective plasma etch process, to extend the via openings into the underlying ILD layer 2302, forming a patterned ILD layer 2302'. Etching is selective to the remaining photobuckets 2318 , the first patterned hardmask 2316 , and the second patterned hardmask 2312 .

23H illustrates the structure of FIG. 23G following removal of the remaining photo barrels, subsequent formation of hard mask material, and subsequent formation of a second plurality of photo barrels, in accordance with an embodiment of the present invention. Referring to Figure 23H, the remaining photo barrels are removed, eg, by a selective etch process. All openings formed (eg, openings formed upon removal of the light barrels 2318 and via locations 2320) are then filled with a hardmask material 2322, such as a carbon-based hardmask material. Thereafter, the first patterned hard mask 2316 is removed (eg, in a selective etch process), and the resulting openings are filled with a second plurality of photo barrels 2324. Light barrels 2324 (at this stage) represent all possible plug locations in the resulting metallization layer. It should be understood that the second patterned hard mask 2312 is not further patterned at this stage in the process.

Figure 23I illustrates the structure of Figure 23H following plug location selection, in accordance with an embodiment of the present invention. Referring to Figure 23I, the light barrel 2324 from Figure 23H is removed from a location 2326 where a plug would not be formed. In the position selected to form the plug, the light barrel 2324 is retained. In one embodiment, to form locations 2326 where plugs will not be formed, lithography is used to expose the corresponding photo barrels 2324. The exposed photobucket can then be removed with the developer.

23J illustrates the structure of FIG. 23I subsequent to removal of the most recently formed hard mask from via and line locations, in accordance with an embodiment of the present invention. Referring to Figure 23J, the hard mask material 2322 depicted in Figure 23I is removed. In one such embodiment, the hardmask material 2322 is a carbon-based hardmask material and is removed by a plasma ash process. As shown, the remaining features include: patterned ILD layer 2302' Although not shown, it should be understood that in one embodiment, the second hard mask layer 2312 is also retained at this stage.

23K illustrates the structure of FIG. 23J after recessing of the patterned ILD layer in locations not protected by plug-forming photobarrels, in accordance with an embodiment of the present invention. 23K, portions of the patterned ILD layer 2302' that are not protected by the photobarrel 2324 are recessed to provide metal line openings 2330, in addition to the via openings 2328.

Figure 23L illustrates the structure of Figure 23K following metal filling, in accordance with an embodiment of the present invention. Referring to FIG. 23L, metallization 2332 is formed in openings 2328 and 2332. In one such embodiment, metallization 2332 is formed by a metal fill and polish back process. Referring to the left-hand portion of Figure 23L, the structure is shown to include a lower portion that includes a patterned ILD layer 2302' with metal lines and vias (shown collectively as 2332) formed therein. The over-structure region 2334 includes the second patterned hard mask 2312 and the remaining (plug location) photo barrels 2324 . In one embodiment, the upper region 2334 is removed (eg, by CMP or etch back) prior to subsequent fabrication. However, in an alternative embodiment, the upper region 2334 is left in the final structure.

The structure of Figure 23L can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 23L may represent the final metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations may be performed in alternate orders, not every operation needs to be performed and/or additional process operations may be performed. Referring again to Figure 23L, self-aligned fabrication by subtractive means can be accomplished at this stage. The next layer fabricated in a similar manner may require another full process start-up. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

In the second form, the plug first and the through hole second form are used. As an example, FIGS. 23M-23S illustrate portions of an integrated circuit layer that represent operations in a method of subtracting self-aligned via and plug patterning, according to another embodiment of the present invention. In each illustration of each of the described operations, the plan view is shown at the top and the corresponding cross-sectional view is shown at the bottom. These views will be referred to herein as the corresponding cross-sectional and plan views.

Figure 23M illustrates a plan view and corresponding cross-sectional view of a starting orthogonal grid formed over substrate 2351, in accordance with an embodiment of the present invention. Referring to plan views and corresponding cross-sectional views (a) and (b) taken along axes a-a' and bb', respectively, starting grid structure 2350 includes a grating ILD layer 2352 with a first hard mask The cap layer 2354 is disposed thereon. The second hard mask layer 2356 is disposed on the first hard mask layer 2354 and is patterned to have a grating structure orthogonal to the underlying grating structure. Additionally, openings 2358 remain between the grating structure of the second hard mask layer 2356 and the underlying grating formed by the ILD layer 2352 and the first hard mask layer 2354 .

23N illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 23M subsequent to opening fill and etch back, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a' and bb', respectively, the opening 2358 of FIG. 23M is filled with a dielectric layer 2360 (such as a silicon oxide layer) ). Such a dielectric layer 2360 may be formed with a deposited oxide film, such as by chemical vapor deposition (CVD), high density plasma deposition (HDP), or spin-on-dielectric. The deposited material may need to be etched back to achieve the relative height shown in Figure 23N, leaving the upper opening 2358'.

23O illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 23N following photobarrel filling, exposure, and development to leave selected plug locations, in accordance with an embodiment of the present invention. With reference to plan views and corresponding cross-sectional views (a) and (b) taken along axes a-a' and b-b', respectively, a light barrel is formed in upper opening 2358' of Figure 23N. After that, most of the light barrels were exposed and removed. However, the selected light barrel 2362 is not exposed and thus remains to provide the selected plug location, as shown in FIG. 23O.

23P illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 23O following removal of portions of dielectric layer 2360, in accordance with an embodiment of the present invention. With reference to the plan views and corresponding cross-sectional views (a) and (b) taken along axes a-a' and bb', respectively, the portion of dielectric layer 2360 not covered by photobarrel 2362 is removed . However, the portion of dielectric layer 2360 not covered by photo barrel 2362 remains in the structure of Figure 23P. In one embodiment, the portion of the dielectric layer 2360 not covered by the photobarrel 2362 is removed by a wet etch process.

23Q illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 23P following photobarrel filling, exposure, and development to leave selected via locations, in accordance with an embodiment of the present invention. With reference to the plan views and corresponding cross-sectional views (a) and (b) taken along axes a-a' and bb', respectively, the photobarrel is formed upon removal of the portion of the dielectric layer 2360 formed in the opening. Afterwards, selected photo barrels are exposed and removed to provide selected via locations 2364, as shown in Figure 23Q.

23R illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 23Q following the etching of the via opening into the underlying ILD, in accordance with an embodiment of the present invention. Referring to the respective plan views and corresponding cross-sectional views (a) and (b) taken along axes a-a' and bb', via location 2364 of FIG. 23Q is subjected to a selective etching process such as selective plasma etching process) to extend via opening 2364 to opening 2364', which is formed into the underlying ILD layer 2352.

23S illustrates a plan view and corresponding cross-sectional view of the structure of FIG. 23R following removal of the second hardmask layer and remaining photobucket material, in accordance with an embodiment of the present invention. Referring to the respective plan views and corresponding cross-sectional views (a) and (b) taken along axes a-a' and bb', the second hard mask layer 2356 and any remaining light barrel material (also That is, the photobarrel material that has not been exposed and developed) is removed. The removal is performed selectively for all other remaining features. In one such embodiment, the second hardmask layer 2356 is a carbon-based hardmask material, and the removal is performed by an _O2 plasma ash process. Referring again to Figure 23S, what remains at this stage is: ILD layer 2352 with via openings 2364' formed therein, and the portion of dielectric layer 2360 that is reserved for plug locations (eg, reserved by the photobarrel material above) . Thus, in one embodiment, the structure of FIG. 23S includes an ILD layer 2352 patterned with via openings (for subsequent metal fill) with locations for a dielectric layer 2360 to create plugs. The remaining openings 2366 may be filled with metal to form metal lines. It should be understood that its hard mask 2354 can be removed.

Thus, once filled with metal interconnect material, the structure of Figure 23S can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, once filled with metal interconnect material, the structure of Figure 23S may represent the final metal interconnect layer in an integrated circuit. Referring again to Figure 23S, self-aligned fabrication by subtractive means can be accomplished at this stage. The next layer fabricated in a similar manner may require another full process start-up. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

It should be understood that the manner described in connection with Figures 23A-23L and 23M-23S is not necessarily performed to form vias aligned with the underlying metallization layers. As such, in some contexts, these process schemes may be viewed as involving a top-down blind shot against any underlying metallization layers. In a third form, the subtractive approach provides alignment with the underlying metallization. For example, FIGS. 24A-24I illustrate portions of integrated circuit layers that represent operations in a method of subtracting self-aligned plug patterning, in accordance with another embodiment of the present invention. In each illustration describing the operation, an oblique three-dimensional cross-sectional view is provided.

FIG. 24A illustrates a starting point structure 2400 for a subtractive via and plug process following deep metal line fabrication, in accordance with an embodiment of the present invention. Referring to FIG. 24A , structure 2400 includes metal lines 2402 with interlayer dielectric (ILD) lines 2404 . It should also be understood that certain lines 2402 may be associated with underlying vias for coupling to previous interconnect layers. In one embodiment, metal lines 2402 are formed by patterning trenches into the ILD material (eg, the ILD material of line 2404). The trenches are then filled with metal and, if necessary, planarized to the top of the ILD line 2404. In one embodiment, the metal trench and fill process involves high aspect ratio features. For example, in one embodiment, the aspect ratio of the metal line height (h) to the metal line width (w) is in the range of about 5-10.

24B illustrates the structure of FIG. 24A following the recess of the metal line, in accordance with an embodiment of the present invention. Referring to FIG. 24B , metal lines 2402 are selectively recessed to provide first-level metal lines 2406 . Recessing is performed selectively on the ILD line 2404 . The recessing can be performed by etching through dry etching, wet etching, or a combination thereof. The degree of recess may be determined by the target thickness of the first level metal lines 2406 for use as appropriate conductive interconnects within a back end of line (BEOL) interconnect structure.

24C illustrates the structure of FIG. 24B following the formation of an interlevel dielectric (ILD) layer, in accordance with an embodiment of the present invention. Referring to FIG. 24C , a layer 2408 of ILD material is deposited and, if necessary, planarized to a level above recessed metal lines 2406 and ILD lines 2404 .

24D illustrates the structure of FIG. 24C following deposition and patterning of a hard mask layer, in accordance with an embodiment of the present invention. Referring to FIG. 24D , a hard mask layer 2410 is formed on the ILD layer 2408 . In one such embodiment, the hard mask layer 2410 is formed with a grating pattern orthogonal to the grating pattern of the first order metal lines 2406/ILD lines 2404, as shown in Figure 24D. In one embodiment, the grating structure formed by the hard mask layer 2410 is a close-pitch grating structure. In this embodiment, tight pitch cannot be achieved directly by conventional lithography. For example, a pattern according to conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask. Even, the original pitch can be reduced by a quarter by a second round of spacer mask patterning. Thus, the grating-like pattern of the second hard mask layer 2410 of FIG. 24D may have hard mask lines of constant width separated by a constant pitch.

24E illustrates the structure of FIG. 24D following the formation of trenches defined using the pattern of the hardmask of FIG. 24D, in accordance with an embodiment of the present invention. Referring to FIG. 24E , exposed regions of ILD layer 2408 (ie, those not protected by 2410 ) are etched to form trenches 2412 and patterned ILD layer 2414 . The etch stops on (and thus exposes) the top surfaces of the first level metal lines 2406 and ILD lines 2404 .

Figure 24F illustrates the structure of Figure 24E following the formation of photobarrels in all possible via locations, in accordance with an embodiment of the present invention. Referring to FIG. 24F , photo barrels 2416 are formed in all possible via locations over exposed portions of recessed metal lines 2406 . In one embodiment, light barrel 2416 is formed substantially coplanar with the top surface of ILD line 2404, as depicted in Figure 24F. Additionally, referring again to FIG. 24F , the hard mask layer 2410 may be removed from the patterned ILD layer 2414 .

Figure 24G illustrates the structure of Figure 24F following via location selection, in accordance with an embodiment of the present invention. Referring to Figure 24G, the light barrel 2416 from Figure 24F is removed when the via location 2418 is selected. In locations that are not selected to form vias, photobuckets 2416 are retained. In one embodiment, to form the via locations 2418, lithography is used to expose the corresponding photo barrels 2416. The exposed photobucket can then be removed with the developer.

Figure 24H illustrates the structure of Figure 24G following conversion of the remaining photobuckets to permanent ILD material, in accordance with an embodiment of the present invention. Referring to FIG. 24H, the material of the light barrel 2416 is modified (eg, by cross-linking during a bake operation) in place to form the final ILD material 2420. In one such embodiment, the cross-linking provides solubility switching upon baking. The final, cross-linked material has inter-dielectric properties and thus can be retained in the final metallization structure.

Referring again to Figure 24H, in one embodiment, the resulting structure includes up to three distinct regions of dielectric material (ILD line 2404 + ILD line 2414 + cross-linked photobarrel 2420) in a single plane 2450 of the metallization structure. In this embodiment, both or all of ILD line 2404, ILD line 2414, and cross-linked photobarrel 2420 are composed of the same material. In another such embodiment, the ILD line 2404, the ILD line 2414, and the cross-linked photobarrel 2420 are all composed of different ILD materials. In either case, in a particular embodiment, vertical seams (eg, seam 2497) and/or between the materials of ILD wire 2404 and ILD wire 2414 may be observed in the final structure. A vertical seam (eg, seam 2498 ) between the ILD line 2404 and the cross-linked light barrel 2420 and/or a vertical seam (eg, seam 2499 ) between the ILD line 2414 and the cross-linked light barrel 2420 , etc. the difference.

Figure 24I illustrates the structure of Figure 24H following the formation of metal lines and vias, in accordance with an embodiment of the present invention. Referring to Figure 24I, metal lines 2422 and vias 2424 are formed on the metal fill of the opening of Figure 24H. Metal line 2422 is coupled to underlying metal line 2406 by via 2424. In one embodiment, the openings are filled in damascene or bottom-up filling to provide the structure shown in Figure 24I. Accordingly, the deposition of metals (eg, copper and associated barrier and seed layers) used to form metal lines and vias in the above-described manner may be typically used by standard back-end-of-line (BEOL) processors. In one embodiment, in subsequent fabrication operations, the ILD lines 2414 may be removed to provide air gaps between the resulting metal lines 2424 .

The structure of Figure 24I can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 24I may represent the final metal interconnect layer in an integrated circuit. Referring again to Figure 24I, self-aligned fabrication by subtractive means can be accomplished at this stage. The next layer fabricated in a similar manner may require another full process start-up. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

According to an embodiment of the present invention, a polychromatic light barrel is described. One or more embodiments described herein pertain to the use of polychromatic light barrels as a way to handle plug and via fabrication below lithography pitch limitations. One or more embodiments described herein relate to a subtractive approach for self-aligned via and plug patterning, and the resulting structures. In one embodiment, the procedures described herein enable the realization of self-aligned metallization for back-end-of-process feature fabrication. Overlap issues anticipated for the next generation of via and plug patterning may be addressed in one or more of the ways described herein.

In an exemplary embodiment, the approach described below builds on the approach using a so-called photobucket, in which every possible feature (eg, a via) is repatterned into the substrate. Next, photoresist is filled into the patterned features and a lithography operation is used only to select selected vias for via opening formation. In the specific embodiment described below, a lithography operation is used to define relatively large holes over a plurality of "polychromatic light barrels", which can then be opened by bulk exposure of specific wavelengths. The polychromatic light-bucket approach allows for larger critical dimension (CD) and/or overlap errors while retaining the ability to select vias of interest. In one such embodiment, trenches are used to contain the resist itself, and most wavelengths of the bulk exposure are used to selectively open vias of interest.

More specifically, one or more of the embodiments described herein relate to using a subtractive method to preform each via or via opening using etched trenches. An additional operation is then used to select which vias and plugs to keep. These operations can be illustrated using photobuckets, although a more traditional resist exposure and ILD backfill approach can also be used to perform the selection process.

In one example, a self-aligned via opening approach may be used. As an example processing scheme, FIGS. 25A-25H illustrate portions of integrated circuit layers that represent various operations in a method of subtractive self-aligned via patterning using a multicolor photobucket, in accordance with embodiments of the present invention. In each illustration of each described operation, a cross-sectional view is shown.

25A illustrates a cross-sectional view of the starting structure 2500 after deposition (but before patterning) of the first hard mask material layer 2504 formed on the interlayer dielectric (ILD) layer 2502, in accordance with an embodiment of the present invention . Referring to FIG. 25A, the patterned mask 2506 has spacers 2508 formed on or over the first layer of hard mask material 2504 (along its sidewalls).

25B illustrates the structure of FIG. 25A following the first patterning of the first hard mask layer and subsequent first color photobucket filling, in accordance with an embodiment of the present invention. Referring to FIG. 25B , the patterned mask 2506 and corresponding spacers 2508 are used together as a mask during the etch to form the trenches 2510 through the first hard mask material layer 2504 and partially into the ILD layer 2502 . Trenches 2510 are then filled with first color light barrels 2512.

25C illustrates the structure of FIG. 25B following a second patterning of the first hard mask layer and subsequent second color photobucket filling, in accordance with an embodiment of the present invention. Referring to FIG. 25C , the patterned mask 2506 is removed and the second plurality of trenches 2514 are etched through the first hard mask material layer 2504 and partially into the ILD layer 2502 , between the spacers 2508 . Afterwards, the trenches 2514 are filled with a layer 2516 of a second color light barrel material.

Referring again to FIG. 25C , the negative pattern of spacers 2508 is thus transferred (eg, by two etching processes forming trenches 2510 and 2514 ) to the first layer of hard mask material 2504 . In one such embodiment, spacers 2508 (and thus trenches 2510 and 2514) are formed in a grating pattern, as depicted in Figure 25C. In one embodiment, the grating pattern is a tight pitch grating pattern. In a particular such embodiment, tight pitch cannot be achieved directly by conventional lithography. For example, the pattern according to conventional lithography can be first limited to mask 2506, but the pitch can be halved by mask patterning using negative spacers, as depicted in Figures 25A-25C. Even, although not shown, the original pitch can be reduced by a quarter by a second round of spacer mask patterning. Thus, the raster-like patterns of light barrels 2512 and 2516 are (collectively) separated by a constant pitch and have a constant width.

25D illustrates the structure of FIG. 25C following planarization to isolate the first and second color photo barrels from each other, in accordance with an embodiment of the present invention. Referring to Figure 25D, the top portions of the second color photobarrel material layer 2516 and spacers 2508 are planarized, eg, by chemical mechanical polishing (CMP), until the top surface of the first color photobarrel 2512 is exposed, forming discrete The second color light barrel 2518 is formed from the light barrel material layer 2516 . In one embodiment, the combination of the first color light barrel 2512 and the second color light barrel 2518 represents all possible via locations in the subsequently formed metallization structure.

Figure 25E illustrates the structure of Figure 25D following exposure and development of the first color photobucket to leave selected via locations, in accordance with an embodiment of the present invention. Referring to FIG. 25E, a second hard mask 2520 is formed and patterned on the structure of FIG. 25D. The patterned second hard mask 2520 reveals the selected first color light bucket 2512A. Selected photo barrels 2512A are exposed to light exposure and removed (ie, developed) to provide selected via openings 2513A. It should be understood that the description herein related to forming and patterning a hard mask layer refers to (in one embodiment) a mask being formed over a later overlying hard mask. Mask formation may involve the use of one or more layers suitable for lithographic processing. When patterning one or more lithographic layers, the pattern is transferred to the hard mask layer by an etching process to provide a patterned hard mask layer.

Referring again to FIG. 25E, it may not be possible to expose only the selected photo barrels 2512A when the second hard mask layer 2520 is patterned. For example, one or more adjacent (or nearby) second color light barrels 2518 may also be revealed. These additional exposed light barrels may not be the desired locations for final via formation. However, any exposed second color photo barrels 2518 (in one embodiment) are not modified when exposed to the illumination it used to pattern the group of first color photo barrels 2512. For example, in one embodiment, the first color photobucket 2512 is subject to a red bulk exposure 2521 and can be developed to remove a selection of the first color photobucket 2512, as shown in Figure 25E. In this embodiment, the second color light barrel 2518 is not susceptible to red bulk exposure, and thus, cannot be developed and removed, even if exposed during red bulk exposure, as shown in Figure 25E. In one embodiment, with adjacent photobarrels having different exposure to exposure, greater pattern and/or deviation tolerances may be provided to relax constraints otherwise associated with patterning the second hard mask layer 2520.

25F illustrates the structure of FIG. 25E following exposure and development of the second color photobucket to leave additional selected via locations, in accordance with an embodiment of the present invention. Referring to Figure 25F, a third hard mask 2522 is formed and patterned on the structure of Figure 25E. A third hard mask 2522 may also fill selected via openings 2513A, as depicted in Figure 25F. The patterned third hard mask 2522 reveals the selected second color light buckets 2518A and 2518B. Selected photo barrels 2518A and 2518B are exposed to light irradiation and removed (ie, developed) to individually provide selected via openings 2519A and 2519B.

Referring again to FIG. 25F, it may not be possible to expose only selected photo barrels 2518A and 2518B when the third hard mask layer 2522 is patterned. For example, one or more adjacent (or nearby) first color light barrels 2512 may also be revealed. These additional exposed light barrels may not be the desired locations for final via formation. However, any exposed first color photo barrels 2512 (in one embodiment) are not modified when exposed to the illumination it used to pattern the group of second color photo barrels 2518. For example, in one embodiment, the second color photobucket 2518 is susceptible to green bulk exposure 2523 and can be developed to remove a selection of the second color photobucket 2518, as shown in Figure 25F. In this embodiment, the first color light barrel 2512 is not susceptible to green bulk exposure, and thus, cannot be developed and removed, even if exposed during green bulk exposure, as shown in Figure 25F. In one embodiment, greater pattern and/or deviation tolerances may be provided to relax constraints otherwise associated with patterning the third hard mask layer 2522 by having adjacent photobarrels with different exposure to exposure.

25G illustrates the structure of FIG. 25F following removal and etching of the third hard mask layer to form via locations, in accordance with an embodiment of the present invention. Referring to Figure 25G, the third hard mask layer 2522 is removed. In one such embodiment, the third hard mask layer 2522 is a carbon-based hard mask layer and is removed by an ashing process. Next, the pattern of via openings 2519A, 2513A, and 2519B is subjected to a selective etching process, such as a selective plasma etching process, to extend the via openings deeper into the underlying ILD layer 2502, forming a via pattern with via locations 2524 The doped ILD layer 2502'. The etching is selective to the remaining photobuckets 2512 and 2518 and to the spacer 2508 .

Figure 25H illustrates the structure of Figure 25G prior to metal filling, in accordance with an embodiment of the present invention. Referring to Figure 25H, all remaining first and second color light barrels 2512 and 2518 are removed. The remaining first and second color photobuckets 2512 and 2518 can be removed directly, or can be exposed and developed first to enable removal. Removal of the remaining first and second color photo barrels 2512 and 2518 provides metal line trenches 2526, which are partially coupled to via locations 2524 in the patterned ILD layer 2502'. Subsequent processing may include removal of spacers 2508 and hard mask layer 2504 , and metal filling of metal line trenches 2526 and via locations 2504 . In one such embodiment, the metallization is formed by a metal fill and polish back process.

The structure of Figure 25H (when metal filled) can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 25H (when metal filled) may represent the last metal interconnect layer in an integrated circuit. Referring again to Figure 25H, self-aligned fabrication by subtractive means can be accomplished at this stage. The next layer fabricated in a similar manner may require another full process start-up. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

Referring again to Figures 25A-25H, several options may be considered for providing a first color light bucket 2512 and a second color light bucket 2518. For example, in one embodiment, two different positive tone organic photoresists are used. It should be understood that in one such embodiment, materials with different chemical structures may be selected for the first color photobarrel 2512 and the second color photobarrel 2518 to allow for different coating, photoactivation, and development processes to be used . As an example embodiment, a conventional 193 nm lithographic polymethacrylate resist system was selected for the first color photobarrel 2512, and a conventional 248 nm polyhydroxystyrene photoresist system was selected for the second color light. Barrel 2518. The significant chemical difference between these two types of resins allows two different organic casting solvents to be used; this may be necessary because the material of the second color light barrel 2518 is coated with its preexisting first color light Material for barrel 2512. The casting solvent used for the first color light barrel 2512 is not limited; while for the second color light barrel 2518, an alcohol solvent may be used because it can still dissolve the PHS material but not the more apolar polymethacrylates.

The combination of the polymethacrylate resin used as the material of the first color light barrel 2512 and the polyhydroxystyrene resin used as the material of the second color light barrel 2518 can (in one embodiment) enable the two to be used different exposure wavelengths. Typical 193nm lithographic polymers are based on polymethacrylates with 193nm absorbing photoacid generators (PAGs) because polymers do not absorb strongly at this wavelength. On the other hand, polyhydroxystyrene may not be suitable because it absorbs strongly at 193 nm and prevents activation of PAGs throughout the membrane. Next, in one embodiment, the material of the first color photobarrel 2512 can be selectively activated and developed in the presence of 193 nm photons. To accentuate the difference in light speed between the first color light bucket 2512 and the second color light bucket 2518, factors such as PAG absorption at 193 nm, PAG loading, and photoacid intensity can be tuned for each. Additionally, a strong 193 nm absorber can be added to (or selectively deposited on top of the second color photobarrel 2518) to reduce PAG activation within the bulk film. Following exposure, in certain embodiments, development of the first color photobucket 2512 is selectively performed with standard TMAH developer, where minimal development of the second color photobucket 2518 will occur.

In one embodiment, to selectively remove the second color light barrel 2518 (in the presence of the first color light barrel 2512), a second lower energy wavelength is used that activates only the second color light barrel 2518 instead of the PAG in the first color light barrel 2512. This can be achieved in two ways. First, in one embodiment, PAGs with different absorption properties are used. For example, trihydrocarbyl perionium salts have very low absorption at wavelengths such as 248 nm, while triaryl perionium salts have very high absorption. Thus, selectivity is achieved by using triaryl perionium or other 248 nm absorbing PAGs in the second color light barrel 2518 and using trihydrocarbyl perionium or other non-248 nm absorbing PAGs in the first color light barrel 2512. Alternatively, a sensitizer can be incorporated into the second color photobucket 2518 that absorbs low energy photons selectively in the second color photobucket 2518 and transfers energy to the PAG without activation occurring in the first color photobucket 2512 in (because no sensitizer is present).

In another embodiment, Figure 25I illustrates an example duotone resist for one photobarrel type and an exemplary monotone resist for another photobarrel type, in accordance with embodiments of the present invention. Referring to FIG. 25I, in one embodiment, a dual tone photoresist system (PB-1) is used for the material of the first color photo barrel 2512. A single tone (slow) photoresist system (PB-2) was used for the second color photo barrel 2518 material. Dual tone photoresists can be characterized as having a photoresponse that is effectively shut down at higher doses due to activation of the photo-based generators included in the system. The light-generated radicals neutralize the photoacid and prevent deprotection of the polymer. In one embodiment, during exposure of the first color photobucket 2512, the dose is selected such that its dual-tone resist (PB-1) operates as a fast positive tone system, while the single-tone resist (PB-2) ) has not received enough photons for soluble switching to be activated. This allows PB-1 to be removed with TMAH developer without removing PB-2. In order to selectively remove PB-2 without removing PB-1, a higher dose is used for the second exposure (ie, the exposure of the second color light barrel 2518). The dose chosen must activate enough PAG in PB-2 to allow dissolution in TMAH and through activation of PBG to move PB-2 into the negative tone response area. In this scheme, the same PAG can be used for PB-1 and PB-2 and the same exposure wavelength can be used for exposures 1 and 2. It is understood that PB-1 may require incorporation of a photo-based generator (PBG); however, it is likely that it will require a different type of polymer to allow coating of PB-2 (once PB-1 has been coated). As mentioned above, the use of a polymethacrylate type resist for PB-1 and a PHS type for PB-2 can satisfy this need.

It should be understood that the materials specified above for the first and second color light barrels 2512 and 2518 individually may be exchanged in accordance with embodiments of the present invention. Meanwhile, the above-described multi-color light barrel approach may be referred to as 1-D. A similar approach can be applied to 2-D systems using cross gratings, although the light barrel material will have to withstand etching and cleaning from the cross gratings described above. The result would be a checkerboard type pattern with smaller vias/plugs in the vertical direction, relative to those in the above-described approach. Furthermore, it should be understood that the manner described in connection with Figures 25A-25H is not necessarily performed to form vias aligned to the underlying metallization layer, although it may certainly be implemented as such. In other contexts, these process schemes can be viewed as involving blind shooting in a top-down direction against any underlying metallization layers.

According to an embodiment of the present invention, a light barrel for a conductive sheet is described.

For example, Figure 26A illustrates a plan view of a conventional back end of line (BEOL) metallization layer. Referring to FIG. 26A, a conventional BEOL metallization layer 2600 is shown with conductive lines or routings 2604 disposed in the interlayer dielectric layer 2602. The metal lines may extend generally parallel to each other and may include cuts, breaks or plugs 2606 in the continuation of one or more of the conductive lines 2604. To electrically couple two or more of the parallel metal lines, upper or lower level routing 2608 is included in the previous or next metallization layer. The upper or lower level routing 2608 may include a conductive line 2610 coupled to a conductive via 2612. It should be understood that because the upper or lower layer routing 2608 is included in the previous or next metallization layer, the upper or lower layer routing 2608 may consume vertical real estate of the semiconductor structure in which it includes the metallization layer.

In contrast, FIG. 26B illustrates a plan view of a back end of line (BEOL) metallization layer having conductive pads to couple the metal lines of the metallization layer, in accordance with an embodiment of the present invention. Referring to FIG. 26B, a BEOL metallization layer 2650 is shown with conductive lines or routings 2654 disposed in an interlayer dielectric layer 2652. The metal lines may extend generally parallel to each other and may include cuts, breaks, or plugs 2656 in the continuation of one or more of the conductive lines 2654. Conductive sheet 158 is included in metallization layer 2650 in order to electrically couple two or more of the parallel metal lines. It will be appreciated that because the conductive pad 2658 is included in the same metallization layer as the conductive line 2654, the vertical real estate conductive pad 2658 consumption of the semiconductor structure including the metallization layer can be reduced relative to the structure of Figure 26A.

One or more embodiments described herein relate to a photobucket approach for damascene plug and wafer patterning. Such patterning schemes can be implemented to enable bidirectional spacer-based interconnects. Embodiments may be particularly suitable for electrically connecting two parallel lines of metallization layers, wherein the two metal lines are fabricated using a spacer-based approach that may otherwise be restricted to the same metallization layer. Including the conductive connection between two adjacent lines. Generally, one or more embodiments relate to an approach that utilizes a damascene technique to form conductive sheets and non-conductive spaces or breaks (plugs) between metals.

More specifically, one or more of the embodiments described herein relate to the use of a damascene method to form sheets and plugs. Initially, each possible patch and plug location is first patterned in the hard mask layer. An additional operation is then used to select which slices and plug locations to keep. These locations are then transferred into the underlying interlevel dielectric layer. Such operations can be illustrated using light barrels. In certain embodiments, a method for damascene patterning of vias, plugs, and sheets is provided for self-alignment, using a photobucket approach and selective hardmasking.

In accordance with embodiments of the present invention, light barrel patterning is used to fabricate plugs and sheets in a self-aligned manner. General Overview A process flow may involve (1) the fabrication of cross gratings, followed by (2) photobarrelization for plug definition and changing the photoresist to a "hard" material that can withstand downstream processing, followed by ( 3) By backfilling with refillable material, recessing the refillable material, and removing the raster tone inversion of the original cross grating, followed by (4) for "slice" defined photobucketing, followed by (5) The pattern etch is transferred into the underlying interlevel dielectric (ILD) layer and the additional hard mask material is polished away. It should be understood that although the general process flow does not include vias, in one embodiment, the approaches described herein can be implemented to extend to multi-pass plugs, vias, and pads using the same self-aligned grating.

For example, FIGS. 27A-27K illustrate oblique cross-sectional views representing various operations in a method of fabricating a back end of line (BEOL) metallization layer having conductive sheets to couple the metal of the metallization layer line, according to an embodiment of the present invention.

Referring to FIG. 27A , the first operation in the cross grating patterning scheme is performed over an interlayer dielectric (ILD) layer 2702 , which is formed over a substrate 2700 . Overlay hardmask 2704 is first formed on ILD layer 2702. A first grating hard mask 2706 is formed along a first direction overlying the hard mask 2704 . In one embodiment, the first grating hardmask 2706 is formed in a grating pattern, as depicted in Figure 27A. In one embodiment, the grating structure of the first grating hard mask 2706 is a tight-pitch grating structure. In a particular such embodiment, tight pitch cannot be achieved directly by conventional lithography. For example, a pattern according to conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask. Even, the original pitch can be reduced by a quarter by a second round of spacer mask patterning. Thus, the raster-like pattern of the first grating hardmask 2706 of FIG. 27A can have hardmask lines of constant width that are closely spaced with a constant pitch.

Referring to FIG. 27B , a second operation in the cross grating patterning scheme is performed over an interlayer dielectric (ILD) layer 2702 . A second grating hard mask 2708 is formed along the second direction overlying the hard mask 2704 . The second direction is orthogonal to the first direction. The second grating hardmask 2708 has an overlying hardmask 2710. In one embodiment, the second grating hardmask 2710 is fabricated in a patterning process using an overlying hardmask 2710. The continuity of the second raster hardmask 2708 is interrupted by the lines of the first raster hardmask 2706 , and as such, portions of the first raster hardmask 2706 extend below the overlying hardmask 2710 . In one embodiment, the second grating hardmask 2708 is formed to be interleaved with the first grating hardmask 2706 . In one such embodiment, the second grating hardmask 2708 is formed by deposition of a second layer of hardmask material (having a different composition than the first grating hardmask 2706). The second layer of hard mask material is then planarized (eg, by chemical mechanical polishing (CMP)), and then patterned using an overlying hard mask 2710 to provide a second grating hard mask 2708 . As was the case for the first grating hardmask 2706, in one embodiment, the grating structure of the second grating hardmask 2708 is a tight-pitch grating structure. In a particular such embodiment, tight pitch cannot be achieved directly by conventional lithography. For example, a pattern according to conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask. Even, the original pitch can be reduced by a quarter by a second round of spacer mask patterning. Thus, the grating-like pattern of the second grating hardmask 2708 of FIG. 27A can have hardmask lines of constant width that are closely spaced with a constant pitch.

Referring to FIG. 27C, the plug photobarrel patterning scheme is performed as the first photobarrel process. In one embodiment, light barrels 2712 are formed over all exposed openings between the first grating hardmask 2706 and the second grating hardmask 2708. In one embodiment, the via patterning process is selectively performed before the plug photo barrel patterning process. Via patterning may be direct patterning or may involve a separate photobarrel process.

Referring to Figure 27D, selected ones of the photo barrels 2712 are removed while other photo barrels 2712 are retained, eg, by leaving the selected photo barrels 2712 unexposed to a lithography and development process that opens all other photo barrels 2712 . The exposed portion of FIG. 27A that covers the hardmask 2704 is then etched to provide the first patterned hardmask 2714. The remaining photobuckets 2712 (at this stage) represent the plug locations in the final metallization layer. That is, in the first photobarrel process, the photobarrel is removed from the position where the plug will not be formed. In one embodiment, to form locations where plugs will not be formed, lithography is used to expose the corresponding photo barrels. The exposed photobucket can then be removed with the developer.

Referring to Figure 27E, the raster tone inversion process is performed. In one embodiment, dielectric regions 2716 are formed in all exposed regions of the structure of Figure 27D. In one embodiment, the dielectric regions 2716 are formed by deposition of a dielectric layer and etching back to form the dielectric regions 2716 .

Referring to FIG. 27F , the portion of the first grating hardmask 2706 not covered by the overlying hardmask 2710 is then removed to leave only the first grating hardmask remaining under the overlying hardmask 2710 Part 2706' of 2706.

Referring to FIG. 27G, the sheet photobarrel patterning scheme is performed as a second photobarrel process. In one embodiment, light barrels 2718 are formed in all exposed openings formed upon removal of exposed portions of the first grating hardmask 2706.

Referring to Figure 27H, selected ones of the photo barrels 2718 are removed while the other photo barrels 2718 are retained, eg, by leaving the photo barrels 2718 unexposed to a lithography and development process used to open the other photo barrels. The exposed portions of the first patterned hardmask 2714 of FIGS. 27D-27G are then etched to provide the second patterned hardmask 2715. The remaining photobuckets 2718 (at this stage) represent the locations where the conductive sheet will not be in the final metallization layer. That is, in the second photobarrel process, the photobarrel is removed from the position where the conductive sheet will be finally formed. In one embodiment, to form the locations where the conductive sheets are to be formed, lithography is used to expose the corresponding photo barrels. The exposed photobucket can then be removed with the developer.

Referring to Figure 27I, the overlying hard mask 2710, the second grating hard mask 2708, and the dielectric region 2716 are removed. Afterwards, the portion of the second patterned hard mask 2715 exposed during the removal of the overlying hard mask 2710 is removed to provide the third patterned hard mask 2720, the second grating hard mask 2708, and dielectric region 2716 is removed. In one embodiment, the remainder of the photo barrels 2712 and 2718 is first hardened (eg, by a bake process), before removing the overlying hard mask 2710, the second grating hard mask 2708, and the dielectric region 2716 Before. At this stage, selected ones of photobucket 2712, selected ones of photobucket 2718, and remaining portion 2706' of first raster hardmask 2706 remain over third patterned hardmask 2720. In one embodiment, overlying hardmask 2710, second grating hardmask 2708, and dielectric region 2716 are removed using a selective wet etch process, while overlying hardmask 2710 is removed The exposed portion of the second patterned hard mask 2715 is removed using a dry etch process to provide the third patterned hard mask 2720 .

Referring to FIG. 27J , the pattern of the third patterned hard mask 2720 is transferred to the upper portion of the ILD layer 2702 to form a patterned ILD layer 2722 . In one embodiment, the plug and sheet patterns of the third patterned hard mask 2720 are then transferred to the ILD layer 2702 to form the patterned ILD layer 2722 . In one embodiment, an etch process is used to transfer the pattern into the ILD layer 2702. In one such embodiment, the selected ones of the photobuckets 2712, the selected ones of the photobuckets 2718, and the remaining portion 2706' of the first raster hardmask 2706 remaining over the third patterned hardmask 2720 is removed or lost during the etch it is used to form the patterned ILD layer 2722. In another embodiment, the selected ones of the photobuckets 2712, the selected ones of the photobuckets 2718, and the remaining portion 2706' of the first raster hardmask 2706 remaining over the third patterned hardmask 2720 are Removed before or after its etch to form patterned ILD layer 2722.

Referring to FIG. 27K, following the formation of the patterned ILD layer 2732, conductive lines 2724 are formed. In one embodiment, the conductive lines 2724 are formed using a metal fill and polish back process. During the formation of the conductive lines 2724, a conductive sheet 2728 coupling the two metal lines 2724 is also formed. Thus, in one embodiment, conductive couplings (sheets 2728 ) between conductive lines 2724 are formed at the same instant as conductive lines 2724 , in the same ILD layer 2722 , and in the same plane as conductive lines 2724 . Additionally, the plugs 2726 may be formed as breaks or interruptions in one or more of the conductive lines 2724, as depicted in Figure 27K. In one such embodiment, the plug 2726 is the area of the ILD layer 2702 that is reserved for the pattern transfer used to form the patterned ILD layer 2722. In one embodiment, the third patterned hard mask 2720 is removed, as depicted in Figure 27K. In one such embodiment, the third patterned hard mask 2720 is removed after forming the conductive lines 2724 and sheets 2728, eg, using a post-metallization chemical mechanical planarization (CMP) process.

Referring again to FIG. 27K , in one embodiment, a back end of line (BEOL) metallization layer for semiconductor structures includes an interlayer dielectric (ILD) layer 2722 disposed over substrate 2700 . A plurality of conductive lines 2724 are disposed in the ILD layer 2722 along the first direction. The conductive sheet 2728 is disposed in the ILD layer 2722 . The conductive sheet couples both of the plurality of conductive lines 2724 along a second direction orthogonal to the first direction.

Such a configuration as shown in Figure 27K cannot otherwise be achieved by conventional lithography processing (at small pitch, small width, or both). At the same time, self-alignment cannot be achieved using conventional processes. Furthermore, the configuration shown in FIG. 27K cannot otherwise be achieved in situations where a pitch division scheme is used to finally provide a pattern of conductive lines 2724.

In one embodiment, both the conductive sheet 2728 and the plurality of conductive lines are continuous rather than contiguous, as depicted in Figure 27K. In one embodiment, both the conductive sheet 2728 and the plurality of conductive lines 2724 are coplanar, as depicted in Figure 27K. In one embodiment, the BEOL metallization layer further includes a dielectric plug 2726 disposed on the end of one of the plurality of conductive lines 2724, as depicted in Figure 27K. In one embodiment, the dielectric plug 2726 is continuous with the ILD layer, rather than contiguous, as depicted in Figure 27K. In one embodiment, although not shown, the BEOL metallization layer further includes conductive vias disposed under and electrically coupled to one of the plurality of conductive lines 2724 .

The structure of Figure 27K can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of FIG. 3K may represent the final metal interconnect layer in an integrated circuit. Referring to Figure 27K, this self-aligned fabrication by damascene photobucket approach can be continued to fabricate the next metallization layer. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches. It should also be understood that, although not depicted, one or more of the conductive lines 2724 may be coupled to underlying conductive vias, which may be formed using additional photobucket operations. In one embodiment, as an alternative to the two-dimensional approach described above, a one-dimensional grating approach can also be implemented for plug and wafer (and possibly via) patterning. This one-dimensional approach provides limited to only one direction. As such, the pitch can be "tight" in one direction and "loose" in one direction.

One or more embodiments described herein relate to a photobucket approach for subtractive plug and sheet patterning. Such patterning schemes can be implemented to enable bidirectional spacer-based interconnects. Embodiments may be particularly suitable for electrically connecting two parallel lines of metallization layers, wherein the two metal lines are fabricated using a spacer-based approach that may otherwise be restricted to the same metallization layer. Including the conductive connection between two adjacent lines. Generally, one or more embodiments relate to a manner that utilizes a subtractive technique to form conductive sheets and non-conductive spaces or breaks between metals (plugs).

One or more embodiments described herein provide a way to subtractively pattern vias, cuts, and/or sheets with self-alignment using photobucketing and selective hardmasking. Embodiments may involve subtractive patterning of self-aligned interconnects, plugs, and vias using so-called fabric patterning. The fabric approach may involve the implementation of the fabric pattern of the hard mask, taking advantage of the etch selectivity between the various hard mask materials. In particular embodiments described herein, fabric treatment schemes are implemented to pattern interconnects, cuts, and vias subtractively.

As an overview of one or more of the embodiments described herein, a general overview process flow may involve the following process sequence: (1) Using a fabric process that utilizes four "color" hard masks that are etch selective to each other Fabrication of the flow, (2) removing the first of the hardmask types for photobucketing of the vias, (3) backfilling the first hardmask material, (4) removing the photobucket for dicing (or plugging) The second type of hard mask type that is modified, (5) backfill the second hard mask material, (6) remove the third type of hard mask for light barrelization of the conductive sheet, (7) reduce the ground Etch cut and sheet metal, and (8) hard mask removal and subsequent backfill and polish back with permanent ILD material.

Figures 28A-28T illustrate oblique cross-sectional views representing various operations in a method of fabricating a back end of line (BEOL) metallization layer having conductive sheets to couple the metal lines of the metallization layer, in accordance with the present invention. Examples of inventions.

Referring to FIG. 28A, a grating patterning scheme is performed over an overlying hard mask layer 2802 formed over a metal layer 2800 formed over a substrate (not shown) . A first grating hard mask 2804 is formed along a first direction overlying the hard mask 2802 . The second grating hardmask 2806 is formed along the first direction and alternates with the first grating hardmask 2804 . In one embodiment, the first grating hardmask 2804 is formed from a material having a different etch selectivity than the material of the second grating hardmask 2806 .

In one embodiment, the first and second grating hardmasks 2804 and 2806 are formed in a grating pattern, as depicted in Figure 28A. In one embodiment, the grating structures of the first and second grating hardmasks 2804 and 2806 are close-pitch grating structures. In a particular such embodiment, tight pitch cannot be achieved directly by conventional lithography. For example, a pattern according to conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask. Even, the original pitch can be reduced by a quarter by a second round of spacer mask patterning. Thus, the raster-like patterns of the first and second grating hardmasks 2804 and 2806 of FIG. 28A can have hardmask lines of constant width closely spaced with a constant pitch.

Referring to Figure 28B, a sacrificial cross grating patterning process is performed. The overlying hardmask 2808 is formed with a grating pattern along the second direction, orthogonal to the first direction, ie, orthogonal to the first and second grating hardmasks 2804 and 2806 .

In one embodiment, the overlying hard mask 2808 is formed as a close pitch grating structure. In a particular such embodiment, tight pitch cannot be achieved directly by conventional lithography. For example, a pattern according to conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask. Even, the original pitch can be reduced by a quarter by a second round of spacer mask patterning. Thus, the raster-like pattern of the overlying hardmask 2808 of FIG. 28B can have hardmask lines of constant width closely spaced with a constant pitch.

Referring to Figure 28C, fabric patterning is performed. The regions of the first hard mask 2804 exposed between the gratings of the overlying hard mask 2808 are selectively etched and replaced with regions of the third hard mask 2810. The regions of the second hard mask 2806 exposed between the gratings of the overlying hard mask 2808 are selectively etched and replaced with regions of the fourth hard mask 2812. In one embodiment, the third grating hardmask 2810 is formed from a material having a different etch selectivity than the material of the first hardmask 2804 and the second hardmask 2806 . In a further embodiment, the fourth hardmask 2812 is formed from a material having an etch selectivity that is different from the material of the first hardmask 2804, the second hardmask 2806, and the third hardmask 2810 .

Referring to Figure 28D, the overlying hard mask 2808 is removed. In one embodiment, the overlying hard mask 2808 uses a selective etch, An ashing or cleaning process is used to remove to leave the fabric pattern as shown in Figure 28D.

28E-28H are associated with the via patterning process. 28E, a third hard mask 2810 is removed, selective to the first hard mask 2804, selective to the second hard mask 2806, and selective to the fourth hard mask 2812, to provide It exposes openings 2814 that cover portions of hardmask 2802. In one embodiment, the third hard mask 2810 is removed, selective to the first hard mask 2804, selective to the second hard mask 2806, and selective to the fourth hard mask 2812, Use selective etching or cleaning processes.

Referring to FIG. 28F, the through hole photobarrel patterning scheme is performed as the first photobarrelization process. In one embodiment, light barrels are formed in all exposed openings 2814 of Figure 28E. Selected ones of the photobarrels are removed to re-expose the openings 2814 and the other photobarrels 2816 remain, eg, by not exposing photobarrels 2816 to a lithography and development process used to open all others of the first photobarrel (In the particular case shown, three light barrels were retained and one was removed).

Referring to FIG. 28G , the exposed portion covering the hard mask 2802 is then etched to provide the first patterned hard mask 2820 . Additionally, the metal layer 2800 is etched through the opening to provide etch trenches 2818 in the first patterned metal layer 2822. The first patterned metal layer 2822 includes conductive vias 2824 . After the subtractive metal etch, the remaining photo barrels 2816 are removed to re-expose the associated openings 2814.

Referring to Figure 28H, trenches 2818 and openings 2814 are backfilled with hard mask material. In one embodiment, a material similar or identical to that of the third hardmask 2810 is formed over the structure of FIG. 28G and planarized or etched back to provide the deep hardmask region 2826 and the shallow hardmask region 2828. In one embodiment, the deep hard mask region 2826 and the shallow hard mask region 2828 are of a third material type (ie, the material type of the third hard mask 2810).

28I-28L relate to wire cutting or plug forming patterning processes. 28I, the first hard mask 2804 is removed, selective to the second hard mask 2806, selective to the deep hard mask area 2826 and shallow hard mask area 2828 of the third material type, and to The fourth hard mask 2812 is selective to provide openings 2830 that expose portions of the first patterned hard mask 2820. In one embodiment, the first hard mask 2804 is removed, selectively to the second hard mask 2806, selectively to the deep hard mask area 2826 and the shallow hard mask area 2828 of the third material type, And to be selective to the fourth hard mask 2812, a selective etching or cleaning process is used.

Referring to FIG. 28J, a dicing or plug photobarrel patterning scheme is performed as a second photobarrelization process. In one embodiment, light barrels are formed in all exposed openings 2830 of Figure 28I. Selected ones of the photobarrels are removed to re-expose the openings 2830 and the other photobarrels 2832 remain, eg, by not exposing photobarrels 2832 to a lithography and development process that opens all others for the second photobarrel (In the particular case shown, three light barrels were retained and one was removed). The photobucket removed (at this stage) represents the location where the cut or plug will be in the final metallization layer. That is, in the second photobarrel process, the photobarrel is removed from the location where the plug or cut will finally be formed.

Referring to Figure 28K, the exposed portions of the first patterned hardmask 2820 are then etched to provide a second patterned hardmask 2834 having trenches 2836 formed therein. After this etch, the remaining photo barrels 2832 are removed to re-expose the associated openings 2830.

Referring to Figure 28L, trenches 2834 and openings 2830 are backfilled with hard mask material. In one embodiment, a material similar to or the same as that of the first hardmask 2804 is formed on the structure of FIG. 28K and planarized or etched back to provide the deep hardmask region 2838 and the shallow hardmask region 2840. In one embodiment, the deep hard mask region 2838 and the shallow hard mask region 2840 are of the first material type (ie, the material type of the first hard mask 2804).

Referring to Figure 28M, the fourth hard mask 2812 is removed, selective for the deep hard mask region 2838 and shallow hard mask region 2840 of the first material type, selective for the second hard mask 2806, and for The deep hard mask region 2826 and the shallow hard mask region 2828 of the third material type are optional. In one embodiment, the fourth hard mask 2812 is removed, selectively for the deep hard mask region 2838 and the shallow hard mask region 2840 of the first material type, selectively for the second hard mask 2806, And to be selective to the deep hard mask region 2826 and the shallow hard mask region 2828 of the third material type, a selective etching or cleaning process is used. The etch back process is performed through the resulting opening and fully through the second patterned hardmask 2834 to form the third patterned hardmask 2842; and through the first through the first patterned metal layer 2822 to form the second Patterned metal layer 2844. Although not depicted, at this stage, a second dicing or plug patterning process may be performed.

Referring to Figure 28N, the deep opening formed in association with Figure 28M is backfilled with hard mask material. In one embodiment, a material similar or identical to that of the fourth hard mask 2812 is formed over the structure of FIG. 28M and planarized or etched back to provide the deep hard mask region 2846. In one embodiment, the deep hard mask region 2846 is of a fourth material type (ie, the material type of the fourth hard mask 2812). In an alternative embodiment, as shown in association with 2899 of FIG. 28S, described below, an ILD layer (such as a low-k dielectric layer) may first be filled and etched back to the level of the second patterned metal layer 2844. . A fourth type of hard mask material (ie, a shallow version of 2846) is then formed over the ILD layer.

Figures 28O-28R are associated with the conductive sheet patterning process. Referring to FIG. 280, the second hard mask 2806 is removed, selectively for the deep hard mask regions 2838 and shallow hard mask regions 2840 of the first material type, and for the deep hard mask regions 2826 and 2840 of the third material type. The shallow hardmask region 2828 is selective, and is selective to the deep hardmask region 2846 of the fourth material type, to provide openings 2848 which expose portions of the third patterned hardmask 2842. In one embodiment, the second hardmask 2806 is removed, selectively for the deep hardmask area 2838 and the shallow hardmask area 2840 of the first material type, and for the deep hardmask area of the third material type Selective to 2826 and shallow hard mask region 2828, and selective to deep hard mask region 2846 of the fourth material type, using a selective etch or clean process.

Referring to FIG. 28P, the conductive sheet photobarrel patterning scheme is performed as the third photobarrelization process. In one embodiment, light barrels are formed in all exposed openings 2848 of Figure 28O. Selected ones of the photobarrels are removed to re-expose the openings 2848 and the other photobarrels 2850 remain, eg, by not exposing photobarrels 2850 to a lithography and development process used to open all others of the third photobarrel (In the particular case shown, one light barrel 2850 is retained and three are removed). The photobuckets removed (at this stage) represent the locations where conductive sheets will not be formed in the final metallization layer. That is, in the third photobarrel process, photobarrel 2850 is left at the position where the conductive sheet will be finally formed.

Referring to FIG. 28Q, the exposed portions of the third-patterned hardmask 2842 are then etched through openings 2848 to provide a fourth-patterned hardmask 2852 having trenches 2854 formed therein. After this etch, the remaining photobuckets 2850 are removed.

Referring to FIG. 28R , the deep hard mask region 2838 and the shallow hard mask region 2840 of the first material type are removed, selectively for the deep hard mask region 2826 and the shallow hard mask region 2828 of the third material type and for The deep hard mask regions 2846 of the fourth material type are selectively to further expose portions of the fourth patterned hard mask 2852. In one embodiment, the deep hardmask regions 2838 and shallow hardmask regions 2840 of the first material type are removed, selectively to the deep hardmask regions 2826 and shallow hardmask regions 2828 of the third material type And to be selective for the deep hard mask region 2846 of the fourth material type, a selective etching or cleaning process is used.

Referring to FIG. 28S, an etch back process is performed through the resulting opening and completely through the second patterned metal layer 2844 to form the third patterned metal layer 2856. At this stage, portions of such an ILD layer 2899 are viewable in the structure of Figure 28S as described above in the alternative embodiment with its ILD layer 2899 being formed during the operations associated with Figure 28N .

Referring to part (a) of Figure 28T, in one embodiment, hard mask removal of the remaining hard mask portions 2828, 2846, 2852 of Figure 28S is performed, and the structure is subsequently planarized. In one embodiment, the height of the deep hard mask region 2826 is reduced, but the region is not removed all together to form the via cap 2858 and the ILD 2860. In addition, a plug region 2862 is formed. In one embodiment, ILD 2899 is formed in association with FIG. 28N; and in one such embodiment, plug region 2862 comprises a different material than ILD 2899. In another embodiment, ILD 2899 is not formed in association with Figure 28N; rather, ILD 2860 and entire portions of plug 2862 are formed simultaneously and in the same material, eg, using an ILD backfill process. In one embodiment, the metallized portion of the structure includes metal lines 2864, conductive vias 2824 (with via caps 2858 thereon), and conductive pads 2866, as depicted in part (a) of Figure 28T.

Referring to part (a) of Figure 28T, in one embodiment, ILD backfill 2861 is formed on the structure of Figure 28S. In one such embodiment, the ILD film is deposited and then etched back to provide the structure of part (b) of Figure 28T. In one embodiment, leaving the hard mask of FIG. 28S in place, the templating of the next metallization layer can be performed. That is, the topography with the hard mask left over can be used to template the next layer patterning process.

In either case, whether it is part (a) or (b) of FIG. 28T, the embodiments described herein include conduction of the remaining hard mask material (2858 or 2826) to the last metallization layer in the semiconductor structure. over via 2824. In addition, referring again to Figures 28A-28T, it should be understood that the order for dicing, via, and sheet patterning may be interchangeable. Also, although the example process flow shows a dicing, a via, and a one-piece pass, multiple passes for each type of patterning can also be performed.

Referring again to part (a) of FIG. 28T , in one embodiment, the back end of line (BEOL) metallization layer for the semiconductor structure includes an interlevel dielectric (ILD) layer 2860 . A plurality of conductive lines 2864 are disposed in the ILD layer 2860 along the first direction. The conductive sheet 2866 couples both of the plurality of conductive lines 2864 along a second direction orthogonal to the first direction.

Such a configuration as shown in Figure 28T cannot otherwise be achieved by conventional lithography processing (at small pitch, small width, or both). At the same time, self-alignment cannot be achieved using conventional processing schemes. Furthermore, the configuration shown in FIG. 28T cannot otherwise be achieved in situations where a pitch division scheme is used to finally provide a pattern of conductive lines 2864.

In one embodiment, both the conductive sheet 2866 and the plurality of conductive lines 2864 are continuous rather than contiguous. In one embodiment, both the conductive sheet 2866 and the plurality of conductive lines 2866 are coplanar. In one embodiment, the BEOL metallization layer further includes a plug of dielectric material 2862 disposed on an end of one of the plurality of conductive lines 2866. In one embodiment, the BEOL metallization layer further includes conductive vias.

The structure of Figure 28T can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 28T may represent the last metal interconnect layer in an integrated circuit. Referring again to FIG. 28T, this self-aligned fabrication by subtractive photobucket approach can be continued to fabricate the next metallization layer. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

In accordance with embodiments of the present invention, resist adaptation for exposure misalignment tolerance is described. Resist conditioning may include one or more of internal suppression, graft layer suppression, or top layer suppression. One or more of the embodiments described herein relate to two-stage bake photoresists with releasable inhibitors. Applications may be directed to one or more of extreme ultraviolet (EUV) lithography, general lithography applications, solutions to overlap problems, and general photoresist techniques. In one embodiment, materials are described that are suitable for enhancing the performance of a light barrel based approach. In this approach, the resist material is limited to the pre-patterned hard mask. The selected light barrels are then removed using a high-resolution lithography tool (eg, an EUV lithography tool). Certain embodiments may be implemented to improve uniformity of resist material response across a given photobarrel.

To provide context, one goal of the photobarrel approach may be to first diffuse the ability of any EUV to release acid across the exposed photobarrel to improve the uniformity of its resist response across the selected photobarrel. In past approaches, this goal has been achieved by using special materials that enable the acid to diffuse across the photobarrel at sufficiently low temperatures to avoid solubility-switching reactions excited from the acids. However, the activity of another resist component (ie, the inhibitor) may prevent this advantage from being fully realized. In particular, inhibitors can neutralize these acids before they can diffuse or spread across a given light barrel. To address these problems, in accordance with one or more of the embodiments described herein, the standard inhibitor is replaced with an inhibitor that can be released by extreme ultraviolet (UV) exposure, etc., which provides protection against premature acid exposure and ability.

More particularly, in accordance with one or more embodiments described herein, a photobarrel resist material including a UV release inhibitor is implemented to effectively provide a "2-stage PEB" in which the effects of EUV exposure are effectively averaged across across the established light barrel. Such embodiments may enable "digital" bucket responses, where the entire light bucket is cleared or not. In certain embodiments, this response is more tolerant of edge layout errors, where the aerial image is not perfectly aligned with the barrel grid.

To demonstrate one or more of the concepts covered herein, FIGS. 29A-29C illustrate cross-sectional views and corresponding plan views of various operations in a method of patterning using a photobucket including a two-stage bake photoresist , according to an embodiment of the present invention.

Referring to FIG. 29A, a pre-patterned hard mask 2904 is disposed over a substrate 2902. The pre-patterned hardmask 2904 has openings filled with a two-stage bake photoresist 2906. The two-stage bake photoresist 2906 is limited to openings in the pre-patterned hardmask 2904, eg, to provide a grid of potential via locations.

Referring to Figure 29B, selected ones of the photo barrels are subjected to exposure 2907 from a lithography tool. The two-stage bake photoresist 2906 is exposed with a lithography tool (eg, EUV lithography tool) to select which vias should be opened. In one embodiment, the alignment between the lithography tool and the pre-patterned hardmask 2904 grid is imperfect, resulting in asymmetry in exposure in the target light barrel and/or in adjacent light barrels. Partial exposure. Exposure 2907 is a shifted aerial image 2908 as seen in the plan view.

Referring to FIG. 29C, although the exposure of FIG. 29B may have involved misalignment and partial exposure of unselected light barrels, only the selected light barrels are cleared to form openings 2920, leaving the unselected light barrels as closed light barrels 2912. In one embodiment, the process is used to ensure that only selected photobarrels are finally opened, following exposure 2907 of selected areas of the two-stage bake photoresist 2906, all two-stage bake photoresists 2906 was first baked to facilitate acid diffusion. Extreme ultraviolet (UV) inhibited release was then performed for acid neutralization. A second bake is then performed to facilitate solubility switching, as described in more detail below. In certain embodiments, the photoacid released from the first bake operation is diffused throughout the photobarrel. UV bulk exposure releases inhibitors and then a final solubility switch bake is performed. The process is detailed below in conjunction with Figures 30A-30E.

As a result, selected locations receiving larger exposures are eventually cleared to provide open photobarrel locations 2920, following development. Unselected positions that are not exposed (or only partially exposed but to a lesser extent, in the case of misalignment) are maintained as closed photobarrel positions 2912 following development.

To demonstrate the opposite scenario where a conventional photoresist is used, Figure ID illustrates a cross-sectional view of a conventional resist photobarrel structure following photobarrel development after misalignment exposure. Photo barrel region 2954 is shown only partially cleared 2950, leaving some residual photoresist 2952. With its photo barrel 2954 the selected photo barrel, the misaligned exposure 2907 only partially clears the photo barrel, which can lead to subsequent poor quality fabrication of conductive structures in these locations. In the event that its light barrel 2954 is a non-selected light barrel, some unwanted opening 2950 occurs, potentially resulting in the subsequent formation of conductive structures in unwanted locations.

In a more detailed process description, Figures 30A-30E illustrate schematic views of various operations in a method of patterning using a photobucket including a two-stage bake photoresist, in accordance with an embodiment of the present invention.

Referring to FIG. 30A , the first 3002 and second 3004 photobarrels each include a photolyzable composition including an acid deprotectable photoresist material, a photoacid generating (PAG) component 3010 , and a light radical generating component 3012 . A misaligned EUV or e-beam exposure 3006 is performed on selected photo barrels 3002 and non-selected photo barrels 3004, which exposes selected photo barrels 3002 substantially and partially (but to a lesser extent) non-selected photo barrels 3004. In certain embodiments, the light-based generating component 3012 is a UV releasable inhibitor.

Referring to Figure 30B, a first bake is performed. In one embodiment, the first bake is performed at a temperature too low to cause solubility switching. In one such embodiment, the bake is a diffusion-only bake, resulting in diffused material 3020 and 3022 of light barrels 3002 and 3004, respectively.

Referring to Figure 30C, inhibitor 3014 is released to form materials 3024 and 3026 of light barrels 3002 and 3004, respectively. In one embodiment, the inhibitor 3014 is an inhibitor of UV release. In certain such embodiments, the inhibitor of UV release is released by UV bulk exposure (eg, 365 nm exposure). In one embodiment, both photo barrels 3002 and 3004 are exposed to the same degree of bulk exposure.

Referring to Figure 30D, a second bake is performed to provide materials 3028 and 3030 for light barrels 3002 and 3004, respectively. In one embodiment, the second bake system produces a solubility switch in which secondary critical acids are concentratedly inhibited. In this way, there is essentially no local acid concentration. That is, undesired deprotection of only a portion of the partially exposed photo barrel does not occur.

Referring to Figure 30E, photo barrels 3002 and 3004 are subjected to a development process. Selected photo barrels 3002 are cleared during development to provide cleared photo barrels 3032. Unselected light barrels 3004 are not cleared during development and remain blocked light barrels 3034. In this way, a digital light barrel response (only on or off, no partial on) is achieved even in the event of misaligned exposures.

It should be understood that not all embodiments require a single composition to achieve a two-stage bake photoresist. In a first alternative example, Figure 30A' illustrates a schematic view of operations in another method of patterning using photobuckets, in accordance with an embodiment of the present invention. Referring to Figure 30A', the first 3002' and second 3004' light barrels each include grafted light-based generating components 3050 along the bottom and sidewalls of the first 3002' and second 3004' light barrels. A photolytic composition is formed within the grafted light-based generating composition 3050. The photolytic composition includes an acid deprotectable photoresist material and a photoacid generating (PAG) composition 3010'. Exposure 3006' and a multi-stage development process can then be performed in a manner similar to that described above.

In a second alternative example, Figure 30A" illustrates a schematic view of operations in another method of patterning using light barrels, in accordance with an embodiment of the present invention. Referring to Figure 30A", a first 3002" and a second 3004" light The barrels each include a photolytic composition including an acid-deprotectable photoresist material and a photoacid generating (PAG) composition 3010". After performing the first bake, a layer 3060 including the radical generating composition is formed on the first 3002" and a second 3004". The photobarrels 3002" and 3004" are then exposed to ultraviolet (UV) radiation. In this case, the base component does not need to be introduced via a photo-based generator, but can be deposited later In the process operation, for example, by vapor deposition of the base layer or exposure to the base atmospheric NMP.

Application of the above-described photoresist compositions and methods can be implemented to produce regular structures that cover all possible via (or plug) locations, followed by selective patterning of only desired features. To provide further material details, in one embodiment, referring again to Figures 30A-30E, light barrels 3002 and 3004 include a photodegradable composition. The photodegradable composition includes an acid deprotectable photoresist material that is substantially transparent at a certain wavelength. Photodegradable compositions also include photoacid generating (PAG) components that have substantial transparency at this wavelength. Photolyzable compositions include radical generating constituents that are substantially absorbing at this wavelength. In an alternative embodiment, the acid may deprotect the photoresist material that is not substantially transparent at this wavelength.

In one embodiment, the radical generating component is one selected from the group consisting of a light-based generating component, an electron-based generating component, a chemical-based generating component, and a UV-based generating component. In one embodiment, the radical generating component is an acoustic vibration radical generating component. In one embodiment, the radical generating component is UV absorbing. In one embodiment, the radical generating component includes a low energy UV chromophore. In a particular such embodiment, the low energy UV chromophore is selected from the group consisting of: anthracenylcarbamates, naphthalenylcarbamates, 2-nitrobenzene 2-nitrophenylcarbamates, arylcarbamates, coumarins, phenylglyoxylic acid, acetophenones and diphenyl ketones ( benzophenones). In one embodiment, the low energy UV chromophore is a photoreleasing amine. In one embodiment, the radical generating component includes a material selected from the group consisting of: N,N-dicyclohexyl-2-nitrophenylcarbamate , N,N-disubstituted carbamates (N,N-disubstituted carbamates) and mono-substituted carbamates (mono-substituted carbamates).

In one embodiment, the PAG component includes a material selected from the group consisting of triethyl, trimethyl, and other trialkylsulfonates, wherein the sulfonate group is The group is selected from the group consisting of trifluoromethylsulfonate, nonanfluorobutanesulfonate, and p-tolylsulfonate, or limited to organic Other examples of groups containing _-SO3 sulfonate anions. In one embodiment, the acid-deprotectable photoresist material is an acid-deprotectable material selected from the group consisting of polymers, molecular glasses, carbosilanes, and metal oxides. In one embodiment, metal oxides are used and release groups are not required. In one embodiment, the acid deprotectable photoresist material includes a material selected from the group consisting of polyhydroxystyrene, polymethylmethacrylate, polyhydroxystyrene, or polymethylmethacrylate The small molecular weight molecular weight glass version of the ® (which contains ester functions sensitive to acid catalyzed deprotection of carboxylic acids), carbosilane, and metal oxide treatment functions (which are sensitive to acid catalyzed deprotection or crosslinking).

In one embodiment, the wavelength is about 365 nm. In one embodiment, the acid-deprotected photoresist material is substantially absorbing, at a wavelength of about 13.5 nm. In one embodiment, the acid can deprotect the photoresist material to substantially absorb energy in the range of about 5-150 keV. In one embodiment, the molar ratio of the PAG component to the base generating component is at least 50:1.

Referring again to FIGS. 30A-30E, 30A' and 30A", in accordance with an embodiment of the present invention, a method of selecting a light barrel for semiconductor processing includes providing a structure having a first light adjacent to a second light barrel 3004 Barrel 3002. The structure is exposed to extreme ultraviolet (EUV) or electron beam radiation 3006, wherein the first photobarrel 3002 is exposed to EUV or electron beam radiation 3006 to a greater extent than the second photobarrel 3004. After exposing the structure to After EUV or e-beam irradiation 3006, a first bake of the first and second photobarrels is performed, as described in connection with Figure 30B. After performing the first bake, the structure is exposed to ultraviolet (UV) radiation, wherein The first photobarrel was exposed to UV radiation to about the same extent as the second photobarrel, as described in connection with Figure 30C. After exposing the structure to UV radiation, a second bake of the first and second photobarrels was Fulfillment, as described in connection with Figure 30D. After performing the second bake, the structure is developed. The development opens the first photobarrel and leaves the second photobarrel closed, as described in connection with Figure 30E.

In one embodiment, exposing the structure to extreme ultraviolet (EUV) or electron beam irradiation includes exposing the structure to energy having a wavelength of about 13.5 nanometers. In another embodiment, exposing the structure to extreme ultraviolet (EUV) or electron beam irradiation includes exposing the structure to energy in the range of 5-150 keV. In one embodiment, exposing the structure to UV radiation includes exposing the structure to energy having a wavelength of about 365 nanometers. In one embodiment, the first bake is performed at a temperature in the range of about 50-120 degrees Celsius for a duration in the range of about 0.5-5 minutes. In one embodiment, the second bake is performed at a temperature in the range of about 100-180 degrees Celsius for a duration in the range of about 0.5-5 minutes.

In one embodiment, referring specifically to FIG. 30A, the first and second photobarrels each include a photolytic composition including an acid deprotectable photoresist material, a photoacid generating (PAG) composition, and a photobased generating Element. In one such embodiment, exposing the structure to extreme ultraviolet (EUV) or electron beam irradiation includes activating the PAG component. The first bake diffuses the acid formed from the activated PAG component throughout the first and second photobarrels. Exposing the structure to UV radiation includes activating the photo-based generating component. The second bake utilizes the radicals generated from the photoradical generating components to suppress the total amount of acid formed in the second photobarrel, but not the total amount of acid formed in the first photobarrel.

In another embodiment, with explicit reference to FIG. 30A', the first and second photobarrels each include a grafted photobase generating composition (along the bottom and sidewalls of the first and second photobarrels) and a photodecomposable composition (forming a in the grafted light-generating component). Photolyzable components include acid deprotectable photoresist materials and photoacid generating (PAG) components. In one such embodiment, exposing the structure to extreme ultraviolet (EUV) or electron beam irradiation includes activating the PAG component. The first bake diffuses the acid formed from the activated PAG component throughout the first and second photobarrels. Exposing the structure to UV radiation includes activating the grafted light-based generating component. The second bake utilizes the radicals generated from the photoradical generating components to suppress the total amount of acid formed in the second photobarrel, but not the total amount of acid formed in the first photobarrel.

In another embodiment, with specific reference to FIG. 30A", the first and second photobarrels each include a photolytic composition comprising an acid deprotectable photoresist material and a photoacid generating (PAG) composition. The method It further includes, after performing the first bake and before exposing the structure to ultraviolet (UV) radiation, forming a layer including a radical generating component on the first and second photobarrels. In one such embodiment, exposing Exposure of the structure to extreme ultraviolet (EUV) or electron beam irradiation includes activating the PAG component. The first bake diffuses it from the acid formed from the activated PAG component throughout the first and second photobarrels. Exposure of the structure to UV radiation includes activating the radical Generation Component. The second bake utilizes the radicals generated from the base-generating component to suppress the total amount of acid formed in the second pass, but not the total amount of acid formed in the first pass.

In any of the above cases, in one embodiment, developing the structure includes (in the case of positive tone development) with a standard aqueous TMAH developer (eg, in a concentration range from 0.1M-1M) or according to Immersion or coating of other aqueous or alcohol developer of tetramethylammonium hydroxide for 30-120 seconds, followed by washing with DI water. In another embodiment, in the case of negative tone development, developing the structure includes dipping or coating with an organic solvent such as cyclohexanone, 2-heptanone, propylene glycol methyl ethyl acetate, or others, followed by Washing with another organic solvent such as hexane, heptane, cyclohexane, etc.

In an exemplary embodiment, the approach described above builds on the approach using a so-called photobucket, where every possible feature (eg, via) is pre-patterned into the substrate. Next, photoresist is filled into the patterned features and a lithography operation is used only to select selected vias for via opening formation. In certain embodiments, a lithography operation is used to define relatively large holes over a plurality of photobarrels including a two-stage bake photoresist, as described above. The two-stage bake photoresist photobucket approach allows for larger critical dimension (CD) and/or overlap errors while preserving the ability to select vias of interest.

In accordance with embodiments of the present invention, image tone inversion of a resist (eg, for photo barrels) is described. One or more embodiments described herein relate to a class of materials having special properties to enable pattern inversion (eg, inversion of holes to posts), and related treatments and structures derived from that class of materials. The material class may be a soft material class, eg, a photoresist-like material. As a general approach, a resist-like material is deposited in a pre-patterned hard mask. The resist-like material can then be selected using high-resolution lithography tools (eg, extreme ultraviolet (EUV) processing tools). On the other hand, the resist-like material can alternatively be left to remain permanently in the final fabricated structure, for example, it forms a fractured interlayer dielectric (ILD) material or structure between the metal lines ("insertion") plug"). The problem of overlap (edge placement) expected for the next generation of plug patterning may be addressed in one or more of the ways described herein.

More specifically, one or more of the embodiments described herein relate to the use of a spin-on dielectric (eg, ILD) with enabling filling of holes ("buckets") in a patterned photoresist layer Without destroying the special properties of the photoresist layer pattern. First, the spin-on dielectric material is introduced into a solvent that does not dissolve or cause intermixing of the photoresist and the dielectric material. It should be understood that good fillability of the pores is required. The initial crosslinking (or setting) of the spin-on dielectric film is accomplished under conditions in which the photoresist and the spin-on dielectric do not intermix and lose pattern information. Once the pattern is reversed, the material within the barrel is then converted (by baking/hardening) to a dielectric with desired properties (such as k-value, modulus, etch selectivity, etc.). While not limited to such materials, spin-on dielectric materials that build blocks from 1,3,5-trisilacyclohexane can be implemented to meet the above criteria. Crosslinking with loss of solubility of this material (or other silicon-based dielectrics) can be initiated (thermally, or at lower temperatures) by processes using acid, base, or Lewis acid catalysts. In one embodiment, this low temperature catalysis is critical to the implementation of the methods described herein.

In one embodiment, the approach described herein involves utilizing optimal imaging properties (eg, from positive tone materials) to produce negative tone patterns, where material properties are pursued in the final film process. The final material properties may be approximate for those high performance low-k dielectric/ILD materials. In contrast, state-of-the-art options for direct patterning of dielectric films are limited and are not expected to exhibit the necessary lithographic performance to be manufacturable in future shrinking technology generations.

As described in greater detail below in conjunction with FIGS. 31 and 32A-32H, in accordance with embodiments described herein, trenches in the ILD material are pre-patterned with chemically amplified photoresist filled. Using high-resolution lithography (eg, EUV), selected holes within the trenches are exposed and removed via conventional positive tone processing. At this stage, the empty pores are treated with a precatalyst layer. In one such embodiment, the precatalyst layer is a self-polymerizing monolayer (SAM) containing additional catalyst layers. The resulting decorated holes are then filled with the dielectric precursor, with concomitant overloading. Localization (or proximity) of the catalyst in the pores results in selective crosslinking and setting of the dielectric only in the pores. Overload and photoresist are removed, following the final hardening of the dielectric (if required) and metallization processes.

In accordance with embodiments of the present invention, key features of the approaches described herein relate to the adaptation of varying pattern densities and varying thicknesses of overload. In one embodiment, this adaptation is enabled because crosslinking only occurs in/near the pores and the overloading is eventually removed by planarization (eg, by chemical mechanical polishing). In one embodiment, selective cross-linking of the dielectric material in the pores is achieved without incurring selective cross-linking in regions of overload. In certain embodiments, subsequent to positive tone lithography patterning and development, the hydrophilic Si-OH terminated surface is exposed in the holes and wherever the photoresist has been removed. The hydrophilic surface can be present prior to photoresist coating or created, for example, during tetramethylammonium hydroxide (TMAH) development or subsequent cleaning. It should be understood that a photoresist that has not been exposed and developed will maintain a mildly or strongly hydrophobic nature in character, and thus, the patterning process effectively creates both hydrophilic and hydrophobic domains.

In one embodiment, the exposed hydrophilic surface is functionalized with a surface grafting agent that carries the catalyst or pre-catalyst required to crosslink the dielectric material. Subsequent coating of the dielectric results in the filling of the holes with overload, as described above, and as explained in more detail below. Upon activation and controlled diffusion of a precatalyst using, for example, a low temperature bake, the dielectric material is selectively cross-linked in the pores, with minimal cross-linking occurring in overloading, that is, directly within the pores. superior. The overloaded dielectric material can then be removed using dissolution in a casting solvent or another solvent. It should be understood that the removal process can also remove the photoresist, or the photoresist can be removed using another solvent or by an ashing process. In one embodiment, the dielectric material may be baked/hardened to a relatively high temperature prior to metallization or other processing as the hue is reversed.

In one or more of the embodiments described herein, there are several ways to dispose the catalyst or pre-catalyst in the pores. For some dielectric materials, strong Brinell acids are required. In other cases, strong Lewis acids can be utilized. For simplicity of description in the text, the term "acid" is used to refer to both situations. In one embodiment, direct absorption of catalyst or precatalyst is utilized. In this context, the catalyst is coated onto a hydrophilic surface and held firmly via H-bonding or other electrostatic interactions. Subsequent coating of the dielectric material results in the localization of the acid and dielectric precursors in the pores, where thermal or other activation initiates the desired cross-linking chemistry. In an exemplary embodiment, the reaction of the Si-OH rich surface with the strong Lewis acid B( _C6F5 ) ₃ results in the formation of Si _- OB( _{C6F5 ) 3H} ⁺ . The resulting Lewis acid is used to catalyze the crosslinking of hydrosilane precursor molecules at relatively lower temperatures than non-catalytic processes. In one embodiment, a large catalyst system is utilized to minimize diffusion into the overload zone.

In another embodiment, the approach involves covalent bonding via catalysts or pre-catalysts of silane chemicals, such as chlorine, alkoxy, and amine silanes or other surface-grafting groups, which may include siloxanes, silicon chlorides, alkenes, alkynes, amines, phosphines, thiols, phosphonic acids or carboxylic acids. In this context, the catalyst or precatalyst is covalently linked to the grafting agent. For example, well-known acid generators (eg, light or heat) based _on onium salts can be adhered to siloxanes (eg, [(MeO _{) 3Si - CH2CH2CH2SR2} ][X], where R = alkyl or aryl group and X = weakly coordinating anion, such as trifluoromethane sulfonate, nonaflate, HB(C ₆ F ₅ ) ₃ , BF ₄ , etc.) . The catalyst or pre-catalyst can be selectively adhered to the ILD of interest, or selectively removed from the resist, using thermal, dry etch, or wet etch processes. In yet another embodiment, a catalyst or pre-catalyst is introduced prior to photoresist coating using similar techniques. In this context, to be effective, the graft material must not interfere with the lithography and must withstand subsequent processing.

When used as an exemplary means of demonstrating the concepts described herein, FIG. 31 illustrates an oblique view of an alternating pattern of interlayer dielectric (ILD) lines and resist lines, with holes, according to embodiments of the present invention. Referring to FIG. 31 , a pattern 3100 includes alternating ILD lines 3102 and resist lines 3104 . A hole 3106 is formed in one of the resist lines 3104, eg, by conventional lithography. As described below, in association with Figures 32A-32H, patterns such as pattern 3100 may be subject to hue inversion.

In an example process flow, Figures 32A-32H illustrate cross-sectional views in a fabrication process involving the use of bottom-up cross-linked image tone inversion with a dielectric, in accordance with embodiments of the present invention.

32A illustrates a cross-sectional view of the starting structure following pre-patterning of trenches 3204 in ILD material 3202. Selected ones of trenches 3204 are filled with chemically amplified photoresist 3206, while others have been processed to provide unfilled trenches (or unfilled trench portions, as shown in FIG. 31). For example, in one embodiment, using high-resolution lithography (eg, extreme ultraviolet (EUV) lithography), selected holes within the trenches 3204 are exposed and removed via conventional positive tone processing.

Although not depicted for simplicity, it is understood that unfilled trenches (or holes formed within filled trenches) may expose underlying features, such as underlying metal lines, in region 3208 . Also, in one embodiment, the starting structure may be patterned in a grating-like pattern with trenches of constant width spaced at a constant pitch. Patterns, for example, can be fabricated by halving the pitch or reducing the pitch by a quarter. Certain trenches may be associated with underlying vias or lower level metallization lines.

32B illustrates a cross-section of the structure of FIG. 32A following the treatment of a blank trench or hole with a precatalyst layer 3210, which, in one embodiment, is a self-polymerizing monolayer (SAM) containing catalyst material. view. In one such embodiment, as shown, precatalyst layer 3210 is formed on exposed portions of ILD 3202, but not on exposed portions of resist 3206 or any exposed metal (such as over regions 3208) . In one embodiment, the precatalyst layer 3210 is formed by exposing the structure of Figure 32A to precatalyst-forming molecules in the gas phase, or molecules dissolved in a solvent. In one embodiment, the pre-catalyst layer is a layer of catalyst or pre-catalyst formed by direct adsorption, as described above. In another embodiment, the pre-catalyst layer 3210 is a layer of catalyst or pre-catalyst formed by covalent adhesion.

32C illustrates a cross-sectional view of the structure of FIG. 32B following the use of a dielectric material 3212 to fill the resulting decorative hole. It should be understood that the dielectric material 3212 has portions 3212A filling the trenches or holes and portions 3212B overlying the trenches or holes. Section 3212B is referred to herein as overload. In one embodiment, the dielectric material 3212 is a spin-on dielectric material.

In one embodiment, the dielectric material 3212 is selected from the class of materials based on hydrosilane precursor molecules, wherein the catalyst mediates Si-H bonds and crosslinkers such as water, tetraethoxysilane (TEOS), hexaethoxysilane hexaethoxytrisilacyclohexane or similar multifunctional cross-linking agents). In one such embodiment, the dielectric material 3212 includes trisilacyclohexane, which can be subsequently linked together by O groups. In other embodiments, an alkoxysilane-based dielectric precursor or semi-siloxane (SSQ) is used for the dielectric material 3212.

32D illustrates a cross-sectional view of the structure of FIG. 32C following cross-linking of portion 3212A of dielectric material 3212. In one embodiment, localization (or proximity) of catalyst (eg, precatalyst layer 3210 ) in unfilled trenches or pores results in selective crosslinking to form crosslinking regions 3214 and setting of portions 3212A of dielectric material 3212 , only in these holes. That is, in one embodiment, the portion 3212B of the dielectric material 3212 is not cross-linked. In one embodiment, the interconnection used to form regions 3214 is accomplished by a thermal hardening process (ie, by heating).

In one embodiment, the dielectric material 3212 includes trisilacyclohexane, and the cross-linking to form the regions 3214 includes cross-linking the trisilacyclohexane together by O groups. Referring to Figure 33A, trisilacyclohexane 3300 is illustrated. Referring to Figure 33B, two cross-linked (XL) trisilacyclohexane molecules 3300 form a cross-linked material 3320. Figure 33C illustrates an idealized representation of the linked trisilacyclohexane structure 3340. It should be understood that, in practice, structure 3340 is used to represent a complex mixture of oligomers, but the common denominator is the H-capped trisilacyclohexane ring.

32E illustrates a cross-sectional view of the structure of FIG. 32D following removal of the overload region 3212B of the dielectric material 3212. 32F illustrates a cross-sectional view of the structure of FIG. 32E following removal of resist 3206 selective to cross-linked regions 3214. In one embodiment, as depicted, resist 3206 is removed in a subsequent and different processing operation, such as a second wet chemical development operation, relative to that of overload region 3212B used to remove dielectric material 3212. A processing operation (such as a first wet chemical development operation). However, in another embodiment, the resist 3206 is removed in the same processing operation (such as a wet chemical development operation) used to remove the overload region 3212B of the dielectric material 3212. In one embodiment, the remaining cross-linked regions 3214 are subjected to an additional hardening process (eg, additional heating following the cross-linking hardening process). In one embodiment, additional hardening is performed subsequent to the removal of resist 3206 and overload region 3212B.

32G illustrates a cross-sectional view of the structure of FIG. 32F following the formation of a metal fill layer 3216. A metal fill layer 3216 can be formed in the open trenches (or holes) from Figure 32F, as well as in the overload regions. The metal fill layer can be a single material layer, or can be formed from several layers, including a conductive liner layer and a fill layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form metal fill layer 3216. In one embodiment, the metal filling layer 3216 is composed of conductive materials such as (but not limited to) Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au or its alloys.

32H illustrates a cross-sectional view of the structure of FIG. 32G following planarization of a metal fill layer used to form metal features 3218 (eg, metal lines or vias). In one embodiment, planarization of the metal fill layer 3216 used to form the metal features 3218 is performed using a chemical mechanical polishing process. An example resulting structure is shown in FIG. 32H, where metal features 3218 are alternated with cross-linked (dielectric) regions 3214 in the ILD material 3202.

It should be understood that the resulting structure of Figure 32H can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 32H may represent the final metal interconnect layer in an integrated circuit. Furthermore, it should be understood that the above examples do not include an etch stop or metal capping layer in the pattern, which may otherwise be required for patterning. However, for clarity, these layers are not included in the figure as they do not affect the overall bottom-up filling concept.

Referring again to Figures 32A-32H, this patterning scheme can be implemented as an integrated patterning approach that involves generating regular structures covering all possible locations, followed by selective patterning of only desired features. The cross-linked region 3214 represents a material that can remain in the final structure as an ILD (eg, as a plug) between the ends of the metal lines.

According to an embodiment of the present invention, a diagonal mask patterning is described. One or more of the embodiments described herein are directed to diagonal hard mask patterning for overlay improvement, particularly in the fabrication of back end of line (BEOL) features in semiconductor integrated circuits. Applications based on patterning of diagonal hard masks may include, but are not limited to, the following embodiments: 193 nm immersion lithography, extreme ultraviolet (EUV) lithography, interconnect fabrication, overlay improvement, overlay budget, plug patterning , through hole patterning. Embodiments are particularly useful for self-aligned fabrication of BEOL structures.

In one embodiment, the approaches described herein relate to an integrated approach that allows increased via and plug overlap tolerance relative to existing approaches. In one such embodiment, all potential vias and plugs are pre-patterned and filled with resist to form photobuckets. Afterwards, in certain embodiments, EUV or 193 nm lithography is used to select certain via and plug locations for actual (final) via and plug fabrication. In one embodiment, diagonal patterning is used to increase the nearest neighbor distance, which results in an increase by a factor of the square root of two of the overlap budget. More specifically, one or more of the embodiments described herein relate to using a subtractive method to preform each via and plug using etched trenches. An additional operation is then used to select which vias and plugs to keep. These operations are illustrated using photobuckets, although a more traditional resist exposure and ILD backfill approach can also be used to perform the selection process.

In one form, a diagonal hard mask approach may be implemented. By way of example, FIGS. 34A-34X illustrate portions of integrated circuit layers that represent various operations in a method of self-aligned via and plug patterning using diagonal hardmasks, in accordance with embodiments of the present invention. . In each illustration of each of the described operations, cross-sectional and/or planar and/or oblique views are shown. These views will be referred to herein as the corresponding cross-sectional, plan and oblique views.

34A illustrates a cross-sectional view of the starting structure 3400 following deposition (but before patterning) of a first hard mask material layer 3404 formed on an interlayer dielectric (ILD) layer 3402, in accordance with an embodiment of the present invention . Referring to Figure 34A, the patterned mask 3406 has spacers 3408 formed on or over the first layer of hard mask material 3404 (along its sidewalls).

34B illustrates a cross-sectional view of the structure of FIG. 34A following patterning of the first hardmask layer by pitch doubling, in accordance with an embodiment of the present invention. Referring to FIG. 34B , the patterned mask 3406 is removed and the resulting pattern of spacers 3408 is transferred (eg, by an etching process) to the first layer of hard mask material 3404 to form a first patterned hard mask 3410 . In one such embodiment, the first patterned hardmask 3410 is formed in a grating pattern, as depicted in Figure 34B. In one embodiment, the grating structure of the first patterned hard mask 3410 is a tight-pitch grating structure. In a particular such embodiment, tight pitch cannot be achieved directly by conventional lithography. For example, a pattern according to conventional lithography can be formed first (mask 3406), but the pitch can be halved by using spacer mask patterning, as depicted in Figures 34A and 34B. Even, although not shown, the original pitch can be reduced by a quarter by a second round of spacer mask patterning. Thus, the raster-like pattern of the first patterned hardmask 3410 of FIG. 34B can have hardmask lines of constant width separated by a constant pitch.

34C illustrates a cross-sectional view of the structure of FIG. 34B subsequent to formation of a second patterned hard mask, in accordance with an embodiment of the present invention. Referring to FIG. 34C , the second patterned hard mask 3412 is formed to be interleaved with the first patterned hard mask 3410 . In one such embodiment, the second patterned hard mask 3412 is formed by deposition of a second layer of hard mask material (eg, having a different composition than the first layer of hard mask material 3404). The second layer of hard mask material is then planarized (eg, by chemical mechanical polishing (CMP)) to provide a second patterned hard mask 3412 .

34D illustrates a cross-sectional view of the structure of FIG. 34C following deposition of a hard mask cap layer (third hard mask layer), in accordance with an embodiment of the present invention. Referring to FIG. 34D , a hard mask cap layer 3414 is formed on the first patterned hard mask 3410 and the first patterned hard mask 3412 . In one such embodiment, the material composition and etch selectivity of the hard mask cap layer 3414 are different from the first patterned hard mask 3410 and the first patterned hard mask 3412.

34E illustrates an oblique view of the structure of FIG. 34D following patterning of the hard mask capping layer, in accordance with an embodiment of the present invention. Referring to FIG. 34E , a patterned hard mask capping layer 3414 is formed on the first patterned hard mask 3410 and the first patterned hard mask 3412 . In one such embodiment, the patterned hardmask cap layer 3414 is formed with a grating pattern orthogonal to the grating patterns of the first patterned hardmask 3410 and the first patterned hardmask 3412, as shown in FIG. shown in 34E. In one embodiment, the grating structure formed by the patterned hard mask cap layer 3414 is a close pitch grating structure. In this embodiment, tight pitch cannot be achieved directly by conventional lithography. For example, a pattern according to conventional lithography can be formed first, but the pitch can be halved by patterning using a spacer mask. Even, the original pitch can be reduced by a quarter by a second round of spacer mask patterning. Thus, the raster-like pattern of the patterned hard mask cap layer 3414 of Figure 34E can have hard mask lines of constant width separated by a constant pitch. It should be understood that the descriptions herein relating to forming and patterning a hard mask layer (or hard mask cap layer, such as hard mask cap layer 3414) relate (in one embodiment) to the formation of a mask overlying a hard mask or a hard mask over the cover layer. Mask formation may involve the use of one or more layers suitable for lithographic processing. In patterning one or more lithographic layers, the pattern is transferred to the hard mask or hard mask capping layer by an etching process to provide a patterned hard mask or hard mask capping layer.

34F illustrates an oblique view and corresponding plan view of the structure of FIG. 34E following further patterning of the first patterned hardmask, in accordance with an embodiment of the present invention. Referring to FIG. 34F , using the patterned hard mask cap layer 3414 as a mask, the first patterned hard mask 3410 is further patterned to form the first patterned hard mask 3416 . The second patterned hard mask 3412 is not further patterned in this process. In one embodiment, the first patterned hard mask 3410 is patterned to a depth sufficient to expose regions of the ILD layer 3402, as depicted in Figure 34F.

34G illustrates a plan view of the structure of FIG. 34F subsequent to removal of the hard mask cap layer and formation of a fourth hard mask layer, in accordance with an embodiment of the present invention. Referring to FIG. 34G, the hard mask cap layer (third hard mask layer) 3414 is removed, eg, by a wet etching process, a dry etching process, or a CMP process. A fourth hard mask layer 3418 is formed on the resulting structure by (in one embodiment) a deposition and CMP process. In one such embodiment, the fourth hard mask layer 3418 is formed by the deposition of a layer of material that is different from that of the second patterned hard mask layer 3412 and the first patterned hard mask layer 3416.

34H illustrates a plan view of the structure of FIG. 34G following deposition and patterning of a first diagonal hardmask layer, in accordance with an embodiment of the present invention. Referring to Figure 34H, a first diagonal hard mask layer 3420 is formed over the fourth hard mask layer 3418, the second patterned hard mask layer 3412, and the first patterned hard mask layer 3416 configuration of Figure 34G . In one embodiment, the first diagonal hardmask layer 3420 has a substantially or highly symmetrical diagonal pattern (eg, at 45 degrees relative to the grating structure of the second patterned hardmask layer 3412) to Alternate lines covering the fourth hard mask layer 3418. In one embodiment, the diagonal pattern of the first diagonal hardmask layer 3420 is printed with a minimum critical dimension (CD), ie, no pitch halving or quarter pitch is used . It should be understood that individual lines can be printed even larger than the minimum CD, as long as some area of the adjacent column of fourth hard mask layer 3418 remains exposed. Regardless, the raster-like pattern of the first diagonal hard mask layer 3420 of FIG. 34H may have hard mask lines of constant width separated by a constant pitch. It should be understood that the descriptions herein relating to forming and patterning a diagonal hardmask layer, such as the first diagonal hardmask layer 3420, relate (in one embodiment) to the formation of a mask over an overlying hardmask layer . Mask formation may involve the use of one or more layers suitable for lithographic processing. In patterning one or more lithographic layers, the pattern is transferred to the hard mask layer by an etching process to provide a diagonally patterned hard mask layer. In certain embodiments, the first diagonal hardmask layer is a carbon-based hardmask layer.

34I illustrates a plan view of the structure of FIG. 34H following removal of the exposed regions of the fourth hard mask layer, in accordance with an embodiment of the present invention. Referring to FIG. 34I, using the first diagonal hard mask layer 3420 as a mask, the exposed area of the fourth hard mask layer 3418 is removed. In one such embodiment, the exposed areas of the fourth hard mask layer 3418 are removed by an isotropic etching process (eg, a wet etching process or an anisotropic plasma etching process) so that any Partial exposure results in complete removal of the partially exposed areas of the fourth hard mask material. In one embodiment, the regions where the fourth hard mask layer 3418 has been removed reveal portions of the ILD layer 3402, as depicted in Figure 34I.

34J illustrates a plan view of the structure of FIG. 34I following removal of the first diagonal hardmask layer, in accordance with an embodiment of the present invention. Referring to FIG. 34J , the first diagonal hard mask layer 3420 is removed to reveal the first patterned hard mask layer 3416 and the second patterned hard mask layer 3412 . Also revealed is the portion of the fourth hardmask layer 3418, which is protected from isotropic etching by the first diagonal hardmask layer 3420. Thus, down each alternating column of the resulting grid-like pattern of FIG. 34J or down each alternating row of the resulting grid-like pattern of FIG. 34J, the regions of the fourth hard mask layer 3418 are exposed with the underlying ILD layer 3402 Alternating zones. That is, the result is a checkerboard pattern of the ILD layer 3402 region and the fourth hard mask layer region 3418. As such, an increase by a factor of the square root of two is achieved at the nearest neighbor distance 3422 (shown as the distance in direction b). In certain embodiments, the first diagonal hardmask layer 3420 is a carbon-based hardmask material and is removed by a plasma ashing process.

34K illustrates a plan view of the structure of FIG. 34J subsequent to formation of the first plurality of optical barrels, in accordance with an embodiment of the present invention. Referring to FIG. 34K, a first plurality of photobuckets 3424 are formed in the openings over the ILD layer 3402 such that no portion of the ILD layer 3402 remains exposed. Light barrel 3424 (at this stage) represents the first half of all possible via locations in the resulting metallization layer.

Figure 34L illustrates a plan view and corresponding cross-sectional view (along a-a' of the structure of Figure 34K following photobarrel exposure and development to form selected via locations, and subsequent via openings etched into the underlying ILD axis), according to an embodiment of the present invention. Referring to FIG. 34L, selected light barrels 3424 are exposed and removed to provide selected via locations 3426. Via locations 3426 are subjected to a selective etch process, such as a selective plasma etch process, to extend the via openings into the underlying ILD layer 3402, forming a patterned ILD layer 3402'. The etch is selective to the remaining (unexposed) photobuckets 3424, the first patterned hardmask layer 3416, the second patterned hardmask layer 3412, and the fourth hardmask layer 3418.

34M illustrates a plan view and corresponding cross-sectional view (taken along the bb' axis) of the structure of FIG. 34L following removal of the remaining photobuckets and subsequent formation of a fifth hardmask material, according to Embodiments of the present invention. Referring to Figure 34M, the remainder of the first plurality of photo barrels 3424 are removed, eg, by a selective etch or gray process. All exposed openings (eg, openings formed upon removal of the light barrel 3424 along with the via locations 3426) are then filled with a hardmask material 3428, such as a carbon-based hardmask material.

34N illustrates a plan view and corresponding cross-sectional view (taken along the cc' axis) of the structure of FIG. 34M after removal of the remaining region of the fourth hard mask layer, in accordance with an implementation of the present invention example. Referring to FIG. 34N, all remaining areas of the fourth hard mask layer 3418 are removed, eg, by a selective etch or gray process. In one embodiment, the regions where the fourth hard mask layer 3418 has been removed reveal portions of the patterned ILD layer 3402', as depicted in Figure 34N.

34O illustrates a plan view and corresponding cross-sectional view (taken along the d-d' axis) of the structure of FIG. 34N subsequent to formation of the second plurality of photobarrels, in accordance with an embodiment of the present invention. Referring to FIG. 34O, a second plurality of photo-buckets 3430 are formed in the openings over the patterned ILD layer 3402' such that the portion thereof without the patterned ILD layer 3402' remains exposed. Light barrel 3430 (at this stage) represents the second half of all possible via locations in the resulting metallization layer.

Figure 34P illustrates a plan view and corresponding cross-sectional view (along e-e' of the structure of Figure 34O following photobarrel exposure and development to form selected via locations, and subsequent via openings etched into the underlying ILD axis), according to an embodiment of the present invention. Referring to FIG. 34P, selected photo barrels 3430 are exposed and removed to provide selected via locations 3432. Via locations 3432 are subjected to a selective etch process, such as a selective plasma etch process, to extend the via openings into the underlying patterned ILD layer 3402', forming a further patterned ILD layer 3402". The etching is selective for Generic: remaining (unexposed) photobucket 3430, first patterned hardmask layer 3416, second patterned hardmask layer 3412, and hardmask material 3428.

34Q illustrates a plan view and corresponding cross-sectional view (taken along the f-f' axis) of the structure of FIG. 34P following removal of fifth hard mask material, trench etch, and subsequent sacrificial layer formation , according to an embodiment of the present invention. Referring to Figure 34Q, the hard mask material layer 3428 is removed, revealing all of the original first and second halves of potential via locations. Patterned ILD layer 3402" is then patterned to form ILD layer 3402", which includes via openings 3432 and 3426, along with trenches 3436 in which the via openings are not formed. Trenches 3436 will ultimately be used for Metal lines are fabricated, as described below. Upon completion of the trench etch, all openings, including via openings 3426 and 3432 and trench 3436, are filled with sacrificial material 3434. In one such embodiment, the hard mask The material layer 3428 is a carbon-based hard mask material and is removed by a plasma ashing process. In one embodiment, the sacrificial material 3434 is a flowable organic or inorganic material, such as a sacrificial light absorbing material (SLAM). The sacrificial material 3434 is formed (or planarized to) the level of the first patterned hardmask 3416 and the second patterned hardmask 3412, as depicted in Figure 34Q.

34R illustrates a plan view of the structure of FIG. 34Q following deposition and patterning of a second diagonal hardmask layer, in accordance with an embodiment of the present invention. Referring to Figure 34R, a second diagonal hard mask layer 3438 is formed over the sacrificial material 3434, second patterned hard mask layer 3412, and first patterned hard mask layer 3416 arrangement of Figure 34Q. In one embodiment, the second diagonal hardmask layer 3438 has a substantially or highly symmetrical diagonal pattern (eg, at 45 degrees relative to the grating structure of the second patterned hardmask layer 3412) to Alternate lines of the first patterned hard mask layer 3416 are covered. In one embodiment, the diagonal pattern of the second diagonal hardmask layer 3438 is printed with a minimum critical dimension (CD), ie, no pitch halving or quarter pitch is used . It should be understood that individual lines can be printed even larger than the minimum CD, as long as some area of the adjacent column of the first hard mask layer 3416 remains exposed. Regardless, the raster-like pattern of the second diagonal hardmask layer 3438 of FIG. 34R may have hardmask lines of constant width separated by a constant pitch. It should be understood that the description herein regarding forming and patterning a diagonal hard mask layer, such as the second diagonal hard mask layer 3438, refers to (in one embodiment) the formation of a mask over an overlying hard mask layer . Mask formation may involve the use of one or more layers suitable for lithographic processing. In patterning one or more lithographic layers, the pattern is transferred to the hard mask layer by an etching process to provide a diagonally patterned hard mask layer. In certain embodiments, the second diagonal hardmask layer 3438 is a carbon-based hardmask layer.

34S illustrates the structure of FIG. 34R following removal of the exposed regions of the first patterned hardmask layer, removal of the second diagonal hardmask layer, and subsequent to formation of the third plurality of photobuckets Plan view and corresponding cross-sectional view (taken along the g-g' axis), according to embodiments of the present invention. Referring to FIG. 34S, using the second diagonal hard mask layer 3438 as a mask, the exposed area of the first hard mask layer 3416 is removed. In one such embodiment, the exposed regions of the first patterned hard mask layer 3416 are removed by an isotropic etch process (eg, a wet etch process or an anisotropic plasma etch process), So that any partial exposure results in complete removal of the partially exposed areas of the first patterned hard mask layer 3416. Referring again to FIG. 34S, the second diagonal hard mask layer 3438 is removed to reveal the sacrificial material 3434 and the second patterned hard mask layer 3412. Also revealed is the portion of the first hardmask layer 3416 that is protected from isotropic etching by the second diagonal hardmask layer 3438. In certain embodiments, the second diagonal hardmask layer 3438 is a carbon-based hardmask material and is removed by a plasma ashing process. Referring again to FIG. 34S, a third plurality of photo-buckets 3440 are formed in the resulting openings over the patterned ILD layer 3402"' such that the portion of it without the patterned ILD layer 3402"' remains exposed. Light barrel 3440 (at this stage) represents the first half of all possible plug locations in the resulting metallization layer. Thus, down each alternating column of the resulting grid-like pattern of FIG. 34S or down each alternating row of the resulting grid-like pattern of FIG. 34S, the regions of the first patterned hard mask layer 3416 alternate with the photo barrels 3440 configuration. That is, the result is a checkerboard pattern of the photobarrel 3440 region and the first patterned hard mask layer 3416 region. As such, an increase by a factor of the square root of two is achieved at the nearest neighbor distance 3442 (shown as the distance in direction b).

Figure 34T illustrates a plan view and corresponding cross-sectional view (taken along the h-h' axis) of the structure of Figure 34S following plug location selection and trench etching, in accordance with an embodiment of the present invention. Referring to Figure 34T, the light barrel 3440 from Figure 34S is removed from a location 3442 where a plug will not be formed. In the position selected to form the plug, the light barrel 3440 is retained. In one embodiment, to form locations 3442 where plugs will not be formed, lithography is used to expose the corresponding photo barrels 3440. The exposed photobucket can then be removed with the developer. The patterned ILD layer 3402''' is then patterned to form an ILD layer 3402'''', which includes trenches 3444 formed on locations 3442. The trenches 3444 will ultimately be used for wire fabrication, as described below.

Figure 34U illustrates a plan view and corresponding cross-sectional view (taken along the i-i' axis) of the structure of Figure 34T following removal of the remaining third photobarrel and subsequent hardmask formation, in accordance with the present invention Examples of inventions. Referring to Figure 34U, all remaining photo barrels 3440 are removed, eg, by an ashing process. Upon removal of all remaining photo barrels 3440, all openings (including trenches 3444) are filled with a layer 3446 of hard mask material. In one embodiment, the hard mask material layer 3446 is a carbon-based hard mask material.

34V illustrates a plan view and corresponding cross-sectional view (taken along the j-j' axis) of the structure of FIG. 34V following the removal of the first patterned hardmask and formation of the fourth plurality of photobuckets, in accordance with the present invention. Examples of inventions. Referring to Figure 34V, the first patterned hard mask layer 3416 is removed (eg, by a selective dry or wet etch process), and a fourth plurality of photobuckets 3448 are formed on the patterned ILD layer 3402""' The portion of the resulting opening above such that it is not patterned with the ILD layer 3402"" remains exposed. Light barrel 3448 (at this stage) represents the second half of all possible plug locations in the resulting metallization layer.

34W illustrates a plan view and corresponding cross-sectional view (taken along the k-k' axis) of the structure of FIG. 34V following plug location selection and trench etching, in accordance with an embodiment of the present invention. Referring to Figure 34W, the light barrel 3448 from Figure 34V is removed from a location 3450 where a plug will not be formed. In the position selected to form the plug, the light barrel 3448 is retained. In one embodiment, to form locations 3450 where plugs will not be formed, lithography is used to expose the corresponding photo barrels 3448. The exposed photobucket can then be removed with the developer. The patterned ILD layer 3402'''' is then patterned to form the ILD layer 3402''''', which includes trenches 3452 formed at locations 3450. The trenches 3452 will ultimately be used for wire fabrication, as described below.

34X illustrates a plan view and corresponding first cross-sectional view (along 1- l' axis) and a second cross-sectional view (taken along the m-m' axis), according to embodiments of the present invention. Referring to Figure 34X, the remaining fourth photo barrel 3448, hard mask material layer 3446, and sacrificial material 3434 are removed. In one such embodiment, the hardmask material layer 3446 is a carbon-based hardmask material, and both the hardmask material layer 3446 and the remaining fourth photobucket 3448 are removed with a plasma ashing Process. In one embodiment, the sacrificial material 3434 is removed in a different etch process. Referring to the plan view of FIG. 34X , metallization 3454 is formed to be interleaved and coplanar with second patterned hard mask layer 3412 . Referring to the first cross-sectional view taken along the l-l' axis of the plan view of Figure 34X, metallization 3454 fills trenches 3452 and 3454 formed in patterned interlayer dielectric layer 3402""" (ie, as corresponding to a cross-sectional view taken along the k-k' axis of Figure 34W). Referring to the second cross-sectional view taken along the m-m' axis of the plan view of FIG. 34X, the metallization 3454 also fills the trenches 3436 and the vias formed in the patterned interlevel dielectric layer 3402''''. Aperture openings 3432 and 3426 (ie, as corresponding to the cross-sectional view taken along the f-f' axis of Figure 34Q). Accordingly, metallization 3454 is used to form conductive lines and conductive vias in interlevel dielectric layers for metallization structures such as BEOL metallization structures.

In one embodiment, metallization 3454 is formed by a metal fill and polish back process. In one such embodiment, the second patterned hard mask layer 3412 is reduced in thickness during the polishing back process. In certain such embodiments, a portion of the second patterned hardmask 3412 remains, although its thickness is reduced, as depicted in Figure 34X. Thus, the metal features 3456 (which are not conductive lines or conductive vias formed in the patterned interlayer dielectric layer 3402""") remain interleaved with the second patterned hard mask layer and located in the interlayer dielectric layer 3402 ''''' on or over (but not in), as also depicted in Figure 34X. In an alternate specific embodiment (not shown), the second patterned hard mask 3412 is completely removed during the polishing back. Therefore, metal features 3456 (which are not conductive lines nor conductive vias) are not preserved in the final structure. In either case, the structure of Figure 34X can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 34X may represent the final metal interconnect layer in an integrated circuit.

It should be understood that the above-described process operations may be performed in alternate orders, not every operation needs to be performed and/or additional process operations may be performed. Referring again to Figure 34X, this stage may be accomplished by metallization layer fabrication using a diagonal hard mask. The next layer fabricated in a similar manner may require another full process start-up. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

In one embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of (or includes) layers of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (eg, silicon dioxide (SiO ₂ )), doped oxides of silicon, fluorinated oxides of silicon, carbon doped silicon oxides, various low-k dielectric materials known in the art, and combinations thereof. This interlayer dielectric material can be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In one embodiment, as also used throughout this specification, metal line or interconnect material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper wires and structures that may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal system includes alloys, stacks, and other combinations of several metals. For example, metal interconnects may include barrier layers (eg, layers including one or more of Ta, TaN, Ti, or TiN), stacks of different metals or alloys, and the like. Thus, interconnect lines may be a single layer of material, or may be formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, can be used to form interconnect lines. In one embodiment, the interconnects are composed of conductive materials such as (but not limited to) Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or its alloys. Interconnects are also sometimes (in the art) referred to as traces, wirings, wires, metals, or just interconnects.

In one embodiment, as also used throughout this specification, the hard mask material is composed of a dielectric material other than the interlayer dielectric material. In one embodiment, different hardmask materials may be used in different regions to provide growth or etch selectivities that are different from each other and from the underlying dielectric and metal layers. In certain embodiments, the hard mask layer includes a layer of silicon nitride (eg, silicon nitride) or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material includes metals. For example, a hard mask or other overlying material may include a layer of titanium or other metal nitrides (eg, titanium nitride). Potentially smaller amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, other hard mask layers known in the art may be used depending on the particular implementation. The hard mask layer can be formed by CVD, PVD, or by other deposition methods.

In one embodiment, as also used throughout this specification, lithography operations are performed using 193 nm immersion lithography (i193), EUV and/or EBDW lithography, and the like. Positive or negative tone resists can be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topographic mask, an anti-reflection coating (ARC), and a photoresist layer. In a particular such embodiment, the topographic mask is a carbon hard mask (CHM) layer and the anti-reflective coating is a silicon ARC layer.

In accordance with the embodiments described herein, optical and SEM metrology for light barrels is described. It should be understood that the use of a pre-patterned hard mask to define a lithographic pattern can make overlay measurements challenging because the response to such patterned exposure is digital (binary) and the feature size is Quantized. Consequently, the size of the underlying mask pattern becomes the smallest measurable unit of overlap, which is too large for effective process control. The approach described below not only enables an overlay measurement much smaller than the size of the underlying pre-patterned hardmask, but also provides a signal response that is amplified by a multiple of the overlay shift, which enables extremely accurate overlay measurements.

To provide a structural framework for the concepts described herein, FIGS. 35A-35D illustrate cross-sectional views and corresponding top-down views representing various operations in a patterning process scheme using a pre-patterned hardmask , according to an embodiment of the present invention.

Referring to FIG. 35A , a first pre-patterned hard mask 3502 and a second pre-patterned hard mask 3504 are formed over the underlying layer 3506 . All possible via or plug locations are exposed as openings 3508 in pre-patterned hard mask 3502 and second pre-patterned hard mask 3504.

Referring to Figure 35B, a plurality of photoresist layer portions 3510 are formed in the openings 3508 of Figure 35A.

Referring to FIG. 35C, selected ones 3512 of the plurality of photoresist layer portions 3510 are exposed by lithographic exposure 3514. The selected 3512 of the plurality of photoresist layer portions 3510 exposed by the lithographic exposure 3514 may represent the via or plug locations that will eventually be opened or selected.

However, according to an embodiment of the present invention, the lithography exposure 3514 has an overlap error in the X direction of FIG. 35C. For example, the exposed photoresist layer 3512 on the left hand side of the cross-sectional view is shifted to the right to the extent that a portion of its photoresist is not exposed by the lithographic exposure 3514. All exposed photoresist layer 3512 of the top-down view is shifted to the right to the extent that a portion of its photoresist is not exposed by lithography exposure 3514. Again, the displacement may be substantially sufficient to partially expose adjacent locations, as depicted in Figure 35C.

Referring to FIG. 35D , selected locations 3512 have been cleared of exposed photoresist to provide openings 3516 . Openings 3516 can be used for subsequent via or plug fabrication, depending on the particular layer of the semiconductor structure.

However, certain openings 3516 may catastrophically not be fully opened in the event that insufficient exposure of their location 3512 is fulfilled due to overlap errors. Typically, exposure 3514 is required to provide a critical number of electrons or photons to completely clear selected ones 3512 of the plurality of photoresist layer portions 3510 to provide openings 3516. Some overlap errors can be tolerated, but significant overlap errors cannot be tolerated. Furthermore, as described in more detail below, even where all openings 3516 are fully opened, successful fabrication of the next layer may require at least some measure of overlap of openings 3516.

One or more embodiments described herein relate to approaches involving the use of multi-pitch grating structures on one layer to extract overlapping information relative to the underlying layer. Embodiments described herein can be implemented to address the concerns between layers patterned on top of a pre-patterned hard mask (eg, via or plug) and pre-patterned below by using an optical metrology tool. The problem of measurement overlap between hardmask layers (eg, light barrels). In one embodiment, the gratings are patterned with two or more pitches that are different from the underlying pre-patterned gratings, but parallel to one of the underlying gratings. The displacement of the current layer relative to the overlay of the hardmask pattern results in an optical signal that moves with the overlay and is proportional to the overlay error. In contrast, optical overlap usually involves real features and thus provides an analogous response. Here, movement is quantified differently than movement in analog action. That is, the response is digital (eg, a digitized and amplified motion) because it is based on steps. In one embodiment, "edge" patterns are measured.

Figures 36A-36E, described below, show the generation of optical signals using optical barrels that respond to changes in overlap. It should be understood that conventional optical metrology tools measure relatively large targets (eg, 20-30 microns). For the embodiments described herein, structures are generated from an array of lines/spaces that are below the resolution limit of the viewing tool and that utilize the light-bucket concept to generate movements that can be detected/measured using conventional overlay measurement algorithms edge. The final pattern seen by the metrology tool shows a measurable optical edge due to diffraction and scattering of light from the sub-resolution pattern as it moves with the overlap. Figure 36F shows possible optical metrology marks for use with Figures 36A-36E.

36A illustrates a top-down view of an overlay scenario where the current layer is overlaid on the underlying pre-patterned hardmask grid, in accordance with an embodiment of the present invention.

Referring to FIG. 36A, the underlying layer includes a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604. Photoresist layer portions 3610 and openings 3616 (which have been exposed and developed) are located between the first pre-patterned hard mask 3602 and second pre-patterned hard mask 3604 structures. The current layer is represented by overlay image 3650A. Overlay image 3650A has an overlay shift of zero and a pitch difference of P/4. The pitch of the overlay image 3650A of the current layer is shown to be 25% larger (in the upper half area 3652A) and 25% smaller (in the lower half area 3654A), as an example embodiment. Wide unexposed features 3656A and 3658A are included in the current layer, as depicted in Figure 36A.

36B illustrates a top-down view of an overlap scenario, where the current layer has a quarter-pitch positive overlap relative to the underlying pre-patterned hardmask grid, in accordance with an embodiment of the present invention.

Referring to FIG. 36B , the underlying layers include a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604 . Photoresist layer portions 3610 and openings 3616 (which have been exposed and developed) are located between the first pre-patterned hard mask 3602 and second pre-patterned hard mask 3604 structures. The current layer is represented by overlay image 3650B. Overlay image 3650B has a positive (+ve) overlay shift of P/4. Wide unexposed features 3656B and 3658B are included in the current layer, with the movement of these wide unexposed features 3656B and 3658B as depicted in Figure 36B.

36C illustrates a top-down view of an overlapping scenario, where the current layer has a positive overlap relative to the half-pitch of the underlying pre-patterned hardmask grid, in accordance with an embodiment of the present invention.

Referring to FIG. 36C , the underlying layer includes a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604 . Photoresist layer portions 3610 and openings 3616 (which have been exposed and developed) are located between the first pre-patterned hard mask 3602 and second pre-patterned hard mask 3604 structures. The current layer is represented by overlay image 3650C. Overlay image 3650C has a positive (+ve) overlay shift of P/2. Wide unexposed features 3656C and 3658C are included in the current layer, with the movement of these wide unexposed features 3656C and 3658C as depicted in Figure 36C.

36D illustrates a top-down view of an overlap scenario, where the current layer has a positive overlap relative to an arbitrary value of Δ of the underlying pre-patterned hardmask grid, in accordance with an embodiment of the present invention.

Referring to FIG. 36D , the underlying layer includes a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604 . Photoresist layer portions 3610 and openings 3616 (which have been exposed and developed) are located between the first pre-patterned hard mask 3602 and second pre-patterned hard mask 3604 structures. The current layer is represented by the overlay image 3650D. Overlay image 3650D has an overlay shift of zero and a pitch difference of P+Δ. Wide unexposed features 3656D and 3658D are included in the current layer, as depicted in Figure 36D.

36E illustrates a top-down view of an overlap scenario where the current layer has a positive overlap relative to an arbitrary value Δ of the underlying pre-patterned hardmask grid, where Δ can be measured by changing resist sensitivity and/or Or the feature size has been depicted and made as small as desired, in accordance with embodiments of the present invention.

Referring to FIG. 36E , the underlying layer includes a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604 . Photoresist layer portions 3610 and openings 3616 (which have been exposed and developed) are located between the first pre-patterned hard mask 3602 and second pre-patterned hard mask 3604 structures. The current layer is represented by overlay image 3650E. Overlay image 3650E has an overlay shift of +Δ and a pitch difference of P+Δ. Wide unexposed features 3656E and 3658E are included in the current layer, with the movement of these wide unexposed features 3656E and 3658E as depicted in Figure 36E. In one embodiment, for small overlapping shifts of Δ, the measurement signal is amplified to the level of P, and Δ can be as small as desired.

36F illustrates an example metrology structure suitable for the manner described above with respect to FIGS. 36A-36E, in accordance with an embodiment of the present invention. 36F, the metrology structure 3697 includes a layer 1 feature 3698 (eg, the lower layer) and a layer 2 feature 3699 (eg, the current layer). In one embodiment, the width of each of the features is about 20-30 microns, as depicted in Figure 36F. Such a structure may be included in the scribe lines or on the die in the interposer unit, for example. In one embodiment, the finished die may include a region with a beat frequency of wide features formed by an array of vias or plugs in a collection of narrow features. The presence of two different beat frequencies in any direction may suggest the use of the techniques described above to measure overlap. The above approach may enable accurate measurement of the overlap in the photobucket of each via or plug patterned layer for which this technique is used. Embodiments may improve the accuracy of future generations of technology using overlay measurement tools of current technology.

One or more of the embodiments described herein relate to approaches involving the use of critical dimension scanning electron microscopy (CDSEM) techniques to measure overlap on pre-patterned hard masks (eg, photo barrels). Embodiments described herein can be implemented to address concerns about patterned vias on top of a pre-patterned hard mask (eg, photobarrel) and /or measurement overlap between the plug layer and the underlying pre-patterned hardmask layer. In one embodiment, the via or plug locations are patterned at a pitch that is slightly different from the underlying pre-patterned hardmask pitch. Due to the overlap mismatch, the position of its clearing barrel depends on the amount of overlap mismatch.

37A illustrates a top-down view of an overlay scenario where the current layer is overlaid on the underlying pre-patterned hardmask, in accordance with an embodiment of the present invention.

Referring to FIG. 37A , the underlying layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704 . Photoresist layer portions 3710 and openings 3716 (which have been exposed and developed) are located between the first pre-patterned hard mask 3702 and second pre-patterned hard mask 3704 structures. The current layer is represented by overlay image 3750A. Overlay image 3750A has an overlay shift of X at zero and Y at zero. The pitch of the overlay image 3750A of the current layer is 25% larger relative to the underlying layer as an example embodiment, ie, patterned at a pitch of +Δ, where Δ=P/4. Region 3760A emphasizes the location of "barrel clusters", shifted at zero overlap (PB _0,0 ).

37B illustrates a top-down view of an overlay scenario where the current layer has a positive overlay shift of a quarter pitch relative to the underlying pre-patterned hardmask grid in the X-direction, in accordance with an embodiment of the present invention .

Referring to FIG. 37B , the underlying layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704 . Photoresist layer portions 3710 and openings 3716 (which have been exposed and developed) are located between the first pre-patterned hard mask 3702 and second pre-patterned hard mask 3704 structures. The current layer is represented by overlay image 3750B. Overlay image 3750B has an overlay shift of _X at Px/4 and Y at zero. The pitch of the overlay image 3750B of the current layer is 25% larger relative to the underlying layer as an example embodiment, ie, patterned at pitch + Δ, where Δ=P/4. Region 3760B emphasizes the location of X=-2P _X and Y=0 for the light bucket cluster for PB _0,0 . Region 3760B and the corresponding open/closed vertical rows are moved to the left by an amount equal to twice the pitch. It should be understood that an open/closed row will have a different contrast than the other rows due to the fact that its exposed optical barrel density is different from the other rows in the area.

37C illustrates a top-down view of an overlap scenario, where the current layer has a negative overlap of a quarter pitch relative to the underlying pre-patterned hardmask grid in the X-direction, in accordance with an embodiment of the present invention.

Referring to FIG. 37C , the underlying layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704 . Photoresist layer portions 3710 and openings 3716 (which have been exposed and developed) are located between the first pre-patterned hard mask 3702 and second pre-patterned hard mask 3704 structures. The current layer is represented by overlay image 3750C. Overlay image 3750C has an overlay shift of _X at -PX/4 and Y at zero. The pitch of the overlay image 3750C of the current layer is 25% larger relative to the underlying layer as an example embodiment, ie, patterned at pitch+Δ, where Δ=P/4. Region 3760C emphasizes the location of X=+2P _X and Y=0 for the light bucket cluster for PB _0,0 . Zone 3760C and the corresponding open/closed vertical row is moved to the right by an amount equal to twice the pitch.

37D illustrates a top-down view of an overlay scenario where the current layer has a quarter-pitch positive overlap relative to the underlying pre-patterned hardmask grid in the Y direction, in accordance with an embodiment of the present invention.

Referring to FIG. 37D , the underlying layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704 . Photoresist layer portions 3710 and openings 3716 (which have been exposed and developed) are located between the first pre-patterned hard mask 3702 and second pre-patterned hard mask 3704 structures. The current layer is represented by overlay image 3750D. Overlay image 3750D has an overlay shift of X at zero and Y at P _Y /4. The pitch of the overlay image 3750D of the current layer is 25% larger relative to the underlying layer as an example embodiment, ie, patterned at pitch + Δ, where Δ=P/4. Region 3760D emphasizes the position of X=0 and Y=-2P _Y for the light bucket cluster for PB _0,0 . Zone 3760D and the corresponding open/closed horizontal series move down by an amount equal to twice the pitch.

37E illustrates a top-down view of an overlay scenario, where the current layer has a quarter-pitch positive overlap relative to the underlying pre-patterned hardmask grid in the X-direction and has a lower relative to the Y-direction A quarter-pitch positive overlap of the pre-patterned hardmask grid, in accordance with embodiments of the present invention.

Referring to FIG. 37E, the underlying layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704. Photoresist layer portions 3710 and openings 3716 (which have been exposed and developed) are located between the first pre-patterned hard mask 3702 and second pre-patterned hard mask 3704 structures. The current layer is represented by overlay image 3750E. Overlay image 3750E has an overlay shift of X at P _X /4 and Y at P _Y /4. The pitch of the overlay image 3750E of the current layer is 25% larger relative to the underlying layer as an example embodiment, ie, patterned at pitch+Δ, where Δ=P/4. Region 3760E emphasizes the location of X=-2P _X and Y=-2P _Y for the light bucket cluster for PB _0,0 . Zone 3760E and the corresponding open/closed horizontal series move down by an amount equal to twice the pitch. Additionally, zone 3760E and the corresponding open/closed vertical rows are moved to the left by an amount equal to twice the pitch.

Referring again to FIGS. 37A-37E, it should be understood that cross-sectional analysis of a semiconductor wafer can reveal alignment marks including vertical and horizontal arrays of vias and/or plugs among a plurality of grids of vias and plugs , as indicating the application of one or more of the embodiments described herein. Such structures may be included in scribe lines or on dies in interposer cells, for example. Application of this approach may enable accurate measurement of the overlap in the photobarrel of each via and/or plug patterned layer for which it is intended to be used with CDSEM metrology. It should also be understood that conventional overlay techniques cannot work with this pattern patterning.

In accordance with embodiments of the present invention, new structures for high-resolution phase shift mask (PSM) fabrication for lithography, such as extreme ultraviolet lithography (EUV), are described. These PSM masks can be used for general (direct) lithography or complementary lithography.

Photolithography is often used in fabrication processes to form patterns in layers of photoresist. In a photolithography process, a photoresist layer is deposited over the underlying layer to be etched. Typically, the underlying layer is a semiconductor layer, but can be any type of hardmask or dielectric material. The photoresist layer is then selectively exposed to radiation through a photomask or reticle. The photoresist is then developed and those portions of the photoresist that are exposed to the irradiated photoresist are removed, in the case of a "positive" photoresist.

A photomask or reticle used to pattern the wafer is placed within a photolithography exposure tool, commonly known as a "stepper" or "scanner." In stepper or scanner machines, a light mask or reticle is placed between the illumination source and the wafer. A light mask or reticle is typically formed from a patterned chromatic (absorber layer), which is placed on a quartz substrate. The illumination passes substantially unattenuated through the quartz section of the light mask or reticle, in locations where there is no chromaticity. In contrast, the illumination does not pass through the chrominance portion of the mask. This type of mask is called a binary mask because illumination incident on the mask is either completely passed through the quartz section or completely blocked by the chrominance section. After the illumination is selectively passed through the mask, the pattern on the mask is transferred to the photoresist by passing through a series of lenses to project the image of the mask into the photoresist.

As the features on the light mask or reticle get closer together, diffraction effects come into play (when the size of the features on the mask corresponds to the wavelength of the light source). Diffraction blurs the projected image on the photoresist, resulting in poor resolution.

A state-of-the-art method to prevent diffraction patterns from interfering with the desired patterning of photoresist is to cover selected openings in the photomask or reticle with a transparent layer (known as a shifter). The shifter shifts one of the sets of exposure rays out of phase with another adjacent set, which cancels out interference patterns from diffraction. This method is called a phase shift mask (PSM) method. However, alternative mask fabrication solutions that reduce defects and increase yield during mask production are an important area of focus for lithography process development.

One or more embodiments of the present invention relate to methods for fabricating lithographic masks and the resulting lithographic masks. To provide context, the need to meet aggressive device scaling goals proposed by the semiconductor industry depends on its ability to pattern lithographic masks of smaller features with high fidelity. However, the manner in which smaller and smaller features are patterned poses significant challenges for mask fabrication. In this regard, lithography masks in widespread use today rely on the concept of phase shift masking (PSM) techniques for patterning features. However, reducing defects while producing smaller and smaller patterns remains one of the biggest hurdles in mask fabrication. The use of phase shifting masks can have several disadvantages. First, the design of the phase-shifting mask is a rather complex procedure that requires enormous resources. Second, due to the nature of the phase-shift mask, it is difficult to check whether no defects appear in the phase-shift mask. These deficiencies in phase-shift masks arise from the current integration schemes utilized to generate the masks themselves. Conventional phase shifting masks employ a cumbersome and somewhat defect-prone way to pattern thick light absorbing material and then transfer the pattern to its secondary layer which assists in phase shifting. To complicate matters, the absorber layer is subjected to plasma etch twice, and as a result, the adverse effects of plasma etch (such as loading effects, reactive ion etch retardation, charging and regeneration effects) cause problems in mask production. defect.

Innovative and novel integration techniques for materials used to fabricate defect-free lithographic masks remain a high priority for device scaling. Therefore, to take advantage of the full benefits of phase-shift masking techniques, a novel integration scheme that utilizes (i) patterning the shifter layer with high fidelity and (ii) patterning the absorber only once and during the final stages of manufacture. In addition, such a fabrication scheme may also provide other advantages such as flexibility in material selection, reduced substrate damage during fabrication, and increased throughput in mask fabrication.

38 illustrates a cross-sectional view of a lithography mask structure 3801, in accordance with an embodiment of the present invention. The lithography mask 3801 includes a die mid region 3810 , a frame region 3820 and a die frame interface region 3830 . The die frame interface region 3830 includes an adjacent portion of the die mid region 3810 and the frame region 3820 . Mid-die region 3810 includes a patterned shifter layer 3806 disposed directly on substrate 3800, wherein the patterned shifter layer has features including sidewalls. The frame region 3820 surrounds the mid-die region 3810 and includes a patterned absorber layer 3802 disposed directly on the substrate 3800 .

The die frame interface region 3830 (disposed on the substrate 3800 ) includes a two-layer stack 3840 . The two-layer stack 3840 includes an upper layer 3804 disposed on a lower patterned shifter layer 3806. The upper layer 3804 of the bilayer stack 3840 is composed of the same material as the patterned absorber layer 3802 of the frame region 3820.

In one embodiment, the uppermost surface 3808 of the features of the patterned shifter layer 3806 has a height that is different from the uppermost surface 3812 of the features in the die frame interface region and different from the uppermost surface 3814 of the features in the frame region . Furthermore, in one embodiment, the height of the uppermost surface 3812 of the features in the die frame interface region is different from the height of the uppermost surface 3814 of the features in the frame region. Typical thicknesses of the patterned shifter layer 3806 range from 40 to 100 nm, and typical thicknesses of the absorber layer range from 30 to 100 nm. In one embodiment, the thickness of the absorber layer 3802 in the frame region 3820 is 50 nm, the combined thickness of the absorber layer 3804 disposed on the shifter layer 3806 in the die frame interface region 3830 is 120 nm and the thickness of the frame region is 120 nm. The thickness of the absorber is 70 nm. In one embodiment, the substrate 3800 is quartz, and the patterned shifter layer includes materials such as, but not limited to, molybdenum silicide, molybdenum silicon oxynitride, molybdenum silicon nitride, silicon oxynitride, or silicon nitride. , while the absorbent material is chromium.

In accordance with embodiments of the present invention, complementary electron beam lithography is described. One or more embodiments described herein relate to lithography methods and tools that are related to or suitable for complementary electron beam lithography (CEBL), including semiconductor processing considerations when implementing such methods and tools.

Complementary lithography leverages the capabilities of the two lithography techniques (cooperating with each other) to reduce the cost of patterning critical layers in logic devices at 20nm half-pitch and below, in high volume manufacturing (HVM). The most cost-effective way to implement complementary lithography is to combine optical lithography with electron beam lithography (EBL). The procedures for transferring integrated circuit (IC) designs to wafers are detailed as follows: photolithography, which is used to print unidirectional lines (strictly unidirectional or predominantly unidirectional) at predefined pitches; pitch dicing techniques, which use to increase the line density; and EBL, to "cut" the line. EBL is also used to pattern other critical layers, especially contacts and vias. Optical lithography can be used alone to pattern other layers. When used to complement optical lithography, EBL is called CEBL, or complementary EBL. CEBL is for cutting lines and holes. By not attempting to pattern all layers, CEBL plays a complementary but critical role in meeting the patterning needs of the industry at advanced (smaller) technology nodes (eg, 10nm or smaller, such as 7nm or 5nm technology nodes) superior. CEBL also extends the use of current photolithography techniques, tools and facilities.

The embodiments disclosed herein can be used to fabricate many different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memory can be fabricated. Furthermore, integrated circuits or other microelectronic devices may be used in a variety of electronic devices known in the art. For example, in computer systems (eg, desktops, laptops, servers), mobile phones, personal electronic devices, and the like. Integrated circuits may be coupled to bus bars or other components in the system. For example, a processor may be coupled to a memory, a chipset, etc. via one or more bus bars. Each processor, memory, chipset can potentially be fabricated using the methods disclosed herein.

As described above, electron beam (ebeam) lithography can be implemented to complement standard lithography techniques to achieve desired scaling of features for integrated circuit fabrication. Electron beam lithography tools can be used to perform electron beam lithography. In an exemplary embodiment, FIG. 39 is a schematic cross-sectional view of an electron beam column of an electron beam lithography apparatus.

Referring to Figure 39, an electron beam row 3900 includes an electron source 3902 for providing a beam 3904 of electrons. The electron beam 3904 passes through the confinement aperture 3906 and then passes through the high aspect ratio illumination optics 3908. The output beam 3910 then passes through the slit 3912 and can be controlled by a thin lens 3914 (eg, which can be magnetic). Finally, the beam 3904 passes through a shaped aperture 3916 (which may be a one-dimensional (1-D) shaped aperture) and then through a canceller aperture array (BAA) 3918. BAA 3918 includes a plurality of physical apertures therein, such as openings formed in thin sheets of silicon. It is possible that only a portion of BAA 3918 was exposed to the electron beam at a given moment. Alternatively, or in combination, only a portion 3920 of the electron beam 3904 passing through the BAA 3918 is allowed to pass through the final aperture 3922 (eg, beam portion 3921 is shown blocking) and (possibly) the stage feedback deflector 3924.

Referring again to Figure 39, the resulting electron beam 3926 eventually strikes a point 3928 on the surface of a wafer 3930, such as a silicon wafer used for IC fabrication. Specifically, the resulting electron beam may impinge on the photoresist layer on the wafer, but embodiments are not limited thereto. Stage scan 3932 moves wafer 3930 relative to beam 3926 in the direction of arrow 3934 shown in FIG. 39 . It should be understood that the e-beam tool may in its entirety include several rows 3900 of the type shown in FIG. 39 . At the same time, the e-beam tool may have an associated base computer, and each row may further have a corresponding row computer.

In one embodiment, all or part of the openings or apertures of the BAA can be switched on or "off" (eg, by beam deflection) when the following refers to openings or apertures in the canceller aperture array (BAA), with The wafer/die is moved underneath along the wafer travel or scan direction. In one embodiment, the BAA can be independently controlled for each opening to pass the electron beam to the sample or to deflect the electron beam into, for example, a Faraday cup or shadow aperture. An electron beam row or apparatus including such a BAA can be built to deflect the overall beam coverage to only a portion of the BAA, and then individual openings in the BAA are electrically configured to pass ("on") or not the electron beam ( "close"). For example, undeflected electrons pass to the wafer and expose the resist layer, while deflected electrons are trapped in a Faraday cup or shadow aperture. It should be understood that its reference to "opening" or "opening height" refers to the spot size impinging on the receiving wafer and not to the physical opening in the BAA, since the physical opening is substantially larger (eg, micron scale) from the BAA eventually. The resulting dot size (eg, nanoscale). Thus, when the pitch of the BAA or the row of openings in the BAA is said to be "corresponding to" the pitch of the wire, the description is actually referring to the pitch between the point of impact as produced from the BAA Relationship to the pitch of the line being cut. As the example provided below, the dots generated from the BAA 4310 have the same pitch as the pitch of the line 4300 (when the two rows of BAA openings are considered together). At the same time, the dots generated from just one row of the staggered array of BAAs 4310 have twice the pitch of lines 4300.

In one embodiment, a staggered beam aperture array is implemented to account for the throughput of the electron beam machine while also enabling a minimum wiring pitch. Without interleaving, edge placement error (EPE) considerations mean that a minimum pitch of twice the wiring width cannot be cut because vertical stacking in a single stack is not possible. For example, FIG. 40 illustrates the aperture 4000 relative to the BAA of the wire 4002 to be cut or having a through hole placed in the target location when the wire is scanned below the aperture 4000 in the direction of arrow 4004. Referring to Figure 40, for a given wire 4002 to be cut or a through hole to be placed, the EPE 4006 of the cutter opening (aperture) results in a rectangular opening in the BAA grid of the pitch of the wire.

41 illustrates two non-staggered apertures 4100 and 4102 individually relative to the BAA of two lines 4104 and 4106 to be cut or with through holes placed in the target location, when the lines are in the direction of arrow 4108 When scanned under apertures 4100 and 4102. Referring to Figure 41, when the rectangular opening 4000 of Figure 40 is placed in a vertical single row with other such rectangular openings (eg, now 4100 and 4102), then the allowable pitch of the lines to be cut is limited by: 2x EPE 4110 plus the distance requirement 4112 between BAA openings 4100 and 4102 plus the width of a trace 4104 or 4106. The resulting gap 4114 is shown by the arrow on the extreme right side of FIG. 41 . Such a one-line array may severely limit the pitch of the wiring to be substantially 3-4 times greater than the width of the wiring, which may be unacceptable. Another possibly unacceptable alternative would be to cut a tighter pitch wiring with two (or more) vias with slightly offset wiring locations; this approach could severely limit the throughput of the e-beam machine.

With respect to FIG. 41, FIG. 42 illustrates two rows 4202 and 4204 of staggered apertures 4206 relative to the BAA 4200 of the plurality of lines 4208 to be cut or having through holes placed in the target locations, when the lines 4208 are scanned along the direction 4210. Below aperture 4206, shown by arrows in the scan direction, in accordance with embodiments of the present invention. Referring to Figure 41, interleaved BAA 4200 includes two linear arrays 4202 and 4204, spatially interleaved as shown. The two staggered arrays 4202 and 4204 cut (or place vias in) alternating lines 4208. Lines 4208 (in one embodiment) are placed on a tight grid with twice the wiring width. As used throughout this disclosure, the term "staggered array" may refer to a staggered array of openings 4206 that are staggered in one direction (eg, the vertical direction) and either have no overlap or some overlap, as When viewed while scanning in an orthogonal direction (eg, horizontal). In the latter case, the effective overlap provides tolerance for misalignment.

It should be understood that although a staggered array is shown in the text as two vertical rows for simplicity, the openings or apertures of a single "row" need not be rows in the vertical direction. For example, in one embodiment, interleaving is obtained as long as a first array collective has a pitch in the vertical direction, and a second array collective that is interleaved with the first array in the scanning direction has a vertical pitch. array. Thus, references or descriptions herein to vertical rows may actually consist of one or more rows, unless indicated as a single row of openings or apertures. In one embodiment, where a "row" of openings is not a single row of openings, any offset within that "row" can be compensated for with strobe timing. In one embodiment, the key point is that the openings or apertures of the staggered array of its BAAs are on a specific pitch in the first direction, but are offset in the second direction to allow them to place cuts or vias without any gaps in the Between cuts or vias in the first direction.

Accordingly, one or more embodiments relate to a staggered beam aperture array in which the openings are staggered to allow for EPE cutting and/or via requirements, as opposed to an inline arrangement that does not accommodate EPE technical requirements. Conversely, without interleaving, the problem of edge placement error (EPE) means that a minimum pitch of twice the wiring width cannot be cut because vertical stacking in a single stack is not possible. Instead, in one embodiment, the use of staggered BAA enables over 4000 times faster electron beam writing to each routing location than independently. Furthermore, the staggered array allows the wiring pitch to be twice the wiring width. In a particular embodiment, the array has 4096 staggered openings over two rows so that EPE for each of the dicing and via locations can be performed. It should be understood that a staggered array (as contemplated herein) may include two or more rows of staggered openings.

In one embodiment, the use of a staggered array leaves space to include metal around the aperture of its BAA containing one or two electrodes for delivering or directing the electron beam to the wafer or to the Faraday cup or shadow aperture. That is, each opening can be controlled separately by electrodes to pass or deflect the electron beam. In one embodiment, the BAA has 4096 openings and the electron beam apparatus covers a complete array of 4096 openings, each of which is electrically controlled. The energy flux is enhanced by sweeping the wafer under the opening (as indicated by the thick black arrow).

In certain embodiments, the staggered BAA has two columns of staggered BAA openings. Such an array allows for tight pitch routing, where the routing pitch can be twice the routing width. Also, all wiring can be cut in a single pass (or vias can be formed in a single pass), thereby enabling flux on the e-beam machine. Figure 21A illustrates two rows of staggered apertures (left) with respect to BAAs with cuts (breaks in horizontal lines) or complex lines (right) with vias patterned using staggered BAAs (filled square boxes), in scan direction by As shown by the arrows, embodiments are in accordance with the present invention.

Referring to Figure 43A, the resulting lines from a single staggered array may be as previously described, where the lines are of a single pitch, with their cuts and vias patterned. In particular, Figure 43A depicts a plurality of lines 4300 or open line locations 4302 in which wireless exists. Vias 4304 and cuts 4306 may be formed along line 4300 . Line 4300 is shown relative to a BAA 4310 having scan direction 4312. Thus, Figure 43A can be viewed as a typical pattern produced by a single staggered array. Dashed lines show where in the patterned lines the cut occurs (including total cuts to remove complete lines or line portions). Via locations 4304 are patterned vias that fall on top of wiring 4300.

It should be understood that an electron beam row comprising a staggered beam aperture array (staggered BAA) as described above may also include other features than those described in conjunction with FIG. 39 . For example, in one embodiment, the sample stage may be rotated 90 degrees to accommodate alternating metallization layers, which may be printed orthogonally to each other (eg, rotated between the X and Y scan directions). In another embodiment, the e-beam tool is capable of rotating the wafer 90 degrees before loading the wafer onto the stage.

43B illustrates a cross-sectional view of a stack 4350 of metallization layers 4352 in an integrated circuit, according to a metal line layout of the type shown in FIG. 43A, in accordance with an embodiment of the present invention. Referring to Figure 43B, in an exemplary embodiment, the metal cross-section of interconnect stack 4350 is taken from a single BAA array of eight matching metal layers 4354, 4356, 4358, 4360, 4362, 4364, 4366 and 4368 below. It should be understood that the thicker/wider metal lines 4370 and 4372 above will not be formed with a single BAA. Via location 4374 is depicted as connecting the underlying eight matching metal layers 4354, 4356, 4358, 4360, 4362, 4364, 4366 and 4368.

In summary, in one embodiment, complementary lithography as described herein involves first fabricating a grid-like layout by conventional or state-of-the-art lithography, such as 193 nm immersion lithography (193i). Pitch division can be implemented to increase the density of lines in a grid layout by a factor of n. Grid layout formation using 193i lithography plus pitch divisions by a factor of n may be designated as 193i+P/n pitch divisions. The patterned grid layout with pitch division can then be patterned using electron beam direct writing (EBDW) "dicing". In one such embodiment, 193 nm immersion scaling can be extended over many generations with cost-effective pitch segmentation. In one embodiment, complementary EBLs are used to break grating continuity and pattern vias. In another embodiment, complementary EUV is used to break grating continuity and pattern vias.

Figure 44 illustrates a computing device 4400, in accordance with one embodiment of the present invention. Computing device 4400 contains circuit board 4402 . The circuit board 4402 may include several components including, but not limited to, a processor 4404 and at least one communication chip 4406 . The processor 4404 is physically and electrically coupled to the circuit board 4402. In some embodiments, at least one communication chip 4406 is also physically and electrically coupled to the circuit board 4402. In further embodiments, the communication chip 4406 is part of the processor 4404.

Depending on its application, computing device 4400 may include other components, which may or may not be physically and electrically coupled to circuit board 4402 . These other components include, but are not limited to, volatile memory (eg, DRAM), non-volatile memory (eg, ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chips group, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, Cameras, and mass storage devices (such as hard drives, compact discs (CD), digital discs (DVD), etc.).

Communication chip 4406 enables wireless communication for data transfer to and from computing device 4400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which can communicate data through the use of modulated electromagnetic radiation through non-solid media. The term does not imply that its associated device does not contain any wiring, although in some embodiments it may not. Communication chip 4406 may implement any of several wireless standards or protocols, including (but not limited to) Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G, and above. Computing device 4400 may include a plurality of communication chips 4406 . For example, the first communication chip 4406 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth; and the second communication chip 4406 can be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE , Ev-DO and others.

The processor 4404 of the computing device 4400 includes an integrated circuit die packaged within the processor 4404 . In some implementations of embodiments of the present invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors constructed in accordance with embodiments of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to convert the electronic data into something that can be stored in registers and/or memory other electronic data.

The communication chip 4406 also includes an integrated circuit die packaged within the communication chip 4406 . According to another embodiment of the present invention, the integrated circuit die of the communication chip is constructed according to the embodiment of the present invention.

In further embodiments, another component included within computing device 4400 may contain an integrated circuit die constructed in accordance with implementations of embodiments of the present invention.

In various implementations, the computing device 4400 may be a laptop computer, a small notebook, a notebook computer, a thin and light notebook, a smartphone, an input pad, a personal digital assistant (PDA), an ultralight mobile PC, a mobile phone , desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further embodiments, computing device 4400 may be any other electronic device that processes data.

Figure 45 illustrates an inserter 4500 that includes one or more embodiments of the present invention. The interposer 4500 is an intermediate substrate for bridging the first substrate 4502 to the second substrate 4504 . The first substrate 4502 may be, for example, an integrated circuit die. The second substrate 4504 can be, for example, a memory module, a computer motherboard, or other integrated circuit die. Typically, the purpose of interposer 4500 is to extend connections to wider pitches or to reroute connections to different connections. For example, the interposer 4500 can couple the integrated circuit die to a ball grid array (BGA) 506 , which can subsequently be coupled to the second substrate 4504 . In some embodiments, the first and second substrates 4502/4504 are mounted to opposite sides of the interposer 4500. In other embodiments, the first and second substrates 4502/4504 are mounted to the same side of the interposer 4500. And in further embodiments, three or more substrates are interconnected via interposer 4500.

The interposer 4500 may be formed from epoxy, glass fiber reinforced epoxy, ceramic materials, or polymeric materials such as polyimide. In further embodiments, the interposer may be formed of alternative hard or elastic materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other III-V or IV materials.

The interposer may include metal interconnects 4508 and vias 4510, including but not limited to through silicon vias (TSVs) 4512. The interposer 4500 may further include embedded devices 4514, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, inductors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices can also be formed on the interposer 4500. The apparatus or process disclosed herein may be used in the manufacture of the interposer 4500 in accordance with embodiments of the present invention.

Accordingly, embodiments of the present invention include sub-10 nm pitch patterned and self-polymerizing devices.

Example Embodiment 1: An integrated circuit structure includes a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a grating pattern interrupted by partial body portions. The trench isolation layer is between the plurality of semiconductor bodies and adjacent to the lower part of the plurality of semiconductor bodies, but not adjacent to the upper part of the plurality of semiconductor bodies, wherein the trench isolation layer is located in the part on the body part. One or more gate electrode stacks are on top surfaces of the upper portions of the plurality of semiconductor bodies and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies, and on the trench isolation layer on the part. A back end of line (BEOL) metallization layer is over the one or more gate electrode stacks, the BEOL metallization layer including a plurality of alternating first and second conductive line types along the same direction, wherein the first conductive The overall composition of the wire types is different from the overall composition of the second conductive wire type.

Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein the lines of the first conductive line type are separated by a pitch, and wherein the lines of the second conductive line type are separated by the pitch.

Example Embodiment 3: The integrated circuit structure of Example Embodiment 1 or 2, wherein the plurality of alternating first and second conductive line types are in an interlayer dielectric (ILD) layer.

Example Embodiment 4: The integrated circuit structure of Example Embodiment 1 or 2, wherein the lines of the plurality of alternating first and second conductive line types are separated by air gaps.

Example Embodiment 5: The integrated circuit structure of Example Embodiments 1, 2, 3, or 4, wherein the overall composition of the first conductive line type comprises substantially copper, and wherein the overall composition of the second conductive line type substantially comprises copper The above includes materials selected from the group consisting of Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au and alloys thereof.

Example Embodiment 6: The integrated circuit structure of Example Embodiments 1, 2, 3, 4, or 5, wherein the lines of the plurality of alternating first and second conductive line types each include a bottom along the line and sidewall barrier layer.

Example Embodiment 7: The integrated circuit structure of Example Embodiments 1, 2, 3, 4, or 5, wherein the lines of the plurality of alternating first and second conductive line types each include a bottom portion along the line but The barrier layer is not along the sidewall of the line.

Example Embodiment 8: The integrated circuit structure of Example Embodiments 1, 2, 3, 4, 5, 6, or 7, wherein one or more of the lines of the plurality of alternating first and second conductive line types which are connected to lower vias, which are connected to lower metallization layers between the one or more gate electrode stacks and the BEOL metallization layer, and wherein the plurality of alternating One or more of the lines of the first and second conductive line types are interrupted by dielectric plugs.

Example Embodiment 9: The integrated circuit structure of Example Embodiments 1, 2, 3, 4, 5, 6, 7, or 8, wherein the grating pattern has a constant pitch.

Example Embodiment 10: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, 5, 6, 7, 8, or 9, further comprising source electrodes on both sides of the one or more gate electrode stacks or drain regions, wherein the source or drain regions are adjacent to the upper portions of the plurality of semiconductor bodies and include a different semiconductor material than the semiconductor material of the semiconductor bodies.

Example Embodiment 11: The integrated circuit structure of Example Embodiment 1, 2, 3, 4, 5, 6, 7, 8, or 9, further comprising source electrodes on both sides of the one or more gate electrode stacks or drain regions, wherein the source or drain regions are located within the upper portions of the plurality of semiconductor bodies.

Example Embodiment 12: The integrated circuit structure of Example Embodiments 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, or 11, wherein each of the one or more gate electrode stacks includes High-k gate dielectric layer and metal gate electrode.

Example Embodiment 13: The integrated circuit structure of Example Embodiments 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, or 12, wherein the first conductive line types have upper surfaces, which having a metal composition different from the metal composition of the upper surface of the second conductive line type.

Example Embodiment 14: An integrated circuit structure includes a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a grating pattern interrupted by partial body portions. The trench isolation layer is between the plurality of semiconductor bodies and adjacent to the lower part of the plurality of semiconductor bodies, but not adjacent to the upper part of the plurality of semiconductor bodies, wherein the trench isolation layer is located in the part on the body part. One or more gate electrode stacks are on top surfaces of the upper portions of the plurality of semiconductor bodies and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies, and on the trench isolation layer on the part. A back end of line (BEOL) metallization layer is over the one or more gate electrode stacks, the BEOL metallization layer including a plurality of alternating first and second conductive line types along the same direction, wherein the plurality of alternating The lines of the first and second conductive line types each include barrier layers along the bottom of the line but not along the sidewalls of the line.

Example Embodiment 15: The integrated circuit structure of Example Embodiment 14, wherein the lines of the first conductive line type are separated by a pitch, and wherein the lines of the second conductive line type are separated by the pitch.

Example Embodiment 16: The integrated circuit structure of Example Embodiment 14 or 15, wherein the plurality of alternating first and second conductive line types are in an interlayer dielectric (ILD) layer.

Example Embodiment 17: The integrated circuit structure of Example Embodiment 14 or 15, wherein the lines of the plurality of alternating first and second conductive line types are separated by air gaps.

Example Embodiment 18: The integrated circuit structure of Example Embodiment 14, 15, 16 or 17, wherein the overall composition of the first conductive line type is the same as the overall composition of the second conductive line type.

Example Embodiment 19: The integrated circuit structure of Example Embodiments 14, 15, 16, or 17, wherein the overall composition of the first conductive line type includes substantially copper, and wherein the overall composition of the second conductive line type includes substantially A material selected from the group consisting of Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au and alloys thereof.

Example Embodiment 20: The integrated circuit structure of Example Embodiments 14, 15, 16, 17, 18, or 19, wherein one or more of the lines of the plurality of alternating first and second conductive line types are connected to an underlying via, which is connected to an underlying metallization layer between the one or more gate electrode stacks and the BEOL metallization layer, and wherein the plurality of alternating first One or more of the lines of one and the second conductive line type are interrupted by dielectric plugs.

Example Embodiment 21: The integrated circuit structure of Example Embodiments 14, 15, 16, 17, 18, 19, or 20, wherein the grating pattern has a constant pitch.

Example Embodiment 22: The integrated circuit structure of Example Embodiment 14, 15, 16, 17, 18, 19, 20, or 21, further comprising source or drain electrodes on both sides of the one or more gate electrode stacks electrode regions, wherein the source or drain regions are adjacent to the upper portions of the plurality of semiconductor bodies and include a semiconductor material different from the semiconductor material of the semiconductor bodies.

Example Embodiment 23: The integrated circuit structure of Example Embodiment 14, 15, 16, 17, 18, 19, 20, or 21, further comprising source or drain electrodes on both sides of the one or more gate electrode stacks regions, wherein the source or drain regions are located within the upper portions of the plurality of semiconductor bodies.

Example Embodiment 24: The integrated circuit structure of Example Embodiments 14, 15, 16, 17, 18, 19, 20, 21, 22, or 23, wherein each of the one or more gate electrode stacks includes a high-k Gate dielectric layer and metal gate electrode.

Example Embodiment 25: An integrated circuit structure includes a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a first grating pattern interrupted by partial body portions. The trench isolation layer is between the plurality of semiconductor bodies and adjacent to the lower part of the plurality of semiconductor bodies, but not adjacent to the upper part of the plurality of semiconductor bodies, wherein the trench isolation layer is located in the part on the body part. One or more gate electrode stacks are on top surfaces of the upper portions of the plurality of semiconductor bodies and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies, and on the trench isolation layer on the part. A first back end of line (BEOL) metallization layer is over the one or more gate electrode stacks, the first BEOL metallization layer including a second grating of alternating metal and dielectric lines in a first direction. A second BEOL metallization layer is over the first BEOL metallization layer, the second BEOL metallization layer including a third grating of alternating metal and dielectric lines in a second direction. The second direction is orthogonal to the first direction. The metal lines of the third grating of the second BEOL metallization layer are attached to a dielectric layer comprising a first dielectric material and a first dielectric layer corresponding to alternating metal lines and dielectric layer lines of the first BEOL metallization layer Two alternating regions of dielectric material. Each dielectric line of the third grating of the second BEOL metallization layer includes a continuous region of third dielectric material that is different from the alternating distinct regions of the first dielectric material and the second dielectric material.

Example Embodiment 26: The integrated circuit structure of Example Embodiment 25, wherein the metal lines of the second BEOL metallization layer are electrically coupled to the metal lines of the first BEOL metallization layer through vias, the via holes There is a center directly aligned with the center of the metal line of the first BEOL metallization layer and with the center of the metal line of the second BEOL metallization layer.

Example Embodiment 27: The integrated circuit structure of Example Embodiment 25 or 26, wherein the metal lines of the second BEOL metallization layer are interrupted by plugs having a connection with the first BEOL metallization layer. The center of the dielectric line is directly aligned with the center.

Example Embodiment 28: The integrated circuit structure of Example Embodiment 25, 26 or 27, wherein the first dielectric material, the second dielectric material, and the third dielectric material are not the same material.

Example Embodiment 29: The integrated circuit structure of Example Embodiments 25, 26, or 27, wherein only two of the first dielectric material, the second dielectric material, and the third dielectric material are the same material.

Example Embodiment 30: The integrated circuit structure of Example Embodiments 25, 26, 27, 28, or 29, wherein the alternating different regions of the first dielectric material and the second dielectric material are separated by seams, and wherein The continuous region of the third dielectric material is separated from the alternating distinct regions of the first dielectric material and the second dielectric material by seams.

Example Embodiment 31: The integrated circuit structure of Example Embodiment 25, 26, 27 or 30, wherein the first dielectric material, the second dielectric material, and the third dielectric material are all the same material.

Example Embodiment 32: The integrated circuit structure of Example Embodiment 25, 26, 27, 28, 29, 30, or 31, wherein the first grating pattern has a constant pitch.

Example Embodiment 33: The integrated circuit structure of Example Embodiments 25, 26, 27, 28, 29, 30, 31 or 32, further comprising source or drain electrodes on both sides of the one or more gate electrode stacks electrode regions, wherein the source or drain regions are adjacent to the upper portions of the plurality of semiconductor bodies and include a semiconductor material different from the semiconductor material of the semiconductor bodies.

Example Embodiment 34: The integrated circuit structure of Example Embodiments 25, 26, 27, 28, 29, 30, 31 or 32, further comprising source or drain electrodes on both sides of the one or more gate electrode stacks regions, wherein the source or drain regions are located within the upper portions of the plurality of semiconductor bodies.

Example Embodiment 35: The integrated circuit structure of Example Embodiments 25, 26, 27, 28, 29, 30, 31, 32, 33, or 34, wherein each of the one or more gate electrode stacks includes a high-k Gate dielectric layer and metal gate electrode.

Example Embodiment 36: The integrated circuit structure of Example Embodiments 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, or 35, wherein an etch stop layer or additional dielectric layer separates the first BEOL metal and the second BEOL metallization layer.

Example Embodiment 37: A method of fabricating an integrated circuit structure comprising forming a plurality of backbone features over a substrate, forming a first set of spacers along sidewalls of each of the plurality of backbone features, the first set of spacers having different A first set of spacers consisting of materials of the plurality of backbone features, forming a second set of spacers along sidewalls of each of the first set of spacers, the second set of spacers having a different material than the first set of spacers a second material composition that is different from the material composition of the plurality of backbone features, forming a third set of spacers along the sidewalls of each of the second set of spacers, the third set of spacers having different The first material composition, a third material composition different from the second material composition, and a third material composition different from the material composition of the plurality of backbone features form a fourth set along the sidewalls of each of the third set of spacers spacers, the fourth set of spacers having the second material composition, forming a fifth set of spacers laterally adjacent to the sidewalls of each of the fourth set of spacers, the fifth set of spacers having the a first material consisting of removing the plurality of backbone features after forming the fifth set of spacers, along the sidewalls of each of the first set of spacers and along the The sidewalls of each of the fifth sets of spacers form a sixth set of spacers having the second material composition formed between adjacent pairs of spacers that are finally characterized by the sixth set of spacers In each opening of the first group of spacers, the second group of spacers, the third group of spacers, the fourth group of spacers, the fifth group of spacers, the Six sets of spacers, and the final features, to form a target base layer, and use the target base layer to form a metallization layer of the semiconductor structure.

Example Embodiment 38: The method of Example Embodiment 37, wherein forming the plurality of backbone features includes using standard lithography operations.

Example Embodiment 39: The method of Example Embodiment 37 or 38, wherein forming the plurality of backbone features includes forming the plurality of features comprising a material selected from the group consisting of silicon nitride, silicon oxide, and silicon carbide.

Example Embodiment 40: The method of example embodiment 37, 38, or 39, wherein forming the first sets of spacers comprises using an atomic layer deposition (ALD) process to deposit the first sets of the plurality of backbone features conformal a material of spacers, anisotropically etching the material of the first set of spacers to form the first set of spacers along the sidewalls of each of the plurality of backbone features.

Example Embodiment 41: The method of example embodiment 37, 38, or 39, wherein forming the first set of spacers comprises selectively growing the first set of spacers along the sidewalls of each of the plurality of backbone features material of the thing.

Exemplary Embodiment 42: The method of Exemplary Embodiments 37, 38, 39, 40, or 41, wherein each final feature has a greater value from the first set of spacers, the second set of spacers, the third set of spacers , the side width of the side widths of the spacers of the fourth group of spacers, the fifth group of spacers, and the spacers of the sixth group of spacers.

Example Embodiment 43: The method of Example Embodiments 37, 38, 39, 40, 41, or 42, wherein each final feature is grown by material formed along adjacent pairs of spacers of the sixth set of spacers. merged to form.

Example Embodiment 44: The method of Example Embodiments 37, 38, 39, 40, 41, 42, or 43, wherein each final feature includes the third material composition.

Example Embodiment 45: The method of Example Embodiment 37, 38, 39, 40, 41, 42, 43, or 44, wherein using the target base layer to form the metallization layer of the semiconductor structure includes removing the first material composition All parts of the first plurality of trenches are formed, and a first plurality of conductive lines are formed in the first plurality of trenches.

Example Embodiment 46: The method of Example Embodiment 45, wherein using the target base layer to form the metallization layer of the semiconductor structure further comprises removing all portions of the third material composition to form a second plurality of trenches, and forming The second plurality of conductive lines are in the second plurality of trenches.

Example Embodiment 47: The method of Example Embodiment 46, wherein the first plurality of conductive lines and the second plurality of conductive lines are of the same composition.

Example Embodiment 48: The method of Example Embodiment 46, wherein the first plurality of conductive lines and the second plurality of conductive lines are of different compositions.

Example Embodiment 49: The method of example embodiments 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, or 48, further comprising forming an additional 20-200 sets of spacers before forming the fifth between the set of spacers and the sixth set of spacers, and before removing the plurality of backbone features.

Example Embodiment 50: A target structure for fabricating an integrated circuit structure includes a first set of spacers over a hard mask layer over a substrate, the first set of spacers having a first material composition. A second set of spacers is along the outer sidewall of each of the first set of spacers, the second set of spacers having a second material composition different from the first material composition. A third set of spacers are along the sidewalls of each of the second set of spacers, the third set of spacers having a third material composition different from the first material composition and different from the second material composition . A fourth set of spacers is along the sidewall of each of the third set of spacers, the fourth set of spacers having the second material composition. A fifth set of spacers is laterally adjacent to a sidewall of each of the fourth set of spacers, the fifth set of spacers having the first material composition. A sixth set of spacers is along the inner sidewall of each of the first set of spacers and along the sidewall of each of the fifth set of spacers, the sixth set of spacers having the second material composition . The final feature is in each opening between adjacent pairs of spacers of the sixth set of spacers.

Example Embodiment 51: The target structure of Example Embodiment 50, wherein the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers The set of spacers, the sixth set of spacers, and the final features are substantially coplanar with each other.

Exemplary Embodiment 52: The target structure of Exemplary Embodiments 50 or 51, wherein each final feature has a greater value from the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers The side width of the side width of each spacer of the set of spacers, the fifth set of spacers, and the sixth set of spacers.

Example Embodiment 53: The target structure of Example Embodiment 52, wherein the side width of each final feature is in the range of 6-12 nm.

Example Embodiment 54: The target structure of example embodiments 50, 51, 52, or 53, wherein each final feature has a seam approximately centered within the final feature.

Example Embodiment 55: The target structure of example embodiments 50, 51, 52, 53, or 54, wherein each final feature includes the third material composition.

100‧‧‧Starting Structure 102‧‧‧Interlayer Dielectric (ILD) Layer 104‧‧‧Hard Mask Material Layer 106‧‧‧Patterned Mask 108‧‧‧Spacers 110‧‧‧Patterned Hard Mask 402‧ ‧‧Bulk semiconductor substrate 404‧‧‧First patterned hard mask 406‧‧‧Pitch 408‧‧‧Second hard mask layer 410‧‧‧Selective brush material layer 414‧‧‧First polymer Block 416‧‧‧Second Polymer Block 416A‧‧‧Part 416B‧‧‧Part 418, 418', 418"‧‧‧Fin 420‧‧‧Patterned Base 422‧‧‧Surface 424‧‧‧ Second patterned hard mask layer 426‧‧‧resulting pitch 428, 428', 428"‧‧‧Interlayer dielectric (ILD) layer 430‧‧‧patterned mask 432‧‧‧opening 434‧‧‧edge layout Error (EPE) 436‧‧‧Cutting Size 438‧‧‧Position 440‧‧‧Level 442‧‧‧Level 444‧‧‧Level 446‧‧‧Protrusion 448‧‧‧Depression 450‧‧‧Patterning Mask 452‧‧‧Opening 454‧‧‧Position 456‧‧‧Level 458‧‧‧Level 460‧‧‧Level 462‧‧‧Level 464‧‧‧Protrusion 466‧‧‧Recess 468, 468 ', 468"‧‧‧Interlayer Dielectric (ILD) Layer 472‧‧‧Protrusion 474‧‧‧Lower Fin Section 476‧‧‧Recess Height 600‧‧‧Semiconductor Structure or Device 602‧‧‧Substrate 604‧‧‧ Protruding Fin Portions 604A, 604B‧‧‧Source and Drain Regions 605‧‧‧Sub-fin Regions 606‧‧‧Isolation Regions 608‧‧‧Gate Lines 614‧‧‧Gate Contacts 616‧‧Over Gate Pole Contact Vias 650‧‧‧Gate Electrode 652‧‧‧Gate Dielectric Layer 654‧‧‧Dielectric Layer Cap 660‧‧‧Overlying Metal Interconnect 670‧‧‧Interlayer Dielectric Stack or Layer 680‧‧‧Interface 699‧‧‧Residual Overhangs 700‧‧‧Target Base Layer 702‧‧‧Patterning Layer 704‧‧‧Hard Mask Layer 706‧‧‧Transfer Layer 708‧‧‧Substrate 710‧‧‧Backbone Features 712‧‧‧ Middle Group 714‧‧‧Small Features of Second Material Type 716‧‧‧Small Features of First Material Type 718‧‧‧Small Features of Third Material Type 750‧‧‧Target Base Layer 752‧‧‧Patterned Layer 754‧‧‧Hard Mask Layer 756‧‧‧Transfer Layer 758‧‧‧Substrate 760‧‧‧Backbone Features 762‧‧‧Intermediate Group 764‧‧‧Small Features of First Material Type 766‧‧‧Second Material Types of Small Features 768‧‧‧Small Features of Third Material Type 802‧‧‧Substrate 804‧‧‧Transfer Layer 806‧‧‧Hard Mask Layer 808 ‧‧‧Second set of small features 814‧‧‧Third set of small features 816‧‧‧Fourth set of small features 818 ‧‧‧Additional Spacer Layer 820‧‧‧Opening 822‧‧‧Opening 824‧‧‧Spacer 826‧‧‧Spacer 828‧‧‧Final Wide Feature 830‧‧‧Metal Line Patterning Feature 830'‧‧‧ Metal Line 832‧‧‧Lower Via Patterned Feature 834‧‧‧Layer 836‧‧‧Overlying Hard Mask Cap Layer 838‧‧‧Second Metal Line Patterned Feature 840‧‧‧Lower Second Via Patterned Features 842‧‧‧Overlying Hard Mask Cap Layer 850‧‧‧Plug Material 900‧‧‧Starting Point Structure 902‧‧‧Hard Mask Layer 904‧‧‧Sacrificial Layer 906‧‧‧Interlayer Dielectric (ILD) Layer 908‧‧‧Patterned hard mask layer 910‧‧‧Patterned sacrificial layer 912‧‧‧First line opening 914‧‧‧Line termination area 916‧‧‧Through hole opening 918‧‧‧Patterned ILD layer 920‧ ‧‧Interconnection line 922‧‧‧Conductive hole 924‧‧‧Wire end opening 926‧‧‧Spacer material layer 928‧‧‧Spacer 930‧‧‧Wire end occupying part 932‧‧‧Plug placeholder Layer 934‧‧‧Plug Placement 936‧‧‧Interconnect Line 938‧‧‧Conductive Via 940‧‧‧Patterned ILD Layer 942‧‧‧Line Terminal Opening 946/948‧‧‧Interlayer Dielectric (ILD) Layer 999‧‧‧Semiconductor Structure 1000‧‧‧Starting Structure 1002‧‧‧Metal Line 1002'‧‧‧Line 1004‧‧‧Interlayer Dielectric Line (ILD) 1006‧‧‧Extra Film 1008‧‧‧Extra Film 1010‧‧‧ Interlayer Dielectric (ILD) Lines 1012‧‧‧Hard Mask 1014‧‧‧Surface Modification Layer 1016‧‧‧Intermediate Lines 1016A‧‧‧Polymer 1016B‧‧‧Polymer 1018‧‧‧Permanent Interlayer Dielectric (ILD) Layer 1020 ‧‧‧Hard Mask Layers 1022A, 1022B, 1022C‧‧‧Through Hole Locations 1024A, 1024B, 1024C‧‧‧Through Hole 1026‧‧‧ILD Layer 1026'‧‧‧Recessed ILD Layer 1028A, 1028B, 1028C‧‧ ‧Plug Location 1030‧‧‧Wire 1032‧‧‧Through Hole 1090‧‧‧First Material Type 1092‧‧‧Second Material Type 1097‧‧‧Seam 1099‧‧‧Seam 1100‧‧‧Starting Structure 1102‧‧‧Metal Lines 1102'‧‧‧Lines 1104‧‧‧Interlayer Dielectric Lines (ILDs) 1106‧‧‧Extra Films 1108‧‧‧Extra Films 1110‧‧‧Structures 1112‧‧‧Structures 1114‧‧‧Structures 1116 ‧‧‧Conformal Layer 1118‧‧‧Structure 1119‧‧‧ILD Material Layer 1120‧‧‧Permanent Interlayer Dielectric (ILD) Line 1120'‧‧‧Recessed ILD Line 1122‧‧‧Structure 1123‧‧‧Conformal Material Layer 1124‧‧‧Hard Mask Layer 1126‧‧‧Structure 1128‧‧‧Permanent ILD Line 1128'‧‧‧Recessed IL D Line 1130‧‧‧Structure 1132‧‧‧Trench 1134‧‧‧Material Layer 1136‧‧‧Mask 1136A‧‧‧Photoresist Layer 1136B‧‧‧Anti-Reflection Coating (ARC) 1136C‧‧‧Topography Shielded portion 1137‧‧‧opening 1138‧‧‧second mask 1140‧‧‧metal wire 1142, 1144‧‧‧reserved plug 1199‧‧‧seam 1200‧‧‧semiconductor structure layer 1202‧‧‧metal wire 1204‧‧‧Interlayer dielectric (ILD) lines 1206‧‧‧First molecular species 1208‧‧‧Second molecular species 1210‧‧‧A/B surface 1212‧‧‧C surface 1214‧‧‧Triblock copolymer 1220 ‧‧‧Separation structure 1222‧‧‧First area 1224‧‧‧Second area 1226‧‧‧Third area 1250‧‧‧Separating three blocks BCP1252‧‧‧Shaft 1260‧‧‧Starting structure 1262‧‧‧Metal Line 1262'‧‧‧Line 1264‧‧‧Interlayer Dielectric Line 1266‧‧‧Extra Film 1268‧‧‧Extra Film 1270‧‧‧Triblock Copolymer Layer 1272‧‧‧Region 1274‧‧‧Second Region 1276‧ ‧‧Third Zone 1280‧‧‧Layer 1282‧‧‧Layer 1290‧‧‧Lithography 1292‧‧‧Some 1294‧‧‧Area 1302‧‧‧Metal Line 1304‧‧‧Dielectric Layer 1306‧‧‧Example 1308 , 1310‧‧‧Plug 1314‧‧‧Dielectric Line 1400‧‧‧Starting Point Structure 1402‧‧‧Metal Line 1404‧‧‧Interlayer Interlayer Dielectric (ILD) Line 1406‧‧‧Plug Cap 1408‧‧‧Section First order metal lines 1410‧‧‧Hard mask layer 1412‧‧‧Second hard mask layer 1414‧‧‧Trenches 1416‧‧‧Second ILD lines 1418‧‧‧Opening 1420‧‧‧Light barrels 1422‧‧ ‧Through Hole Location 1424‧‧‧Area 1426‧‧‧Hard Mask Layer 1428‧‧‧Light Barrel 1430‧‧‧Non-Plug Location 1432‧‧‧Area 1434‧‧‧Through Hole Opening 1436‧‧‧Metal Line 1438 ‧‧‧Through hole 1496‧‧‧Seam 1497‧‧‧Seam 1498‧‧‧Seam 1499‧‧‧Seam 1500‧‧‧Start plug grid structure 1502‧‧‧ILD layer 1504‧‧‧Section A hard mask layer 1506‧‧‧Third hard mask layer 1508‧‧‧Second hard mask layer 1510‧‧‧Opening 1512‧‧‧Light barrel 1514‧‧‧Plug position 1516‧‧‧Plug 1600 ‧‧‧Starting Point Structure 1602‧‧‧Interlayer Dielectric (ILD) Layer 1604‧‧‧Hard Mask Layer 1606‧‧‧First Metal Line 1607‧‧‧Conductive Via 1608‧‧‧Trench 1608A‧‧‧Sidewall 1608B‧‧‧Bottom 1610‧‧‧Non-Conformal Dielectric Cap 1610A‧‧‧First Part 1610B‧‧‧Second Part 16 12‧‧‧Second Metal Line 1613‧‧‧Through Hole 1614‧‧‧First Hard Mask Layer 1616‧‧‧Second Hard Mask Layer 1630‧‧‧Starting Point Structure 1632‧‧‧Interlayer Dielectric (ILD) Layer 1634‧‧‧Hard Mask Layer 1636‧‧‧First Metal Line 1636A‧‧‧Projection 1637‧‧‧Conductive Via 1638‧‧‧Dielectric Spacer 1640‧‧‧Sacrificial Hard Mask Layer 1642‧‧‧ Trench 1644‧‧‧Sacrificial Material 1646‧‧‧Non-Conformal Dielectric Cap 1648‧‧‧Sacrificial Cap 1650‧‧‧Location 1652‧‧‧Via Location 1654‧‧‧Second Metal Line 1656‧‧‧Conductive Through hole 1658‧‧‧First placeholder material 1660‧‧‧Second placeholder material 1662‧‧‧First hard mask layer 1664‧‧‧Second hard mask layer 1666‧‧‧Top ILD layer 1668‧‧ ‧Opening 1670‧‧‧Conductive Via 1672‧‧‧Part 1700‧‧‧Starting Point Structure 1702‧‧‧Interlayer Dielectric (ILD) Layer 1704‧‧‧Hard Mask Layer 1706‧‧‧First Metal Line 1706A‧‧ ‧Projections 1707‧‧‧Conductive Vias 1708‧‧‧Dielectric Spacers 1710‧‧‧Sacrificial Hardmask 1712‧‧‧Trenches 1714‧‧‧Sacrificial Material 1715‧‧‧Recessed Sacrificial Material 1716‧‧‧Non Conformal Dielectric Cap Layer 1716A‧‧‧Top Part 1722‧‧‧Via Location 1724‧‧‧Second Metal Line 1726‧‧‧Conductive Via 1728‧‧‧First Placeholder Material 1730‧‧‧Second Placeholder Material 1732‧‧‧First Hard Mask Layer 1734‧‧‧Second Hard Mask Layer 1736‧‧‧Upper ILD Layer 1738‧‧‧Opening 1740‧‧‧Conductive Via 1742‧‧‧Part 1800‧‧‧Start Dot Structures 1802‧‧‧Metal Lines 1804‧‧‧Dielectric Lines 1806‧‧‧Etch Stop Layer 1808‧‧‧Interlayer Dielectric Layer 1810‧‧‧Patterned Hardmask 1812‧‧‧Patterned Interlayer Dielectric Layer 1814‧‧ ‧Metal Line Area 1816‧‧‧Hard Mask Layer 1818‧‧‧Etch Stop Layer 1820‧‧‧Pattern Accumulation Layer 1822‧‧‧Patterned Hard Mask 1824‧‧‧Hard Mask 1826‧‧‧One Pattern Memory Bulk Layer 1828‧‧‧Barrier Line 1830‧‧‧Insulating Spacer Forming Material Layer 1832‧‧‧Spacer 1834‧‧‧Secondary Patterned Memory Layer 1836‧‧‧Patterned Etch Stop Layer 1838‧‧‧Patterned Hardmask Cap Layer 1840‧‧‧Secondary Patterned Interlayer Dielectric Layer 1842‧‧‧Patterned Etch Stop Layer 1844‧‧‧Via Location 1846‧‧‧Location 1848‧‧‧Metal Via 1850‧‧‧Metal Line 1900‧‧ ‧Starting Point Structure 1900'‧‧‧Structure 1900"‧‧‧Structure 1902‧‧‧Metal Line 1904‧‧‧Dielectric Line 1 906‧‧‧Hard mask layer 1908‧‧‧Next patterned layer 1910‧‧‧Etch stop layer 1912‧‧‧Dielectric layer 1914‧‧‧Grate structure 1916‧‧‧Patterned dielectric layer 1918‧‧‧Patterned Etch Stop Layer 1920‧‧‧Via Locations 1922‧‧‧Patterned Hard Mask 1924‧‧‧Region 1926‧‧‧Patterned Lithography Mask 1928‧‧‧Region 1930‧‧‧Underlying Structure 1932‧‧‧Metal Vias 1934‧‧‧Metal Lines 1936‧‧‧Metal Lines 1938‧‧‧Metal Lines 1940‧‧‧Hard Mask Layer 2000‧‧‧Starting Point Structure 2002‧‧‧Interlayer Dielectric (ILD) Material Layer 2004‧‧‧ First Hard Mask Layer 2006‧‧‧Second Hard Mask Layer 2008‧‧‧Third Hard Mask Layer 2010‧‧‧Photolithography Patterned Mask 2012‧‧‧Patterned Hard Mask Layer 2014‧‧‧ Patterned ILD Layer 2016‧‧‧Patterned Hard Mask Layer 2018‧‧‧Metal Lines 2020‧‧‧Conductive Vias 2100‧‧‧Metalization Layer 2102‧‧‧Metal Lines 2103‧‧‧Lower Vias 2104‧‧ ‧Dielectric layer 2105‧‧‧Line termination or plug area 2106‧‧‧Line trench 2108‧‧‧Through hole trench 2110‧‧‧Hard mask layer 2112‧‧‧Line trench 2114‧‧‧Through hole trench Trenches 2120‧‧‧Metalization layer 2122‧‧‧Metal line 2124‧‧‧Dielectric layer 2126‧‧‧Interlayer dielectric (ILD) material layer 2128, 2128'‧‧‧Line trench 2130‧‧‧Lower portion 2130' ‧‧‧Patterned lower portion 2132A, 2132B‧‧‧Through hole trench 2134‧‧‧Sacrificial material 2134'‧‧‧Patterned and filled sacrificial material 2136‧‧‧Patterned hard mask layer 2138‧‧‧ Dielectric Material 2140A, 2140B‧‧‧Dielectric Plug 2142‧‧‧Metal Line 2144‧‧‧Conductive Via 2150‧‧‧Seam 2152‧‧‧Dielectric Plug 2152A, 2152B‧‧‧Dielectric Plug 2154'‧‧ ‧Patterned dielectric layer 2202‧‧‧Substrate or layer 2204‧‧‧holes/trenches 2206‧‧‧placeholder material 2208‧‧‧Minor depressions 2210‧‧‧patterned layer 2212‧‧‧openings 2214‧‧‧re Exposed holes/trenches 2216‧‧‧Material layer 2252‧‧‧Metalization layer 2254‧‧‧Metal line 2256, 2258‧‧‧ILD material 2260‧‧‧Sacrificial placeholder material 2262‧‧‧mask layer 2264‧‧ ‧Opening 2266‧‧‧Via location 2300‧‧‧Starting structure 2302‧‧‧Interlayer dielectric (ILD) layer 2302'‧‧‧Patterned ILD layer 2304‧‧‧First hard mask material layer 2306‧‧‧ Patterned Mask 2308‧‧‧Spacer 2310‧‧‧First Patterned Hard Mask 2312‧‧‧Second Image Patterned Hard Mask 2314‧‧‧Hard Mask Cover Layer 2316‧‧‧First Patterned Hard Mask 2318‧‧‧Light Barrel 2320‧‧‧Through Hole Positions 2322‧‧‧Hard Mask Material 2324‧‧‧ Light Barrel 2326‧‧‧Location 2328‧‧‧Through Hole Opening 2330‧‧‧Wire Opening 2332‧‧‧Metalization 2334‧‧‧Top Area 2350‧‧‧Start Grid Structure 2351‧‧‧Substrate 2352‧‧‧ Grating ILD layer 2354‧‧‧First hard mask layer 2356‧‧‧Second hard mask layer 2358‧‧‧Opening 2358'‧‧‧Opening 2360‧‧‧Dielectric layer 2362‧‧‧Light barrel 2364‧‧ ‧Through Hole Location 2364'‧‧‧Opening 2366‧‧‧Remaining Opening 2400‧‧‧Starting Point Structure 2402‧‧‧Metal Line 2404 ‧‧‧ILD Material Layer 2410‧‧‧Hard Mask Layer 2412‧‧‧Trench 2414‧‧‧Patterned ILD Layer 2416 ‧‧‧Metal Lines 2424‧‧‧Through Holes 2450‧‧‧Single Plane 2497‧‧‧Seam 2498‧‧‧Seam 2499‧‧‧Seam 2500‧‧‧Starting Structure 2502‧‧‧Interlayer Dielectric (ILD) Layer 2502'‧‧‧Patterned ILD Layer 2504‧‧‧First Hard Mask Material Layer 2506‧‧‧Patterned Mask 2508‧‧‧Spacer 2510‧‧‧Trenches 2512‧‧‧First Color Light Barrel 2512A‧‧‧Selected 1st Color Light Barrel 2513A‧‧‧Selected Via Opening 2514‧‧‧Groove 2516‧‧‧Second Color Light Barrel Material Layer 2518‧‧‧Second Color Light Barrel 2518A, 2518B ‧‧‧Selected 2nd Color Light Barrel 2519A, 2519B‧‧‧Through Hole Opening 2520‧‧‧Second Hard Mask 2521‧‧‧Red Mass Exposure 2522‧‧‧Third Hard Mask 2523‧‧‧Green Mass Exposure 2524‧‧‧Through Hole Locations 2526‧‧‧Metal Line Trench 2600‧‧‧Traditional BEOL Metallization 2602‧‧‧Interlayer Dielectric Layer 2604‧‧‧Conductive Lines or Routing 2606‧‧‧Cutting, Interrupting, or Plugging 2608‧‧‧Top or Bottom Routing 2610‧‧‧Conducting Lines 2612‧‧‧Conducting Vias 2650‧‧‧BEOL Metallization 2652‧‧‧Interlayer Dielectric Layer 2654‧‧‧Conducting Lines or Routing 2656‧‧‧Cutting, Interruption or Plug 2658‧‧‧Conductive Sheet 2700‧‧‧Substrate 2702‧‧‧Interlayer Dielectric (ILD) Layer 2704‧‧‧Covering Hard Mask 2706‧‧‧First Grating Hard Mask 2706'‧‧‧Part 2708 ‧‧‧Second Grating Hard Mask 2710‧‧‧Overlying Hard Mask 2712‧‧‧Light Barrel 2714‧ ‧‧First Pattern Hard Mask 2715‧‧‧Second Pattern Hard Mask 2716‧‧‧Dielectric Region 2718‧‧‧Light Barrel 2720‧‧‧Third Pattern Hard Mask 2722‧‧‧ Patterned ILD layer 2724‧‧‧conductive line 2726‧‧‧plug 2728‧‧‧conducting sheet 2800‧‧‧metal layer 2802‧‧‧covering hard mask layer 2804‧‧‧first grating hard mask 2806‧‧ ‧Second Grating Hard Mask 2808‧‧‧Overlying Hard Mask 2810‧‧‧Third Hard Mask 2812‧‧‧Fourth Hard Mask 2814‧‧‧Opening 2816‧‧‧Light Barrel 2818‧‧‧Etching Trench 2820‧‧‧First pattern hard mask 2822‧‧‧First pattern metal layer 2824‧‧‧Conductive via 2826‧‧‧Deep hard mask area 2828‧‧‧Shallow hard mask area 2830‧‧‧Opening 2832‧‧‧Light Barrel 2834‧‧‧Second Patterning Hard Mask 2836‧‧‧Groove2838‧‧‧Deep Hard Mask Area 2840‧‧‧Light Hard Mask Area 2842‧‧ ‧Third time patterning hard mask 2844‧‧‧Second time patterning metal layer 2846‧‧‧Deep hard mask area 2848‧‧‧Opening 2850‧‧‧Light barrel 2852‧‧‧Fourth time patterning hard mask Mask 2854‧‧‧Trench 2856‧‧‧Third Pattern Metal Layer 2858‧‧‧Through Hole Cover 2860‧‧‧ILD2861‧‧‧ILD Backfill 2862‧‧‧Plug Area 2864‧‧‧Conductive Line 2866 ‧‧‧Conductive sheet 2899‧‧‧ILD layer 2902‧‧‧Substrate 2904‧‧‧Pre-patterned hard mask 2906‧‧‧Two-stage bake photoresist 2907‧‧‧Exposure 2908‧‧‧Shifted Aerial Image 2912‧‧‧Closed Light Barrel 2920‧‧‧Opening 2950‧‧‧Partially Cleared 2952‧‧‧Residual Photoresist 2954‧‧‧Light Barrel 3002, 3002', 3002"‧‧‧First Light Barrel 3004, 3004', 3004"‧‧‧Second Light Barrel 3006, 3006'‧‧‧Exposure 3010, 3010', 3010"‧‧‧Photo Acid Generating (PAG) Component 3012‧‧‧Light Radical Generating Component 3014‧‧ ‧Inhibitor 3020, 3022‧‧‧Diffused material 3024, 3026‧‧‧Material 3028, 3030‧‧‧Material 3032‧‧‧Removed light barrel 3034‧‧‧Blocked light barrel 3050‧‧‧Grafted light base Composition 3060‧‧‧Layer 3100‧‧‧Pattern 3102‧‧‧ILD Line 3104‧‧‧Resist Line 3106‧‧‧hole 3202‧‧‧ILD Material 3204‧‧‧Trench 3206‧‧‧Chemical Amplified Light Resist 3208‧‧‧region 3210‧‧‧precatalyst layer 3212‧‧‧dielectric material 3212A, 3212B‧‧‧part 3214‧‧‧crosslinking region 3216‧‧‧metal filling layer 3218‧‧‧Metallic Features 3300‧‧‧Trisilacyclohexane 3320‧‧‧Crosslinking Material 3340‧‧‧Linking Trisilacyclohexane Structure 3400‧‧‧Starting Structure 3402‧‧‧Interlayer Dielectric (ILD) ) layer 3402', 3402", 3402''', 3402'''', 3402'''''‧‧‧Patterned ILD layer 3404‧‧‧First hard mask material layer 3406‧‧‧Patterned mask Mask 3408‧‧‧Spacer 3410‧‧‧First patterned hard mask 3412‧‧‧Second patterned hard mask 3414‧‧‧Hard mask cover layer 3416‧‧‧First patterned hard mask 3418 ‧‧‧Fourth hard mask layer 3420‧‧‧First diagonal hard mask layer 3422‧‧‧Closest adjacent distance 3424‧‧‧Light barrel 3426‧‧‧Through hole position 3428‧‧‧Hard mask Mask Material 3430‧‧‧Light Barrel 3432‧‧‧Through Hole Locations 3434‧‧‧Sacrificial Material 3436‧‧‧Groove 3438‧‧‧Second Diagonal Hard Mask Layer 3440‧‧‧Light Barrel 3442‧‧‧ Nearest Adjacent Distance 3444‧‧‧Trench 3446‧‧‧Hard Mask Material Layer 3448‧‧‧Light Barrel 3450‧‧‧Location 3452‧‧‧Trench 3454‧‧‧Metalization 3456‧‧‧Metal Feature 3502 ‧‧‧First Pre-Patterned Hard Mask 3504‧‧‧Second Pre-Patterned Hard Mask 3506‧‧‧Lower Layer 3508‧‧‧Opening 3510‧‧‧Part of Photoresist Layer 3512‧‧‧Selected 3514‧‧‧Lithographic exposure 3516‧‧‧Opening 3602‧‧‧First pre-patterned hard mask 3604‧‧‧Second pre-patterned hard mask 3610‧‧‧Part of photoresist layer 3616‧‧‧ Openings 3650A, 3650B, 3650C, 3650D, 3650E‧‧‧Overlay Image 3652A‧‧‧Top Half 3654A‧‧‧Bottom Half 3656A, 3656B, 3656C, 3656D, 3656E‧‧‧ Wide Unexposed Features 3658A, 3658B, 3658C , 3658D, 3658E‧‧‧Wide Unexposed Features 3697‧‧‧Measuring Structures 3698‧‧‧Layer 1 Features 3699‧‧‧Layer 2 Features 3702‧‧‧First Pre-Patterned Hardmask 3704‧‧‧Second Pre Patterned hard mask 3710‧‧‧Photoresist layer portion 3716‧‧‧Opening 3750A, 3750B, 3750C, 3750D, 3750E‧‧‧Overlay image 3760A, 3760B, 3760C, 3760D, 3760E‧‧‧area 3800‧‧ ‧Substrate 3801‧‧‧Photolithography mask structure 3802‧‧‧Patterned absorber layer 3804‧‧‧Top layer 3806‧‧‧Patterned shifter layer 3808‧‧‧Top surface 3810‧‧‧Middle grain area 3812 ‧‧‧Top surface 3814‧‧‧Top surface 3820‧‧‧Frame Area 3830‧‧‧Die Frame Interface Area 3840‧‧‧Double Stacking 3900‧‧‧Electron Beam Row 3902‧‧‧Electron Source 3904‧‧‧Electron Beam 3906‧‧‧Limited Aperture 3908‧‧‧Illumination Optics 3910‧‧‧Output Beam 3912‧‧‧Slit 3914‧‧‧Thin Lens 3916‧‧‧Formed Aperture 3918‧‧‧Canceller Aperture Array (BAA) 3920‧‧‧Section 3921‧‧‧Beam Section 3922‧‧‧ Final Aperture 3924‧‧‧ Stage Feedback Deflector 3926‧‧‧Resulting Electron Beam 3928‧‧‧Spot 3930‧‧‧Wafer 3932‧‧‧ Stage Scanning 3934‧‧‧Arrow 4000‧‧‧Aperture 4002‧‧‧ Line 4004‧‧‧Arrow 4006‧‧‧Edge Layout Error (EPE) 4100, 4102‧‧‧Aperture 4104, 4106‧‧‧Line 4108‧‧‧Arrow 4110‧‧‧EPE4112‧‧‧Distance Requirement 4114‧‧ ‧Interval 4200‧‧‧BAA4202, 4204‧‧‧Line 4206‧‧‧Aperture 4208‧‧‧Line 4210‧‧‧Direction 4300‧‧‧Line 4302‧‧‧Open Line Position 4304‧‧‧Through Hole 4306‧‧‧ Cutting 4310‧‧‧BAA4312‧‧‧Scanning Direction 4350‧‧‧Stack 4352‧‧‧Metalization 4354, 4356, 4358, 4360, 4362, 4364, 4366, 4368‧‧‧Metal 4370, 4372‧‧‧Metal Line 4374‧‧‧Through Hole Location 4400‧‧‧Computer Device 4402‧‧‧Circuit Board 4404‧‧‧Processor 4406‧‧‧Communication Chip 4500‧‧‧Interposer 4502‧‧‧First Substrate 4504‧‧‧Part Two Substrates 4506‧‧‧Ball Grid Array (BGA) 4508‧‧‧Metal Interconnect 4510‧‧‧Through Via 4512‧‧‧Through Silicon Via (TSV) 4514‧‧‧Embedded Device

1A illustrates a cross-sectional view of the starting structure following deposition (but before patterning) of a layer of hard mask material formed on an interlayer dielectric (ILD) layer.

FIG. 1B illustrates a cross-sectional view of the structure of FIG. 1A subsequent to patterning by a pitch halved hard mask layer.

2 illustrates a cross-sectional view in a spacer-based six-fold patterning (SBSP) processing scheme involving a factor of six pitch division.

3 illustrates a cross-sectional view in a spacer-based nine-fold patterning (SBNP) processing scheme involving factor-of-nine pitch divisions.

4A-4N illustrate cross-sectional views of various operations in a method of fabricating a non-planar semiconductor device, in accordance with an embodiment of the present invention, wherein:

5 illustrates the structure of FIG. 4N following exposure of the upper portion of the plurality of fins, in accordance with an embodiment of the present invention.

6A illustrates a cross-sectional view of a non-planar semiconductor device, in accordance with an embodiment of the present invention.

6B illustrates a plan view taken along the a-a' axis of the semiconductor device of FIG. 6A, in accordance with an embodiment of the present invention.

7A and 7B illustrate cross-sectional views of a target infrastructure for enabling a very tight pitch final pattern of semiconductor layers, in accordance with an embodiment of the present invention.

8A-8H illustrate cross-sectional views representing various operations in a method of fabricating a target base structure for enabling a very tight pitch final pattern of semiconductor layers, in accordance with an embodiment of the present invention.

8H' and 8H" illustrate cross-sectional views of exemplary structures following patterning of vias and plugs, in accordance with embodiments of the present invention.

9A-9L illustrate oblique cross-sectional views of a portion of an integrated circuit layer representing various operations in a method involving pitch division patterning for increased overlap tolerance for back end of line (BEOL) interconnect fabrication , according to an embodiment of the present invention.

10A-10M illustrate portions of integrated circuit layers that represent various operations in a method of self-aligned vias and metal patterning, in accordance with embodiments of the present invention.

11A-11M illustrate portions of integrated circuit layers that represent various operations in a method of self-aligned vias and metal patterning, in accordance with embodiments of the present invention.

FIGS. 12A-12C illustrate oblique cross-sectional views representing various operations in a method of using triblock copolymers to form self-aligned vias or contacts for back end of line (BEOL) interconnects, in accordance with the present invention. Example.

12D illustrates an oblique cross-sectional view representing operation in a method of using triblock copolymers to form self-aligned vias or contacts for back end of line (BEOL) interconnects, in accordance with an embodiment of the present invention.

12E illustrates an oblique cross-sectional view showing operation in another method of using triblock copolymers to form self-aligned vias or contacts for back end of line (BEOL) interconnects, according to another aspect of the present invention Example.

12F illustrates a triblock copolymer used to form self-aligned vias or contacts for back end of line (BEOL) interconnects, in accordance with an embodiment of the present invention.

Figures 12G and 12H illustrate plan views and corresponding cross-sectional views representing various operations in a method of using triblock copolymers to form self-aligned vias or contacts for back end of line (BEOL) interconnects, according to Embodiments of the present invention.

Figures 12I-12L illustrate plan views and corresponding cross-sectional views representing various operations in a method of using triblock copolymers to form self-aligned vias or contacts for back end of line (BEOL) interconnects, according to Embodiments of the present invention.

13 illustrates a plan view and corresponding cross-sectional view of a self-aligned via structure subsequent to the formation of metal lines, vias, and plugs, in accordance with an embodiment of the present invention.

14A-14N illustrate portions of integrated circuit layers that represent operations in a method of subtracting self-aligned vias and plugs patterning, in accordance with embodiments of the present invention.

15A-15D illustrate portions of integrated circuit layers that represent operations in a method of subtractive self-aligned plug patterning, in accordance with another embodiment of the present invention.

16A-16D illustrate cross-sectional views of portions of integrated circuit layers representing various operations in a method involving the formation of a dielectric helmet for back-end-of-line (BEOL) interconnect fabrication, in accordance with an embodiment of the present invention.

16E-16P illustrate cross-sectional views of a portion of an integrated circuit layer representing various operations in another method involving the formation of a dielectric helmet for back end of line (BEOL) interconnect fabrication, in accordance with an embodiment of the present invention.

17A-17J illustrate cross-sectional views of portions of integrated circuit layers representing various operations in another method involving the formation of dielectric helmets for back-end-of-line (BEOL) interconnect fabrication, in accordance with embodiments of the present invention.

18A-18W illustrate plan views and corresponding oblique and cross-sectional views representing various operations in a through metal via processing scheme for back end of line (BEOL) interconnects, in accordance with embodiments of the present invention.

FIGS. 19A-19L illustrate plan views and corresponding oblique cross-sectional views representing various operations in a grid self-aligned metal via processing scheme for back end of line (BEOL) interconnects, in accordance with an implementation of the present invention. example.

20A-20G illustrate plan views and corresponding cross-sectional views representing various operations in a method of fabricating grating-based plugs and dicing feature end formation for back-end-of-line (BEOL) interconnects, in accordance with the present invention example.

Figure 21A illustrates a plan view and a corresponding cross-sectional view taken along the a-a' axis of a plan view of a metallization layer of a currently known semiconductor device.

21B illustrates a cross-sectional view of a wire end or plug fabricated using currently known processing schemes.

Figure 21C illustrates another cross-sectional view of a wire end or plug fabricated using currently known processing schemes.

21D-21J illustrate cross-sectional views representing various operations in a process for patterning metal line terminations for back end of line (BEOL) interconnects, in accordance with embodiments of the present invention.

21K illustrates a cross-sectional view of a metallization layer of an interconnect structure of a semiconductor die including a dielectric line end or plug having a seam therein, in accordance with an embodiment of the present invention.

21L illustrates a cross-sectional view of a metallization layer of an interconnect structure of a semiconductor die that includes dielectric line ends or plugs that are not immediately adjacent conductive vias, in accordance with an embodiment of the present invention.

22A-22G illustrate portions of integrated circuit layers that represent various operations in a method involving self-aligned isotropic etching of pre-formed vias or plug locations, in accordance with embodiments of the present invention.

22H-22J illustrate oblique cross-sectional views showing portions of integrated circuit layers representing various operations in a method involving self-aligned isotropic etching of preformed via locations, in accordance with embodiments of the present invention .

23A-23L illustrate portions of an integrated circuit layer that represent operations in a method of subtracting self-aligned via and plug patterning, in accordance with an embodiment of the present invention.

23M-23S illustrate portions of integrated circuit layers that represent operations in a method of subtracting self-aligned via patterning, in accordance with embodiments of the present invention.

24A-24I illustrate portions of an integrated circuit layer that represent operations in a method of subtracting self-aligned vias and plugs patterning, in accordance with embodiments of the present invention.

25A-25H illustrate portions of integrated circuit layers that represent various operations in a method of subtractive self-aligned via patterning using a polychromatic light barrel, in accordance with an embodiment of the present invention.

25I illustrates an example duotone resist for one photobarrel type and an exemplary monotone resist for another photobarrel type, in accordance with embodiments of the present invention.

26A illustrates a plan view of a conventional back end of line (BEOL) metallization layer.

26B illustrates a plan view of a back end of line (BEOL) metallization layer having conductive pads to couple metal lines of the metallization layer, in accordance with an embodiment of the present invention.

27A-27K illustrate oblique cross-sectional views representing various operations in a method of fabricating a back end of line (BEOL) metallization layer having conductive sheets to couple metal lines of the metallization layer, in accordance with the present disclosure. Examples of inventions.

Figures 28A-28T illustrate oblique cross-sectional views representing various operations in a method of fabricating a back end of line (BEOL) metallization layer having conductive sheets to couple the metal lines of the metallization layer, in accordance with the present invention. Examples of inventions.

29A-29C illustrate cross-sectional views and corresponding plan views of various operations in a method of patterning using a photobucket including a two-stage bake photoresist, in accordance with an embodiment of the present invention.

29D illustrates a cross-sectional view of a conventional resist photobarrel structure following photobarrel development after misalignment exposure.

30A-30E illustrate schematic views of various operations in a method of patterning using a photobucket including a two-stage bake photoresist, in accordance with an embodiment of the present invention.

Figure 30A' illustrates a schematic view of operations in another method of patterning using photobuckets, in accordance with an embodiment of the present invention.

Figure 30A'' illustrates a schematic view of operations in another method of patterning using photobuckets, in accordance with an embodiment of the present invention.

31 illustrates an oblique view of an alternating pattern of interlayer dielectric (ILD) lines and resist lines with holes formed in one of the resist lines, in accordance with an embodiment of the present invention.

32A-32H illustrate cross-sectional views in a fabrication process involving tone inversion of images with dielectrics using bottom-up cross-linking, in accordance with embodiments of the present invention.

Figure 33A illustrates a trisilacyclohexane molecule, according to embodiments of the present invention.

33B illustrates two cross-linked (XL) trisilacyclohexane molecules used to form a cross-linked material, in accordance with an embodiment of the present invention.

Figure 33C illustrates an idealized representation of a linked trisilacyclohexane structure, in accordance with an embodiment of the present invention.

34A-34X illustrate portions of integrated circuit layers that represent various operations in a method of self-aligned via and plug patterning using diagonal hardmasks, in accordance with embodiments of the present invention.

35A-35D illustrate cross-sectional views and corresponding top-down views representing various operations in a patterning process scheme using a pre-patterned hardmask, in accordance with an embodiment of the present invention.

36A illustrates a top-down view of an overlay scenario where the current layer is overlaid on the underlying pre-patterned hardmask grid, in accordance with an embodiment of the present invention.

36B illustrates a top-down view of an overlap scenario, where the current layer has a quarter-pitch positive overlap relative to the underlying pre-patterned hardmask grid, in accordance with an embodiment of the present invention.

36C illustrates a top-down view of an overlapping scenario, where the current layer has a positive overlap relative to the half-pitch of the underlying pre-patterned hardmask grid, in accordance with an embodiment of the present invention.

36D illustrates a top-down view of an overlap scenario, where the current layer has a positive overlap relative to an arbitrary value of Δ of the underlying pre-patterned hardmask grid, in accordance with an embodiment of the present invention.

36E illustrates a top-down view of an overlap scenario where the current layer has a positive overlap relative to an arbitrary value Δ of the underlying pre-patterned hardmask grid, where Δ can be measured by changing resist sensitivity and/or Or the feature size has been depicted and made as small as desired, in accordance with embodiments of the present invention.

36F illustrates an example metrology structure suitable for the manner described above with respect to FIGS. 36A-36E, in accordance with an embodiment of the present invention.

37A illustrates a top-down view of an overlay scenario where the current layer is overlaid on the underlying pre-patterned hardmask, in accordance with an embodiment of the present invention.

37B illustrates a top-down view of an overlap scenario, where the current layer has a quarter-pitch positive overlap relative to the underlying pre-patterned hardmask grid in the X-direction, in accordance with an embodiment of the present invention.

37C illustrates a top-down view of an overlap scenario, where the current layer has a negative overlap of a quarter pitch relative to the underlying pre-patterned hardmask grid in the X-direction, in accordance with an embodiment of the present invention.

37D illustrates a top-down view of an overlay scenario where the current layer has a quarter-pitch positive overlap relative to the underlying pre-patterned hardmask grid in the Y direction, in accordance with an embodiment of the present invention.

37E illustrates a top-down view of an overlay scenario, where the current layer has a quarter-pitch positive overlap relative to the underlying pre-patterned hardmask grid in the X-direction and has a lower relative to the Y-direction A quarter-pitch positive overlap of the pre-patterned hardmask grid, in accordance with embodiments of the present invention.

38 illustrates a cross-sectional view of a lithography mask structure, in accordance with an embodiment of the present invention.

Figure 39 is a schematic cross-sectional view of an electron beam column of an electron beam lithography apparatus.

Figure 40 illustrates the aperture (left) of the Blind Aperture Array (BAA) relative to the line to be cut or with the through hole placed in the target location (right), when the line is scanned under the aperture.

Figure 41 illustrates two non-staggered apertures (left) relative to the BAA to be cut or with two lines (right) of through holes placed in the target location, when the lines are scanned under the apertures.

Figure 42 illustrates two rows of staggered apertures (left) relative to the BAA to be cut or with multiple lines (right) of through-holes placed in target locations, with the scan direction indicated by arrows as the lines are scanned under the apertures shown, in accordance with embodiments of the present invention.

Figure 43A illustrates two rows of staggered apertures (left) with respect to BAAs with cuts (breaks in horizontal lines) or complex lines (right) with vias patterned using staggered BAAs (filled square boxes), in scan direction by As shown by the arrows, embodiments are in accordance with the present invention.

43B illustrates a cross-sectional view of a metallization layer stack in an integrated circuit, according to a metal line layout of the type shown in FIG. 21A, in accordance with an embodiment of the present invention.

44 illustrates a computing device, in accordance with one embodiment of the present invention.

Figure 45 illustrates an inserter which includes one or more embodiments of the present invention.

100‧‧‧Start Structure

102‧‧‧Interlayer Dielectric (ILD) Layer

104‧‧‧Hard mask material layer

106‧‧‧Patterned Mask

108‧‧‧Spacers

Claims (55)

An integrated circuit structure, comprising: a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a grating pattern interrupted by part of the body portion; a trench isolation layer interposed between the plurality of semiconductor bodies Between and adjacent to the lower part of the plurality of semiconductor bodies, but not adjacent to the upper part of the plurality of semiconductor bodies, wherein the trench isolation layer is located above the part of the body part; One or more gate electrode stacks , which are on the top surfaces of the upper portions of the plurality of semiconductor bodies and are laterally adjacent to the sidewalls of the upper portions of the plurality of semiconductor bodies, and on portions of the trench isolation layer; and subsequent stages a process (BEOL) metallization layer over the one or more gate electrode stacks, the BEOL metallization layer comprising a plurality of alternating first and second conductive line types along the same direction, wherein the first The overall composition of the conductive line type is different from the overall composition of the second conductive line type. The integrated circuit structure of claim 1, wherein the wires of the first conductive line type are separated by a pitch, and wherein the wires of the second conductive wire type are separated by the pitch. The integrated circuit structure of claim 1, wherein the plurality of alternating first and second conductive line types are in an interlayer dielectric (ILD) layer. The integrated circuit structure of claim 1, wherein the lines of the plurality of alternating first and second conductive line types are separated by air gaps. The integrated circuit structure of claim 1, wherein the overall composition of the first conductive line type substantially comprises copper, and wherein the overall composition of the second conductive line type substantially comprises a group selected from Al, Ti, A material of the group consisting of Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au and their alloys. The integrated circuit structure of claim 1, wherein the lines of the plurality of alternating first and second conductive line types each include barrier layers along bottoms and sidewalls of the lines. The integrated circuit structure of claim 1, wherein the lines of the plurality of alternating first and second conductive line types each include a barrier layer along the bottom of the line but not along sidewalls of the line . The integrated circuit structure of claim 1, wherein one or more of the lines of the plurality of alternating first and second conductive line types are connected to an underlying via, which is connected to an underlying metal a metallization layer, the underlying metallization layer is between the one or more gate electrode stacks and the BEOL metallization layer, and wherein the plurality of alternating first and second conductive line types of the lines One or more are interrupted by dielectric plugs. The integrated circuit structure of claim 1, wherein the grating pattern has a constant pitch. The integrated circuit structure of claim 1 further comprises: source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are adjacent A semiconductor material different from the semiconductor material of the semiconductor bodies is included in the upper portions of the plurality of semiconductor bodies. The integrated circuit structure of claim 1, further comprising: source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are located in the within the upper portions of the plurality of semiconductor bodies. The integrated circuit structure of claim 1, wherein each of the one or more gate electrode stacks includes a high-k gate dielectric layer and a metal gate electrode. The integrated circuit structure of claim 1, wherein the first conductive line types have upper surfaces having a metal composition different from the metal composition of the upper surfaces of the second conductive line types. An integrated circuit structure, comprising: a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a grating pattern interrupted by part of the body portion; a trench isolation layer interposed between the plurality of semiconductor bodies Between and adjacent to the lower part of the plurality of semiconductor bodies, but not adjacent to the upper part of the plurality of semiconductor bodies, wherein the trench isolation layer is located above the part of the body part; One or more gate electrode stacks , which are on the top surfaces of the upper portions of the plurality of semiconductor bodies and are laterally adjacent to the sidewalls of the upper portions of the plurality of semiconductor bodies, and on portions of the trench isolation layer; and subsequent stages a process (BEOL) metallization layer over the one or more gate electrode stacks, the BEOL metallization layer comprising a plurality of alternating first and second conductive line types along the same direction, wherein the plurality of Alternating lines of the first and second conductive line types each include barrier layers along the bottom of the line but not along the sidewalls of the line. The integrated circuit structure of claim 14, wherein the wires of the first conductive line type are separated by a pitch, and wherein the wires of the second conductive wire type are separated by the pitch. The integrated circuit structure of claim 14, wherein the plurality of alternating first and second conductive line types are in an interlayer dielectric (ILD) layer. The integrated circuit structure of claim 14, wherein the lines of the plurality of alternating first and second conductive line types are separated by air gaps. The integrated circuit structure of claim 14, wherein the overall composition of the first conductive line type is the same as the overall composition of the second conductive line type. The integrated circuit structure of claim 14, wherein the overall composition of the first conductive line type substantially comprises copper, and wherein the overall composition of the second conductive line type substantially comprises the group consisting of Al, Ti, Zr, A material of the group consisting of Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au and their alloys. The integrated circuit structure of claim 14, wherein one or more of the lines of the plurality of alternating first and second conductive line types are connected to an underlying via which is connected to an underlying metal a metallization layer, the underlying metallization layer is between the one or more gate electrode stacks and the BEOL metallization layer, and wherein the plurality of alternating first and second conductive line types of the lines One or more are interrupted by dielectric plugs. The integrated circuit structure of claim 14, wherein the grating pattern has a constant pitch. The integrated circuit structure of claim 14, further comprising: source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are adjacent A semiconductor material different from the semiconductor material of the semiconductor bodies is included in the upper portions of the plurality of semiconductor bodies. The integrated circuit structure of claim 14, further comprising: source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are located in the within the upper portions of the plurality of semiconductor bodies. The integrated circuit structure of claim 14, wherein each of the one or more gate electrode stacks includes a high-k gate dielectric layer and a metal gate electrode. An integrated circuit structure, comprising: a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a first grating pattern interrupted by a portion of the body portion; a trench isolation layer interposed between the plurality of semiconductor bodies Between the bodies and adjacent to the lower part of the plurality of semiconductor bodies, but not adjacent to the upper part of the plurality of semiconductor bodies, wherein the trench isolation layer is located above the part of the body part; One or more gates electrode stacks on top surfaces of the upper portions of the plurality of semiconductor bodies and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies, and on portions of the trench isolation layer; a first back end of line (BEOL) metallization layer over the one or more gate electrode stacks, the first BEOL metallization layer comprising a second grating of alternating metal and dielectric lines in a first direction; and a second BEOL metallization layer over the first BEOL metallization layer, the second BEOL metallization layer comprising a third grating of alternating metal and dielectric lines in a second direction, the second direction being positive intersecting the first direction, wherein the metal lines of the third grating of the second BEOL metallization layer are tied to a dielectric layer comprising alternating metal lines and dielectric layers corresponding to the first BEOL metallization layer alternating distinct regions of a first dielectric material and a second dielectric material of lines, and wherein each dielectric line of the third grating of the second BEOL metallization layer includes a continuous region of a third dielectric material that is distinct from the first The alternating regions of dielectric material and the second dielectric material. The integrated circuit structure of claim 25, wherein the metal lines of the second BEOL metallization layer are electrically coupled to the metal lines of the first BEOL metallization layer through vias having a A center directly aligned with the center of the metal line of the first BEOL metallization layer and with the center of the metal line of the second BEOL metallization layer. The integrated circuit structure of claim 25, wherein the metal lines of the second BEOL metallization layer are interrupted by plugs having centers with the dielectric lines of the first BEOL metallization layer Align directly to the center. The integrated circuit structure of claim 25, wherein the first dielectric material, the second dielectric material, and the third dielectric material are not the same material. The integrated circuit structure of claim 25, wherein only two of the first dielectric material, the second dielectric material, and the third dielectric material are the same material. The integrated circuit structure of claim 25, wherein the alternating distinct regions of the first dielectric material and the second dielectric material are separated by seams, and wherein the continuous region of the third dielectric material The alternating distinct regions of the first dielectric material and the second dielectric material are separated by seams. The integrated circuit structure of claim 25, wherein the first dielectric material, the second dielectric material, and the third dielectric material are all the same material. The integrated circuit structure of claim 25, wherein the first grating pattern has a constant pitch. The integrated circuit structure of claim 25, further comprising: source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are adjacent A semiconductor material different from the semiconductor material of the semiconductor bodies is included in the upper portions of the plurality of semiconductor bodies. The integrated circuit structure of claim 25, further comprising: source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are located in the within the upper portions of the plurality of semiconductor bodies. The integrated circuit structure of claim 25, wherein each of the one or more gate electrode stacks includes a high-k gate dielectric layer and a metal gate electrode. The integrated circuit structure of claim 25, wherein an etch stop layer or additional dielectric layer separates the first BEOL metallization layer and the second BEOL metallization layer. A method of fabricating an integrated circuit structure, the method comprising: forming a plurality of backbone features over a substrate; forming a first set of spacers along sidewalls of each of the plurality of backbone features, the first set of spacers having different forming a second set of spacers along sidewalls of each of the first set of spacers, the second set of spacers having a different material composition than the first set of spacers and a second material composition different from the material composition of the plurality of backbone features; forming a third group of spacers along sidewalls of each of the second group of spacers, the third group of spacers having different a first material composition, a third material composition different from the second material composition, and a third material composition different from the material composition of the plurality of backbone features; forming a fourth set of spacers along sidewalls of each of the third set of spacers forming a fifth set of spacers laterally adjacent to the sidewalls of each of the fourth set of spacers, the fifth set of spacers having the second set of spacers a material composition; after forming the fifth set of spacers, removing the plurality of backbone features; after removing the plurality of backbone features, along the sidewalls of each of the first set of spacers and along the The sidewalls of each of the fifth set of spacers form a sixth set of spacers, the sixth set of spacers having the second material composition; forming an adjacent pair of spacers finally characterized by the sixth set of spacers in each opening between; flattening the first group of spacers, the second group of spacers, the third group of spacers, the fourth group of spacers, the fifth group of spacers, the the sixth set of spacers, and the final features to form a target base layer; and using the target base layer to form a metallization layer of the semiconductor structure. The method of claim 37, wherein forming the plurality of backbone features comprises using standard lithography operations. The method of claim 37, wherein forming the plurality of backbone features comprises forming the plurality of features comprising a material selected from the group consisting of silicon nitride, silicon oxide, and silicon carbide. The method of claim 37, wherein forming the first set of spacers comprises: using an atomic layer deposition (ALD) process to deposit material of the first set of spacers conformal to the plurality of backbone features; and anisotropically etching the material of the first set of spacers to form the first set of spacers along the sidewalls of each of the plurality of backbone features. The method of claim 37, wherein forming the first set of spacers comprises selectively growing material of the first set of spacers along the sidewalls of each of the plurality of backbone features. 37. The method of claim 37, wherein each final feature has a greater value from the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the the side width of the side widths of the spacers of the fifth group of spacers and the spacers of the sixth group of spacers. The method of claim 37, wherein each final feature is formed by amalgamation of material growth formed along adjacent pairs of spacers of the sixth set of spacers. The method of claim 37, wherein each final feature comprises the third material composition. The method of claim 37, wherein using the target base layer to form the metallization layer of the semiconductor structure comprises: removing all portions of the first material composition to form a first plurality of trenches; and forming a first plurality of trenches A plurality of conductive lines are in the first plurality of trenches. The method of claim 45, wherein using the target base layer to form the metallization layer of the semiconductor structure further comprises: removing all portions of the third material composition to form a second plurality of trenches; and forming a first plurality of trenches Two pluralities of conductive lines are in the second pluralities of trenches. The method of claim 46, wherein the first plurality of conductive lines and the second plurality of conductive lines have the same composition. The method of claim 46, wherein the first plurality of conductive lines and the second plurality of conductive lines are of different compositions. The method of claim 37, further comprising forming an additional 20-200 sets of spacers between forming the fifth set of spacers and the sixth set of spacers, and before removing the plurality of backbone features . A target structure for fabricating an integrated circuit structure, the target structure comprising: a first set of spacers over a hard mask layer over a substrate, the first set of spacers having a first material composition; along the first set of spacers a second set of spacers of the outer sidewalls of each of a set of spacers, the second set of spacers having a second material composition different from the first material composition; along each of the second set of spacers a third group of spacers of the sidewalls, the third group of spacers having a third material composition different from the first material composition and different from the second material composition; along each of the third group of spacers a fourth group of spacers of the sidewalls of the fourth group of spacers, the fourth group of spacers having the second material composition; a fifth group of spacers laterally adjacent to the sidewalls of each of the fourth group of spacers, the a fifth set of spacers having the first material composition; a sixth set of spacers along inner sidewalls of each of the first set of spacers and along sidewalls of each of the fifth set of spacers, the The sixth sets of spacers have the second material composition; and the last feature in each opening between adjacent pairs of spacers of the sixth set of spacers. The target structure of claim 50, wherein the first group of spacers, the second group of spacers, the third group of spacers, the fourth group of spacers, and the fifth group of spacers The spacers, the sixth set of spacers, and the final features are substantially coplanar with each other. The target structure of claim 50, wherein each final feature has greater values from the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, The side width of the spacers of the fifth group of spacers and the side width of each spacer of the sixth group of spacers. The target structure of claim 52, wherein the side width of each final feature is in the range of 6-12 nm. The target structure of claim 50, wherein each final feature has a seam approximately centered within the final feature. The target structure of claim 50, wherein each final feature comprises the third material composition.

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