TW201936486A - Advanced lithography and self-assembled devices - Google Patents

Abstract

Advanced lithography techniques including sub-10nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Description

Advanced lithography and self-polymerizing device

Embodiments of the present invention are in the field of semiconductor devices and processing, and in particular, relate to sub-10 nm pitch patterning and self-polymerizing devices.

Over the past few decades, the scaling of features in integrated circuits has been the driving force behind the growing semiconductor industry. Scaling to smaller and smaller features enables increased density of functional units on a limited surface of the semiconductor wafer. For example, reducing the size of the transistor allows for the incorporation of an increased number of memory or logic devices on the wafer, resulting in the manufacture of products that increase throughput. However, the desire for more and more capacity is not without problems. The need to optimize the performance of each device becomes more and more important.

The variability in conventional and currently known manufacturing processes may limit the possibility of further extending it into the sub-10 nm range. Therefore, the manufacture of functional components required for future technology nodes may require the introduction of new methodologies or the integration of new technologies into current manufacturing processes or replacing current manufacturing processes.

and

Descriptions of advanced pitch patterning and self-polymerizing devices, particularly advanced pitch patterning techniques and self-polymerizing device fabrication methods for generating sub-10 nanometer (nm) devices and structures. In the following description, numerous specific details are set forth, such as specific combinations and materials, in order to provide a thorough understanding of the embodiments of the invention. It will be apparent to those skilled in the art that the embodiments of the invention can be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, have not been described in detail in order to avoid obscuring the embodiments of the invention. In addition, the various embodiments shown in the figures are understood to be illustrative and not necessarily to scale.

The following detailed description is merely illustrative of the nature of the embodiments of the invention As used herein, the word "example" refers to "action as a scope, example, or diagram." Any implementations described herein as examples are not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, there is no intention to be bound by any explicit or implied theory set forth in the prior art, the background, the brief summary or the following detailed description.

This description includes references to "an embodiment" or "an embodiment". The appearances of the terms "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with the present invention.

the term. The following paragraphs provide definitions and/or backgrounds for terms found in this specification (including the scope of the appended patent application):

"Include." This term is open ended. This term does not exclude additional structures or steps, as used in the scope of the appended claims.

"Configured to." Each unit or component can be described or requested to "configure" to perform a work or majority of work. In this context, "configured to" is used to imply a structure by indicating that its unit/component includes its structure for performing those tasks during operation. As such, the unit/component can be said to be configured to perform the work even when the indicated unit/component is not currently operating (eg, not open/active). It is stated that the unit/circuit/component is "configured to" perform one or more tasks to explicitly indicate that 35 U.S.C. § 112 (sixth paragraph) is not referenced in the unit/component.

"First," "Second," and so on. As used herein, these terms are used as an indication of the nouns that are suffixed thereto, and do not imply any type of ordering (eg, space, time, logic, etc.). For example, a reference to a "first" solar cell does not necessarily imply that the solar cell is the first solar cell in a certain sequence; instead, the term "first" is used to make the solar cell and other solar cells (eg, There is a difference between "second" solar cells.

"Coupling" - The following description refers to a component or node or feature that is "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element/node/feature is directly or indirectly coupled to (either directly or indirectly communicated with) another element/node/feature Not necessarily mechanically.

In addition, some terms may be used in the following description for reference purposes only, and thus are not intended to be limiting. For example, such as "higher", "lower", "above", and "below" refer to the direction in the graphic to which the reference applies. Terms such as "front", "back", "rear", "side", "outward", and "inward" are used to describe the orientation and/or position of a portion of a component within a constant (but arbitrary) frame of a reference. It is made clear by reference to the text describing the components in the discussion and related graphics. This term may include words that are explicitly mentioned above, derivatives thereof, and words of similar meaning.

"Prohibited" - as used in the text, is prohibited from being used to describe the effect of reducing or reducing. When a component or feature is described as disabling an action, action, or condition, it can completely prevent the result or consequence or future state. In addition, "prohibition" may also refer to reductions or reductions in fruit, performance, and/or effects that may occur after additional occurrences. Thus, when a component, component, or feature is referred to as a prohibited result or state, it does not need to completely prevent or remove the result or state.

Embodiments described herein may be directed to front-end processing (FEOL) semiconductor processing and structures. FEOL is the first part of the fabrication of integrated circuits (ICs) in which individual devices (eg, transistors, capacitors, resistors, etc.) are patterned into a semiconductor substrate or layer. FEOL typically covers all steps up to, but not including, the deposition of metal interconnect layers. Following the final FEOL operation, the result is typically a wafer with an isolated transistor (eg, without any wiring).

Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second part of IC fabrication in which individual devices (eg, transistors, capacitors, resistors, etc.) are interconnected with wiring on a wafer (eg, a metallization layer or layers). BEOL includes contacts, insulating layers (dielectrics), metal steps, and joints for wafer-to-package connections. In the BEOL of the manufacturing stage, contacts (pads), interconnect wiring, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added to BEOL. The embodiments described below are applicable to both FEOL processing and structure, BEOL processing and structure, or both FEOL and BEOL processing and structures. In particular, although the example processing scheme can be illustrated using a FEOL processing context, these approaches can also be applied to BEOL processing. Similarly, while the example processing scheme can be illustrated using a BEOL processing context, these approaches can also be applied to FEOL processing.

The pitch segmentation process and patterning scheme can be implemented to enable the embodiments described herein or can be included as part of the embodiments described herein. Pitch splitting is usually done by halving the pitch, reducing the pitch by a quarter, and so on. The pitch division scheme can be applied to both FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. In accordance with one or more embodiments described herein, optical lithography is first implemented to print a unidirectional line at a predefined pitch (eg, strictly unidirectional or primarily unidirectional). The pitch division process is then implemented as a technique for increasing the line density.

In one embodiment, the term "grating structure" for metal lines, ILD lines, or hard mask lines is used herein to refer to a closely spaced grating structure. In this embodiment, the tight pitch cannot be obtained directly through conventional lithography. For example, a pattern according to conventional lithography may be formed first, but the pitch may be halved by patterning using spacer masks, as is known in the art. Even the original pitch can be reduced to a quarter by the second round of spacer mask patterning. Thus, the grating-like pattern described herein can have metal lines, ILD lines, or hard mask lines that are separated by a substantially constant pitch and have a substantially constant width. For example, in some embodiments, the pitch variation may be within ten percent and the width variation may be within ten percent, and in some embodiments, the pitch variation may be within five percent and width The change can be less than five percent. The pattern can be created by halving the pitch or reducing the pitch by a quarter (or other pitch division). In an embodiment, the grating is not necessarily a single pitch.

In the first example, the pitch halving can be implemented to double the linear density of the resulting grating structure. Figure 1A illustrates a cross-sectional view of the starting structure following deposition of a layer of hard masking material formed on an interlayer dielectric (ILD) layer (but prior to patterning). Figure 1B illustrates a cross-sectional view of the structure of Figure 1A following the patterning of the hard mask layer halved by the pitch.

Referring to FIG. 1A, the starting structure 100 has a layer of hard masking material 104 formed on an interlayer dielectric (ILD) layer 102. The patterned mask 106 is disposed over the hard mask material layer 104. The patterned mask 106 has spacers 108 formed along the sidewalls of its features (lines) on the hard mask material layer 104.

Referring to FIG. 1B, the hard mask material layer 104 is patterned in a half pitch manner. Specifically, the patterned mask 106 is first removed. The resulting pattern of spacers 108 has twice the density of the mask 106, or half of its pitch or feature. The pattern of spacers 108 is transferred, for example, to the hard mask material layer 104 by an etching process to form a patterned hard mask 110, as shown in FIG. 1B. In one such embodiment, the patterned hard mask 110 is formed to have a grating pattern of unidirectional lines. The grating pattern of the patterned hard mask 110 can be a tight pitch grating structure. For example, tight pitches may not be directly achieved by conventional lithography techniques. Even though not shown, the original pitch can be reduced to a quarter by the second round of spacer mask patterning. Thus, the raster-like pattern of patterned hard mask 110 of FIG. 1B can have hard mask lines that are separated by a constant pitch and have a constant width relative to one another. The size obtained may be much smaller than the critical dimensions of the lithography technology that has been utilized.

Thus, for front-end (FEOL) or back-end (BEOL) (or both) integration schemes, the cover film may use lithography and etching processes (which may involve, for example, spacer-based double patterning (SBDP) Patterned by either halving the pitch, or spacer-based quadruple patterning (SBQP) or pitch reduction of a quarter. It should be understood that other pitch division methods can also be implemented.

For example, Figure 2 illustrates a cross-sectional view of a six-times patterning (SBSP) processing technique based on a spacer segmentation of a pitch factor of six. Referring to FIG. 2, in operation (a), the sacrificial pattern X after lithography, thinning, and etching is displayed. In operation (b), spacers A and B after deposition and etching are shown. In operation (c), the pattern of the operation (b) after the spacer A is removed is displayed. In operation (d), the pattern of operation (c) after deposition of spacer C is shown. In operation (e), the pattern of the operation (d) after the spacer C is etched is displayed. In operation (f), a pitch/6 pattern is obtained after the sacrificial pattern X removal and the spacer B removal.

In another example, FIG. 3 illustrates a cross-sectional view of a nine-times patterning (SBNP) processing technique based on a spacer segmentation pitch factor of nine. Referring to FIG. 3, in operation (a), the sacrificial pattern X after lithography, thinning, and etching is displayed. In operation (b), spacers A and B after deposition and etching are shown. In operation (c), the pattern of the operation (b) after the spacer A is removed is displayed. In operation (d), the pattern of operation (c) after deposition and etching of spacers C and D is shown. In operation (e), a pitch/9 pattern is obtained after the spacer C is removed.

In any event, in one embodiment, the grid layout can be fabricated by conventional or up-to-date lithography, such as 193 nm immersion in lithography (193i). Pitch segmentation can be implemented to increase the density of the lines in the grid layout by a factor of n. The grid layout formation using 193i lithography plus pitch division by a factor of n can be specified as 193i+P/n pitch division. In one such embodiment, the 193 nm immersion calibration can be extended to many generations using cost effective pitch segmentation.

In the fabrication of integrated circuit devices, multi-gate transistors such as three-gate transistors have become more common as device sizes continue to shrink. In conventional processes, three-gate transistors are typically fabricated on bulk germanium or germanium insulator substrates. In some instances, bulk germanium substrates are preferred due to their lower cost and compatibility with existing high throughput bulk substrate facilities.

However, the reduction of multi-gate transistors is not inconclusive. As the size of these basic building blocks of microelectronic circuits decreases and as the total number of basic building blocks fabricated in a given area increases, the limitations on the semiconductor process used to fabricate these building blocks become cumbersome.

In one embodiment, directed self-polymerization (DSA) is implemented for hard mask distinction (eg, forming a hard mask with different etch properties). In some embodiments, a distinguishing hard mask may also be referred to as a "colored" hard mask, wherein hard masks of the same color have the same or similar etch selectivity and have a hard cover of different colors therein. The hood has different etch selectivity. It should be noted that in actual practice, the term "color" does not refer to the actual color of the hard mask material. The hard mask distinction (or coloring) can be used to pattern or selectively remove semiconductor fins in a plurality of grid semiconductor fins. One or more embodiments described herein relate to a procedure for reducing (or resulting from) an aligned pitch to a quarter (or other) patterning (for edge placement error (EPE) correction) and structure. One or more embodiments may be described as a differentiated or "colored" alternating hard mask for semiconductor fin patterning. Embodiments may include DSA, semiconductor material patterning, pitch segmentation (such as pitch reduction of a quarter), differentiated hard mask selectivity, self-alignment for fin patterning, or more By. One or more embodiments are particularly suited for the fabrication of non-planar semiconductor devices.

In accordance with an embodiment of the present invention, the doubling of the allowable edge layout error and the doubling of the cut size for small features on the cut tight pitch are implemented in very fine fin patterning. In one embodiment, all features (eg, fin lines) are transferred into a semiconductor substrate with a single population of critical dimension (CD) variations. This approach is contrary to the current state of the art, which relies on spacers based on three discrete groups of line widths (eg, backbone or mandrel, complementary and spacer dimensions) to be reduced by a quarter. .

In order to provide a background, it may be desirable to use a semiconductor device that is bulky to the fin or triple gate. In one embodiment, directed self-polymerization (DSA) is implemented to complete the pitch division of every other feature and "paint" the desired pattern. In one such embodiment, the patterning is particularly applicable to patterned fin fins in a three-gate transition patterning process. In an embodiment, the advantages of the embodiments described herein may include one or more of the following: (1) enabling a single population of feature widths, and (2) doubling the edge layout error requirements for feature cutting, (3) ) doubling the size of the holes or openings required to cut a single feature (eg, relaxing the limit on the size of the opening), or (4) reducing the cost of the patterning process. The structural artifacts resulting from the process include (in one embodiment) a single population of critical dimensions and are surrounding the wafer as it transitions from one pitch to another and/or from one grid to another. The guard ring of the die. Embodiments can enable the cutting of tight pitch lines without scaling the edge layout error requirements.

In the example processing scheme, Figures 4A-4N illustrate cross-sectional views of various operations in a method of fabricating a non-planar semiconductor device, in accordance with an embodiment of the present invention.

FIG. 4A illustrates a bulk semiconductor substrate 402 having a first patterned hard mask 404 formed thereon. In one embodiment, the bulk semiconductor substrate 402 is a bulk single crystal germanium substrate having fins 402 etched therein. In one embodiment, the bulk semiconductor substrate 402 is undoped or less doped at this stage. For example, in certain embodiments, a bulk semiconductor substrate 402 has a concentration of less than about 1E17 atoms / cm ³ of boron dopant impurity atoms.

In one embodiment, the first patterned hard mask 404 includes features having a pitch 406. In one such embodiment, the first patterned hard mask 404 represents one-half of the possible number of fins that are ultimately formed in the substrate 402. That is, the pitch 406 is effectively relaxed to double the pitch of the last pattern of fins formed. In one embodiment, the first hard mask 404 is directly patterned using a lithography process. However, in other embodiments, pitch segmentation is applied (eg, the pitch is halved) and is used to provide a patterned hard mask 404 having a pitch 406. It should be understood that in one embodiment, the first guiding pattern can be formed using conventional patterning (lithography/etching), lithography only, spacer based double patterning or other pitch segmentation methods. In one embodiment, the guide pattern is separated from the DSA pattern by use of two or more hard masks such that its CD is formed from a single population (eg, an etch).

4B illustrates the structure of FIG. 4A following the formation of the second hard mask layer 408 between the first patterned hard masks 404. In one embodiment, the second hard mask layer 408 is formed by forming a cover hard mask layer over the substrate 402 and the first patterned hard mask 404 and then covering the hard mask layer. The planarization is to form a second hard mask layer 408, for example, by chemical mechanical planarization (CMP). In another embodiment, the ALD or CVD technique will follow the contour of the surface of the wafer; and since fin cutting is used as an example, the wafer is substantially flat at the point of the process.

In one embodiment, the second hard mask layer 408 has an etch characteristic that is different from the etch characteristics of the first patterned hard mask 404. In one embodiment, one of the second hard mask layer 408 and the first patterned hard mask 404 or both is a layer of tantalum nitride (eg, tantalum nitride) or a layer of tantalum oxide, or Both, or a combination thereof. Other suitable materials may include carbon based materials such as tantalum carbide. In another embodiment, the hard mask material comprises a metal. For example, the hard mask or other overlying material may comprise a layer of titanium or other metal nitride (eg, titanium nitride). Potentially lesser amounts of other materials, such as oxygen, can be included in one or more of these layers. The hard mask layer can be formed by CVD, PVD, or by other deposition methods.

Figure 4C illustrates the structure of Figure 4B following the application of the selective brush material layer 410. The selective brush material 410 is a selective material (in some embodiments) that can be applied by a brush. It should be noted that "brush material" is often used as a technical term in the DSA process and does not imply that its selective material 410 is used as a brush. In one embodiment, the selective brush material layer 410 is only adhered to the first patterned hard mask 404, as shown in Figure 4C. However, in another embodiment, a selective brush material is instead applied to the second hard mask layer 408. In yet another embodiment, the selective brush material layer 410 is only adhered to the first patterned hard mask 404 and a second different selective brush material is formed on the second hard mask layer 408.

In one embodiment, the selective brush material layer 410 includes a molecular species comprising having selected from the group consisting of -SH, -PO ₃ H ₂ , -CO ₂ H, -NRH, -NRR', and -Si(OR) ₃ The polystyrene of the head group of the group formed. In another embodiment, the selective brush material layer 410 includes a molecular species comprising having a selected from the group consisting of -SH, -PO ₃ H ₂ , -CO ₂ H, -NRH, -NRR', and -Si(OR) Polymethyl methacrylate of the head group of ₃ groups. In one embodiment, the selective brush material layer 410 is attracted to a component of a DSA block copolymer (eg, polystyrene or polymethyl methacrylate). Selective material layer 410 can include other suitable materials in other embodiments.

Figure 4D illustrates the structure of Figure 4C following the direct self-polymerization (DSA) block copolymer 414/416 (A/B) coating and polymer polymerization procedure. In one embodiment, the DSA block copolymer is coated on the surface and annealed to separate the polymer into a first polymer block 414 and a second polymer block 416 (identified as 416A in Figure 4D and 416B). In one embodiment, the polymer block 416 preferentially adheres to the selective brush material layer 410 during the annealing process. The polymer block 414 is adhered to the second hard mask layer 408. However, in a particular embodiment, the pitch of the polymerization is one-half the pitch of the first patterned hard mask 404. In this case, portion 416A of polymer block 416 is adhered to selective brush material layer 410 on first hard mask 404, while portion 416B of polymer block 416 is formed between polymer block 414. On the second hard mask layer 408.

In one embodiment, the block copolymer molecules 414/416 (A/B) are polymer molecules formed from chains of covalently bonded monomers. In a two-block copolymer, there are two different types of monomers, and these different types of monomers are primarily included in two different blocks or adjacent sequences of monomers. The block copolymer molecules shown include blocks of polymer 414 and blocks of polymer 416 (A/B). In one embodiment, the block of polymer 414 significantly comprises a chain of covalently linked monomer A (eg, AAAAA...), while the block of polymer 416 (A/B) significantly includes a covalent chain The chain of monomer B of the knot (for example, BBBBB...). Monomers A and B can represent any of the different types of monomers used in the block copolymers known in the art. For example, monomer A may represent a monomer used to form polystyrene, and monomer B may represent a monomer used to form polymethyl methacrylate (PMMA), or vice versa, although the invention The scope is not so limited. In other embodiments, there may be more than two blocks. Moreover, in other embodiments, each of the blocks may comprise a different type of monomer (eg, each block may itself be a copolymer). In one embodiment, the blocks of polymer 414 and the blocks of polymer 416 (A/B) are covalently joined together. The blocks of polymer 414 and the blocks of polymer 416 (A/B) may be of approximately equal length, or one block may be significantly longer than the other.

Generally, blocks of block copolymers (e.g., blocks of polymer 414 and blocks of polymer 416 (A/B)) can each have different chemical properties. For example, one of the blocks can be relatively hydrophobic (eg, water repellent) and the other can be relatively hydrophilic (water absorbing). At least conceptually, one of the blocks may be relatively similar to oil and the other block may be relatively similar to water. These differences in the chemical properties between the different blocks of the polymer (whether hydrophilic-hydrophobic differences or others) may cause self-polymerization of the block copolymer molecules. For example, self-polymerization can be separated according to the microphase of the polymer block. Conceptually, this can be similar to the phase separation of oil and water that it usually cannot mix. Similarly, differences in hydrophilicity between polymer blocks (eg, one block is relatively hydrophobic while another block is relatively hydrophilic) may result in similar microphase separation, where different polymer regions Blocks try to "separate" each other because they don't like each other chemically.

However, in one embodiment, because the polymer blocks are covalently joined to each other, they are not completely separated on a macroscopic scale. Conversely, a given type of polymer block tends to separate or aggregate with polymer blocks of other molecules of the same type in very small (eg, nano-sized) regions or phases. The particular size and shape of the zone or microphase generally depends, at least in part, on the relative length of the polymer block. In one embodiment, for example, in a two-block copolymer, if the blocks are approximately the same length, a grid pattern of alternating polymer 414 lines and polymer 416 (A/B) lines is produced. .

In one embodiment, the polymer 414/polymer 416 (A/B) grating is first coated as an unpolymerized block copolymer layer portion, including, for example, by brush or other coating process. Block copolymer material. The unpolymerized form refers to a case in which (at the time of deposition) the block copolymer has not been substantially phase separated and/or self-polymerized to form a nano. In this unpolymerized form, the block polymer molecules are relatively highly randomized, with different polymer blocks that are highly randomly oriented and positioned. The unpolymerized block copolymer layer portion can be coated in a number of different ways. For example, the block copolymer can be dissolved in a solvent and then spin coated onto the surface. Alternatively, the unpolymerized block copolymer can be spray coated, dip coated, dip coated, or otherwise coated or coated onto the surface. Other ways of coating the block copolymer, as well as other means known in the art for applying similar organic coatings, can potentially be used. Next, the unpolymerized layer can form a portion of the polymeric block copolymer layer, for example, by microphase separation and/or self-polymerization of the unpolymerized block copolymer layer portion. Microphase separation and/or self-polymerization occurs through reconfiguration and/or relocation of the block copolymer molecules, and in particular, reconfiguration and/or relocation of different polymer blocks of the block copolymer molecules.

In this embodiment, the annealing treatment can be applied to the unpolymerized block copolymer to initiate, accelerate, increase, or enhance the quality of the microphase separation and/or self-polymerization. In certain embodiments, the annealing treatment can include a treatment that is operable to increase the temperature of the block copolymer. An example of such a treatment is baking the layer, heating the layer in an oven or above a heat lamp, applying infrared radiation to the layer, or applying heat to the layer or increasing the temperature of the layer. The desired increase in temperature will generally be sufficient to significantly accelerate microphase separation and/or self-polymerization of the block polymer without damaging any other important materials or structures of the block copolymer or integrated circuit substrate. Generally, the heating range can be from about 50 ° C to about 300 ° C, or from 75 ° C to about 250 ° C, but does not exceed the thermal degradation limit of the block copolymer or integrated circuit substrate. Heating or annealing can assist in providing energy to the block copolymer molecules to make them more mobile/elastic to increase the rate of microphase separation and/or to enhance the quality of the microphase separation. This microphase separation or reconfiguration/relocation of the block copolymer molecules can result in self-polymerization to form a very small (e.g., nanoscale) structure. Self-polymerization can occur under the influence of surface energy, molecular affinity, and other surface-related and chemically related forces.

In any event, in certain embodiments, the self-polymerization of the block copolymer (whether or not based on hydrophobic-hydrophilic differences) can be used to form very small periodic structures (eg, precisely spaced nanoscale structures or line). In some embodiments, it can be used to form nanoscale lines or other nanoscale structures that can ultimately be used to form semiconductor fin lines.

Figure 4E illustrates the structure of Figure 4D, followed by removal of one of the blocks of the dual block copolymer. In one embodiment, polymer portion 414 is selectively removed through a wet or dry etch process to leave portion 416 (A/B). The pitch of the remaining portion 416 (A/B) is approximately one-half the pitch of the first patterned hard mask 404.

Figure 4F illustrates the structure of Figure 4E, following the transfer of the pattern of the remaining polymer portion into the underlying fully crystalline semiconductor substrate. In one embodiment, the pattern of the remaining polymer portion 416 (A/B) (i.e., the pattern of the first patterned hard mask 404 when the pitch is halved) is etched into the bulk semiconductor substrate 402. The patterning operation patterns the second hard mask layer 408 to form a second patterned hard mask layer 424 corresponding to the polymer portion 416B. The first patterned hard mask 404 corresponds to the polymer portion 416A. In one embodiment, the plurality of fins 418 are formed directly on the bulk substrate 402 (which becomes the patterned substrate 420) and (as such) are formed to be connected to the bulk substrate 402/420, in an approximate On a flat surface 422.

Figure 4G illustrates the structure of Figure 4F following the removal of the remaining polymer layer and any brush layers. In one embodiment, the remaining polymer layer 416 (A/B) and brush layer 410 are removed to leave a plurality of alternating fins 418 having alternating "colored" first patterned hard masks 404 and A second patterned hard mask 424 is placed thereon. In one embodiment, the remaining polymer layer 416 (A/B) and brush layer 410 are removed using an ashing and cleaning process. The resulting pitch 426 of the fins is half of the pitch 406 of the original first patterned hard mask 404.

4H illustrates the structure of FIG. 4G following the formation of an interlayer dielectric (ILD) layer 428 between the plurality of fins 418. In one embodiment, the ILD layer 428 is comprised of cerium oxide, such as used in a shallow trench isolation process. However, other dielectrics may be used instead, such as nitrides of carbides. The ILD layer 428 can be deposited by chemical vapor deposition (CVD) or other deposition processes (eg, ALD, PECVD, PVD, HDP, assisted CVD, low temperature CVD) and can be chemically polished (CMP) Planar to reveal the uppermost surface of the hard mask layers 404 and 428.

4I illustrates the structure of FIG. 4H following the formation and patterning of a photoresist material used to form patterned mask 430. In one embodiment, the patterned mask 430 has an opening 432 formed therein. The opening 432 exposes one of the targets having the plurality of fins 418 on which the first patterned hard mask 404 is over for the final fin to be removed. Opening 432 has a cut size 436. In one embodiment, the limits for the cut size 436 are relaxed and may even expose portions of adjacent fins having the second patterned hard mask 424 thereon. In one embodiment, the patterning operation uses "coloring" or hard mask material distinctions to prepare to cut away unwanted features to allow the cut size to be twice the pitch 426 of feature 418 (ie, to cause Original pitch 406). In one embodiment, the hard mask material allows for a difference in wet etch selectivity between the plasma or between the two hard mask materials. Furthermore, the edge layout error (EPE) 434 is half pitch. In contrast, in the standard patterning process (no coloring), the cut size is 1X pitch and the edge layout error (EPE) is 1/4 pitch. Thus, in one embodiment, the process described herein doubles the edge layout error budget and doubles the size of the holes or openings required to cut a single feature.

In one embodiment, the patterned mask 430 is comprised of a photoresist layer, as is known in the art, and can be patterned by conventional lithography and development processes. In a particular embodiment, the portion of the photoresist layer that is exposed to the light source is removed while developing the photoresist layer. Therefore, the patterned photoresist layer is composed of a positive photoresist material. In a particular embodiment, the photoresist layer is comprised of a positive photoresist material such as, but not limited to, a 248 nm resist, a 193 nm resist, a 157 nm resist, an extreme ultraviolet (EUV) resist, e A beam resist, an imprint layer, or a phenol resin matrix having a diazonaphthoquinone sensitizer. In another particular embodiment, the portion of the photoresist layer that is exposed to the light source is retained while developing the photoresist layer. Therefore, the photoresist layer is composed of a negative photoresist material. In a particular embodiment, the photoresist layer is comprised of a negative photoresist material such as, but not limited to, poly-cis-isoprene or poly-vinyl-cinnamate. (poly-vinyl-cinnamate). In one embodiment, the lithography operation is performed using 193 nm immersion lithography (193i), EUV and/or electron beam direct writing (EBDW) lithography, and the like. A positive tone or negative tone resist can be used. In one embodiment, the patterned mask 430 is a three-layer mask composed of a topographical masking portion, an anti-reflective coating (ARC), and a photoresist layer. In a particular such embodiment, the terrain shielding portion is a carbon hard mask (CHM) layer and the anti-reflective coating is a germanium containing ARC layer. In one such embodiment, a spin-on glass material with an additional chromophore is used to assist in inhibiting reflectivity. Chemically it is a (p-oxane) ruthenium carbon polymer. When annealed, it forms a mixture of cerium oxide and a carbon polymer.

4J illustrates the structure of FIG. 4I following the etching of selected ones of the plurality of fins 418 and subsequent removal of the patterned mask 430. In one embodiment, the process is referred to as a "fin cut" or "feature selection" operation of the process. In one embodiment, one of the plurality of fins 418 is removed at location 438 to form a patterned plurality of fins 418' having a first interrupt pattern. In one such embodiment, the exposed first patterned hard mask 404 is first removed using an etch process that is selective for any exposed second patterned hard mask 424 and for The ILD layer 428 is selective. In another embodiment, a "fin-hold" approach is used in which the features are selected using the opposite hue of the photoresist and are protected during the etching process while the background or unprotected fins are Remove. It is the opposite polarity of the lithography process (eg, negative versus positive tone imaging). It should be understood that any process can be used for this operation. The exposed fins are then removed to location 438 using an etch process that is selective for the exposed second patterned hard mask 424 and selective for the ILD layer 428. In the first embodiment, the fins are removed from position 438 to level 440, leaving a protruding portion 446 that is higher than flat surface 422. In the second embodiment, the fins are removed from position 438 to level 442, approximately coplanar with flat surface 422. In the third embodiment, the fins are removed from position 438 to level 444, leaving a recess 448 below flat surface 422.

4K illustrates the structure of FIG. 4J following the formation and patterning of a photoresist material used to form patterned mask 450. In one embodiment, the patterned mask 450 has an opening 452 formed therein. The opening 452 exposes a target second of the plurality of fins 418' having the second patterned hard mask 424 thereon for removal of the final fin. In one embodiment, the patterning operation uses "coloring" or hard mask material distinctions to prepare to cut away unwanted features to allow the cut size to be twice the pitch 426 of feature 418'. As described in relation to Figure 4I, the process described herein doubles the edge layout error budget and doubles the size of the holes or openings required to cut a single feature. In one embodiment, the patterned mask 450 is comprised of materials such as those associated with FIG. 4I.

Figure 4L illustrates the structure of Figure 4K after etching of the selected second of the plurality of fins 418'. In one embodiment, the second of the plurality of fins 418' is removed at location 454 to form a patterned plurality of fins 418 having a second interrupt pattern. In one such embodiment, the exposed The second patterned hard mask 424 is first removed using an etch process that is selective for any exposed first patterned hard mask 104 and selective for the ILD layer 428. The exposed fins The wafer is then removed to location 454 using an etch process that is selective to the exposed first patterned hard mask 404 and selective to the ILD layer 428. In the first embodiment The fin is removed from position 454 to level 456, leaving a raised portion above flat surface 422 at a height above surface 440 of protruding portion 446. In the second embodiment, the fin is Removed from position 454 to level 458, leaving a raised portion 464 that is higher than flat surface 422 and at approximately the same height as surface 440 of protruding portion 446. In the third embodiment, the fin is removed At position 454 and to position 460, approximately with the flat surface 422 . In the fourth embodiment, the fin to be removed to a level 462 while leaving a flat surface 422 of the recess 466 is lower than the position 454.

4M illustrates FIG. 4L following the removal of patterned mask 450 and the formation of interlayer dielectric (ILD) layer 468 over complex fins 418" and at locations 438 and 454 where fins have been removed. In one embodiment, the ILD layer 468 is composed of hafnium oxide, such as used in a shallow trench isolation process. However, other dielectrics may be used instead, such as nitride carbides. 468 can be deposited by chemical vapor deposition (CVD) or other deposition processes (eg, ALD, PECVD, PVD, HDP assisted CVD, low temperature CVD). Spin-on materials are another common option for these films. Many low-k dielectric materials can be spin-coated on a wafer and hardened. These are often used in the industry.

4N illustrates the structure of FIG. 4M following the planarization of ILD layer 468 and the removal of first and second patterned hard masks 404 and 424. In one embodiment, a chemical mechanical polishing (CMP) technique is used to remove the first patterned hard mask 404 and the second hard mask 424 to individually recess the ILD layers 428 and 468 to the resulting planarization. ILD layers 428' and 468', and surfaces for exposing the plurality of fins 418". In one embodiment, the planarized ILD layer 428' is composed of the same material substantially as the planarized ILD layer 468'. In one embodiment, the planarized ILD layer 428' is comprised of a different material than the planarized ILD layer 468'. In either case, in one embodiment, a seam is formed in the ILD layer 468' and the ILD layer. Between 428', for example, at location 438 or 454. It should be understood that in one embodiment, the exposed surface of the plurality of fins 418" can be used to form a planar semiconductor device.

According to another embodiment, Figure 5 illustrates the structure of Figure 4N after exposure of portions above the plurality of fins 418. Referring to Figure 5, the ILD layer 468' and the ILD layer 428' are recessed to expose the fins 418' The portion 472 is raised and provides a recessed ILD layer 468" and a recessed ILD layer 428" to a recess height 476. The recess height 476 defines the location between the upper fin portion 472 and the lower fin portion 474. The ILD layer 468' and the ILD The recess of layer 428' can be performed by a plasma, vapor or wet etch process. In one embodiment, a dry etch process selective for samarium fin 418" is used, which is based on a dry etch process Plasma generated by gases such as, but not limited to, NF ₃ , CHF ₃ , C ₄ F ₈ , HBr and O ₂ , with a pressure in the range of typically 30-100 mTorr and a plasma bias of 50-1000 Watts .

In an exemplary embodiment, referring again to FIGS. 4J, 4L, and 5, a semiconductor structure includes a plurality of semiconductor fins 418" that protrude from a substantially planar surface 422 of a semiconductor substrate 420. The plurality of semiconductor fins 418" have a first The grating pattern interrupted by position 438 has a first fin portion 446 having a first height. The grating pattern of the semiconductor fins is further interrupted by a second location 454 having a second fin portion 464 having a second height. In one embodiment, the second height of the second fin portion 454 is different from the first height of the first fin portion 446. In another embodiment, the second height of the second fin portion 454 is the same as the first height of the first fin portion 446. In one embodiment, the grating pattern has a constant pitch 126 when viewed without such interruptions.

In an exemplary embodiment, referring again to FIGS. 4J, 4L, and 5, a semiconductor structure includes a plurality of semiconductor fins 418" that protrude from a substantially planar surface 422 of a semiconductor substrate 420. The plurality of semiconductor fins 418" have a first The grating pattern interrupted by position 438 has a first depression. In one embodiment, the grating pattern of the semiconductor fins is further interrupted by a second location 454 having a second recess, or one of the fin portions. In one embodiment, the grating pattern has a constant pitch 426 when viewed without such interruptions. In one embodiment, the trench isolation layer 468" is disposed in and on the recess.

It should be understood that the above approach can be applied to the fabrication of other semiconductor geometries than semiconductor fins. For example, in one embodiment, the above manner is implemented to produce a semiconductor nanowire or a semiconductor nanobelt. In one embodiment, the terms "semiconductor body" or "majority semiconductor body" generally refer to geometries such as fins, nanowires, and nanoribbons.

It should be understood that the structures resulting from the above exemplary processing scheme (e.g., the structures from Figures 4N and 5) can be used in the same or similar forms of subsequent processing operations to complete device fabrication (such as PMOS and NMOS device fabrication). 6A and 6B individually illustrate cross-sectional and plan views of a non-planar semiconductor device (taken along the a-a' axis of the cross-sectional view), in accordance with an embodiment of the present invention. example.

Referring to FIG. 6A, the semiconductor structure or device 600 includes a non-planar active region formed from the substrate 602 (and within the isolation region 606) (eg, a fin structure including the protruding fin portion 604 and the sub-fin region 605). Gate line 608 is disposed over protruding portion 604 of the non-planar active region and over a portion of isolation region 606. As shown, gate line 608 includes gate electrode 650 and gate dielectric layer 652. In an embodiment, the gate line 608 can also include a dielectric layer cap layer 654. The gate contact 614 and the upper gate contact via 616 are also seen from this perspective view, along with the upper metal interconnect 660, which are all disposed in the interlayer dielectric stack or layer 670. As also seen in the perspective view of FIG. 6A, the gate contact 614 (in one embodiment) is disposed over the isolation region 606, but not above the non-planar active region.

As also shown in FIG. 6A, in one embodiment, the artifacts of the fin selection recess remain in the final structure. For example, in the illustrated embodiment, the residual protrusions 699 remain. In other embodiments, the depressions may remain as described above.

As also shown in FIG. 6A, in one embodiment, interface 680 is present between protruding fin portion 604 and sub-fin panel region 605. Interface 680 can be a transition region between the doped sub-fin region 605 and the slightly or undoped upper fin portion 604. In one such embodiment, each fin is about 10 nanometers wide or less, and the sub-fin dopant is supplied from an adjacent solid doped layer at the sub-fin location. In certain such embodiments, each fin is less than 10 nanometers wide.

Referring to FIG. 6B, gate line 608 is shown disposed over protruding fin portion 604. The source and drain regions 604A and 604B of the protruding fin portion 604 can be seen from this perspective view. In one embodiment, the source and drain regions 604A and 604B are doped portions of the original material that protrudes from the fin portion 604. In another embodiment, the material of the protruding fin portion 604 is removed and replaced with another semiconductor material, such as by epitaxial deposition. In either case, the source and drain regions 604A and 604B can extend below the height of the dielectric layer 606, that is, into the sub-fin region 605. In accordance with an embodiment of the present invention, the thicker heavily doped sub-fin regions (i.e., the doped portions of the fins under the interface 680) prevent source-to-drain leakage through the portion of the bulk semiconductor fins.

In one embodiment, the semiconductor structure or device 600 is a non-planar device such as, but not limited to, a fin-FET or a three-gate device. In this embodiment, the corresponding semiconductor channel region is composed of a three-dimensional body or is formed as a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 608 surrounds at least a top surface of the three-dimensional body and a pair of sidewalls.

Substrate 602 can be comprised of a semiconductor material that can withstand manufacturing processes and in which charge can migrate. In one embodiment, the substrate 602 is a bulk substrate that is doped with a crystalline germanium, ruthenium/iridium or ruthenium layer doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof. Composition to form active zone 604. In one embodiment, the concentration of germanium in the bulk substrate 602 is greater than 97%. In another embodiment, the bulk substrate 602 is comprised of an epitaxial layer grown on top of the separated crystalline substrate, for example, a germanium epitaxial layer grown on top of a boron doped bulk germanium single crystal substrate. The bulk substrate 602 can alternatively be composed of a group III-V material. In one embodiment, the bulk substrate 602 is composed of a III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium arsenide. Gallium, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, the bulk substrate 602 is composed of a group III-V material, and the charge carrier dopant impurity atoms are such as, but not limited to, carbon, germanium, germanium, oxygen, sulfur, selenium or germanium. And so on.

The isolation region 606 can be comprised of a material that is adapted to ultimately electrically isolate (or facilitate isolation) portions of the permanent gate structure from the underlying bulk substrate or to isolate it from the active region within the underlying bulk substrate. , such as the isolation fin active area. For example, in one embodiment, isolation region 606 is comprised of a dielectric material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium nitride, or carbon doped tantalum nitride.

Gate line 608 can be comprised of a gate electrode stack including gate dielectric layer 652 and gate electrode layer 650. In one embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium ruthenate, hafnium oxide, zirconium oxide, zirconium niobate, hafnium oxide. , barium titanate, barium titanate, barium titanate, barium oxide, aluminum oxide, lead oxide antimony, lead zinc antimonate, or a combination thereof. Further, a portion of the gate dielectric layer can include a layer of natural oxide formed from a plurality of layers on top of the substrate 602. In one embodiment, the gate dielectric layer is comprised of a top high k portion and a lower portion (composed of an oxide of a semiconductor material). In one embodiment, the gate dielectric layer is composed of a top portion of yttrium oxide and a bottom portion of ruthenium dioxide or yttrium oxynitride. In some embodiments, the portion of the gate dielectric is a "U"-like structure that includes a bottom portion that is substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.

In one embodiment, the gate electrode is composed of a metal layer such as, but not limited to, a metal nitride, a metal carbide, a metal halide, a metal aluminide, hafnium, zirconium, titanium, hafnium, aluminum, Rhodium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a particular embodiment, the gate electrode is comprised of a non-working function setting fill material formed over the metal work function setting layer. The gate electrode layer may be composed of a P-type work function metal or an N-type work function metal, which will be a PMOS or NMOS transistor depending on the transistor. In some embodiments, the gate electrode layer can include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer. For PMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode having a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, tantalum, zirconium, titanium, hafnium, aluminum, alloys of these metals, and carbides of these metals, such as tantalum carbide, zirconium carbide, titanium carbide. , tantalum carbide, and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode can include a "U"-like structure that includes a bottom portion that is substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode can be only a planar layer that is substantially parallel to the top surface of the substrate and does not include a sidewall portion that is substantially perpendicular to the top surface of the substrate. In a further embodiment of the invention, the gate electrode can comprise a U-shaped structure and a combination of planar, non-U-shaped structures. For example, the gate electrode can include one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.

The spacer associated with the gate electrode stack can be comprised of a material that is adapted to ultimately electrically isolate (or facilitate isolation) the permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. . For example, in one embodiment, the spacer is comprised of a dielectric material such as, but not limited to, ceria, hafnium oxynitride, hafnium nitride, or carbon doped tantalum nitride.

The gate contact 614 and the upper gate contact via 616 may be comprised of a conductive material. In one embodiment, one or more of the contacts or vias are comprised of a metal species. The metal species may be a pure metal such as tungsten, nickel, or cobalt; or may be an alloy such as a metal metal alloy or a metal semiconductor alloy (eg, such as a telluride material).

In one embodiment (although not shown), the provisioning structure 600 involves forming a contact pattern that is excellently aligned with an existing gate pattern while eliminating the need for a lithographic operation with an extremely severe login budget. . In one such embodiment, this approach enables the use of essentially highly selective wet etching (e.g., relative to conventionally implemented dry or plasma etching) to create contact openings. In one embodiment, the contact pattern is formed by utilizing an existing gate pattern in conjunction with a contact plug lithography operation. In one such embodiment, this approach enables the elimination of the need for other key lithographic operations (e.g., users in conventional manner) to create contact patterns. In one embodiment, the trench contact grids are not separately patterned, but are formed between polycrystalline (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grating patterning but before the gate grating is cut.

Furthermore, the gate stack structure 608 can be fabricated by a replacement gate process. In this technique, a virtual gate material such as a polysilicon or tantalum nitride material can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in the process, unlike the one that was completed since the earlier process. In one embodiment, the dummy gate is removed by a dry etch or a wet etch process. In one embodiment, the dummy gate is composed of polysilicon or amorphous germanium and is removed by a dry etch process including the use of SF ₆ . In another embodiment, the dummy gate of polysilicon or amorphous silicon-based and is composed include aqueous NH ₄ OH or of tetramethylammonium hydroxide, using a wet etch process to remove. In one embodiment, the dummy gate is composed of tantalum nitride and is removed by wet etching including aqueous phosphoric acid.

In one embodiment, one or more of the ways described herein essentially consider a virtual and replacement gate process in conjunction with a virtual and replacement contact process to obtain structure 600. In one such embodiment, the replacement contact program is performed after the replacement gate procedure to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in certain such embodiments, annealing of at least a portion of the permanent gate structure (eg, after the gate dielectric layer is formed) is performed at a temperature greater than about 600 degrees Celsius. Annealing is performed before the formation of permanent joints.

Referring again to Figure 6A, the semiconductor structure or device 600 is configured to place a gate contact over the isolation region. This configuration can be considered as an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed over an active region. Typically, one or more of the present invention is formed prior to forming a gate contact structure (such as a via) on the active portion of the gate and in the same layer as the trench contact via (eg, otherwise) Or more embodiments include first using a gate-aligned trench contact process. This process can be implemented to form a trench contact structure for semiconductor structure fabrication, for example, for integrated circuit fabrication. In one embodiment, the trench contact pattern is formed to align with an existing gate pattern. Conversely, the conventional approach typically involves an additional lithography process with a lithographic contact pattern closely aligned to the existing gate pattern, in conjunction with selective contact etching. For example, conventional processes may include patterning of separately patterned polycrystalline (gate) grids with contact features.

It is to be understood that not all of the above-described embodiments are required to be practiced within the spirit and scope of the embodiments of the invention. For example, in one embodiment, the dummy gate need not be formed before the fabrication of the gate contact over the active portion of the gate stack. The gate stack described above may actually be a permanent gate stack, as formed at the outset. At the same time, the procedures described herein can be used to fabricate one or more semiconductor devices. The semiconductor device may be a device such as a transistor. For example, in one embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Also, in one embodiment, the semiconductor device has a three-dimensional architecture, such as a three-gate device, an independently accessed dual gate device, or a FIN-FET. One or more embodiments may be particularly useful in fabricating semiconductor devices on sub-10 nanometer (10 nm) technology nodes.

It should be understood that in the above exemplary FEOL embodiment, in one embodiment, the sub-10 nanometer process is implemented directly in the manufacturing scheme as well as in the resulting structure. In other embodiments, FEOL considerations may be driven by BEOL's 10 nanometer processing requirements. For example, material selectivity and layout for FEOL layers and devices may need to accommodate BEOL sub-10 nanometer processing. In one such embodiment, the material selectivity and gate stacking architecture is selected to accommodate high density metallization of the BEOL layer, for example, to reduce edge capacitance in the transistor structure, which is formed in the FEOL layer but borrowed Coupled together by high density metallization of the BEOL layer. As such, the FEOL structure and processing can be directly affected by the next 10 nm process or can be indirectly affected by the next 10 nm process of the BEOL layer.

The integrated circuit back end of line (BEOL) layer typically includes a conductive microelectronic structure (known in the art as a via) for electrically connecting metal lines or other interconnects over the via to the metal under the via. Line or other interconnection. Through holes are typically formed by lithography procedures. Typically, a photoresist layer can be spin coated onto the dielectric layer, the photoresist layer can be exposed to the patterned actinic radiation through the patterned mask, and then the exposed layer can be developed to form Opening in the photoresist layer. Next, the opening for the via can be etched into the dielectric layer by using an opening in the photoresist layer as an etch mask. This opening is referred to as a through hole opening. Finally, the via opening can be filled with one or more metals or other conductive materials to form the vias.

In the past, the size and spacing of vias have been significantly reduced, and it is expected that the size and spacing of vias will continue to decrease significantly in the future, for at least some types of integrated circuits (eg, advanced microprocessors, chipset components, graphics). Wafer, etc.). When such a lithography procedure is used to pattern very small vias having a very small pitch, there are several challenges in their own right. One of these challenges is that the overlap between the via and the upper interconnect, and the overlap between the via and the underlying interconnect typically need to be controlled to a high tolerance of a quarter of the pitch of the via. As the via pitch dimensions become smaller and smaller, the overlap tolerance tends to shrink at a greater rate than the lithography device can follow.

Another of these challenges is that the critical dimensions of the via opening typically tend to shrink more quickly than the resolution of the lithography scanner. There are shrinking technologies to reduce the critical size of the via opening. However, the amount of reduction tends to be limited by the minimum via pitch, and is limited by the ability of the reduction procedure to be sufficiently optically approximated (OPC) neutral, and does not significantly compromise line width roughness (LWR) and/or critical Size uniformity (CDU). Yet another of these challenges is that the LWR and/or CDU characteristics of the photoresist typically need to be modified as the critical dimensions of the via opening are reduced to maintain the same overall segment of the critical size budget. However, most of the current LWR and/or CDU characteristics of photoresists have not been as rapid as the critical dimension reduction of via openings.

A further such challenge is that very small via pitches tend to be lower than the resolution capabilities of even extreme ultraviolet (EUV) lithography scanners. As a result, typically several different lithographic masks can be used, which tend to increase cost. At some point, if the pitch continues to decrease, it may not be possible (even with multiple masks) to use EUV scanners to print these very small pitch via openings.

The above factors are also related to the layout and expansion of non-conducting spaces or interruptions (called "plugs", "dielectric plugs" or "wire ends") between metal lines, in the latter stage (BEOL). Metal interconnects between metal lines. The above factors are also related to a conductive sheet, which (by definition) is a conductive link between two conductive metal lines, such as between two parallel conductive lines. The conductive sheets are typically located in the same layer as the metal lines. Therefore, there is a need to improve the field of metallization manufacturing techniques for fabricating metal lines, metal vias, conductive sheets, and dielectric plugs.

In some of the embodiments described below, the patterning and alignment of via features (or other BEOL features) is achieved using a number of reticle and critical alignment strategies. In other embodiments, the manner described herein enables the fabrication of self-aligned plugs and/or vias. In the latter embodiment, it may be the case where only one critical overlap step (Mx+1 raster) needs to be implemented.

It should be understood that the layers and materials described below in connection with the back end of line (BEOL) structure and processing are typically formed on or over the underlying semiconductor substrate or structure, such as the device layer below the integrated circuitry. In one embodiment, the lower semiconductor substrate represents a general workpiece object used to fabricate an integrated circuit. Semiconductor substrates often include wafers or other pieces of germanium or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal germanium, polycrystalline germanium and germanium insulators (SOI), and similar substrates formed from other semiconductor materials (such as substrates including germanium, carbon, or III-V materials). Semiconductor substrates (according to the stage of manufacture) often include transistors, integrated circuits, and the like. The substrate can also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, the depicted structure can be fabricated on the lower order interconnect layer below.

While the method of fabricating the metallization layer (or portion of the metallization layer) of the BEOL metallization layer is described in detail for the selection operation, it should be understood that additional or intermediate operations of its fabrication may include standard microelectronic fabrication processes, such as micro Shadowing, etching, thin film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, and/or related to microelectronic component fabrication Any other action. At the same time, it should be understood that the process operations described in the following process flow can be performed in an alternate order, not every operation needs to be performed and/or additional process operations can be performed.

In some cases, the resulting structure enables it to be concentrated directly on the fabrication of vias on the underlying metal lines. The vias may have a wider, narrower, or the same thickness than the underlying metal lines, for example, due to imperfect selective etching processes. However, in one embodiment, the center of the via is aligned (matched) with the center of the metal line. As such, in one embodiment, the deviation from conventional lithography/dual damascene patterning (which is otherwise tolerated) will not be a factor in the resulting structure of one or more of the following process schemes.

It should be understood that certain interconnect fabrication schemes described below can be implemented to save a lot of alignment/exposure, can be implemented to improve electrical contact (eg, by reducing via resistance), or can be implemented to reduce overall process operation. And processing time, as needed to pattern these features using conventional methods. It should also be understood that in subsequent or additional manufacturing operations beyond those shown, in some examples, the dielectric layer can be removed from the layers of the metal lines to provide an air gap between the metal lines.

In accordance with an embodiment of the invention, a backbone mode is described. This backbone approach can involve most stages of atomic layer deposition (ALD). In one embodiment, tight pitch formation is achieved by iterative spacer formation, for example, using ALD processing.

To provide a background, lithographic patterning for features of semiconductor fabrication is limited to the resolution of imaging tools, whether optical (eg, 193 nm), electron beam, or EUV. Process methods such as multi-pass patterning, pattern reduction, and spacer-based pitch segmentation can be used to extend the resolution by a factor of 2 to 4 or even a factor of 8. However, such methods can be limited in that process variations in the original lithography step are left with similar values in the final pattern. For example, the lithography operation can have a variation of +/- 3 nm. If so, the pitch division process method is utilized to produce a final pitch of 8 nm (4 nm feature size), and the resulting final pattern is changed to 4 nm +/- 3 nm.

One or more embodiments described herein relate to the use of iterative spacers or thin film deposition to define all or substantially all of the last critical small features for a layer, such as a BEOL layer. These features can be better than +/- 1 nm, which is consistent with ALD technology. Most materials can be utilized to enable "coloring" of the pattern to enable it to address alternative features (eg, vias, cuts, plugs, etc.) that have an amplification tolerance for edge layout errors.

7A and 7B illustrate cross-sectional views of a target infrastructure for enabling a very tight pitch final pattern of a semiconductor layer, in accordance with an embodiment of the present invention.

Referring to FIG. 7A, target base layer 700 includes a patterned layer 702 over hard mask layer 704 over transfer layer 706 over substrate 708. Patterned layer 702 includes backbone features 710. Backbone feature 710 is a relatively wide feature (eg, 6-12 nm), a relatively small feature of intermediate group 712 (eg, a smaller feature of 6-100 s between adjacent backbone features 710, where Smaller features are, for example, 4-6 nm wide).

In one embodiment, each of the intermediate groups 712 of relatively small features includes a small feature 716 of a first material type, a small feature 714 of a second material type different from the first material type, and a different from the first A small feature 718 of a material type and a third material type of the second material type. The difference in material type can provide different etch characteristics or selectivity between the material types. In one embodiment, the material of the backbone feature 710 is the same material as the third material type of the small feature 718, as depicted in Figure 7A. In another embodiment, the material of the backbone feature 710 is different from the material of the third material type of the small feature 718, but has similar etch characteristics or selectivity as the third material type of the small feature 718.

Referring to FIG. 7B, the target base layer 750 includes a patterned layer 752 over the hard mask layer 754 above the transfer layer 756 above the substrate 758. Patterned layer 752 includes a backbone feature 760. Backbone feature 760 is a relatively wide feature (eg, 6-12 nm), a relatively small feature of intermediate group 762 (eg, a smaller feature of 6-100 s between adjacent backbone features 760, where Smaller features are, for example, 4-6 nm wide).

In one embodiment, each of the intermediate groups 762 of relatively small features includes a small feature 764 of a first material type, a small feature 766 of a second material type different from the first material type, and a different from the first A small feature 768 of a material type and a third material type of the second material type. The difference in material type can provide different etch characteristics or selectivity between the material types. In one embodiment, the material of the backbone feature 760 is the same material as the second material type of the small feature 766, as depicted in Figure 7B. In another embodiment, the material of the backbone feature 760 is different from the material of the second material type of the small feature 766, but has similar etch characteristics or selectivity as the third material type of the small feature 766.

Referring to both FIGS. 7A and 7B, in one embodiment, structure 700 or 750 includes a plurality of iterative vertical layers of alternating materials that will ultimately define a semiconductor pattern (eg, metal, transistor, etc.) The last position of the feature. Occasionally larger features may appear because they represent a lithographically defined structure that (in one embodiment) is larger (wider) due to its larger size variation. In one embodiment, six to hundreds of narrow features are between the wide features.

8A-8H illustrate cross-sectional views showing various operations in a method of fabricating a target infrastructure for enabling a very tight pitch final pattern of a semiconductor layer, in accordance with an embodiment of the present invention. In general, in one embodiment, an iterative film generation operation is utilized. For example, conformal film deposition is performed, followed by anisotropic etching (eg, spacer formation), selective growth, or directed self-polymerization (DSA). A patterning process such as that described below can be implemented to provide a patterning process suitable for producing a very tight pitch final pattern of a semiconductor layer. In one embodiment, the advantages of implementing such a process stream include enhanced dimensional control of the tight pitch feature, utilizing a built-in method for coloring alternating features to allow for self-aligned vias, plugs, and cuts. .

Figure 8A illustrates a process operation involving high backbone formation. A plurality of backbone features 808 are formed over the hard mask layer 806, which is formed over the transfer layer 804, which is formed over the substrate 802. In one embodiment, the formation of the plurality of backbone features 808 involves the use of standard lithography operations (eg, 193 nm or EUV) followed by etching into a hard mask (eg, SiN, SiO ₂ , SiC) and then removing any remaining Retaining the resist and/or anti-reflective layer (eg, by ashing or wet cleaning).

Figure 8B illustrates a process operation involving the formation of a first spacer (spacer 1). A first set of small features 810 of the first material composition are formed along the sidewalls of each of the plurality of backbone features 808. In one embodiment, the first set of small features 810 are formed using deposition (eg, ALD) and etching. In another embodiment, the first set of small features 810 are formed using a selective growth mode.

8C illustrates a process operation involving formation of a second spacer (spacer 2), formation of a third spacer (spacer 3), and formation of a fourth spacer (spacer 4), as shown by way of example Specific layer of the example. A second set of small features 812 of second material composition are formed along the exposed sidewalls of each of the first set of small features 810. A third set of small features 814 of the third material composition are formed along the exposed sidewalls of each of the two sets of small features 812. A fourth set of small features 816 of second material composition is formed along the exposed sidewalls of each of the third set of small features 814. In one embodiment, the second set of small features 812 are first formed using deposition (eg, ALD) and etching or selective growth. The third set of small features 814 are then formed using another deposition (eg, ALD) and etching or selective growth. The fourth set of small features 816 are then formed using another deposition (eg, ALD) and etching or selective growth.

Figure 8D illustrates a process operation involving continuous layer generation. Additional spacer layers 818 are formed sequentially, ordered by selection of material types. The additional spacer layer 818 can be fabricated using deposition and etching methods, selective growth methods, or a combination thereof. It should be understood that more layers than those shown may be added. For example, in one embodiment, an additional 20-200 sets of spacers are formed at this stage. The deposition of the spacers can be completed prior to the combination of adjacent sidewall growth, for example, spacer formation is stopped while the opening 820 remains. It should be understood that although the deposition and etching modes or selective growth modes are described as being for the options of Figures 8A-8D, directed self-polymerization (DSA) can be used in place of or as one of the options for spacer formation as described herein. In one such example, a three-block based DSA is used. An example of a three-block based DSA is described below with respect to Figures 12A-12K.

In one embodiment, collectively referring to Figures 8A-8D, iterative generation of thin layers of alternating material on the side of the template features defined by the original lithography is performed. One potential method for achieving this structure is through thin film deposition followed by anisotropic etching. In one embodiment, a single process tool is used to perform both deposition and etching to significantly increase the efficiency of this approach. Other methods of producing a thin layer of well controlled thickness include selective growth or DSA.

Figure 8E illustrates a process operation involving bone removal. The backbone feature 808 is removed to leave an opening 822. In one embodiment, the opening 822 has a width that is approximately the same as the width of the opening 820, as depicted in Figure 8E. In one embodiment, each of the openings 820 and 822 has a spacer 824 that is a sidewall and a spacer 824 that is comprised of a first material. As shown, certain spacers 824 are reassigned from previously labeled spacers 810. In an embodiment, the backbone feature 808 is removed to provide more space for further small feature generation.

Figure 8F illustrates a process operation involving continuous layer generation. Openings 820 and 822 are formed using continuous spacers and are ultimately completely filled. In an exemplary embodiment, spacers 826 are formed along the exposed sidewalls of spacers 824. In one such embodiment, the spacer 826 is of a second material composition. In one embodiment, the final wide feature 828 is ultimately formed at the center of each of the openings 820 and 822 at a stage when further spacer formation is undesirable or achievable. In one embodiment, the formation of the final wide feature 828 involves a combination of material growth along the adjacent sidewalls of the spacer 826. In one such embodiment, the combination of material growth provides a final wide feature 828, each having a seam that is approximately centered within the final wide feature 828. In one embodiment, the last wide feature 828 is of a third material composition.

Figure 8G illustrates a process operation involving planarization of the structure of Figure 8F. In one embodiment, the planarization is performed using a chemical mechanical polishing (CMP) operation. In one embodiment, the planarization process provides a planar structure prior to plug/cut and via process operations. Position 828 that directly concentrates under the original lithography feature (which results in opening 822) and is halfway separated therebetween (which results in opening 820) can be targeted to accommodate larger size changes associated with lithographic operations, Compared to a single film (plus etching) operation. In one embodiment, as shown, the structure of Figure 8G is similar or identical to that described in connection with Figure 7A.

Figure 8H illustrates a process operation involving selective removal of all features of the first material composition, for example, spacers 810/824 (corresponding to the small features 716 of the first material type from the structure of Figure 7A, as in Figure 8G Shown). In one embodiment, the small features 716 of the first material type are removed using a selective etch process that does not remove (or only remove a small amount of) the remaining spacer material. In the exemplary embodiment illustrated in FIG. 8H, after removing the small features 716 of the first material type, metal line patterned features 830 are formed in the openings that are small in removing all of the first material types. Feature 716 is produced. Portions of the metal line patterned features 830 are associated with the underlying via patterning features 832. Although not depicted, the selected one of the small features 716 of the first material type may be retained (eg, by a photolithography blocking process that blocks the selected ones of the small features 716 of the first material type from being removed) to form Plug patterning features. In one embodiment, the metal line patterning features 830, via patterning features 832, and any plug patterning features are ultimately patterned into a hard mask layer 806 and a transfer layer 804 for the final pattern of the underlying layer. Chemical. In another embodiment, as shown, metal line patterning features 830, via patterning features 832, and any plug patterning features actually represent metal lines, vias, and plugs formed in layer 834. ,as the picture shows. Either a metal line patterned feature 830 or an actual metal line, each may have an overlying hard mask cap layer 836 to protect the features during subsequent processing of layer 834, as shown in Figure 8H. Referring again to FIG. 8H, in one embodiment, by shifting only one spacer type, additional tolerance is provided to the plug, via, and/or process variations in the patterning operation.

Figures 8H' and 8H" illustrate cross-sectional views of exemplary structures following the patterning of vias and plugs, in accordance with an embodiment of the present invention.

Figure 8H' illustrates a process operation involving selective removal of all of the materials from the backbone features 710 of Figure 8H and all of the small features 718 of the third material type. In one embodiment, the backbone feature 710 and the third feature of the third material type are removed using a selective etch process that does not remove (or only remove a small amount) the remaining Spacer material or replaced spacer material. In the exemplary embodiment illustrated in FIG. 8H′, after the backbone feature 710 and the small feature 718 of the third material type are removed, the second metal line patterned feature 838 is formed in most or all of the openings. This is produced when the backbone feature 710 and the small feature 718 of the third material type are removed. In one embodiment, any remaining openings of the openings created when the backbone features 710 and the small features 718 of the third material type are removed are filled with plug material 850 (eg, to provide a source such as SiN or SiO _{2 )} A line end feature composed of a non-conductive material, or is retained as a plug region. Portions of the second metal line patterning feature 838 are associated with the lower second via patterning feature 840. In one embodiment, the second metal line patterning feature 838, the second via patterning feature 840, and any of the plug patterning features 850 are ultimately patterned into a hard mask layer 806 and a transfer layer 804 for The final patterning of the lower layer. In another embodiment, as shown, the second metal line patterning feature 838, the second via patterning feature 840, and any of the plug patterning features 850 actually represent metal lines, vias, and plugs, individually. Plug.

Either a metal line second patterned feature 838 or an actual metal line, or whether it is a patterned plug feature 850 or an actual plug feature 850, each may have an overlying hard mask cap layer 842 to protect the features for subsequent processing During operation, as shown in Figure 8H'. In one embodiment, the overlying hard mask cap layer 842 has a different composition than the overlying hard mask cap layer 836. Thus, in one embodiment, the alternating features have different hard mask materials. This configuration may preferably facilitate subsequent connections of the vias, with subsequent formation of layers from above, with increased edge layout tolerances to prevent vias from erroneous metal features.

It should be understood that the composition of metal lines 830 and second metal lines 838 may be different because metal lines 830 (or patterned features) and second metal lines 838 (or patterned features) are formed in different processing operations. In the exemplary embodiment, Figure 8H" illustrates an example in which metal line 830' has a different composition than metal line 838. Thus, alternating features may be comprised of different electrically conductive materials.

It should be understood that some older forms of spacer-based pitch segmentation techniques can be used for mass production. The above-described embodiments surrounding the backbone mode can be implemented to extend the one or two-pass spacer-based pitch division to an extremely high number of iterative spacer forming operations. One or more embodiments provide a way to scale the density of semiconductor wafers at high manufacturing yields. One or more embodiments provide a tight interconnect for making a feature feature that is constantly well formed, or even a transistor (if applied to FEOL processing). It should be understood that reverse engineering of products made using backbone methods can reveal significant tight pitch features (e.g., sub-10 nm pitch features) with occasionally wide one-dimensional (1D) features. Cross-sectional scanning electron microscopy (XSEM) reveals that "colored" (eg, different properties such as etch selectivity) are hard masked on alternating features.

In accordance with an embodiment of the present invention, pitch segmentation is applied to provide a means for fabricating alternating metal lines in a BEOL fabrication scheme. One or more embodiments described herein have a joint pitch splitting patterning process that increases the overlap tolerance for through holes, cuts, and plugs. Embodiments enable continuous expansion of the pitch of the metal layer beyond the resolution capabilities of state of the art lithography equipment. In one embodiment, the spacing between the metal lines is constant and can be controlled to an angstrom level accuracy using ALD. In one embodiment, the process flow is designed such that its "replacement of ILD" flow is possible. That is, the ILD can be deposited after patterning and metallization is completed. The patterning process typically damages the ILD through an etch/clean step; however, in this process, the ILD can be deposited last and thus avoid damage during patterning.

In order to provide background, edge layout errors in through-hole, dicing, and plug patterning are problematic when feature size and pitch are scaled. The most advanced solution to solve these problems involves attempting to tighten edge layout errors by increasing scanner overlap and enhancing critical dimension (CD) control or attempting to use super-self-aligned integration. Conversely, the embodiments described herein relate to an embodiment of a process that achieves similar improvements in the marginal layout error range without the need for lithographic tools or super-self-alignment enhancements.

In accordance with an embodiment of the present invention, metal lines are fabricated in two separate operational sequences to double the amount of overlap tolerance for the dicing/plug and via patterning. In a first portion of the example process flow, a pitch segmentation method is used to pattern metal lines, plugs, and then vias into the interlayer dielectric material. In the second part of the example process flow, the trench/via opening is filled with metal (eg, dual damascene metallization) and then polished. The sacrificial hard mask layer is then removed between the metal lines. The metal lines are then coated to sacrifice the dielectric material using, for example, atomic layer deposition (ALD). In a third portion of the example process flow, an isotropic spacer etch is performed to expose the bottom of the trench. Using the plug patterning process, a dielectric material is applied to where the metal line ends should occur, and via etching is done on the complementary metal lines. The metal from the first metal line acts as an etch stop to prevent etching in these locations. In the fourth part of the example process flow, the trench is filled with metal and polished to expose the metal. After polishing, the sacrificial hard mask material is removed and, optionally, replaced with a dielectric material and then polished again to complete the metallization process. The air gap can also be inserted by tuning the deposition of the dielectric material. Moreover, embodiments may involve sacrificing the use of a hard mask material (instead of a metal). The sacrificial hard mask can be removed and replaced with metal during the "second" metallization operation.

In the example processing scheme, FIGS. 9A-9L illustrate oblique angle cross-sectional views of portions of an integrated circuit layer that represent a pitch segmentation patterning that involves increased overlap tolerance for post-process (BEOL) interconnect fabrication. Each of the methods is in accordance with an embodiment of the present invention.

Referring to Figure 9A, a starting point structure 900 is provided as a starting point for making a new metallization layer. The starting point structure 900 includes a hard mask layer 902 disposed on the sacrificial layer 904 that is disposed on the interlayer dielectric (ILD) layer 906. The ILD layer can be disposed over the substrate, and (in one embodiment) is disposed over the underlying metallization layer. In one embodiment, the hard mask layer 902 is a tantalum nitride (SiN) or titanium nitride hard mask layer. In an embodiment, the sacrificial layer is a germanium layer, such as a polysilicon layer or an amorphous germanium layer.

Referring to FIG. 9B, the hard mask layer 902 and the sacrificial layer 904 of the structure of FIG. 9B are patterned. The hard mask layer 902 and the sacrificial layer 904 are patterned to form the patterned hard mask layer 908 and the patterned sacrificial layer 910 individually. The patterned hard mask layer 908 and the patterned sacrificial layer 910 include a pattern of first line openings 912 and line end regions 914. In one embodiment, the tantalum sacrificial layer is adapted to be patterned to fine features using an anisotropic plasma etching process. In one embodiment, a lithography resist mask exposure and etch process is used to form a patterned hard mask layer 908 and a patterned sacrificial layer 910 with subsequent removal of the resist layer or stack. In one embodiment, the first line opening 912 has a raster type pattern, as depicted in Figure 9B. In an embodiment, a pitch division patterning scheme is used to form a pattern of first line openings 912. An example of a suitable pitch segmentation scheme is described in more detail below. Subsequent line "cut" or plug retention lithography processes can then be used to define the line end region 914.

Figure 9C illustrates the structure of Figure 9B following the patterning of the underlying via locations. A via opening 916 can be formed at selected locations on the ILD layer 906 to form a patterned ILD layer 918. In one embodiment, the vias are patterned using a self-aligned via process. The selected location is formed within the region of the ILD layer 906 that is exposed by the first line opening 912. In one embodiment, separate lithography and etching processes are used to form via openings 916 after the lithographic patterning process to form first line openings 912.

Figure 9D illustrates the structure of Figure 9C following the first metallization process. In one embodiment, a dual damascene metallization process is used in which vias and metal lines are simultaneously filled. Interconnect lines 920 and conductive vias 920 are formed in the first line openings and via openings 916. In one embodiment, a metal fill process is performed to provide interconnect lines 920 and conductive vias 920. In one embodiment, the metal fill process is performed using metal deposition and subsequent planarization processing schemes, such as chemical mechanical planarization (CMP) processes. Where the patterned sacrificial hard mask layer 910 is substantially composed of tantalum, the liner material can be deposited prior to forming the conductive fill layer to prevent patterning of the sacrificial hard mask layer 910.

FIG. 9E illustrates the structure of FIG. 9D following exposure of interconnect 920. The patterned hard mask layer 908 and the patterned sacrificial layer 910 are removed to leave the interconnect lines 920 exposed, with underlying conductive vias in the patterned ILD layer 918. The wire end opening 924 is revealed. The wire end opening 924 provides a break in the grating pattern of the interconnect 920. In one embodiment, the patterned hard mask layer 908 and the patterned sacrificial layer 910 are removed using a selective wet etch process.

Figure 9F illustrates the structure of Figure 9E following the formation of the conformal patterned layer. A spacer material layer 926 is formed over and conformal to the grating pattern of interconnect 920. In one embodiment, atomic layer deposition (ALD) is used because of its fact that it is highly conformal and extremely accurate (eg, controlling the Dae's level). It should be understood that the wire end opening 924 is (in one embodiment) too short to effectively break the general grating pattern of the interconnect 920 for the formation of the conformal spacer material layer 926. In one such embodiment, the wire end opening 924 is filled with a spacer material layer 926 without disrupting the general grating pattern of the interconnect 920. In one embodiment, the spacer material layer 926 is deposited using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. In one embodiment, the spacer material layer 926 is a germanium layer, such as a polysilicon layer or an amorphous germanium layer. In certain such embodiments, a lining material is deposited on the interconnect 920 to prevent de-ization of the spacer material layer 926 prior to forming the ruthenium spacer material layer. In one embodiment, the wire end cut (plug) is less than or equal to twice the thickness of the spacer such that it is completely filled with a conformal dielectric material. If the tie is greater than 2 times the thickness, the seam may form and the metal may short the wires together during subsequent processing.

Figure 9G illustrates the structure of Figure 9F following the formation of spacer lines from the spacer material layer. In one embodiment, spacers 928 are formed along sidewalls of interconnect 920 using an anisotropic plasma etch process. In one embodiment, spacer material layer 926 remains in line end opening 924 to form a wire end footprint portion 930 for interconnect 920.

Figure 9H illustrates the structure of Figure 9G following the formation of the plug footprint. A plug footprint layer 932 is formed between the spacers 928 of adjacent interconnect lines 920. The plug footprint 932 is initially formed in a location where the second set of interconnect lines will ultimately be formed. In one embodiment, the plug footprint layer 932 is formed using a deposition and planarization process that confines the plug footprint 932 between the spacers 928.

Figure 9I illustrates the structure of Figure 9H following the patterning of the plug footprint. The plug footprint 932 is patterned to retain the plug footprint 934 in selected locations where the wire ends are ultimately formed. In one embodiment, a lithography resist mask exposure and etch process is used to form the plug footprint 934 with subsequent removal of the resist layer or stack.

Figure 9J illustrates the structure of Figure 9I following the second metallization process. Interconnect lines 936 are formed in the openings (second line openings) that are formed during the patterning of the plug footprints 932 that are used to form the plug footprints 934. Moreover, although the pattern omits separate processing operations, via openings (and ultimately conductive vias 938) may be formed in selected locations under conductive lines 936. This process results in a double patterning (two different via patterning operations) ILD layer 940, as depicted in Figure 9J.

In one embodiment, a metal fill process is performed to provide interconnect lines 936 and conductive vias 938. In one embodiment, the metal fill process is performed using metal deposition and subsequent planarization processing schemes, such as chemical mechanical planarization (CMP) processes. Where the spacers 928 are substantially composed of tantalum, the liner material can be deposited prior to forming the conductive fill layer to prevent the spacers 928 from deuterating.

It should be understood that in one embodiment, interconnects 936 (and corresponding conductive vias 938) are formed in a process that is later than the process used to fabricate interconnects 920 (and corresponding conductive vias 922). Medium, so interconnect 936 can be fabricated using a different material than that used to fabricate conductive line 920. In one such embodiment, the metallization layer ultimately includes alternating, distinct first and second conductive interconnects.

Figure 9K illustrates the structure of Figure 9J following exposure of the two sets of interconnect lines 920 and 936. Spacer 928, wire end occupancy portion 930, and plug footprint 934 are removed to leave exposed interconnect lines 920 and 936, individually having lower conductive vias 922 and 938 in patterned ILD layer 940. The wire end opening 942 is revealed. The wire end opening 942 provides a break in the grating pattern of the interconnect 920 and in the grating pattern of the interconnect 936. In one embodiment, the spacers 928, the wire end footprints 930, and the plug footprints 934 are removed using a selective wet etch process.

In one embodiment, the structure of Figure 9K represents the final metallization structure with an air gap architecture. That is, because interconnects 920 and 936 are ultimately exposed to the processes described herein, the air gap architecture is enabled. In another embodiment, because interconnects 920 and 936 are exposed to this stage in the process, there is an opportunity to remove the sidewall portions of the diffusion barrier layer of the interconnect. For example, in one embodiment, the removal of this diffusion barrier layer physically thins the conductive features of interconnects 920 and 936. In another embodiment, the resistance values of interconnects 920 and 936 are reduced when the sidewall portions of the diffusion barrier layer are removed. As indicated in Figure 9K, the feature sidewall portions 960 of interconnects 920 and 936 are exposed, while the portion 962 below the lines is no. As such, in one embodiment, the diffusion barrier layers of interconnects 920 and 936 are removed from sidewalls 960 of interconnects 920 and 936 but are not removed from regions 962 of interconnects 920 and 936. In a particular embodiment, the removal of the sidewall portion of the diffusion barrier layer involves the removal of Ta and/or TaN layers.

Thus, with reference to operations 9A-9K, in one embodiment, a method of fabricating a back end of line (BEOL) metallization layer includes forming a plurality of conductive lines 920/936 in a sacrificial material 928 formed over the substrate. Each of the plurality of conductive lines 920/936 includes a barrier layer formed along the bottom and sidewalls of the conductive fill layer. The sacrificial material 928 is then removed. The barrier layer is removed from the sidewalls of the conductive fill layer (eg, at location 960). In an embodiment, removing the barrier layer from the sidewall of the conductive filling layer comprises from the group consisting of Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au The sidewalls of the conductive fill layer of the material of the group of alloys thereof and the alloy remove the tantalum nitride or tantalum layer.

Figure 9L illustrates the structure of Figure 9K following the formation of the permanent ILD layer. An interlayer dielectric (ILD) layer 946/948 is formed between interconnect lines 920 and 936. ILD layer 946/948 includes a portion 946 between interconnects 920 and 936. The ILD layer 946/948 also includes a line end (or dielectric plug) portion 948 between the locations where the lines of interconnects 920 and 936 break.

Referring again to FIG. 9L, in one embodiment, semiconductor structure 999 includes a substrate (the lower ILD layer 940 is shown). The plurality of alternating first 920 and second 936 conductive line types are disposed along the same direction of their back end of line (BEOL) metallization layer disposed over the substrate. In one embodiment, as described in relation to FIG. 9K, the total composition of the first conductive line type 920 is different from the total composition of the second conductive line type 936. In certain such embodiments, the total composition of the first conductive line type 920 is substantially comprised of copper, and the total composition of the second conductive line type 936 is substantially selected from the group consisting of Al, Ti, Zr, Hf, A material consisting of groups of V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au, and alloys thereof, and vice versa. However, in another embodiment, the total composition of the first conductive line type 920 is the same as the total composition of the second conductive line type 936.

In one embodiment, the lines of the first conductive line type 920 are isolated by a pitch, and the lines of the second conductive line type 936 are isolated by the same pitch. In one embodiment, the plurality of alternating first and second conductive line types are disposed in an interlayer dielectric (ILD) layer 946/948. However, in another embodiment, the lines of the plurality of alternating first and second conductive line types 920/936 are separated by an air gap, as described in connection with Figure 9K.

In one embodiment, the plurality of alternating first and second conductive line types 920/936 lines each include a barrier layer disposed along the bottom and sidewalls of the line. However, in another embodiment, the plurality of alternating first and second conductive line types 920/936 lines each include a barrier layer disposed along a bottom 962 of the line and not along a sidewall 960 of the line, As described in the embodiment of Figure 9K. In one embodiment, one or more of the plurality of alternating first and second conductive line types 920/936 lines are connected to lower vias 922/938 that are connected to the underlying metallization layer of the semiconductor structure. In one embodiment, one or more of the plurality of alternating first and second conductive line types 920/936 are interrupted by dielectric plug 948.

The resulting structure 999 (or the air gap structure of Figure 9K), such as described in association with Figure 9L, can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, structure 999 of Figure 9L (or the structure of Figure 9K) may represent the last metal interconnect layer in the integrated circuit. It should be understood that the above-described process operations can be performed in an alternate order, not every operation needs to be performed and/or additional process operations can be performed. It should also be understood that the above examples have been concentrated on metal wires and plugs or wire ends. However, in other embodiments, a similar manner can be used to form via openings in the ILD layer.

In accordance with one or more embodiments of the present invention, a self-aligned DSA dual block or selective growth is described in a bottom-up manner. One or more embodiments described herein relate to self-aligned vias and plug patterns. The self-aligned morphology of the procedures described herein can be based on a directed self-polymerization (DSA) mechanism, as described in more detail below. However, it should be understood that its selective growth mechanism can be utilized to replace (or bind to) a DSA based approach. In one embodiment, the procedures described herein enable the implementation of self-aligned metallization for the fabrication of back-end process features. More specifically, one or more embodiments relate to a manner in which the underlying metal is used as a template to establish conductive vias and non-conductive spaces or interruptions (referred to as "plugs") between the metals.

Figures 10A-10M illustrate portions of an integrated circuit layer shown in various operations in a method of self-aligned via and metal patterning, in accordance with an embodiment of the present invention. In each of the illustrated operations, a plan view is shown on the left hand side and a corresponding cross-sectional view is displayed on the right hand side. These views will be referred to herein as corresponding cross-sectional views and plan views.

Figure 10A illustrates a plan view and corresponding cross-sectional view of a selection of a front metallization structure, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view selection (a), the starting structure 1000 includes a pattern of metal lines 1002 and interlayer dielectric lines (ILD) 1004. The starting structure 1000 can be patterned into a grating-like pattern with metal lines spaced at a constant pitch and having a constant width (eg, for a DSA embodiment, but not necessarily for a directional selective growth embodiment), as in Figure 10A The person depicted. The pattern, for example, can be manufactured by halving the pitch or reducing the pitch by a quarter. Some lines may be associated with the underlying vias, such as line 1002' shown in one of the cross-sectional views.

Referring again to FIG. 10A, alternatives (b)-(f) are discussed in which an additional film is formed on the surface of one of the metal lines 1002 and the interlayer dielectric line 1004 (eg, deposited, grown, or The case of leaving the artifacts left from the previous patterning process. In example (b), additional film 1006 is disposed over interlayer dielectric line 1004. In example (c), an additional film 1008 is disposed on the metal line 1002. In the example (d), the additional film 1006 is disposed on the interlayer dielectric line 1004, and the additional film 1008 is disposed on the metal line 1002. Moreover, although metal line 1002 and interlayer dielectric line 1004 are described as being coplanar in (a), in other embodiments, they may be non-coplanar. For example, in (e), metal line 1002 protrudes above interlayer dielectric line 1004. In the example (f), the metal line 1002 is recessed below the interlayer dielectric line 1004.

Referring again to examples (b)-(d), additional layers (eg, layers 1006 or 1008) can be used as hard masks (HM) or protective layers or used to enable selective growth as described below in relation to subsequent processing operations. And / or self-polymerization. These additional layers can also be used to protect the ILD from further processing. Furthermore, selectively depositing another material over the metal line may be advantageous for similar reasons. Referring again to examples (e) and (f), the ILD lines or wires can also be recessed by any combination of protective/HM materials on either or both surfaces. In summary, there are several options at this stage to prepare for the final underlying surface of the selective or directed self-polymerization process.

Figure 10B illustrates a plan view and corresponding cross-sectional view of the structure of Figure 10A following the formation of the interlayer dielectric (ILD) line 1010 over the structure of Figure 10A, in accordance with an embodiment of the present invention. Referring to the plan views taken along axes a-a' and c-c' and the corresponding cross-sectional views (a) and (c), the ILD line 1010 is formed in a grating structure perpendicular to the direction of the lower line 1004. in. In one embodiment, the cover film of the material of line 1010 is deposited by chemical vapor deposition or the like. In one embodiment, the cover film is then patterned using lithography and etching processes (which may involve, for example, spacer-based quadratic patterning (SBQP) or pitch reduction of one-quarter). It should be understood that the grating pattern of line 1010 can be fabricated by a number of methods, including EUV and/or EBDW lithography, directed self-polymerization, and the like. As will be described in more detail below, the subsequent metal layers will thus be patterned in an orthogonal direction relative to the previous metal layer because the grating of line 1010 is orthogonal to the direction of the underlying structure. In one embodiment, a single 193 nm lithography mask is used to align/align to the previous metal layer 1002 (eg, the grating of line 1010 is aligned with X to the previous layer "plug" pattern and aligned with Y Previous metal grating). Referring to the cross-sectional structures (b) and (d), the hard mask 1012 can be formed on the dielectric line 1010 or retained after patterning of the dielectric line 1010. A hard mask 1012 can be used to protect the line 1010 during subsequent patterning steps. As described in more detail below, the formation of the line 1010 in a raster pattern exposes the area of the previous metal line 1002 and the previous ILD line 1004 (or the corresponding hard mask layer on 1002/1004). The exposed areas correspond to all possible future via locations where the metal is exposed. In one embodiment, the previous layer of metal (eg, line 1002) is protected, marked, brushed, etc., at this point in the process stream.

Figure 10C illustrates a plan view and corresponding cross-sectional view of the structure of Figure 10B following selective separation of all potential via locations from all plug locations, in accordance with an embodiment of the present invention. The reference plane view and the corresponding cross-sectional views (a)-(d) are taken individually along the axes a-a', b-b', c-c' and d-d', continuing to the ILD line 1010. After formation, surface modification layer 1014 is formed over the exposed regions of lower ILD line 1004. In one embodiment, the surface modification layer 1014 is a dielectric layer. In one embodiment, the surface modification layer 1014 is formed by selective bottom-up growth. In one such embodiment, the bottom-up growth mode involves a directed self-polymerization (DSA) brush coating having a preferential focus on the lower ILD line 1004 or (alternatively) on the metal line 1002 (or at the expense of The layer of the sacrificial layer is disposed on or grown on the underlying metal or ILD material.

Figure 10D illustrates a plan view and corresponding cross-sectional view of the structure of Figure 10C following its addition to the exposed polymer of the underlying metal and ILD lines of Figure 10C, in accordance with an embodiment of the present invention. Reference plane view and corresponding cross-sectional views (a)-(d), taken individually along axes a-a', b-b', c-c' and d-d', underneath metal/ILD Oriented self-polymerization (DSA) or selective growth on the exposed portions of the 1002/1004 grating is used to form an intermediate line 1016 having alternating polymers or alternating polymer components between the ILD lines 1010. For example, as shown, polymer 1016A (or polymer component 1016A) is formed on or over the exposed portion of interlayer dielectric (ILD) line 1004 of Figure 10C, while polymer 1016B (or polymer component 1016B) is formed. On or above the exposed portion of metal line 1002 of Figure 10C. While polymer 1016A is formed on or over the surface modification layer 1014 described with respect to FIG. 10C (see cross-sectional views (b) and (d) of FIG. 10D), it should be understood that in other embodiments, surface modification Layer 1014 may be omitted or alternating polymers or alternating polymer components may alternatively be formed directly in the structure described in relation to Figure 10B.

Referring again to FIG. 10D, in one embodiment, once the surface of the underlying structure (eg, structure 1000 of FIG. 10A) has been prepared (eg, such as the structure of FIG. 10B or the structure of FIG. 10C) or is used directly, then one A 50-50 diblock copolymer, such as polystyrene-polymethyl methacrylate (PS-PMMA), is coated onto the substrate and annealed to drive self-polymerization, resulting in polymer 1016A of Figure 10D. / Polymer 1016B layer 1016. In this embodiment, the block copolymer is separated according to the underlying material exposed between the ILD lines 1010 using appropriate surface energy conditions. For example, in a particular embodiment, the polystyrene is selectively aligned to the exposed portion of the underlying metal line 1002 (or a corresponding metal line cap or hard mask material). At the same time, polymethyl methacrylate is selectively aligned to the exposed portion of the ILD line 1004 (or corresponding metal line cap or hard mask material).

Thus, in one embodiment, the underlying metal and ILD grid (as exposed between the ILD lines 1010) is regenerated from the block copolymer (BCP, ie, polymer 1016A/polymer 1016B). This may be especially true if the BCP pitch is comparable to the lower grating pitch. The polymer grid (Polymer 1016A/Polymer 1016B), in one embodiment, is tough for some small deviation from the proper alignment grid. For example, if a small plug effectively sets a material such as an oxide (where the proper alignment grid will have a metal), a properly aligned polymer 1016A/polymer 1016B grid can still be achieved. However, because the ILD line grating (in one embodiment) is an idealized grating structure, the metal without the ILD backbone is broken, so it may be necessary to make the ILD surface neutral because both types of polymer (1016A and 1016B) will In this example) it is exposed to the ILD-like material and only one type is exposed to the metal.

In one embodiment, the thickness of the coated polymer (polymer 1016A/1016B) is approximately the same (or slightly thicker) than the final thickness of the ILD ultimately formed in its location. In one embodiment, as described in more detail below, the polymer grid is not formed as an etch resist, but as a support for ultimately growing a permanent ILD layer around it. As such, the thickness of polymer 1016 (polymer 1016A/polymer 1016B) may be important because it can be used to define the final thickness of the subsequently formed permanent ILD layer. That is, in one embodiment, the polymer grating shown in Figure 10D is eventually replaced with an ILD grating of approximately the same thickness.

In one embodiment, as described above, the grid of polymer 1016A/polymer 1016B of Figure 10D is a block copolymer. In one embodiment, the block copolymer molecule is a polymer molecule formed from a chain of covalently bonded monomers. In the block copolymer, there are at least two different types of monomers, and these different types of monomers are primarily included in different blocks or adjacent sequences of the monomers. The block copolymer molecules shown include blocks of polymer 1016A and blocks of polymer 1016B. In one embodiment, the block of polymer 1016A primarily comprises a chain of covalently bonded monomer A (eg, AAAAA...), while the block of polymer 1016B primarily comprises a covalently linked monomer B. Chain (for example, BBBBB...). Monomers A and B can represent any of the different types of monomers used in the block copolymers known in the art. For example, monomer A may represent a monomer used to form polystyrene, while monomer B may represent a monomer used to form polymethyl methacrylate (PMMA), although the scope of the invention is not so limited. In other embodiments, there may be more than two blocks. Moreover, in other embodiments, each of the blocks may comprise a different type of monomer (eg, each block may itself be a copolymer). In one embodiment, the block of polymer 1016A and the block of polymer 1016B are covalently joined together. The blocks of polymer 1016A and the blocks of polymer 1016B can be about the same length, or one block can be significantly longer than the other.

Generally, blocks of block copolymers (e.g., blocks of polymer 1016A and blocks of polymer 1016B) can each have different chemical properties. For example, one of the blocks can be relatively hydrophobic (eg, water repellent) and the other can be relatively hydrophilic (water absorbing). At least conceptually, one of the blocks may be relatively similar to oil and the other block may be relatively similar to water. These differences in the chemical properties between the different blocks of the polymer (whether hydrophilic-hydrophobic differences or others) may cause self-polymerization of the block copolymer molecules. For example, self-polymerization can be separated according to the microphase of the polymer block. Conceptually, this can be similar to the phase separation of oil and water that it usually cannot mix. Similarly, the difference in hydrophilicity between polymer blocks (eg, one block is relatively hydrophobic while the other block is relatively hydrophilic) may result in a substantially similar microphase separation where different polymers Blocks try to "separate" each other because they don't like each other chemically.

However, in one embodiment, because the polymer blocks are covalently joined to each other, they are not completely separated on a macroscopic scale. Conversely, a given type of polymer block tends to separate or aggregate with polymer blocks of other molecules of the same type in a very small (e.g., nanometer size) region or phase. The particular size and shape of the zone or microphase generally depends, at least in part, on the relative length of the polymer block. In one embodiment, via an example (as shown in FIG. 10D), in a two-block copolymer, if the blocks are approximately the same length, alternating grids of polymer 1016A and polymer 1016B are produced. Grid pattern. In another embodiment (not shown), in a two-block copolymer, a columnar structure can be formed if one of the blocks is longer than the other but not too much longer than the other. In a columnar structure, the block copolymer molecules can be separated from the microphase into its shorter polymer block inside the column and its longer polymer block extending away from the column and surrounding the column. For example, if the block of polymer 1016A is longer (but not too long) than the block of polymer 1016B, a columnar structure can be formed in which many of the block copolymer molecules are aligned with the shorter blocks of polymer 1016B. Precisely, a columnar structure surrounded by a phase having a longer block of polymer 1016A is formed. When this occurs in a region of sufficient size, a two-dimensional array of generally hexagonal packed columnar structures can be formed.

In one embodiment, the polymer 1016A/polymer 1016B grating is first coated as an unpolymerized block copolymer layer portion comprising, for example, a block copolymer coated by a brush or other coating process. material. The unpolymerized form refers to the case where the block copolymer has not been substantially phase separated and/or self-polymerized to form nanoparticles (at the time of deposition). In this unpolymerized form, the block polymer molecules are relatively highly randomized, having relatively highly randomly oriented and disposed different polymer blocks, which are opposite to the polymeric blocks discussed in connection with the resulting structure of Figure 10D. The copolymer layer portion. The unpolymerized block copolymer layer portion can be coated in a number of different ways. For example, the block copolymer can be dissolved in a solvent and then spin coated onto the surface. Alternatively, the unpolymerized block copolymer can be spray coated, dip coated, dip coated, or otherwise coated or coated onto the surface. Other ways of coating the block copolymer, as well as other means known in the art for applying similar organic coatings, can potentially be used. Next, the unpolymerized layer can form a portion of the polymeric block copolymer layer, for example, by microphase separation and/or self-polymerization of the unpolymerized block copolymer layer portion. Microphase separation and/or self-polymerization occurs through reconfiguration and/or relocation of the block copolymer molecules, and in particular, reconfiguration and/or relocation of different polymer blocks of the block copolymer molecules.

In this embodiment, the annealing treatment can be applied to the unpolymerized block copolymer to initiate, accelerate, increase, or enhance the quality of the microphase separation and/or self-polymerization. In certain embodiments, the annealing treatment can include a treatment that is operable to increase the temperature of the block copolymer. An example of such a treatment is baking the layer, heating the layer in an oven or above a heat lamp, applying infrared radiation to the layer, or applying heat to the layer or increasing the temperature of the layer. The desired increase in temperature will generally be sufficient to significantly accelerate microphase separation and/or self-polymerization of the block polymer without damaging any other important materials or structures of the block copolymer or integrated circuit substrate. Generally, the heating range can be from about 50 ° C to about 300 ° C, or from 75 ° C to about 250 ° C, but does not exceed the thermal degradation limit of the block copolymer or integrated circuit substrate. Heating or annealing can assist in providing energy to the block copolymer molecules to make them more mobile/elastic to increase the rate of microphase separation and/or to enhance the quality of the microphase separation. This microphase separation or reconfiguration/relocation of the block copolymer molecules can result in self-polymerization to form a very small (e.g., nanoscale) structure. Self-polymerization can occur under the influence of surface energy, molecular affinity, and other surface-related and chemically related forces.

In any event, in certain embodiments, the self-polymerization of the block copolymer (whether or not based on hydrophobic-hydrophilic differences) can be used to form very small periodic structures (eg, precisely spaced nanoscale structures or line). In some embodiments, it can be used to form nanoscale lines or other nanoscale structures that can ultimately be used to form vias and openings. In certain embodiments, the oriented self-polymerization of the block copolymer can be used to form vias that are self-aligned with the interconnect, as described in more detail below.

Referring again to FIG. 10D, in one embodiment, for the DSA process, the growth process can be affected by the sidewalls of the material of the ILD line 1010, except from the direction of the lower ILD/metal 1004/1002 surface. As such, in one embodiment, the DSA is controlled by pattern epitaxy (from the sidewall of line 1010) and chemical epitaxy (the surface characteristics are exposed from below). The physical and chemical limitations of the DSA process can significantly assist in the process, from a defect perspective. The resulting polymer 1016A/1016B has less freedom and is completely trapped in all directions, by chemistry (eg, by means of, for example, brushing the underlying ILD or wire, or surface modification) and Physical (eg, trenches formed between ILD lines 1010).

In an alternate embodiment, a selective growth process is used in place of the DSA approach. Figure 10E illustrates a cross-sectional view of the structure of Figure 10B following the selection of the exposed portions of the underlying metal and ILD lines, in accordance with another embodiment of the present invention. Referring to FIG. 10E, a first material type 1090 is grown over the exposed portion of the lower ILD line 1004. A second (different) material type 1092 is grown over the exposed portion of the underlying metal line 1002. In one embodiment, selective growth is achieved by a dep-etch-dep-etch approach for each of the first and second materials, resulting in each of the materials The plural layers of the person, as depicted in Figure 10E. This approach may be desirable with respect to conventional selective growth techniques that form a "mushroom top" shaped film. The mushroom apex growth tendency can be reduced by an alternate dep-etch-dep-etch. In another embodiment, the film is selectively deposited on the metal, successively deposited on the ILD with different films (or vice versa), and repeated several times to create a sandwich-like stack. In another embodiment, the two materials are simultaneously grown in a reaction chamber (e.g., by a CVD pattern process) that is selectively grown on each exposed region of the underlying substrate.

Figure 10F illustrates a plan view and corresponding cross-sectional view of the structure of Figure 10D following removal of a polymer, in accordance with an embodiment of the present invention. Reference plane view and corresponding cross-sectional views (a)-(d), taken individually along axes a-a', b-b', c-c' and d-d', polymer or polymer Portion 1016A is removed to re-expose ILD line 1004 (or a hard mask or cap layer formed on ILD line 1004) while polymer or polymer portion 1016B is retained over metal line 1002. In one embodiment, a deep ultraviolet (DUV) exposure followed by wet etching or selective dry etching is used to selectively remove polymer 1016A. It should be understood that instead of the first removal of the polymer from the ILD line 1004 (as shown), the removal from the metal line 1002 may alternatively be performed first. Alternatively, a dielectric film is selectively grown over the zone and the hybrid stent is not used.

Figure 10G illustrates a plan view and corresponding cross-sectional view of the structure of Figure 10F following the formation of the ILD material in a position opened during removal of a polymer, in accordance with an embodiment of the present invention. The reference plane view and the corresponding cross-sectional views (a)-(d) are taken individually along the axes a-a', b-b', c-c' and d-d', and the lower ILD line 1004 The exposed areas are filled with a permanent interlayer dielectric (ILD) layer 1018. As such, the open space between all possible via locations is filled with an ILD layer 1018 that includes a hard mask layer 1020 disposed thereon, such as a 10G plan view and a cross-sectional view (b) And the person depicted in (d). It should be understood that the material of the ILD layer 1018 need not be the same material as the ILD line 1010. In one embodiment, the ILD layer 1018 is formed by a deposition and polishing process. In the case where the ILD layer 1018 is formed with the accompanying hard mask layer 1020, a special ILD fill material can be used (eg, it fills the pores/grooves of the ILD polymer encapsulated nanoparticle). In this case, a polishing operation may not be required.

Referring again to FIG. 10G, in one embodiment, the resulting structure includes a uniform ILD structure (ILD line 1010 + ILD layer 1018), with all possible plug locations covered with a hard mask 1020 and all possible vias located at polymer 1016B In the area. In this embodiment, the ILD line 1010 and the ILD layer 1018 are composed of the same material. In another such embodiment, the ILD line 1010 and the ILD layer 1018 are comprised of different ILD materials. In either case, in a particular embodiment, a distinction such as a seam between the ILD line 1010 and the material of the ILD layer 1018 can be observed in the final structure. An example seam 1099 is shown in Figure 10G for illustration.

Figure 10H illustrates a plan view and corresponding cross-sectional view of the structure of Figure 10G following the patterning of vias, in accordance with an embodiment of the present invention. The reference plane view and the corresponding cross-sectional views (a)-(d) are taken individually along the axes a-a', b-b', c-c' and d-d', the through-hole positions 1022A, 1022B and 1022C are opened by removal of polymer 1016B in the selected location. In one embodiment, selective via location formation is accomplished using lithography techniques. In one such embodiment, polymer 1016B is integrally removed to ash and refilled with a photoresist. The photoresist can be highly sensitive and have large acid diffusion and positive deprotection or cross-linking (depending on the resist hue) since the latent image is from the ILD (eg, by the ILD line 1010 and the ILD layer 1018). Limited to two directions. The resist acts as a digital switch for "on" or "off" depending on whether a via is required in a particular location. Ideally, the photoresist can be used to fill only the holes without spilling. In one embodiment, via locations 1022A, 1022B, and 1022C are completely limited to the process such that their line edge or width roughness (LWR) and line collapse and/or reflection are mitigated (if not eliminated). In one embodiment, the low dose is used with EUV/EBDW and significantly increases the operating rate. In one embodiment, an additional advantage of utilizing EBDW is that there is only one single type/size that increases the rate of operation by significantly reducing the number of apertures required and reducing the dose to be delivered. In the case where 193 nm immersion lithography is used, in one embodiment, the process flow limits the via position to two directions such that the size of the via that is actually patterned is the actual via on the wafer. Double the size (for example, assuming a 1:1 line/space pattern). Alternatively, the via location may be selected for anti-tone, where the vias that need to be retained are protected with photoresist and the remaining locations are removed and later filled with ILD. This approach allows for a single metal fill/polish process at the end of the patterning process rather than two separate metal deposition steps.

Figure 10I illustrates a plan view and corresponding cross-sectional view of the structure of Figure 10H following the formation of the vias, in accordance with an embodiment of the present invention. The reference plane view and the corresponding cross-sectional views (a)-(d) are taken individually along the axes a-a', b-b', c-c' and d-d', the through-hole positions 1022A, 1022B and 1022C are individually filled with metal to form vias 1024A, 1024B, and 1024C. In one embodiment, via locations 1022A, 1022B, and 1022C are filled with excess metal and subsequent polishing operations are performed. However, in another embodiment, the via locations 1022A, 1022B, and 1022C are filled without metal overfill and the polishing operation is omitted. It should be understood that the via fill shown in FIG. 10I can be skipped in the reverse tone via selection mode.

Figure 10J illustrates a plan view and corresponding cross-sectional view of the structure of Figure 10I following the removal of the second polymer and replacement with the ILD material, in accordance with an embodiment of the present invention. The reference plane view and the corresponding cross-sectional views (a)-(d) are taken individually along the axes a-a', b-b', c-c' and d-d', leaving the remaining polymer Or polymer portion 1016B (eg, where the via location has not been selected) is removed to re-expose metal line 1002. Thereafter, ILD layer 1026 is formed in a location where the remaining polymer or polymer portion 1016B is removed, as depicted in Figure 10J.

Referring again to FIG. 10J, in one embodiment, the resulting structure includes a uniform ILD structure (ILD line 1010 + ILD layer 1018 + ILD layer 1026), with all possible plug locations covered with a hard mask 1020. In this embodiment, the ILD line 1010, the ILD layer 1018, and the ILD layer 1026 are comprised of the same material. In another embodiment, the ILD line 1010, the ILD layer 1018, and the ILD layer 1026 are both composed of the same material and the third portion is composed of different ILD materials. In still another embodiment, the ILD line 1010, the ILD layer 1018, and the ILD layer 1026 are each composed of ILD materials that are different from each other. In either case, in a particular embodiment, a distinction such as a seam between the ILD line 1010 and the material of the ILD layer 1026 can be observed in the final structure. An example seam 1097 is shown in Figure 10J for illustration. Similarly, differences such as seams between the material of the ILD layer 1018 and the ILD layer 1026 can be observed in the final structure. An example seam 1098 is shown in Figure 10J for illustration.

Figure 10K illustrates a plan view and corresponding cross-sectional view of the structure of Figure 10J following the patterning of the resist or mask in the selected plug location, in accordance with an embodiment of the present invention. Referring to the plan view taken along axes a-a' and b-b' and the corresponding cross-sectional views (a) and (b), the plug positions 1028A, 1028B and 1028C are formed by masking or resisting The etchant layer is retained above those locations. This retention patterning can be referred to as metal end-to-end lithography patterning where the plug location is determined to be where it is needed for the break in the subsequently formed metal line. It should be understood that because the plug position can only be in those locations where the ILD layer 1018 / hard mask 1020 is placed, the plug can occur over the previous layer ILD line 1004. In one embodiment, patterning is achieved by using lithography operations (eg, EUV, EBDW, or immersion 193 nm). In one embodiment, the process illustrated in Figure 10K demonstrates the use of a positive tone patterning process in which the area required for the space between the metals is retained. It should be understood that in another embodiment, it is also possible to alternatively open the aperture and reverse the hue of the process.

Figure 10L illustrates a plan view and corresponding cross-sectional view of the structure of Figure 10K following the removal of the hard mask and the depression of the ILD layer, in accordance with an embodiment of the present invention. The reference plan view and corresponding cross-sectional views (a)-(d) are taken individually along the axes a-a' and b-b', the hard mask 1020 is removed and the ILD layer 1018 and the ILD layer 1026 are removed. The recessed ILD layer 1018' and the recessed ILD layer 1026' are individually recessed by etching the layers below their original uppermost surface. It should be understood that the depressions of ILD layer 1018 and ILD layer 1026 are performed without etching or recessing ILD line 1010. Selectivity can be achieved by using a hard mask layer 1012 on the ILD line (as depicted in cross-sectional views (a) and (b)). Alternatively, where the ILD line 1010 is composed of ILD material that is different from the material of the ILD layer 1018 and the ILD layer 1026, selective etching can be used even in the absence of the hard mask 1012. The depressions of ILD layer 1018 and ILD layer 1026 are used to provide a location to the second order metal line, as isolated by ILD line 1010, as described below. The extent or depth of the depression (in one embodiment) is selected based on the desired final thickness of the metal lines formed thereon. It should be understood that the ILD layer 1018 in the plug locations 1028A, 1028B, and 1028C is not recessed.

Figure 10M illustrates a plan view and corresponding cross-sectional view of the structure of Figure 10L following the formation of the metal lines, in accordance with an embodiment of the present invention. Reference plane views and corresponding cross-sectional views (a), (b) and (c) are taken individually along axes a-a', b-b' and b-b' for forming metal interconnections The metal of the wire is conformally formed over the structure of Figure 10L. The metal is then planarized (e.g., by CMP) to provide metal lines 1030 that are limited to locations above the recessed ILD layer 1018' and the recessed ILD layer 1026'. The metal line 1030 is coupled to the underlying metal line 1002 through a predetermined via location 1024A, 1024B, and 1024C (1024B is shown in cross-sectional view (c); note: for illustrative purposes, in a cross-sectional view ( Another via 1032 in b) is depicted as directly abutting plug 1028B, even if this is inconsistent with the previous pattern). Metal lines 1030 are isolated from one another by ILD lines 1010 and are interrupted or separated by retained plugs 1028A, 1028B, and 1028C. Any hard mask remaining on the plug location and/or on the ILD line 1010 can be removed in this portion of the process flow, as depicted in Figure 10M. The deposition and planarization process of the metal used to form metal lines 1030 (e.g., copper and associated barrier and seed layers) can be typically used in standard back end of line (BEOL) single or dual damascene processors. In an embodiment, in a subsequent manufacturing operation, the ILD line 1010 can be removed to provide an air gap between the resulting metal lines 1030.

The structure of Figure 10M can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 10M can represent the last metal interconnect layer in the integrated circuit. It should be understood that the above-described process operations can be performed in an alternate order, not every operation needs to be performed and/or additional process operations can be performed. Furthermore, although the above process flow is focused on directed self-polymerization (DSA) applications, the selective growth process can alternatively be used in one or more locations of the process flow. In any case, the resulting structure enables the fabrication of vias that are directly concentrated on the underlying metal lines. That is, the vias can have a wider, narrower, or the same thickness than the underlying metal lines, for example, due to imperfect selective etch processing. However, in one embodiment, the center of the via is directly aligned (matched) with the center of the metal line. As such, in one embodiment, the deviation from conventional lithography/dual damascene patterning (which is otherwise tolerated) will not be a factor in the resulting structure described herein.

One or more embodiments described herein relate to front layer self-aligned vias and plug patterns. The self-aligned morphology of the procedures described herein can be based on a directed self-polymerization (DSA) mechanism, as described in more detail below. However, it should be understood that selective growth mechanisms can be utilized to replace (or bind to) a DSA based approach. In one embodiment, the procedures described herein enable the implementation of self-aligned metallization for the fabrication of back-end process features.

Figures 11A-11M illustrate portions of an integrated circuit layer that illustrate various operations in a method of self-aligned vias and metal patterning, in accordance with an embodiment of the present invention. In each of the illustrated operations, a plan view is shown on the left hand side and a corresponding cross-sectional view is displayed on the right hand side. These views will be referred to herein as corresponding cross-sectional views and plan views.

Figure 11A illustrates a plan view and corresponding cross-sectional view of a selection of a front metallization structure, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view selection (a), the starting structure 1100 includes a pattern of metal lines 1102 and interlayer dielectric lines (ILD) 1104. The starting structure 1100 can be patterned into a grating-like pattern with metal lines spaced at a constant pitch and having a constant width, as depicted in Figure 11A, if a self-polymerizing material would be used. If a directional selective growth technique is used, the lower pattern need not be a single pitch or width. The pattern, for example, can be manufactured by halving the pitch or reducing the pitch by a quarter. Certain lines may be associated with the underlying vias, such as line 1102' shown in one of the cross-sectional views.

Referring again to FIG. 11A, alternatives (b)-(f) are discussed in which an additional film is formed on the surface of one of the metal lines 1102 and the interlayer dielectric lines 1104 (eg, deposited, grown, or The case of leaving the artifacts left from the previous patterning process. In example (b), additional film 1106 is disposed over interlayer dielectric line 1104. In example (c), additional film 1108 is disposed on metal line 1102. In the example (d), the additional film 1106 is disposed on the interlayer dielectric line 1104, and the additional film 1108 is disposed on the metal line 1102. Moreover, although metal line 1102 and interlayer dielectric line 1104 are described as being coplanar in (a), in other embodiments they may be non-coplanar. For example, in (e), metal line 1102 protrudes above interlayer dielectric line 1104. In the example (f), the metal line 1102 is recessed below the interlayer dielectric line 1104.

Referring again to examples (b)-(d), additional layers (eg, layer 1106 or 1108) can be used as a hard mask (HM) or protective layer or used to enable selective growth as described below in relation to subsequent processing operations. And / or self-polymerization. These additional layers can also be used to protect the ILD from further processing. Furthermore, selectively depositing another material over the metal line may be advantageous for similar reasons. Referring again to examples (e) and (f), the ILD lines or wires can also be recessed by any combination of protective/HM materials on either or both surfaces. In summary, there are several options at this stage to prepare for the final underlying surface of the selective or directed self-polymerization process.

Figure 11B illustrates a plan view and corresponding cross-sectional view of the selection of directed self-polymerization (DSA) growth on a lower metal/ILD grating (e.g., on a structure such as that shown in Figure 11A), in accordance with an implementation of the present invention example. Referring to plan view, structure 1110 includes a layer having alternating polymers or alternating polymer components. For example, as shown, polymer A (or polymer component A) is formed on or above the interlayer dielectric (ILD) line 1104 of Figure 11A, while polymer B (or polymer component B) is formed in Figure 11A. On or above the metal line 1102. Referring to the cross-sectional view, in (a), polymer A (or polymer component A) is formed on ILD line 1104, and polymer B (or polymer component B) is formed on metal line 1102. In (b), polymer A (or polymer component A) is formed on additional film 1106 formed on ILD line 1104, while polymer B (or polymer component B) is formed on metal line 1102. In (c), polymer A (or polymer component A) is formed on ILD line 1104, while polymer B (or polymer component B) is formed on additional film 1108 formed on metal line 1102. In (d), polymer A (or polymer component A) is formed on additional film 1106 formed on ILD line 1104, while polymer B (or polymer component B) is formed on metal line 1102. An additional film 1108 is formed.

Referring again to Figure 11B, in one embodiment, once the surface of the underlying structure (e.g., structure 1100 of Figure 11A) has been prepared, a 50-50 dual block copolymer, such as polystyrene-polymethacrylate The ester (PS-PMMA), coated on the substrate and annealed to drive self-polymerization, results in a polymer A/polymer B layer of structure 1110 of Figure 11B. In this embodiment, the block copolymer is separated according to the underlying material of structure 1100 using suitable surface energy conditions. For example, in a particular embodiment, the polystyrene is selectively aligned to the underlying metal line 1102 (or a corresponding metal line cap or hard mask material). At the same time, polymethyl methacrylate is selectively aligned to the ILD line 1104 (or a corresponding metal wire cap or hard mask material).

Thus, in one embodiment, the underlying metal and ILD grids are regenerated from the block copolymer (BCP, ie, polymer A/polymer B). This may be especially true if the BCP pitch is comparable to the lower grating pitch. The polymer grid (Polymer A/Polymer B), in one embodiment, is tough for a small amount of deviation from a properly aligned grid. For example, if a small plug effectively sets a material such as an oxide (where a very properly aligned grid would have a metal), a very properly aligned polymer A/polymer B grid can still be achieved. However, because the ILD line grating (in one embodiment) is an idealized grating structure, the metal without the ILD backbone is broken, so it may be necessary to make the ILD surface neutral because both types of polymers (A and B) will In this example) it is exposed to the ILD-like material and only one type is exposed to the metal.

In one embodiment, the thickness of the coated polymer (A/B) is about the same as (or slightly thicker than) the final thickness of the ILD that is ultimately formed in its location. In one embodiment, as described in more detail below, the polymer grid is not formed as an etch resist, but as a support for ultimately growing a permanent ILD layer around it. As such, the thickness of the polymer (A/B) may be important because it can be used to define the final thickness of the subsequently formed permanent ILD layer. That is, in one embodiment, the polymer grating shown in Figure 11B is ultimately replaced with an ILD grating of approximately the same thickness.

In one embodiment, as described above, the grid of polymer A/polymer B of FIG. 2 is a block copolymer. In one such embodiment, the block copolymer molecule is one such as described above in association with Figure 10D. In one embodiment, via the first example (as shown in FIG. 11B), in a two-block copolymer, if the blocks are approximately the same length, alternating polymer A lines and polymer B lines are produced. Grid-like pattern. In another embodiment, via the second example (not shown), in the two-block copolymer, if one of the blocks is longer than the other, but does not grow too much, a vertical columnar structure can be formed. . In a columnar structure, the block copolymer molecules can be separated from the microphase into its shorter polymer block inside the column and its longer polymer block extending away from the column and surrounding the column. For example, if the block of polymer A is longer (but not too long) than the block of polymer B, a columnar structure can be formed in which many of the block copolymer molecules are aligned with their shorter blocks of polymer B. Forming a columnar structure surrounded by a phase having a longer block of polymer A. When this occurs in a region of sufficient size, a two-dimensional array of generally hexagonal packed columnar structures can be formed.

In one embodiment, the polymer A/polymer B grating is first coated as an unpolymerized block copolymer layer portion comprising, for example, a block copolymer coated by a brush or other coating process. Materials, as described above in connection with Figure 10D. In this embodiment, the annealing treatment can be applied to the unpolymerized block copolymer to initiate, accelerate, increase its quality, or enhance microphase separation and/or self-polymerization, as described above in connection with FIG. 10D.

Figure 11C illustrates a plan view and corresponding cross-sectional view of the structure of Figure 11B following removal of a polymer, in accordance with an embodiment of the present invention. Referring to Figure 11C, polymer B is removed to re-expose metal line 1102 (or a hard mask or capping layer formed on metal line 1102) while polymer A is retained in ILD line 1104 to form structure 1112. In one embodiment, a deep ultraviolet (DUV) exposure followed by wet etching or selective dry etching is used to selectively remove polymer B. It will be understood that instead of the first removal of the polymer from the metal line 1102 (as shown), the removal from the ILD line may alternatively be performed first.

Figure 11D illustrates a plan view and corresponding cross-sectional view of the structure of Figure 11C following the formation of a layer of sacrificial material over metal line 1102, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (b), structure 1114 includes a sacrificial B layer formed between polymer A on or over metal line 1102 and over or over ILD line 1104. In one embodiment, referring to cross-sectional view (a), the low temperature deposition fills the trench between the polymer A lines, for example, as an oxide (eg, TiO _x ) or other sacrificial material as a conformal Layer 1116. The conformal layer 1116 is then confined to the region above the metal line 1102 by a dry etch or chemical mechanical planarization (CMP) process. The resulting layer is referred to herein as Sacrificial B because, in certain embodiments, its material is ultimately replaced with a permanent ILD material. However, in other embodiments, it will be appreciated that its permanent ILD material may alternatively be formed at this stage. In the case of a sacrificial material, in one embodiment, the sacrificial material has the necessary deposition properties, thermal stability, and etch selectivity for other materials used in the process.

Figure 11E illustrates a plan view and corresponding cross-sectional view of the structure of Figure 11D following replacement of polymer A with a permanent interlayer dielectric (ILD) material, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (c), structure 1118 includes a permanent interlayer dielectric (ILD) line 1120 on or over ILD line 1104 and between the sacrificial B material lines. In one embodiment, the polymer A line is removed as depicted in cross-sectional view (a). Next, referring to cross-sectional view (b), ILD material layer 1119 is conformally formed over the resulting structure. The conformal layer 1119 is then confined to the region above the ILD line 1104 by a dry etch or chemical mechanical planarization (CMP) process. In one embodiment, structure 1118 effectively replaces the polymer (A/B) grating of FIG. 11B with a very thick material grating (eg, permanent ILD 1120 and sacrificial B), the grating of the extremely thick material and the underlying metal grating Symmetric and aligned with the underlying grating. Two different materials can be used to ultimately define the possible locations of the plugs and vias, as described in more detail below.

Figure 11F illustrates a plan view and corresponding cross-sectional view of the structure of Figure 11E following the formation of a selective hard mask on a permanent ILD line, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (c), structure 1122 includes a hard mask layer 1124 formed over a permanent interlayer dielectric (ILD) line 1120. In one embodiment, referring to cross-sectional view (c), a selective growth process is used to form hard mask layer 1124 to a surface that is limited to permanent ILD line 1120. In another embodiment, the conformal material layer 1123 is first formed (cross-sectional view (a)) onto a structure having recessed permanent ILD lines 1120. The conformal layer 1123 then undergoes a timed etch and/or CMP process to form a hard mask layer 1124 (cross-sectional view (b)). In the latter case, the ILD line 1120 is recessed relative to the sacrificial B material, and then a non-conformal (planarized) hard mask 1123 is deposited on the resulting grating. Material 1123 is thinner on the sacrificial B line than on the recessed ILD line 1120 such that a hard mask timing etching or polishing operation selectively removes material 1123 from the sacrificial B material.

Figure 11G illustrates a plan view and corresponding cross-sectional view of the structure of Figure 11F following the removal of the sacrificial B line and replacement with the permanent ILD line 1128, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view (c), structure 1126 includes a permanent ILD line 1128 that replaces the sacrificial B line of FIG. 11F, that is, over metal line 1102 and aligned with metal line 1102. In one embodiment, the sacrificial B material is removed (cross-sectional view (a)) and replaced with a permanent ILD line 1128 (cross-sectional view (c)), for example, by deposition of conformal layers and subsequent Timing etching or CMP processing (cross-sectional view (b)). In one embodiment, the resulting structure 1126 includes a uniform ILD material (permanent ILD line 1120 + permanent ILD line 1128) in which all possible plug locations are covered with a hard mask 1124 and all possible vias are located on the exposed permanent ILD line In the area of 1128. In this embodiment, the permanent ILD line 1120 and the permanent ILD line 1128 are comprised of the same material. In another such embodiment, the permanent ILD line 1120 and the permanent ILD line 1128 are comprised of different ILD materials. In either case, in a particular embodiment, a distinction such as a seam between the material of the permanent ILD line 1120 and the permanent ILD line 1128 can be observed in the final structure 1126. Example seam 1199 is shown in Figure 11F for illustration.

Figure 11H illustrates a plan view and corresponding cross-sectional view of the structure of Figure 11G following the trench formation (e.g., grating definition), in accordance with an embodiment of the present invention. The reference plane view and the corresponding cross-sectional views (a)-(d) are taken individually along the axes a-a', b-b', c-c' and d-d', in Figure 11G A trench 1132 is formed in the structure to define a grating in the structure 1130 (perpendicular to the grating of FIG. 11G) to ultimately define a region between the patterns of the metal lines. In one embodiment, the trenches 1132 are formed by patterning and etching the grating pattern into a sacrificial grating of an earlier structure. In one embodiment, a grid is formed to effectively define all of the spacing between the finally formed metal lines, along with the location of all of the plugs and vias. In one embodiment, trench 1132 reveals the location of lower ILD line 1104 and metal line 1102.

Figure 11I illustrates a plan view and corresponding cross-sectional view of the structure of Figure 11H following the formation of the sacrificial material grating in the trench of Figure 11H, in accordance with an embodiment of the present invention. Reference plane view and corresponding cross-sectional views (a)-(d), taken individually along axes a-a', b-b', c-c' and d-d', material layer 1134 (which An interlayer dielectric layer or a sacrificial layer is formed in the trench 1132 of the structure of FIG. 11H. In one embodiment, material layer 1134 is formed by conformal deposition using a permanent ILD material or sacrificial layer and subsequent timing etching or CMP (eg, if an air gap is to be fabricated, it can be removed later) . In the former case, material layer 1134 eventually becomes an ILD material between the subsequently formed parallel metal lines on the same metal layer. In the latter case, the material can be referred to as a sacrificial C material as shown. In one embodiment, material layer 1134 has high etch selectivity to other ILD materials and to hard mask layer 1128.

Figure 11J illustrates a plan view and corresponding cross-sectional view of the structure of Figure 11I following the formation and patterning of the mask and subsequent etching of the via locations, in accordance with an embodiment of the present invention. The reference plan view and corresponding cross-sectional views (a) and (b) are taken individually along the axes a-a' and b-b', and the mask 1136 is formed on the structure of Figure 11I. The mask is patterned, for example, by a lithography process to have openings 1137 formed therein. In one embodiment, the opening is determined according to the desired patterning of the vias. That is, at this stage, all possible vias and plugs (eg, as placeholders) have been patterned and self-aligned to the upper and lower final metal layers. Here, a subset of vias and plug locations are selected for retention, such as to etch the location of the metal lines. In one embodiment, an ArF or EUV or electron beam resist is used to cut or select the via to be etched, i.e., at the exposed portion of the metal line 1102. It should be understood that the hard mask 1124 and the material layer 1134 act as actual etch masks that determine the shape and location of the vias. The mask 1136 acts only to block the remaining vias from being etched. As such, the tolerance for the size of the opening 1137 is relaxed because of the selected via location (ie, the portion of the opening 1137 directly above the exposed portion of the metal line 1102) (eg, the hard mask 1124 and Material layer 1134) is resistant to etching processes used to remove ILD lines 1128 over selected portions of metal lines 1102 for fabrication of the final vias. In one embodiment, the mask 1136 is comprised of a topographical masking portion 1136C, an anti-reflective coating (ARC) layer 1136B, and a photoresist layer 1136A. In a particular such embodiment, the terrain shield portion 136C is a carbon hard mask (CHM) layer and the anti-reflective coating 136B is a 矽ARC layer.

Figure 11K illustrates a plan view and corresponding cross-sectional view of the structure of Figure 11J following the mask and hard mask removal and subsequent plug patterning and etching, in accordance with an embodiment of the present invention. The reference plan view and corresponding cross-sectional views (a) and (b) are taken individually along the axes a-a' and b-b', and the mask 1136 shown in Figure 11J is patterned at the through-hole position. It was removed later. Thereafter, a second mask 1138 is formed and patterned to cover the selected plug locations. Specifically, in one embodiment, and as depicted in Figure 11K, portions of the hard mask 1124 are retained in a position in which the plug will be finally formed. That is, at this stage, there are all possible plugs in the form of hard mask plugs. The patterning operation of Figure 11K acts to remove all of the hard mask 1124 portions except those selected for plug retention. The patterning effectively exposes substantially the upper portions of the ILD lines 1120 and 1128, for example, as a unified dielectric layer.

Figure 11L illustrates a plan view and corresponding cross-sectional view of the structure of Figure 11K following the mask removal and metal line trench etch, in accordance with an embodiment of the present invention. The reference plan view and corresponding cross-sectional views (a) and (b) are taken individually along the axes a-a' and b-b', and the mask 1138 shown in Figure 11K is patterned at the through-hole position. It was removed later. Thereafter, partial etching of the exposed portions of ILD lines 1120 and 1128 is performed to provide recessed ILD lines 1120' and 1128'. The degree of dishing can be based on a timed etch process, such as the depth of the desired wire thickness. Portions of the ILD line 1120 protected by the portion of the remaining hard mask 1124 are not recessed by etching, as shown in Figure 11L. Additionally, material layer 1134 (which may be a sacrificial material or a permanent ILD material) is also not etched or recessed. It should be understood that the process illustrated in FIG. 11L does not require lithographic operation because the via location (on the exposed portion of metal line 1102) has been etched and plugged (in the location where hard mask 1124 is retained).

Figure 11M illustrates a plan view and corresponding cross-sectional view of the structure of Figure 11L following metal line deposition and polishing, in accordance with an embodiment of the present invention. Referring to plan views and corresponding cross-sectional views (a) and (b), taken individually along axes a-a' and b-b', the metal used to form the metal interconnects is conformally formed Above the structure of Figure 11L. The metal is then planarized (eg, by CMP) to provide metal lines 1140. The metal lines are coupled to the underlying metal lines through predetermined via locations and are isolated by the remaining plugs 1142 and 1144. The deposition and planarization process of metals (eg, copper and associated barrier and seed layers) can be a standard BEOL dual damascene process. It should be understood that in subsequent manufacturing operations, the material layer line 1134 can be removed to provide an air gap between the resulting metal lines 1140.

The structure of Figure 11M can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 11M can represent the last metal interconnect layer in the integrated circuit. It should be understood that the above-described process operations can be performed in an alternate order, not every operation needs to be performed and/or additional process operations can be performed. Furthermore, although the above process flow is focused on directed self-polymerization (DSA) applications, the selective growth process can alternatively be used in one or more locations of the process flow. In any case, the resulting structure enables the fabrication of vias that are directly concentrated on the underlying metal lines. That is, the vias can have a wider, narrower, or the same thickness than the underlying metal lines, for example, due to imperfect selective etch processing. However, in one embodiment, the center of the via is directly aligned (matched) with the center of the metal line. As such, in one embodiment, the deviation from conventional lithography/dual damascene patterning (which is otherwise tolerated) will not be a factor in the resulting structure described herein.

In accordance with an embodiment of the present invention, a self-aligned DSA three block is described in a bottom-up manner. One or more embodiments described herein relate to a three-block copolymer of self-aligned vias or contacts. By using more advanced block copolymers and directed self-polymerization strategies, alignment of the underlying metal layers can be achieved. Embodiments described herein can be implemented to increase cost, scalability, pattern layout errors, and variability.

In general, one or more embodiments described herein relate to the use of three phases of a three-block copolymer material for phase separation into a "self-aligned light bucket", for example, to produce aligned light. The use of a self-aligned three-block copolymer of a barrel is described. Additional embodiments for the manufacture and use of the light bucket are described in more detail below, in an embodiment that goes beyond the current embodiment of Figures 12A-12K. However, it should also be understood that the embodiments are not limited to the concept of a light barrel, but have a wide range of applications for pre-formed features having a bottom-up and/or directed self-polymerization (DSA) approach.

12A-12C illustrate oblique cross-sectional views showing various operations in a method of using a three-block copolymer to form self-aligned vias or contacts of a back end of line (BEOL) interconnect, in accordance with the present invention. Example.

Referring to FIG. 12A, semiconductor structure layer 1200 has a grating pattern of alternating metal lines 1202 and interlayer dielectric (ILD) lines 1204. Structure 1200 can be disposed to have a first molecular brush operation (i) of first molecular species 1206. Structure 1200 can also be disposed to have a second molecular brush operation (ii) of second molecular species 1208. It should be understood that the order of operations (i) and (ii) may be reversed or may even be performed at substantially the same time.

Referring to Figure 12B, the molecular brush operation can be performed to modify or provide a derivative surface to alternating metal lines 1202 and ILD lines 1204. For example, the surface of the metal line 1202 can be disposed to have an A/B surface 1210 on the metal line 1202. The surface of the ILD line 1204 can be disposed to have a C surface 1212 on the ILD line 1204.

Referring to Figure 12C, the structure of Figure 12B can be disposed of a treatment operation (iii) involving the application of a three-block block copolymer (three-block BCP) 1214, and possibly subsequent separation treatment to form a separation structure 1220 . The separation structure 1220 includes a first region 1222 of a separate three block BCP above the ILD line 1204. The alternating second zone 1224 and third zone 1226 separating the three blocks BCP are located above the metal line 1202. The final configuration of the three blocks of triblock copolymer 1214 is based on chemical epitaxy since only the underlying pattern (rather than the coplanar pattern, as used in the epitaxy) is used to direct the polymerization of the triblock copolymer 1214. The separation structure 1220 is formed.

Referring collectively to Figures 12A-12C, in one embodiment, the structure 1220 for directed self-polymerization of a back end of line (BEOL) semiconductor structure metallization layer includes a substrate (not shown, but described below, and should be understood as low On ILD line 1204 and metal line 1202). The lower metallization layer includes alternating metal lines 1202 and dielectric lines 1204 disposed thereon. A three-block copolymer layer 1214 is disposed over the lower metallization layer. The three-block copolymer layer includes a first discrete block component 1222 disposed over the dielectric line 1204 of the lower metallization layer. The three-block copolymer layer includes alternating second 1224 and third 1226 separation block assemblies disposed over dielectric lines 1202 of the lower metallization layer.

In one embodiment, the third discrete block 1226 component of the three block copolymer layer 1214 is light sensitive. In one embodiment, the three-block copolymer layer 1214 is formed to a thickness in the range of about 5 to 100 nanometers. In one embodiment, the three-block copolymer layer 1214 comprises a three-block copolymer species selected from the group consisting of: polystyrene and other polyarylenes, polyisoprene And other polyolefins, polymethacrylates and other polyesters, polydimethyl methoxy oxane (PDMS) and related ruthenium based polymers, polyferrocene decane, polyethylene oxide (PEO) and related Polyether and polyvinyl pyridine. In one embodiment, the alternating second 1224 and third 1226 separation block assemblies have a ratio of about 1:1, as depicted in FIG. 21C (and as described below in association with FIG. 12H). In another embodiment, the alternating second 1224 and third 1226 separation block assemblies have a ratio of X:1, and the second discrete block assembly 1224 is relative to the third discrete block assembly 1226, where X is greater than one, and The third discrete block assembly 1226 has a columnar structure surrounded by a second discrete block assembly, as described below in connection with FIG. 12I. In another embodiment, the triblock copolymer layer 1214 is a homopolymer of A, B, and/or C or a mixture of A-B, B-C, or a double block BCP of the A-C assembly to achieve the desired morphology.

In one embodiment, the structure 1220 further includes a first molecular brush layer 1212 disposed on the dielectric line 1204 of the lower metallization layer. In this embodiment, the first discrete block assembly 1222 is disposed on the first molecular brush layer. In one embodiment, the structure 1220 also includes a second (different) molecular brush layer 1210 disposed on the metal line 102 of the lower metallization layer. The alternating second 1224 and third 1226 separation block assemblies are disposed on the second molecular brush layer 1210. In one embodiment, the first molecular brush layer 1212 includes a molecular species 1208 comprising having selected from the group consisting of -SH, -PO ₃ H ₂ , -CO ₂ H, -NRH, -NRR', and -Si(OR) ₃ The first group of brush layers 1210 includes a molecular species 1206 comprising a molecule selected from the group consisting of -SH, -PO ₃ H ₂ , -CO ₂ H, -NRH, -NRR Polymethyl methacrylate of the head group of ', and -Si(OR) ₃ groups.

In one embodiment, the alternating metal lines 1202 and dielectric lines 1204 of the lower metallization layer have a grating pattern comprising a constant pitch. In one embodiment, the third discrete block assembly 1226 of the three-block copolymer layer 1214 defines all possible via locations for the metallization layer above the lower metallization layer. In one embodiment, the third discrete block assembly 1226 of the three block copolymer layer 1214 is light sensitive to extreme ultraviolet (EUV) sources or electron beam sources.

Figure 12D illustrates a beveled cross-sectional view showing the operation in a method of using a three-block copolymer to form a self-aligned via or junction of a back end of line (BEOL) interconnect, in accordance with an embodiment of the present invention.

Referring to Figure 12D, all portions of the third discrete block assembly 1226 of structure 1220 of Figure 12C are removed. In one such embodiment, the removal of all portions of the third discrete block assembly 1226 opens all possible via locations that can be formed over the underlying metallization layer. The openings can be filled with a photoresist layer to ultimately allow for the selection of only those via locations for a particular design. It should be understood that in the case of FIG. 12D, the third discrete block component 1226 of the structure 1220 can be (but need not be) light sensitive because the third discrete block component 1226 of the structure 1220 of FIG. 12C can be selected solely by The etch is performed (e.g., selective for the first discrete block component 1222 and for the second discrete block component 1224). In one such embodiment, selective etching can be performed using selective dry etching or selective wet etching (or both).

Figure 12E illustrates a beveled cross-sectional view showing another operation in a method of using a three-block copolymer to form a self-aligned via or junction of a back end of line (BEOL) interconnect, in accordance with another aspect of the present invention Example.

Referring to Figure 12E, only selected portions of the third discrete block assembly 1226 of structure 1220 of Figure 12C are removed. In one such embodiment, the removal of only selected portions of the third discrete block assembly 1226 only opens those via locations above the underlying metallization layer required for a particular design. It should be understood that in the case of Figure 2E, the third discrete block assembly 1226 of the structure 1220 is light sensitive and the position selection is performed using localized, but highly tolerated, lithographic exposure. The exposure can be described as being tolerated because adjacent materials 1222 and 1224 are adjacent to location 1226 (in one embodiment) and are not light sensitive to the lithography of the selected location for the removal of component 1226.

Figure 12F illustrates a three-block copolymer used to form self-aligned vias or contacts of a back end of line (BEOL) interconnect, in accordance with an embodiment of the present invention.

Referring to FIG. 12F, the split three block BCP 1250 can be divided along portions 1222, 1224, 1226 along the axis 1252. It should be understood that other split configurations may be possible, such as an asymmetric configuration. In one embodiment, there is an etch selectivity between components 1222, 1224, and 1226, which can be as large as 10: 1 etch selectivity for one component relative to the other. In one embodiment, the use of a three-block BCP 1250 can enhance pattern fidelity and reduce critical dimension (CD) variations. In one embodiment, the split three-block BCP 1250 can be implemented to enable a self-aligned strategy that complements the 193 nm immersion lithography (193i) or extreme ultraviolet lithography (EUVL) process.

It should be understood that, in general, the blocks of the triblock copolymer may each have different chemical properties. For example, one of the blocks can be relatively hydrophobic (eg, water repellent) and the other two blocks can be relatively hydrophilic (absorbent), or vice versa. At least conceptually, one of the blocks may be relatively similar to oil and the other two blocks may be relatively similar to water, or vice versa. These differences in the chemical properties between the different blocks of the polymer (whether hydrophilic-hydrophobic differences or others) may cause self-polymerization of the block copolymer molecules. For example, self-polymerization can be separated according to the microphase of the polymer block. Conceptually, this can be similar to the phase separation of oil and water that it usually cannot mix.

Similarly, differences in hydrophilicity between polymer blocks may result in approximately similar microphase separations in which different polymer blocks attempt to "separate" from each other due to chemical dislike of each other. However, in one embodiment, because the polymer blocks are covalently joined to each other, they are not completely separated on a macroscopic scale. Conversely, a given type of polymer block may tend to separate or aggregate with polymer blocks of other molecules of the same type in a very small (e.g., nano-sized) region or phase. The particular size and shape of the zone or microphase generally depends, at least in part, on the relative length of the polymer block. In one embodiment, for example, Figures 12C, 12H, and 12I depict possible polymerization schemes for a three-block copolymer.

It should be understood that the pattern used to open the pre-formed vias or plug locations can be formed to be relatively small, enabling an increase in the overlap tolerance of the lithography process. The pattern features can be made of a uniform size that reduces the scan time for direct writing of the electron beam and/or the optical proximity correction (OPC) complexity with optical lithography. The pattern features can also be formed to be shallow, which can enhance the patterning resolution. The subsequent etch process can be an isotropic chemiselective etch. This etch process mitigates the associated contours and critical dimensions and alleviates the anisotropy problems typically associated with dry etch methods. This etching process is also relatively cheaper (from the standpoint of equipment and throughput) compared to other selective removal methods.

The following is a description of a portion of an integrated circuit layer that represents various operations in a method of self-aligned vias and metal patterning. In particular, Figures 12G and 12H illustrate a plan view and corresponding cross-sectional views showing each of the methods of using a three-block copolymer to form a self-aligned via or junction of a back end of line (BEOL) interconnect. The operation is in accordance with an embodiment of the invention.

Figure 12G illustrates a plan view of the selection of the front layer metallization structure and corresponding cross-sectional views taken along the a-a' axis, in accordance with an embodiment of the present invention. Referring to the plan view and corresponding cross-sectional view selection (a), the starting structure 1260 includes a pattern of metal lines 1262 and interlayer dielectric lines (ILD) 1264. The starting structure 1260 can be patterned into a grating-like pattern with metal lines spaced at a constant pitch and having a constant width, as depicted in Figure 12G, where the self-polymeric material is ultimately formed. In the case of cross-sectional view (a), metal lines 1262 and interlayer dielectric (ILD) lines 1264 are coplanar with each other. Certain lines may be associated with the underlying vias, such as the line 1262' shown in one of the cross-sectional views.

Referring again to FIG. 12G, alternatives (b)-(f) are discussed in which an additional film is formed on the surface of one of the metal lines 1262 and the interlayer dielectric lines 1264 (eg, deposited, grown, or The case of leaving the artifacts left from the previous patterning process. In example (b), additional film 1266 is disposed over interlayer dielectric line 1264. In example (c), an additional film 1268 is disposed on the metal line 1262. In the example (d), the additional film 1266 is disposed on the interlayer dielectric line 1264, and the additional film 1268 is disposed on the metal line 1262. Moreover, although metal lines 1262 and interlayer dielectric lines 1264 are described as being coplanar in (a), in other embodiments they may be non-coplanar. For example, in (e), metal line 1262 protrudes above interlayer dielectric line 1264. In the example (f), the metal line 1262 is recessed below the interlayer dielectric line 1264.

Referring again to examples (b)-(d), additional layers (eg, layer 1266 or 1268) can be used as a hard mask (HM) or protective layer or used to enable the self-aggregation described below in relation to subsequent processing operations. These additional layers can also be used to protect the ILD from further processing. Furthermore, selectively depositing another material over the metal line may be advantageous for similar reasons. Referring again to examples (e) and (f), the ILD lines or wires can also be recessed by any combination of protective/HM materials on either or both surfaces. In summary, there are several options at this stage to prepare for the final underlying surface of the directed self-polymerization process.

Referring to Figure 12H, a three-block copolymer layer 1270 is formed on the structure of Figure 12G (e.g., a plan view of the cross-sectional structure (a)). The three-block copolymer layer 1270 is separated to have a region 1272 formed over the ILD line 1264, and has alternating second regions 1274 and third regions 1276 formed over the metal lines 1262.

Referring to the cross-sectional view along the b-b' axis of Figure 12H, third region 1276 is shown over metal line 1262, while first region 1272 is displayed over ILD line 1264. According to an embodiment, it is also shown that between the first region 1272 and the ILD line 1264 is a layer 1280, which may be the residual portion of the molecular brush layer. However, it should be understood that layer 1280 may not be present. According to an embodiment, the third zone 1276 is shown as being formed directly on the metal line 1262. However, it should be understood that the residue of the molecular brush layer may be between the third zone 1276 and the metal line 1262.

Referring to the cross-sectional view along the c-c' axis of Figure 12H, second region 1274 is shown over metal line 1262, while first region 1272 is displayed over ILD line 1264. According to an embodiment, it is also shown that between the first region 1272 and the ILD line 1264 is a layer 1280, which may be the residual portion of the molecular brush layer. However, it should be understood that layer 1280 may not be present. According to an embodiment, it is also shown that between the second region 1274 and the metal line 1262 is a layer 1282 which may be a residual portion of the molecular brush layer. However, it should be understood that layer 1282 may not be present. It should also be understood that zone 1276 can be formed to be light sensitive or can be replaced with a light sensitive material.

Thus, in one embodiment, the underlying metal and ILD grids are regenerated in a block copolymer (BCP). This may be especially true if the BCP pitch is comparable to the lower grating pitch. The polymer grid, in one embodiment, is tough for a small amount of deviation from a properly aligned grid. For example, if a small plug effectively sets a material such as an oxide (where a very properly aligned grid would have a metal), then a substantially perfectly aligned block copolymer grid can still be achieved.

In one embodiment, referring again to Figure 12H, the thickness of the coated three-block copolymer layer 1270 is approximately the same (or slightly thicker) than the final thickness of the ILD ultimately formed in its location. In one embodiment, as described in more detail below, the polymer grid is not formed as an etch resist, but as a support for ultimately growing a permanent ILD layer around it. As such, the thickness of the three-block copolymer layer 1270 may be important because it can be used to define the final thickness of the subsequently formed permanent ILD layer. That is, in one embodiment, the polymer grating shown in Figure 12H is ultimately replaced with an ILD/wire grating of approximately the same thickness.

In one embodiment, the three-block copolymer layer 1270 molecules are polymer molecules formed from chains of covalently bonded monomers. In a three-block copolymer, there are three different types of monomers, and these different types of monomers are primarily included in two different blocks or adjacent sequences of monomers. In one embodiment, the three-block copolymer layer 1270 is first coated as an unpolymerized block copolymer layer portion comprising, for example, a block copolymer material applied by a brush or other coating process. . The unpolymerized form refers to where the block copolymer has not been substantially phase separated and/or self-polymerized (at the time of deposition) to form a nanostructure. In this unpolymerized form, the block polymer molecules are relatively highly randomized, having relatively highly randomly oriented and disposed different polymer blocks, which are opposite to the polymeric three zones discussed in connection with the resulting structure of Figure 12H. Block copolymer layer 1270. The unpolymerized block copolymer layer portion can be coated in a number of different ways. For example, the block copolymer can be dissolved in a solvent and then spin coated onto the surface. Alternatively, the unpolymerized block copolymer can be spray coated, dip coated, dip coated, or otherwise coated or coated onto the surface. Other ways of coating the block copolymer, as well as other means known in the art for applying similar organic coatings, can potentially be used. Next, the unpolymerized layer can form a portion of the polymeric block copolymer layer, for example, by microphase separation and/or self-polymerization of the unpolymerized block copolymer layer portion. Microphase separation and/or self-polymerization occurs through reconfiguration and/or relocation of the block copolymer molecules, and in particular, reconfiguration and/or relocation of different polymer blocks of the block copolymer molecules to A three-block copolymer layer 1270 is formed.

In this embodiment, an annealing treatment can be applied to the unpolymerized block copolymer to initiate, accelerate, increase, or enhance the quality of the microphase separation and/or self-polymerization to form a three-block copolymer layer 1270. In certain embodiments, the annealing treatment can include a treatment that is operable to increase the temperature of the block copolymer. An example of such a treatment is baking the layer, heating the layer in an oven or above a heat lamp, applying infrared radiation to the layer, or applying heat to the layer or increasing the temperature of the layer. The desired increase in temperature will generally be sufficient to significantly accelerate microphase separation and/or self-polymerization of the block polymer without damaging any other important materials or structures of the block copolymer or integrated circuit substrate. Generally, the heating range can be from about 50 ° C to about 300 ° C, or from 75 ° C to about 250 ° C, but does not exceed the thermal degradation limit of the block copolymer or integrated circuit substrate. Heating or annealing can assist in providing energy to the block copolymer molecules to make them more mobile/elastic to increase the rate of microphase separation and/or to enhance the quality of the microphase separation. This microphase separation or reconfiguration/relocation of the block copolymer molecules can result in self-polymerization to form a very small (e.g., nanoscale) structure. Self-polymerization can occur under the influence of forces such as surface tension, molecular likes and dislikes, and other surface related and chemically related forces.

In any event, in certain embodiments, the self-polymerization of the block copolymer (whether or not based on hydrophobic-hydrophilic differences) can be used to form very small periodic structures (eg, precisely spaced nanoscale structures or Line) in the form of a three-block copolymer layer 12720. In some embodiments, it can be used to form nanoscale lines or other nanoscale structures that can ultimately be used to form via openings. In certain embodiments, the oriented self-polymerization of the block copolymer can be used to form vias that are self-aligned with the interconnect, as described in more detail below.

It should be understood that the two components of the three-block copolymer structure formed over the metal lines need not have a 1:1 ratio (a 1:1 ratio is shown in Figures 12C and 12H). For example, the third discrete block assembly can be present in a smaller amount than the second component and can have a columnar structure surrounded by the second discrete block assembly. 12I-12L illustrate plan views and corresponding cross-sectional views showing various operations in a method of using a three-block copolymer to form self-aligned vias or contacts of a back end of line (BEOL) interconnect, Embodiments of the invention.

Referring to Figure 12I, a plan view and corresponding cross-sectional views taken along the d-d' axis show a third component 1276 that is smaller than the second component 1274. The third separation block assembly 1276 has a columnar structure surrounded by a second separation block assembly 1274.

Referring to Figure 12J, a plan view shows that the lithography 1290 selection of certain 1292 of the third discrete block assembly 1276 is fulfilled to ultimately provide a via location for the upper metallization structure.

It should be understood that Figure 12I effectively illustrates the unexposed light sensitive DSA structure, while Figure 12J illustrates the exposed light sensitive DSA structure. In contrast to FIG. 12H, FIGS. 12I and 12J show an example of a columnar structure which can be formed in a shorter block in which a plurality of block copolymer molecules form a columnar structure with a polymer (which is composed of another polymer) When the phase of the longer block is surrounded by) alignment. In accordance with embodiments of the present invention, the photoactivated nature of the DSA structure provides the ability to effectively "insert" or "cut" one type of DSA polymer region using, for example, electron beam or EUV exposure.

Referring to Figure 12K, the plan view shows the exposed/chemically enlarged regions 1294 in the exposed zone. The only effective modification for selectivity is the material associated with the exposed portion of the third discrete block component 1276. It should be understood that although shown as cleared in Figure 12K, the selected area may not have been cleared.

Referring to Figure 12L, a plan view and corresponding cross-sectional views taken along the e-e' axis are shown to provide lithographic development after the cleared region 1294 has been provided. The cleared region 1294 can ultimately be used for via formation.

The resulting patterned DSA structure of Figure 12L (or Figures 12C, 12D, 12E or 12H) above may ultimately be used as a stent from which a permanent layer is ultimately formed. That is, it is possible that no DSA material is present in the final structure, but is used to direct the fabrication of the finalized interconnect structure. In one such embodiment, the permanent ILD replaces one or more regions of the DSA material, and subsequent processing, such as wire fabrication, is completed. That is, it is possible that all of the DSA components are eventually removed for final self-aligned vias and plug formation. In other embodiments, at least some of the DSA material may remain in the final structure.

Referring again to FIGS. 12A-12C, 12G, 12H, and 12I-12L, in one embodiment, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer having alternating metal lines and dielectric lines Above the substrate. A three-block copolymer layer is formed over the lower metallization layer. The three-block copolymer layer is separated to form a first discrete block assembly over the dielectric line of the lower metallization layer and to form alternating second and third discrete block assemblies disposed over the metal line of the lower metallization layer . The third discrete block assembly is light sensitive. The method also includes illuminating and developing a selected location of the third discrete block assembly to provide a via opening above the metal line of the lower metallization layer.

In one embodiment, the alternating second and third discrete block assemblies have a ratio of about 1:1, as described in association with Figures 12C and 12H. In another embodiment, the alternating second and third discrete block assemblies have a ratio of about X:1, and the second discrete block assembly is relative to the third discrete block assembly, wherein X is greater than one. In this embodiment, the third discrete block assembly has a columnar structure surrounded by a second discrete block assembly, as described in connection with FIG. 12I.

In one embodiment, the method further includes: after illuminating and developing the selected position of the third separation block assembly to provide the via opening, using the resulting patterned three-block copolymer layer as a support to form a second order The alternating metal and dielectric lines are over, coupled to, and orthogonal to the first order alternating metal and dielectric lines. In one embodiment, one or more components of the three-block copolymer layer are retained in the final structure. However, in other embodiments, all of the components of the three-block copolymer layer are ultimately sacrificed since no such material is retained in the final product. An exemplary embodiment of an embodiment of the latter embodiment is described below in conjunction with FIG.

In one embodiment, the method further includes (before forming the three-block copolymer layer) forming a first molecular brush layer on the dielectric line of the lower metallization layer, and forming a second (different) molecular brush layer on the lower metal The metal lines of the layers are described above in connection with Figures 12A-12C. In one embodiment, illuminating and developing the selected location of the third discrete block assembly includes exposing selected locations of the third discrete block assembly to an extreme ultraviolet (EUV) source or electron beam source.

Only an example of the final structure that can be finally obtained is provided. FIG. 13 is a plan view and a corresponding cross-sectional view of the self-aligned via structure formed after the formation of the metal lines, vias and plugs, according to the present invention. Embodiments of the invention. The reference plane view and corresponding cross-sectional views (a) and (b) are taken individually along the axes f-f' and g-g', and the upper-order metal lines 1302 are provided with a dielectric frame (eg, for a dielectric) Layer 1304 is on and adjacent to dielectric line 1314). Metal line 1302 is coupled to lower metal line 1262 through a predetermined via location (example 1306 is shown in cross-sectional view (a)) and is isolated by a plug (examples of which include plugs 1308 and 1310) . Lower lines 1262 and 1264 can be described above in association with FIG. 12G, as formed in a direction orthogonal to metal line 1302. It should be understood that in subsequent manufacturing operations, the dielectric lines 1314 can be removed to provide an air gap between the resulting metal lines 1302.

The resulting structure, such as those described in connection with Figure 13, can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 13 can represent the last metal interconnect layer in the integrated circuit. It should be understood that the above-described process operations can be performed in an alternate order, not every operation needs to be performed and/or additional process operations can be performed. In any case, the resulting structure enables the fabrication of vias that are directly concentrated on the underlying metal lines. That is, the vias can have a wider, narrower, or the same thickness than the underlying metal lines, for example, due to imperfect selective etch processing. However, in one embodiment, the center of the via is directly aligned (matched) with the center of the metal line. As such, in one embodiment, the deviation from conventional lithography/dual damascene patterning (which is otherwise tolerated) will not be a factor in the resulting structure described herein. It should be understood that the above examples have focused on via/contact formation. However, in other embodiments, a similar manner can be used to preserve or form regions for line end terminations (plugs) within the wire layer.

It should be understood that the processes described herein can be described as being primarily DSA based (such as several process schemes described above), while others can be primarily etch based. In accordance with an embodiment of the present invention, a deep subtraction mode is implemented in BEOL processing. One or more embodiments described herein relate to a subtractive manner for self-aligned vias and plug patterning, and the resulting structure. In one embodiment, the procedures described herein enable the implementation of self-aligned metallization for the fabrication of back-end process features. The overlap problem expected for next generation via and plug patterning can be handled in one or more ways as described herein. In general, one or more of the embodiments described herein involve the use of a subtractive method to pre-form each via and plug using an etched trench. An additional operation is then used to select which vias and plugs to retain.

Figures 14A-14N illustrate portions of an integrated circuit layer that represent various operations in a method of subtracting self-aligned vias and plug patterning, in accordance with an embodiment of the present invention. In each of the illustrated operations, a beveled three-dimensional cross-sectional view is provided.

Figure 14A illustrates a starting point structure 1400 for a reduced via and plug process following fabrication of a deep metal line, in accordance with an embodiment of the present invention. Referring to FIG. 14A, structure 1400 includes a metal line 1402 having an intermediate interlayer dielectric (ILD) line 1404. The ILD line 1404 includes a plug cap layer 1406. In one embodiment, as described in more detail below in conjunction with FIG. 14E, the plug cap layer 1406 is later patterned to ultimately define all possible locations for subsequent plug formation.

In one embodiment, the grating structure formed by the metal lines 1402 is a closely pitched grating structure. In this embodiment, the tight pitch cannot be obtained directly through conventional lithography. For example, a pattern according to a conventional lithography may be formed first, but the pitch may be halved by patterning using a spacer mask. Even the original pitch can be reduced to a quarter by the second round of spacer mask patterning. Therefore, the grating-like pattern of FIG. 14A may have metal wires separated by a constant pitch and having a constant width. The pattern can be created by halving the pitch or reducing the pitch by a quarter. It should also be understood that certain lines 1402 may be associated with lower vias for coupling to previous interconnect layers.

In one embodiment, metal line 1402 is formed by patterning a trench into an ILD material (eg, ILD material of line 1404) having a plug cap layer 1406 formed thereon. The trench is then filled with metal and, if desired, planarized to the plug cap layer 1406. In one embodiment, the metal trench and fill process are characterized by high aspect ratio features. For example, in one embodiment, the aspect ratio of the metal line height (h) to the metal line width (w) is in the range of about 5-10.

Figure 14B illustrates the structure of Figure 14A following the recess of the metal lines, in accordance with an embodiment of the present invention. Referring to FIG. 14B, metal line 1402 is selectively recessed to provide first order metal line 1408. The recess is selectively performed to the ILD line 1404 and the plug cap layer 1406. The recess can be performed by etching through dry etching, wet etching, or a combination thereof. The degree of dishing can be determined by the target thickness (th) of the first order metal line 1408 for use as a suitable conductive interconnect within the back end of line (BEOL) interconnect structure.

Figure 14C illustrates the structure of Figure 14B after the hard mask fill in the recessed regions of the recessed metal lines, in accordance with an embodiment of the present invention. Referring to FIG. 14C, a hard mask layer 1410 is formed in a region formed during recessing to form the first-order metal lines 1408. The hard mask layer 1410 can be formed to the level of the plug cap layer 1406 by a material deposition and chemical mechanical planarization (CMP) process, or by a controlled bottom-up growth process. In a particular embodiment, the hard mask layer 1410 is comprised of a carbon-rich material.

Figure 14D illustrates the structure of Figure 14C following deposition and patterning of the hard mask layer, in accordance with an embodiment of the present invention. Referring to FIG. 14D, a second hard mask layer 1412 is formed on or over the hard mask layer 1410 and the plug cap layer 1406. In this embodiment, the second hard mask layer 1412 is formed with a grating pattern orthogonal to the grating pattern of the first order metal line 1408/ILD line 1404, as shown in FIG. 14D. In a particular embodiment, the second hard mask layer 1412 is comprised of a ruthenium-based anti-reflective coating material. In one embodiment, the grating structure formed by the second metal line 1412 is a closely pitched grating structure. In this embodiment, the tight pitch cannot be obtained directly through conventional lithography. For example, a pattern according to conventional lithography may be formed first, but the pitch may be halved by patterning using spacer masks, as is known in the art. Even the original pitch can be reduced to a quarter by the second round of spacer mask patterning. Thus, the raster pattern of the second hard mask layer 1412 of Figure 14D can have a hard mask line that is separated by a constant pitch and has a constant width.

Figure 14E illustrates the structure of Figure 14D following the formation of the trenches defined by the pattern of the hard mask of Figure 14D, in accordance with an embodiment of the present invention. Referring to FIG. 14E, the exposed regions of the hard mask layer 1410 and the plug cap layer 1406 (ie, not protected by 1412) are etched to form trenches 1414. The etch stop is stopped (and thus exposed) on the top surface of the first order metal line 1408 and the ILD line 1404.

Figure 14F illustrates the structure of Figure 14E following the removal of the ILD in the trench of Figure 14E and the removal of the second hard mask, in accordance with an embodiment of the present invention. Referring to Figure 14F, a second ILD line 1416 is formed in the trench 1414 of Figure 14E. In one embodiment, a flowable ILD material is used to fill the trenches 1414. In one embodiment, the trenches 1414 are filled and the fill material is then planarized. The planarization can be further used to remove the second hard mask layer 1412, re-expose the hard mask layer 1410, and the plug cap layer 1406, as shown in Figure 14F.

Referring again to Figure 14F, in one embodiment, the resulting structure includes a uniform ILD structure (ILD line 1404 + ILD line 1416). All possible plug locations are occupied by the remainder of the plug cap layer 1406, while all possible via locations are occupied by the remainder of the hard mask layer 1410. In this embodiment, the ILD line 1404 and the ILD line 1416 are comprised of the same material. In another such embodiment, the ILD line 1404 and the ILD line 1416 are comprised of different ILD materials. In either case, in a particular embodiment, a distinction such as a seam between the material of the ILD line 1404 and the ILD line 1416 can be observed in the final structure. Moreover, in one embodiment, there is no distinct etch stop layer in which the ILD line 1404 meets the ILD line 1416, unlike conventional single or dual damascene patterning.

Figure 14G illustrates the structure of Figure 14F following the removal of the remainder of the hard mask layer occupying all possible via locations, in accordance with an embodiment of the present invention. Referring to Figure 14G, the remaining portion of the hard mask layer 1410 is selectively removed to form openings 1418 for all possible via locations. In this embodiment, the hard mask layer 1410 is substantially composed of carbon and is selectively removed in a gray process.

In general, one or more of the embodiments described herein involve the use of a subtractive method to pre-form each via and plug using an etched trench. An additional operation is then used to select which vias and plugs to retain. These operations can be illustrated using a "light bucket", although a more traditional resist exposure and ILD backfilling method can be used to perform the selection process. It should also be understood that the embodiments are not limited to the concept of a light bucket, but rather have a wide range of configurations for use with pre-formed features fabricated using a bottom-up and/or directed self-polymerization (DSA) approach. Additional embodiments for the manufacture and use of the light bucket are described in more detail below, in an embodiment that goes beyond the current embodiment of Figures 14A-14N and 15A-15D.

Figure 14H illustrates the structure of Figure 14G following the formation of a light bucket in all possible through-hole locations, in accordance with an embodiment of the present invention. Referring to Figure 14H, a light bucket 1420 is formed in all possible through hole locations above the exposed portions of the first order metal lines 1408. In one embodiment, the opening 1418 of FIG. 14G is filled with an ultra-high speed photoresist or electron beam resist or other photosensitive material. In this embodiment, thermal backfilling of the polymer entering the opening 1418 is followed by application after spin coating. In one embodiment, the fast photoresist is fabricated by removing the inhibitor from existing photoresist materials. In another embodiment, the optical tub 1420 is formed by an etch back process and/or a lithography/reduction/etch process. It should be understood that the light bucket need not be filled with the actual photoresist as long as the material acts as a photosensitive switch.

Figure 14I illustrates the structure of Figure 14H following the selection of the via locations, in accordance with an embodiment of the present invention. Referring to Figure 14I, the light bucket 1420 from Figure 14H is removed when the through hole position is selected. In locations where the vias are not selected for formation, the light bucket 1420 is retained, converted to permanent ILD material, or replaced with permanent ILD material. For example, FIG. 14I illustrates via location 1422 with the corresponding light bucket 1420 removed to expose a portion of one of the first order metal lines 1408. Other locations previously occupied by the light bucket 1420 are now shown as zone 1424 in Figure 14I. Location 1424 is not selected to form a via and instead form a portion of the final ILD structure. In one embodiment, the material of the light bucket 1420 is retained in position 1424 to become the final ILD material. In another embodiment, the material of the light bucket 1420 is modified (eg, by cross-linking) in position 1424 to form the final ILD material. In yet another embodiment, the material of the light bucket 1420 in position 1424 is replaced with the last ILD material.

Referring again to FIG. 14I, in order to form the via location 1422, lithography is used to expose the corresponding light bucket 1420. However, the lithography limitations can be relaxed and the misalignment tolerance can be high because the light bucket 1420 is surrounded by a non-photosolvable material. Further, in an embodiment, instead of exposure to, for example, 30 mJ/cm ² , the optical barrel may be exposed to, for example, 3 mJ/cm ² . Usually this will result in very poor CD control and roughness. In this case, however, the CD and roughness control will be defined by the light bucket 1420, which can be optimally controlled and defined. Thus, the light bucket approach can be used to prevent imaging/dosage tradeoffs, which limits the throughput of next generation lithography processes.

Referring again to Figure 14I, in one embodiment, the resulting structure includes a uniform ILD structure (ILD 1424 + ILD line 1404 + ILD line 1416). In this embodiment, both or all of ILD 1424, ILD line 1404, and ILD line 1416 are comprised of the same material. In another such embodiment, ILD 1424, ILD line 1404, and ILD line 1416 are comprised of different ILD materials. In either case, in a particular embodiment, a seam such as between the material of the ILD 1424 and the ILD line 1404 (eg, seam 1497) and/or between the ILD 1424 and/or is observed in the final structure. The seam between the materials of the ILD wire 1416 (eg, seam 1498) is different.

Figure 14J illustrates the structure of Figure 14I after the hard mask fill in the opening of Figure 14I, in accordance with an embodiment of the present invention. Referring to FIG. 14J, a hard mask layer 1426 is formed in the via location 1422 and above the ILD location 1424. Hard mask layer 1426 can be formed by deposition and subsequent chemical mechanical planarization.

Figure 14K illustrates the structure of Figure 14J following the removal of the plug cap layer and the formation of the second plurality of light barrels, in accordance with an embodiment of the present invention. Referring to Figure 14K, the plug cap layer 1406 is removed, for example, by a selective etch process. Light bucket 1428 is then formed in all possible plug locations above the exposed portion of ILD line 1404. In one embodiment, the opening formed during removal of the plug cap layer 1406 is filled with an ultra-high speed photoresist or electron beam resist or other photosensitive material. In this embodiment, thermal backfilling of the polymer entering the opening is followed by application after spin coating. In one embodiment, the fast photoresist is fabricated by removing the inhibitor from existing photoresist materials. In another embodiment, the light bucket 1428 is formed by an etch back process and/or a lithography/reduction/etch process. It should be understood that the light bucket need not be filled with the actual photoresist as long as the material acts as a photosensitive switch.

Figure 14L illustrates the structure of Figure 14K following the selection of the plug position, in accordance with an embodiment of the present invention. Referring to Figure 14L, the light bucket 1428 from Figure 14K is removed in the selected plug position. In a position where the plug is selected for formation, the light bucket 1428 is retained, converted to a permanent ILD material, or replaced with a permanent ILD material. For example, FIG. 14L illustrates the non-plug position 1430 with the corresponding light bucket 1428 removed to expose a portion of the ILD line 1404. Other locations previously occupied by the light bucket 1428 are now shown as zone 1432 in Figure 14L. Region 1432 is selected to form a plug and form part of the final ILD structure. In one embodiment, the material of the respective light bucket 1428 is retained in zone 1432 to become the final ILD material. In another embodiment, the material of the light bucket 1428 is modified (eg, by cross-linking) into the region 1432 to form the final ILD material. In yet another embodiment, the material of the light bucket 1428 in zone 1432 is replaced with the last ILD material. In any case, zone 1432 may also be referred to as plug 1432.

Referring again to FIG. 14L, in order to form opening 1430, lithography is used to expose the corresponding light bucket 1428. However, the lithography limit can be relaxed and the misalignment tolerance can be high because the light bucket 1428 is surrounded by a non-photosolvable material. Further, in an embodiment, instead of exposure to, for example, 30 mJ/cm ² , such a light bucket may be exposed to, for example, 3 mJ/cm ² . Usually this will result in very poor CD control and roughness. In this case, however, the CD and roughness control will be defined by the light bucket 1428, which can be optimally controlled and defined. Thus, the light bucket approach can be used to prevent imaging/dosage tradeoffs, which limits the throughput of next generation lithography processes.

Referring again to Figure 14L, in one embodiment, the resulting structure includes a uniform ILD structure (plug 1432+ ILD 1424 + ILD line 1404 + ILD line 1416). In this embodiment, two or more of plug 1432, ILD 1424, ILD line 1404, and ILD line 1416 are comprised of the same material. In another such embodiment, the plug 1432, the ILD 1424, the ILD line 1404, and the ILD line 1416 are comprised of different ILD materials. In either case, in a particular embodiment, a seam such as between the material of the plug 1432 and the ILD line 1404 (eg, seam 1499) and/or intervening is observed in the final structure. 1432 differs from the seam between the material of the ILD line 1416 (eg, seam 1496).

Figure 14M illustrates the structure of Figure 14L following the removal of the hard mask of Figure 14L, in accordance with an embodiment of the present invention. Referring to FIG. 14M, the hard mask layer 1426 is selectively removed to form metal lines and via openings 1434. In this embodiment, the hard mask layer 1426 is substantially composed of carbon and is selectively removed in a gray process.

Figure 14N illustrates the structure of Figure 14M following the formation of metal lines and vias, in accordance with an embodiment of the present invention. Referring to Figure 14N, metal lines 1434 and vias (shown as one of 1438) are formed on the metal fill of opening 1434 of Figure 14M. Metal line 1436 is coupled to lower metal line 1408 by via 1438 and is interrupted by plug 1432. In one embodiment, the opening 1434 is filled in a damascene manner in which metal is used to overfill the opening and then planarized back to provide the structure shown in FIG. 14N. Therefore, the deposition and planarization processes of the metal (eg, copper and associated barrier and seed layers) used to form the metal lines and vias in the above manner can be typically used for standard back end of line (BEOL) single or dual damascene Processor. In an embodiment, in subsequent fabrication operations, the ILD line 1416 can be removed to provide an air gap between the resulting metal lines 1436.

The structure of Figure 14N can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 14N can represent the last metal interconnect layer in the integrated circuit. It should be understood that the above-described process operations can be performed in an alternate order, not every operation needs to be performed and/or additional process operations can be performed. In any case, the resulting structure enables the fabrication of vias that are directly concentrated on the underlying metal lines. That is, the vias can have a wider, narrower, or the same thickness than the underlying metal lines, for example, due to imperfect selective etch processing. However, in one embodiment, the center of the via is directly aligned (matched) with the center of the metal line. Furthermore, the ILDs used to select which plugs and vias will likely be very different from the primary ILD and will be highly self-aligned in both directions. As such, in one embodiment, the deviation from conventional lithography/dual damascene patterning (which is otherwise tolerated) will not be a factor in the resulting structure described herein. Referring again to Figure 14N, then, this stage can be accomplished by self-aligned fabrication in a subtractive manner. Manufacturing the next layer in a similar manner may involve performing the above process again. Alternatively, other ways can be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene.

The above process flow system involves the use of deep trench etching. In another form, the shallower approach involves a plug-only self-aligned subtraction processing technique. For example, Figures 15A-15D illustrate portions of an integrated circuit layer that represent various operations in a method of subtracting self-aligned plug patterning, in accordance with another embodiment of the present invention. In each of the illustrated operations, a plan view is shown at the top and a corresponding cross-sectional view is shown at the bottom. These views will be referred to herein as corresponding cross-sectional views and plan views.

Figure 15A illustrates a plan view and corresponding cross-sectional view of a starting plug grid, in accordance with an embodiment of the present invention. Referring to the planar views taken along axes a-a' and b-b' and the corresponding cross-sectional views (a) and (b), the starting plug grid structure 1500 includes an ILD layer 1502 having a first hard A mask layer 1504 is disposed thereon. The second hard mask layer 1508 is disposed on the first hard mask layer 1504 and patterned to have a grating structure. The third hard mask layer 1506 is disposed on the second hard mask layer 1508 and on the first hard mask layer 1504. Moreover, the opening 1510 remains between the second hard mask layer 1508 and the grating structure of the third hard mask layer 1506.

Figure 15B illustrates a plan view and corresponding cross-sectional view of the structure of Figure 15A following filling, exposure and development of the light bucket, in accordance with an embodiment of the present invention. The light bucket 1512 is formed in the opening 1510 of Fig. 15A with reference to a plan view taken along axes a-a' and b-b' and corresponding cross-sectional views (a) and (b). Thereafter, the selected light bucket is exposed and removed to provide a selected plug location 1514, as shown in Figure 15B.

Figure 15C illustrates a plan view and corresponding cross-sectional view of the structure of Figure 15B following the formation of the plug, in accordance with an embodiment of the present invention. Referring to the plan views taken along axes a-a' and b-b' and the corresponding cross-sectional views (a) and (b), a plug 1516 is formed in the opening 1514 of Fig. 15B. In one embodiment, the plugs 1516 are formed by spin coating and/or deposition and etching back.

Figure 15D illustrates a plan view and corresponding cross-sectional view of the structure of Figure 15C following removal of the hard mask layer and the residual light barrel, in accordance with an embodiment of the present invention. Referring to the plan view taken along axes a-a' and b-b' and the corresponding cross-sectional views (a) and (b), the third hard mask layer 1506 is removed, leaving a second hard Mask layer 1508 and plug 1516. The resulting pattern (second hard mask layer 1508 and plug 1516) can then be used to pattern hard mask layer 1504 for final patterning of ILD layer 1502. In one embodiment, the third hard mask layer 1506 is substantially composed of carbon and is removed by performing a gray process.

Thus, the structure of Figure 15D can then be used as the basis for forming the ILD lines and plug patterns. It should be understood that the above-described process operations can be performed in an alternate order, not every operation needs to be performed and/or additional process operations can be performed. In any event, the resulting structure enables the fabrication of self-aligned plugs. As such, in one embodiment, the deviation from conventional lithography/dual damascene patterning (which is otherwise tolerated) will not be a factor in the resulting structure described herein.

In accordance with an embodiment of the present invention, a dielectric helmet-based approach and/or a hard mask selectivity-based approach (and resulting structure) for a back end of line (BEOL) process are described. One or more embodiments described herein are directed to methods of using dielectric helmets for directed self-polymerization (DSA) or selective growth to enable fabrication of self-aligned interconnects. Embodiments may explore or implement one or more of the use of dielectric helmets, directed self-polymerization, selective deposition, self-alignment, or tight pitch patterned interconnections. Embodiments can be implemented to provide enhanced via short-circuit tolerance by utilizing self-alignment through selective "coloring" of deposition, and subsequent directed self-polymerization (eg, for sub-10 nm technology nodes).

In order to provide a background, current solutions for increasing the short-circuit tolerance may include: (1) using metal recesses to fill alternating metal trenches with different hard masks, and (2) using different "color" metal covers for use as Directed self-polymerization (DSA) or selective growth of the template, or (3) recessing the metal or ILD to "guide" the via toward the associated line. In general, a typical process flow to increase via short circuit tolerance requires metal recesses. However, recessed metals with acceptable uniformity have proven to be a challenge in many such treatment scenarios.

In accordance with an embodiment of the present invention, one or more of the above problems are addressed by implementing a method of depositing a non-conformal dielectric cover over a half of the interconnect. A non-conformal dielectric cover is used as a template for selective growth or directed self-polymerization. In one such embodiment, this approach can be applied to any interconnect metal layer and (possibly) to a gate contact. In certain embodiments, the need for metal recesses as seen in the most advanced manners is effectively eliminated from the processing schemes described herein.

As a general overview of the concepts involved in the text, FIGS. 16A-16D illustrate cross-sectional views of portions of an integrated circuit layer that illustrate a method of forming a dielectric helmet for use in back end of line (BEOL) interconnect fabrication. Each of the operations is in accordance with an embodiment of the present invention.

Referring to Figure 16A, a starting point structure 1600 is provided as a starting point for making a new metallization layer. The starting point structure 1600 includes a hard mask layer 1602 that is disposed on an interlayer dielectric (ILD) layer 1602. As described below, the ILD layer can be disposed over the substrate, and (in one embodiment) is disposed over the underlying metallization layer. An opening is formed in the hard mask layer 1604 (which corresponds to the trench formed in the ILD layer 1602). The trenches are each filled with a conductive layer to provide a first metal line 1606 (and, in some cases, a corresponding conductive via 1607). The remaining trenches are unfilled, which provides an open trench 1608. In one embodiment, the starting structure 1600 is fabricated by patterning the hard mask and the ILD layer and then metallizing one half of the metal trenches (eg, one of the trenches), leaving The other half is open. In one embodiment, the trenches in the ILD are patterned using a pitch division patterning process flow. It should be understood that the following process operations described below may first involve pitch segmentation or may not involve. In either case, but particularly when pitch segmentation is also used, embodiments can enable continuous expansion of the pitch of the metal layer beyond the resolution capabilities of state of the art lithography equipment.

FIG. 16B illustrates the structure of FIG. 16A following deposition of the non-conformal dielectric cap layer 1610 over the structure 1600. The non-conformal dielectric cap layer 1610 includes a first portion 1600A that covers the exposed surface of the hard mask layer 1604 and the metal lines 1606. The non-conformal dielectric cap layer 1610 includes a second portion 1610B that is coupled to the first portion 1610A. A second portion 1610B of the non-conformal dielectric cap layer 1610 is formed in the open trench 1608 along the sidewalls 1608A and 1608B of the open trench 1608. In one embodiment, the second portion 1610B of the non-conformal dielectric cap layer 1610 is substantially thinner than the first portion 1610A, as depicted in FIG. 16B. In other embodiments, portion 1610B is absent or discontinuous. In this manner, deposition of the non-conformal dielectric cap layer 1610 is considered to be non-conformal deposition because the thickness of the non-conformal dielectric cap layer 1610 is not the same in all locations. The resulting geometry may be referred to as a helmet shape for the non-conformal dielectric cap layer 1610 because the uppermost portion of the ILD layer 1602 has the thickest portion of the non-conformal dielectric cap layer 1610 thereon, and thus is protected to be more than other regions. Great degree. In one embodiment, the non-conformal dielectric cap layer 1610 is a dielectric material such as, but not limited to, tantalum nitride or hafnium oxynitride. In one embodiment, the non-conformal dielectric cap layer 1610 is formed using a plasma enhanced chemical vapor deposition (PECVD) process or (in another embodiment) physical vapor deposition (PVD).

Fig. 16C illustrates the structure of Fig. 16B after the via patterning, metallization, and planarization of the second half of the metal line. In one embodiment, the metal fill process is performed to provide a second metal line 1612. However, in one embodiment, the via location is first selected and opened prior to metal filling. Next, vias 1613 are formed to be associated with some of the second metal lines 1612 during metal filling. In one such embodiment, the via opening is formed by one of the extended open trenches 1608 by etching through the non-conformal dielectric cap layer 1610 on the bottom of the selected trench 1608 and then extending The trench passes through dielectric layer 1602. The result is an interruption in the continuity of the non-conformal dielectric cap layer 1610 at the via location of the second metal line 1612, as depicted in Figure 16C.

In one embodiment, the metal fill process used to form the second metal line 1612 and the conductive vias 1613 is performed using metal deposition and subsequent planarization processing schemes, such as chemical mechanical planarization (CMP) processes. The planarization process exposes (but does not remove) the non-conformal dielectric cap layer 1610, as depicted in Figure 16C. It should be understood that in one embodiment, the second metal line 1612 (and the corresponding conductive via 1613) is formed later than the process for fabricating the first metal line 1606 (and the corresponding conductive via 1607). In the process, the second metal line 1612 can be fabricated using a different material than that used to fabricate the first metal line 1606. In one such embodiment, the metallization layer ultimately includes alternating, distinct first and second conductive interconnects. However, in another embodiment, metal lines 1612 and 1606 are fabricated from substantially the same material.

In one embodiment, the first metal line 1606 is isolated at a pitch and the second metal line 1612 is isolated at the same pitch. In other embodiments, the lines are not necessarily isolated by pitch. However, by including the non-conformal dielectric cap layer 1610 (or dielectric helmet), only the surface of the second metal line 1612 is exposed. Thus, the pitch between adjacent first and second metal lines that it will otherwise be exposed is relaxed to a pitch of only the second metal lines. Thus, the exposed dielectric surface of the alternating non-conformal dielectric cap layer 1610 and the exposed surface of the second metal line 1612 provide a distinct surface to the pitch of the second metal line 1612.

Figure 16D illustrates the structure of Figure 16C following successive self-polymerization or selective deposition methods to ultimately form two different (alternating) first and second hard mask layers 1614 and 1616 individually. In one embodiment, the materials of the hard mask layers 1614 and 1616 exhibit different etch selectivity from each other. The first hard mask layer 1614 is aligned with the exposed regions of the non-conformal dielectric cap layer 1610. The second hard mask layer 1616 is aligned with the exposed regions of the second metal lines 1612. As described in more detail below, directed self-polymerization or selective growth can be used to selectively individually align the first and second hard mask layers 1614 and 1616 to the dielectric and metal surfaces.

In a first general embodiment, in order to ultimately form the first and second hard mask layers 1614 and 1616, a directed self-polymerization (DSA) block copolymer deposition and polymer polymerization process is performed. In one embodiment, the DSA block copolymer is coated on the surface and annealed to separate the polymer into a first block and a second block. In one embodiment, the first polymer block preferentially adheres to the non-conformal dielectric cap layer 1610. The second polymer block adheres to the second metal line 1612. In one embodiment, the block copolymer molecule is a polymer molecule formed from a chain of covalently bonded monomers, an example of which is described above.

Referring again to FIG. 16D, in the case of the DSA process, in the first embodiment, the first and second hard mask layers 1614 and 1616 are individually the first and second block polymers. However, in the second embodiment, the first and second block polymers are sequentially replaced with the materials of the first and second hard mask layers 1614 and 1616, respectively. In one such embodiment, a selective etch and deposition process is used to individually replace the first and second block polymers with the materials of the first and second hard mask layers 1614 and 1616.

In a second general embodiment, in order to ultimately form the first and second hard mask layers 1614 and 1616, a selective growth process is substituted for the DSA mode. In one such embodiment, the material of the first hard mask layer 1614 is grown over the exposed portion of the underlying non-conformal dielectric cap layer 1610. A second (different) material of the second hard mask layer 1616 is grown over the exposed portion of the lower second metal line 1612. In one embodiment, selective growth is achieved by a dep-etch-dep-etch approach for each of the first and second materials, resulting in each of the materials The plural layer of the person. This approach may be desirable with respect to conventional selective growth techniques that form a "mushroom top" shaped film. The mushroom apex growth tendency can be reduced by an alternate dep-etch-dep-etch. In another embodiment, the film is selectively deposited on the metal, successively deposited on the ILD with different films (or vice versa), and repeated several times to create a sandwich-like stack. In another embodiment, the two materials are simultaneously grown in a reaction chamber (e.g., by a CVD pattern process) that is selectively grown on each exposed region of the underlying substrate.

As described in more detail below, in one embodiment, the resulting structure of FIG. 16D enables improved via short circuit tolerance when a later via layer is fabricated on the structure of FIG. 16D. In one embodiment, the improved short circuit tolerance is achieved because the fabrication of a structure having alternating "color" hard masks reduces the risk of via shorting to the wrong metal line. In one embodiment, self-alignment is achieved because the alternating color hard mask is self-aligned to the underlying metal trench. In one embodiment, the need for metal recesses is removed from the processing scheme as it reduces process variation.

In a first more detailed example process flow, FIGS. 16E-16P illustrate cross-sectional views of portions of an integrated circuit layer, which illustrate another method of forming a dielectric helmet for use in back end of line (BEOL) interconnect fabrication. Each of the operations is in accordance with an embodiment of the present invention.

Referring to Figure 16E, a starting point structure 1630 is provided (continuous to the first metal pass process) as the starting point for making a new metallization layer. The starting point structure 1630 includes a hard mask layer 1634 (eg, tantalum nitride) that is disposed on the interlayer dielectric (ILD) layer 1632. As described below, the ILD layer can be disposed over the substrate, and (in one embodiment) is disposed over the underlying metallization layer. A first metal line 1636 (and, in some cases, a corresponding conductive via 1637) is formed in the ILD layer 1632. The protruding portion 1636A of the metal line 1636 has an adjacent dielectric spacer 1638. A sacrificial hard mask layer 1640 (eg, amorphous germanium) is included between adjacent dielectric spacers 1638. Although not depicted, in one embodiment, the metal lines 1636 are formed by first removing a second sacrificial hard mask material between the dielectric spacers 1638 and then etching the hard mask layer 1634 and the ILD layer 1632 (to form It will be formed by a trench that will be filled in the metallization process.

Figure 16F illustrates the structure of Figure 16E following the second pass metal treatment until trench etching is included. Referring to FIG. 16F, the sacrificial hard mask layer 1640 is removed to expose the hard mask layer 1634. The exposed portion of the hard mask layer 1634 is removed and the trenches 1642 are formed in the ILD layer 1632.

Figure 16G illustrates the structure of Figure 16F following the filling of the sacrificial material. Sacrificial material 1644 is formed in trench 1642 and over spacer 1638 and metal line 1636. In one embodiment, the sacrificial material 1644 is formed in a spin-on process, leaving a substantially planar layer, as depicted in Figure 16G.

Figure 16H illustrates the structure of Figure 16G following a planarization process for re-exposing the hard mask layer 1634, removing the dielectric spacers 1638, and removing the protruding portions 1636A of the metal lines 1636. In addition, the planarization process confines the sacrificial material 1644 to the trenches 1642 formed in the dielectric layer 1632. In one embodiment, the planarization process is performed using a chemical mechanical polishing (CMP) process.

Figure 16I illustrates the structure of Figure 16H following the removal of the sacrificial material. In one embodiment, the sacrificial material 1644 is removed from the trench 1642 using a wet etch or dry etch process.

Figure 16J illustrates the structure of Figure 16I following deposition of a non-conformal dielectric cap layer 1646 (which may be referred to as a dielectric helmet). In one embodiment, the non-conformal dielectric cap layer 1646 is formed using a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process, such as a plasma enhanced CVD (PECVD) process. The non-conformal dielectric cap layer 1646 can be associated with the non-conformal dielectric cap layer 1610 as described above.

Figure 16K illustrates the structure of Figure 16J following deposition of a sacrificial cap layer. A sacrificial cap layer 1648 is formed over the upper surface of the non-conformal dielectric cap layer 1646 and can be implemented to protect the non-conformal dielectric cap layer 1646 during subsequent etching or CMP processes. In one embodiment, the sacrificial cap layer 1648 is a titanium nitride (TiN) layer formed by, for example, PVD or CVD processing.

Fig. 16L illustrates the structure of Fig. 16K following the via lithography and etching process. The selected one of the trenches 1638 is exposed and subjected to an etch process that breaks the non-conformal dielectric cap layer 1646 at location 1650 and extends the trenches to provide via locations 1652, as described above.

Fig. 16M illustrates the structure of Fig. 16L following the fabrication of the second metal line. In one embodiment, the second metal line 1654 (and in some cases, the associated conductive vias 1656) is formed by performing a metal fill and polish process. The polishing process can be a CMP process that further removes the sacrificial cap layer 1648.

Figure 16N illustrates a diagram following successive directed self-polymerization (DSA) or selective growth (for example) to provide first and second alternating placeholder materials 1658 and 1660 (or may be permanent materials, as described in conjunction with Figure 16D). 16M structure.

Figure 16O illustrates the structure of Figure 16N following successive replacement of the first and second alternating placeholder materials 1658 and 1660 with permanent first and second hard mask layers 1662 and 1664, respectively. The processing of Figures 16N and 16O can be described in conjunction with Figure 16D.

Figure 16P illustrates the structure of Figure 16O following the patterning of the next via. Upper ILD layer 1666 is formed over first and second hard mask layers 1662 and 1664. Opening 1668 is formed in upper ILD layer 1666. In one embodiment, the opening 1668 is formed to be wider than the via feature. A selected one of the exposed first and second hard mask layers 1662 and 1664 locations is selected for selective removal, for example, by a selective etch process. In this case, the first hard mask 1662 region is removed, which is selective for the exposed portion of the second hard mask layer 1664. Conductive vias 1670 are then formed in opening 1668 and in the region where the first hard mask 1662 region has been removed. The conductive via 1670 is in contact with one of the first metal lines 1636. In one embodiment, the conductive via 1670 contacts one of the first metal lines 1636 without shorting to one of the adjacent second metal lines 1654. In a particular embodiment, portion 1672 of conductive via 1670 is disposed over the second hard mask layer 1664 portion without contacting the lower second metal line 1654, as depicted in Figure 16P. Next, in an embodiment, an improved short circuit tolerance is achieved.

In one embodiment, the first hard mask 1662 region is removed for fabrication of the via 1670 as described in the above embodiments. In this case, forming the opening during removal of the selected first hard mask 1662 region further requires etching through the uppermost portion of the non-conformal dielectric cap layer 1646. However, in another embodiment, the second hard mask 1664 region is removed for fabrication of the via 1670. In this case, the opening formed during the removal of the selected second hard mask 1664 region directly exposes the metal line 1654 to which the via 1670 is attached.

In a second more detailed example process flow, which involves a first way of via etching, FIGS. 17A-17J illustrate cross-sectional views of portions of the integrated circuit layer, which represent another type of processing for back end processing (BEOL). Each of the methods of forming a dielectric helmet is constructed in accordance with an embodiment of the present invention.

Referring to Figure 17A, a starting point structure 1700 is provided (continuous to the first metal pass process) as the starting point for making a new metallization layer. The starting point structure 1700 includes a hard mask layer 1704 (eg, tantalum nitride) that is disposed on an interlayer dielectric (ILD) layer 1702. As described below, the ILD layer can be disposed over the substrate, and (in one embodiment) is disposed over the underlying metallization layer. A first metal line 1706 (and, in some cases, a corresponding conductive via 1707) is formed in the ILD layer 1702. The protruding portion 1706A of the metal line 1706 has an adjacent dielectric spacer 1708. A sacrificial hard mask layer 1710 (eg, amorphous germanium) is included between adjacent dielectric spacers 1708. Although not depicted, in one embodiment, the metal line 1706 is formed by first removing a second sacrificial hard mask material between the dielectric spacers 1708 and then etching the hard mask layer 1704 and the ILD layer 1702 (to form It will be formed by a trench that will be filled in the metallization process.

Figure 17B illustrates the structure of Figure 17A following the second pass metal treatment until etching including trench and via locations. Referring to FIG. 17B, the sacrificial hard mask layer 1710 is removed to expose the hard mask layer 1704. The exposed portion of the hard mask layer 1704 is removed and the trenches 1712 are formed in the ILD layer 1702. Moreover, in one embodiment, via locations 1722 are formed in selected locations using via lithography and etching processes, as depicted in FIG. 17B.

Figure 17C illustrates the structure of Figure 17B following the filling of the sacrificial material. Sacrificial material 1714 is formed in trench 1712 and over spacer 1708 and metal line 1706. In one embodiment, the sacrificial material 1714 is formed in a spin-on process, leaving a substantially planar layer, as depicted in Figure 17C.

Figure 17D illustrates the structure of Figure 17C following a planarization process for re-exposing the hard mask layer 1704, removing the dielectric spacers 1708, and removing the protruding portions 1706A of the metal lines 1706. In addition, the planarization process confines the sacrificial material 1714 to the trenches 1712 formed in the dielectric layer 1702. In one embodiment, the planarization process is performed using a chemical mechanical polishing (CMP) process.

Figure 17E illustrates the structure of Figure 17D following the partial removal of the sacrificial material 1714 to provide the recessed sacrificial material 1715. In one embodiment, the sacrificial material 1714 is recessed within the trench 1712 using a wet etch or dry etch process. The recessed sacrificial material 1715 can be retained at this point to protect the metal layer below the via location 1722.

Figure 17F illustrates the structure of Figure 17E following deposition of a non-conformal dielectric cap layer 1716 (which may be referred to as a dielectric helmet). In one embodiment, the non-conformal dielectric cap layer 1716 is formed using a physical vapor deposition (PVD), a selective growth process, or a chemical vapor deposition (CVD) process such as a plasma enhanced CVD (PECVD) process. form. The non-conformal dielectric cap layer 1716 can be associated with the non-conformal dielectric cap layer 1710 as described above. Alternatively, the non-conformal dielectric cap layer 1716 can include only the upper portion 1716A that is substantially free of portions of the non-conformal dielectric cap layer 1716 that are formed in the trenches 1712, as depicted in Figure 17F.

Figure 17G illustrates the structure of Figure 17F following the fabrication of the second metal line. In one embodiment, the second metal line 1724 (and in some cases, the associated conductive via 1726) is formed by performing a metal fill and polish process (continued after removal of the recess sacrificial material 1715). . The polishing process can be a CMP process.

Figure 17H illustrates a diagram following successive directed self-polymerization (DSA) or selective growth (for example) to provide first and second alternating placeholder materials 1728 and 1730 (or may be permanent materials, as described in conjunction with Figure 16D). 17G structure.

Figure 17I illustrates the structure of Figure 17H following successive replacement of the first and second alternating placeholder materials 1728 and 1730 with permanent first and second hard mask layers 1732 and 1734, respectively. The processing of Figures 17H and 3I can be described in conjunction with Figure 16D.

Figure 17J illustrates the structure of Figure 17I following the patterning of the next via. Upper ILD layer 1736 is formed over first and second hard mask layers 1732 and 1734. An opening 1738 is formed in the upper ILD layer 1736. In one embodiment, the opening 1738 is formed to be wider than the via feature. A selected one of the exposed first and second hard mask layers 1732 and 1734 locations is selected for selective removal, for example, by a selective etch process. In this case, the first hard mask 1732 region is removed, which is selective for the exposed portion of the second hard mask layer 1734. A conductive via 1740 is then formed in the opening 1738 and in the region where the first hard mask 1732 region has been removed. The conductive via 1740 contacts one of the first metal lines 1706. In one embodiment, the conductive vias 1740 contact one of the first metal lines 1706 without shorting to one of the adjacent second metal lines 1724. In a particular embodiment, portion 1742 of conductive vias 1740 is disposed over portions of second hard mask layer 1734 without contacting lower second metal lines 1724, as depicted in Figure 17J. Next, in an embodiment, an improved short circuit tolerance is achieved.

In one embodiment, as described in the above embodiments, the first hard mask 1732 region is removed for fabrication of the vias 1740. In this case, forming the opening during removal of the selected first hard mask 1732 region further requires etching through the uppermost portion of the non-conformal dielectric cap layer 1716. However, in another embodiment, the second hard mask 1734 region is removed for fabrication of the via 1740. In this case, the opening formed during the removal of the selected second hard mask 1734 region directly exposes the metal line 1724 to which the via 1740 is attached.

Referring again to Figures 16P and 17J, by cross-sectional analysis, the dielectric helmet can be viewed over a total of half of the metal. In addition, hard masks of different materials are self-aligned to the dielectric helmet. Such structures may include one or more of the conductive vias with enhanced short circuit tolerance, alternating hard mask material, and the presence of a dielectric helmet. The resulting structure, such as those described in association with Figures 16P or 17J, can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 16P or 17J may represent the last metal interconnect layer in the integrated circuit. It should be understood that the above-described process operations can be performed in an alternate order, not every operation needs to be performed and/or additional process operations can be performed.

In accordance with an embodiment of the present invention, a pattern accumulation layer for vias and plugs is described. One or more embodiments described herein relate to a process scheme for through-hole critical dimension (CD) control. Embodiments may include improvements in via CD control, via CD uniformity, edge layout error (EPE), via via self-alignment. Embodiments may improve edge placement error (EPE) in semiconductor patterning of vias and may enable self-alignment of most via lithography passes. In one embodiment, all via edges are defined with a grating to replace the standard resist edge. The sacrificial grating is produced under the via resist, in the same direction as the metal via. The vias are patterned using standard photoresist. However, during subsequent etching through a grating of a sacrificial grating and a self-aligned via (SAV) metal grating (eg, two crossed gratings), all via edges are defined by the gratings. In one embodiment, no variability from the edge of the via resist is transferred into the substrate, and the resulting process capability provides better control of the vias CD and enhances throughput and process capability.

In order to provide a background for the embodiments described below, a currently known solution involves the use of a resist edge to define a via edge, which determines the short circuit tolerance for the underlying metal. However, standard via resist patterning is known to have much higher edge layout errors than raster patterning. Conversely, in accordance with the embodiments described herein, the use of a sacrificial grating to define the via edge provides more enhanced control of the via edge and the risk of shorting to the wrong metal is significantly improved.

In accordance with the embodiments described herein, the pattern accumulation process is described for a plurality of via patterns having a sacrificial grating in a stack to define a via edge etch. The "sieve" stack is established by applying a hard mask to the patterned upper metal (M1) interlayer dielectric layer (with plugs already present). A hard mask flattens the wafer for subsequent processing. The next layer formed can be used to stop the etching, followed by the formation of a buildup layer. At this stage, the grating can be produced twice the pitch of the lower metal (M0) layer of the lower side and in the same direction as the M0 grating. This grating effectively blocks the M0 line at each interval underneath and ultimately defines the critical dimension (CD) of the post via. In one embodiment, since the grating is twice the pitch of the lower M0, the solid mass (+/- 20 nm) of the hard mask between the vias is included to allow overlying the edge of the resist feature. Layout error (EPE).

Next, most of the via mask patterns are accumulated through the grating and tied into the accumulation layer. After accumulation, the grating is inverted without additional lithography operations to expose other lower metal (M0) lines and protect the vias that they have created. A lining is added between the gratings to ensure that the vias on adjacent M0 lines do not merge. The spacing between the through holes can be modulated to the thickness of the liner.

Finally, the via pattern from one to several via masks can be accumulated through the inverted grating to complete patterning in the accumulation of all of the depicted vias. The grating is then removed and the accumulated via pattern in the accumulation layer is etched down through the upper metal (M1) hard mask grating into the interlayer dielectric under the M1 line and to the underlying M0. The stacking and overlying hard mask layers above the M1 grating are removed. Thereafter, the trenches and vias are metallized and then polished. The result is excellent CD control of the vias that have been formed in both directions, and self-alignment of all vias for each other.

Next, in one aspect, one or more embodiments described herein relate to a manner in which a lower metal grating structure (or an orthogonal portion of such a structure) is used to establish an overlying conductive via. template. In the example processing scheme, FIGS. 18A-18W illustrate a plan view (top portion of the graph) and corresponding bevel angles (middle portion of the graph) and a cross-sectional view (lower portion of the graph) representing a post-stage process ( BEOL) The various operations in the interconnected metal via processing scheme are in accordance with embodiments of the present invention.

Referring to Figure 18A, a starting point structure 1800 is provided as a starting point for making a new metallization layer. The starting point structure 1800 includes an array of alternating metal lines 1802 and dielectric lines 1804. Metal line 1802 has an upper surface that is approximately coplanar with the upper surface of dielectric line 1804. An etch stop layer 1806 is then formed over the starting structure 1800, as depicted in Figure 18B.

Referring to FIG. 18C, an interlayer dielectric layer 1808 is formed on the structure of FIG. 18B. A patterned hard mask 1810 is then formed over the structure of FIG. 18C, and the pattern of the patterned hard mask 1810 is partially transferred into the interlayer dielectric layer 1808 to form a patterned interlayer dielectric layer 1812 having metal line regions 1814 Formed therein) as depicted in Figure 18D. In one embodiment, the patterned hard mask 1810 has a raster type pattern, as depicted in the figures. In a particular embodiment, the patterned hard mask 1810 is comprised of titanium nitride (TiN).

Referring to Figure 18E, a hard mask layer 1816 is formed on the structure of Figure 18D. In one embodiment, the bottom surface of the hard mask layer 1816 is conformal to the topography of the structure of FIG. 18D, while the upper surface of the hard mask layer 1816 is planarized. In a particular embodiment, the hard mask layer 1816 is a carbon hard mask (CHM) layer. Etch stop layer 1818 is then formed on the structure of Figure 18E, as depicted in Figure 18F. In a particular embodiment, the etch stop layer 1818 is comprised of yttrium oxide (SiOx or SiO ₂ ).

Referring to FIG. 18G, a pattern accumulation layer 1820 is then formed on the structure of FIG. 18F. In one embodiment, pattern accumulation layer 1820 is a layer in which more than one pattern will eventually accumulate, for example, for final via patterning. In a particular embodiment, pattern accumulation mask 1820 is comprised of amorphous germanium (a-Si). A patterned hard mask 1822 is then formed on the structure of Figure 18G, as depicted in Figure 18H. In one embodiment, the patterned hard mask 1822 has a raster type pattern, as depicted in the figures. In one such embodiment, the grating type pattern is orthogonal to the grating of the patterned hard mask 1810 and parallel to the grating of the metal line 1802. However, in an embodiment, from a top down perspective, the patterned hard mask 1822 exposes only the spaced apart metal lines 1802 (eg, metal lines 1802 (A)) and blocks alternating metal lines 1802 (eg, Metal line 1802(B)), as depicted in Figure 18H. In a particular embodiment, the patterned hard mask 1822 is comprised of tantalum nitride (SiN).

Referring to Figure 18I, a hard mask 1824 is then formed over the structure of Figure 18H. In a particular embodiment, the hard mask 1824 is a carbon hard mask (CHM). The hard mask 1824 is then patterned (eg, by a lithography process using a single or multiple layer resist structure) and the pattern is transferred into portions of the pattern accumulation layer 1820 that is exposed by the patterned hard mask 1822. A patterned memory layer 1826 is formed once, as depicted in Figure 18J. In one embodiment, the pattern is transferred into portions of the pattern accumulation layer 1820 by an etch process that uses the etch stop layer 1818 as a termination point. In one embodiment, after forming the patterned memory layer 1826, the hard mask 1824 is removed, as also depicted in FIG. 18J. It should be understood that the process can be repeated for several different masking operations.

Referring to Figure 18K, the barrier line 1828 is then formed by filling the opening in the patterned hard mask 1822 of the structure of Figure 18J with a layer of barrier material. In a particular embodiment, the barrier material layer is a flowable yttria material. In other embodiments, the barrier material layer is any of a number of other suitable materials. The patterned hard mask 1822 is then removed from the structure of Figure 18K such that the barrier line 1828 remains, as depicted in Figure 18L.

Referring to FIG. 18M, an insulating spacer forming material layer 1830 is then formed on the structure of FIG. 18L, which is conformal to the barrier line 1828. In one embodiment, the insulating spacer forming material layer 1830 is composed of a dielectric material. In one embodiment, the spacer forming material layer 1830 is composed of yttrium oxide (SiOx or SiO ₂ ). The spacer forming material layer 1830 is then patterned to form spacers 1832 that abut the sidewalls of the barrier line 1828, as depicted in Figure 18N. In one embodiment, the spacer forming material layer 1830 is patterned using an anisotropic dry etch process to form spacers 1832.

Referring to FIG. 18O, a pattern of barrier lines 1828, spacers 1832, and a guard region of the patterned mask formed after spacers 1832 are formed is then transferred into the primary patterned memory layer 1826 to form a secondary patterned memory layer. 1834. In one embodiment, the pattern is transferred into the patterned memory layer 1826 by an etch process that uses the etch stop layer 1818 as a termination point. Any additional masking material that blocks the line 1828, spacers 1832, and the structure of FIG. 18O is then removed to expose the secondary patterned memory layer 1834, as depicted in FIG. 18P.

Referring to FIG. 18Q, the pattern of the secondary patterned memory layer 1834 of the structure of FIG. 18P is then transferred to the etch stop layer 1818 to form the patterned etch stop layer 1836 and expose portions of the hard mask layer 1816. In one embodiment, the pattern of the secondary patterned memory layer 1834 is transferred to the etch stop layer 1818 using a dry etch process. The secondary patterned memory layer 1834 of the structure of Figure 18Q is then removed, as depicted in Figure 18R.

Referring to FIG. 18S, the pattern of patterned etch stop layer 1836 of the structure of FIG. 18R is then transferred into hard mask layer 1816 to form patterned hard mask layer 1838. The patterned hard mask layer 1838 exposes portions of the line region 1814 of the patterned interlayer dielectric layer 1812 and portions of the patterned hard mask 1810. That is, while the patterned hard mask layer 1838 exposes a wider area than the line region 1814 of the patterned interlayer dielectric layer 1812, the patterned hard mask 1810 protects the patterned interlayer dielectric layer 1812 outside of the line region 1814. "Exposed" area. The pattern of patterned hard mask layer 1838 of the structure of FIG. 18S is then transferred to patterned interlayer dielectric layer 1812 to form secondary patterned interlayer dielectric layer 1840 and expose etch stop layer 1806, as depicted in FIG. 18T. However, in one embodiment, the patterned hard mask 1810 disables the overall transfer pattern, as also depicted in FIG. 18T. In one embodiment, the pattern of the patterned hard mask layer 1838 is transferred to the patterned interlayer dielectric layer 1812 by an etch process that uses the etch stop layer 1806 as a termination point.

Referring to FIG. 18U, the exposed portions of the etch stop layer 1806 of the structure of FIG. 18T are removed to form a patterned etch stop layer 1842 and expose the via locations 1844 of the metal lines 1802. The patterned etch stop layer 1836, patterned hard mask layer 1838, and patterned hard mask 1810 of the structure of FIG. 18U are then removed, as depicted in FIG. 18V. The removal exposes the secondary patterned interlayer dielectric layer 1840 and via location 1844 of the metal line 1802, and the location 1846 of the upper metal line. In one embodiment, the patterned etch stop layer 1836, the patterned hard mask layer 1838, and the patterned hard mask 1810 are removed using a selective wet etch process.

Referring to Figure 18W, the upper metallization layer is formed in the structure of Figure 18V. In particular, a metal fill process is performed to provide metal vias 1848 and metal lines 1850. In one embodiment, the metal fill process is performed using metal deposition and subsequent planarization processing schemes, such as chemical mechanical planarization (CMP) processes. In one embodiment, the surface of the structure of FIG. 18W is substantially identical to the surface of the starting structure 1800 of FIG. 18A (although orthogonal thereto). Thus, in one embodiment, the process described with respect to Figures 18B-18W can be repeated on the structure of Figure 18W to form the next metallization layer, and so on.

The resulting structure, such as those associated with FIG. 18W, can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 18W can represent the last metal interconnect layer in the integrated circuit. It should be understood that the above-described process operations can be performed in an alternate order, not every operation needs to be performed and/or additional process operations can be performed. It should also be understood that the above examples have focused on the formation of vias/contacts. However, in other embodiments, a similar manner can be used to preserve or form regions for line end terminations (plugs) within the wire layer.

Grid-based vias and plug patterning are described in accordance with embodiments of the present invention. One or more embodiments described herein relate to grid self-aligned and super-self-aligned metal via processing schemes. Embodiments described herein can be implemented to provide a self-aligned method for a metal/via layer. Almost all plug and via geometry is made possible by implementing the methods described herein. In addition, the final via critical dimension (CD) can be independently self-imaged for lithography. Furthermore, the manner described herein provides a "cyclic flow" since the end of the process flow has the same or substantially the same layer stack and layout as the beginning of the process flow. Thus, once each operation in the process stream is completed, the process stream can be repeated as many times as needed to add as many metal/via layers as desired. In one or more embodiments, the overlap between the vertical grids is used to define the layout of the vias and metal lines. The size of the through hole can be determined by an overlapping area between the two grids.

In order to provide a background for the embodiments described below, the manner described herein provides almost any plug and via layout available, as is currently known in the art for via self-alignment. The manner described herein may require less selective etching. The manner described herein provides a final plug and via CD that is independent of the lithography utilized. Next, in one aspect, one or more of the embodiments described herein relate to a manner in which the underlying metal grating structure is used to create a template for overlying conductive vias. It should be understood that a similar manner can be implemented to create a non-conductive spacing or interruption between metals (plugs).

In the example processing scheme, FIGS. 19A-19L illustrate a plan view (top portion of the graph) and a corresponding oblique cross-sectional view (lower portion of the graph) representing a grid for a back end of line (BEOL) interconnect. Each of the operations in the self-aligned metal via processing scheme is in accordance with an embodiment of the present invention. It should be understood that although this is not the case, different metallization layers are shown as separate (upper and lower) views in a beveled cross-sectional view for clarity.

Referring to Figure 19A, a starting point structure 1900 is provided as a starting point for making a new metallization layer. The starting point structure 1900 includes an array of alternating metal lines 1902 and dielectric lines 1904. Metal line 1902 is recessed below dielectric line 1904. The hard mask layer 1906 is disposed over the metal lines 1902 and alternately disposed with the dielectric lines 1904. In one embodiment, the dielectric line 1904 is composed of tantalum nitride (SiN), and the hard mask layer 1906 is composed of tantalum carbide (SiC) or tantalum oxide (SiO ₂ ). The next patterned layer 1908 is then fabricated over the starting point structure 1900, as depicted in Figure 19B. In one embodiment, the next patterned layer 1908 includes an etch stop layer 1910, a dielectric layer 1912, and a grating structure 1914. In one embodiment, the etch stop layer 1910 is composed of yttrium oxide (SiO), the dielectric layer 1912 is composed of tantalum nitride (SiN), and the grating structure 1914 is composed of yttrium oxide (SiO). In one embodiment, the grating structure 1914 is formed using a pitch halving or pitch reduction to a quarter (eg, by spacer patterning).

Referring to FIG. 19C, the pattern of grating structures 1914 is transferred to dielectric layer 1912 to form patterned dielectric layer 1916. In one embodiment, the pattern of the grating structure 1914 is transferred to the dielectric layer 1912 using an etch process that utilizes the etch stop layer 1910 as the end point of the etch process. A through etch is then performed to remove the exposed portions of the etch stop layer 1910 to form a patterned etch stop layer 1918, as depicted in Figure 19D. In an embodiment, through etching reveals that it can potentially be formed into all possible via locations 1920 in structure 1900.

Referring to Figure 19E, the plug patterning is then performed by forming a patterned hard mask 1922 on the structure of Figure 19D (in a position where the plug is to be retained). The joint pattern of patterned hard mask 1922 and grating structure 1914 is then transferred into structure 1900 to form structure 1900' having regions 1924 for metal line formation within structure 1900, as depicted in Figure 19F. In one embodiment, the joint pattern of the patterned hard mask 1922 and the grating structure 1914 is transferred into the structure 1900 using an etching process. This etch process can etch both layers 1904 and 1906 at substantially the same rate (or can be implemented as a number of etch operations) and can be followed by a cleaning process to remove the patterned hard mask 1922, as also shown. Depicted in 19F.

Referring to Figure 19G, via patterning is then performed by forming a patterned lithographic mask 1926 on the structure of Figure 19F, which exposes the location in which the vias are to be formed ( For example, the through hole selection process). The joint pattern of patterned lithography mask 1926 and grating structure 1914 is then transferred into structure 1900' to form structure 1900" having a region 1928 for metal via formation in structure 1900', as depicted in Figure 19H. In one embodiment, the combined pattern of patterned lithography mask 1926 and grating structure 1914 is transferred into structure 1900' using an etch process. This etch process can selectively etch layer 1906 for layer 1904, and A cleaning process for removing the patterned lithographic mask 1926 can be continued, as also depicted in Figure 19H.

Referring to Figure 19I, a metal fill process is performed on the structure of Figure 19I to provide a lower structure 1930. The metal filling process forms metal vias 1932 and metal lines 1934 in structure 1930. The metal fill process can also fill the region between the grating structure 1914 and the metal line 1936, as depicted in Figure 19I. In one embodiment, the metal fill process is performed using metal deposition and subsequent planarization processing schemes. The structure of FIG. 19I can then be reduced in thickness to remove the grating structure 1914 to expose the patterned dielectric 1916 and the top providing metal line 1938, which reduces its thickness from the metal line 1936, as depicted in FIG. 19J. In one embodiment, the structure of FIG. 19I can then be reduced in thickness using a planarization process, such as a chemical mechanical planarization (CMP) process.

Referring to Figure 19K, metal line 1938 is removed from the structure of Figure 19J to leave patterned dielectric layer 1916 and patterned etch stop layer 1918. Metal line 1938 can be removed by a selective etch process that removes metal line 1938 and also ensures that it has no metal remaining above the height of material layers 1904 and 1906 (ie, causing It has no metal remaining on the plug region of structure 1930). A hard mask layer 1940 is then formed over the structure of Figure 19K between the lines of patterned dielectric layer 1916, as depicted in Figure 19L. In one embodiment, the hard mask layer 1940 is comprised of tantalum carbide (SiC) or tantalum oxide (SiO ₂ ) and is formed using a deposition and planarization process. In one embodiment, the hard mask layer 1940 is comprised of the same material as the hard mask layer 1906. In one embodiment, the surface of the structure formed from patterned dielectric layer 1916 and hard mask layer 1940 is substantially identical to the surface of the starting structure 1900 of FIG. 19A (although orthogonal thereto). Thus, in one embodiment, the process described in conjunction with Figures 19B-19L can be repeated on the structure of Figure 19L to form the next metallization layer, and so on.

It should be understood that the process described with respect to Figures 19B-19L (such as repeated on the structure of Figure 19L to form the next metallization layer) may be referred to as a cyclic process since the end of the process flow has the same as the beginning of the process flow. Or substantially the same layer stacking and layout. In one embodiment, forming an additional metallization layer includes using this one-cycle process. However, it should also be understood that the cyclic or iterative process can only be implemented on selected metallization layers. Other metallization layers in the resulting stack (e.g., layers above or below or between layers made using the processing schemes of Figures 19B-19L) can be fabricated using conventional dual damascene or other means.

The resulting structure, such as 1931 as described in association with Figure 19L, can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, structure 1931 of Figure 19L may represent the last metal interconnect layer in the integrated circuit. It should also be understood that in subsequent manufacturing operations, the dielectric lines can be removed to provide an air gap between the resulting metal lines. It should be understood that the above examples have focused on via/contact formation. However, in other embodiments, a similar manner can be used to preserve or form regions for line end terminations (plugs) within the wire layer.

In accordance with embodiments of the present invention, grating-based vias and plug patterns are described. One or more embodiments described herein relate to grating-based plugs and cuts for feature end formation. Embodiments may involve one or more of lithographic patterning, associated line end CD generation, and spacer based patterning. Embodiments utilize methods to produce plugs and cuts with layout control and uniformity of one-dimensional (1D) features. It should be understood that there is a trade-off between better control for the wire end (plug) or via layout, suggesting that the through hole and the wire end are placed in more restricted positions.

In order to provide a background for the embodiments described herein, in order to enable the patterning of tighter pitch features in semiconductor fabrication, gratings and plugs or gratings and cutting methods are applied to more layers. As feature sizes continue to shrink, the ability to toughly pattern cuts and plugs may limit expansion and yield. The dicing and plug features are typically defined directly by a lithography operation having primarily two-dimensional (2D) features. These 2D features have much higher variations and non-uniformities than one-dimensional (1D) features.

Referring to Figures 20A-20G, described below, in one embodiment, an overview of a simplified patterning process for creating a grating-defining plug is presented. The sacrificial 1D pattern is produced to be orthogonal to the main direction of the layer in which it is patterned. The selection mask is then used to cut or save portions of the 1D pattern that will ultimately be used to cut or preserve portions of the primary grating. The final edge of the cut/save on the primary pattern is thus defined by the edges of the 1D sacrificial grating with much better control and uniformity. 20A-20G illustrate a plan view (top) and corresponding cross-sectional views (middle and bottom) showing a method of fabricating a grating-based plug and cutting for forming a characteristic end of a back end of line (BEOL) interconnect. Each of the operations is in accordance with an embodiment of the present invention.

Referring to Figure 20A, a starting point structure 2000 is provided as a starting point for making a new metallization layer. The starting point structure 2000 includes an interlayer dielectric (ILD) material layer 2002 having a first hard mask layer 2004 formed thereon. A second hard mask layer 2006 is formed on the first hard mask layer 2004. The second hard mask layer 2006 has a grating pattern that can be considered as a predominantly one-dimensional (1D) grating pattern. In one embodiment, the grating pattern of the second hard mask 2006 is ultimately used to define the 1D position of the last layer that it will be patterned but does not yet have the end of the feature location that is patterned therein. The first hard mask layer 2004 and/or the second hard mask layer 2006 may be fabricated from a material such as, but not limited to, tantalum nitride (SiN), tantalum oxide (SiO ₂ ), titanium nitride (TiN) ), or 矽 (Si). In one embodiment, the first hard mask layer 2004 and the second hard mask layer 2006 are fabricated from materials different from each other.

Referring to FIG. 20B, a third hard mask layer 2008 is formed on the structure of FIG. 20A. In one embodiment, the third hard mask layer 2008 has a grating pattern that can be considered as a predominantly one-dimensional (1D) grating pattern that is orthogonal to the 1D grating pattern of the second hard mask layer 2006. The third hard mask layer 2008 can be fabricated from a material such as, but not limited to, tantalum nitride (SiN), tantalum oxide (SiO ₂ ), titanium nitride (TiN), or germanium (Si). In one embodiment, the third hard mask layer 2008 is fabricated from a material that is different from the materials of the first hard mask layer 2004 and the second hard mask layer 2006. It should be understood that any of the above hard mask layers may actually comprise a plurality of sub-layers, for example, to provide improved etch selectivity.

In one embodiment, the grating pattern of the third hard mask layer 2008 and the grating pattern of the second hard mask layer 2006 together define all of the allowable line end positions for the metallization layer of the metal line. In one such embodiment, the grating pattern of the third hard mask layer 2008 and the grating pattern of the second hard mask layer 2006 together define a line end position at a position where the lines of the grating patterns overlap. In another such embodiment, the grating pattern of the third hard mask layer 2008 and the grating pattern of the second hard mask layer 2006 together define a line in which the spacing is exposed to the position between the lines of the grating patterns. End position.

Referring to Figure 20C, the area of the lithographic patterned mask 2010 is formed on the structure of Figure 20B. The area of the lithographic patterned mask 2010 can be formed from a photoresist layer or multiple layers, or a similar lithographic patterned mask. In one embodiment, the region of the lithographic patterned mask 2010 provides a pattern of dicing/storage regions on the sacrificial grating formed from the second hard mask layer 2006 and the third hard mask layer 2008. Next, in one embodiment, the lithography process is used to select the (cut or save) portion of the sacrificial grating that will ultimately define the end position of the main pattern of the metal lines. In one such embodiment, 193 nm or EUV lithography is used, along with etching of the resist pattern, into the underlying layer prior to etching the sacrificial grating pattern. In one embodiment, the lithography process involves multiple exposure or deposition/etch/deposition repeat processing of the resist layer. It should be understood that the shadowing zone may be referred to as a cutting or holding location in which orthogonal grating overlap zones or spaces between the gratings are used to define the plug (or possibly through hole) location.

Referring to FIG. 20D, the region of the lithographic patterned mask 2010 using the structure of FIG. 20C is a mask, and the third hard mask layer 2008 is selectively etched to form a patterned hard mask layer 2012. That is, a portion of the sacrificial grating is etched to occupy portions of the pattern of the regions of the lithographic patterned mask 2010 that protect a portion of the self-etching process of the third hard mask layer 2008. In one embodiment, the portion of the third hard mask layer 2008 that was removed during the etching process is not part of the final target design. In one embodiment, the regions of the lithographic patterned mask 2010 are removed after forming the patterned hard mask layer 2012, as depicted in Figure 20D.

Referring to FIG. 20E, the combined pattern formed by the second hard mask layer 2006 and the patterned hard mask layer 2012 of the structure of FIG. 20D is transferred into the first hard mask layer 2004 and transferred into the ILD material layer 2002, for example, By selective etching process. The patterning forms a patterned ILD layer 2014 and a patterned hard mask layer 2016.

Referring to FIG. 20F, the patterned hard mask layer 2012 and the second hard mask layer 2006 (ie, the sacrificial grating) of the structure of FIG. 20E are subsequently removed. The patterned hard mask layer 2016 can be left at this stage, as depicted in Figure 20F, or can be removed. Selective wet or dry processing techniques can be utilized for the removal of the patterned hard mask layer 2012 and the second hard mask layer 2006 (and, possibly, the patterned hard mask layer 2016). It should be understood that the resulting structure of FIG. 20F can be subsequently used as the starting point for metal filling with the option of first removing the remaining patterned hard mask layer 2016. Which would define the end position (line end) of the metal feature from the edge of the 1D sacrificial grating that it was transferred into the ILD material layer 2002, and thus was well controlled.

Referring to FIG. 20G, a metal fill process is performed on the structure of FIG. 20F to form metal lines 2018 in the openings of patterned ILD layer 2014. The metal lines have line ends formed by interruptions in continuity formed in the patterned ILD layer 2014. In one embodiment, the metal fill process is performed by depositing and then planarizing one or more metal layers over the patterned ILD layer 2014. The patterned hard mask layer 2016 can be retained during the metal deposition process and then removed during the planarization process, as depicted in Figures 20F and 20G. However, in other embodiments, the patterned hard mask layer 2016 is removed prior to the metal fill process. In still other embodiments, the patterned hard mask layer 2016 is retained in the final structure. Referring again to FIG. 20G, it should be understood that the metal lines 2018 can be formed over features such as conductive vias 2020 shown as examples.

The resulting structure, such as those described in association with Figure 20G, can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 20G can represent the last metal interconnect layer in the integrated circuit. It should be understood that the above-described process operations can be performed in an alternate order, not every operation needs to be performed and/or additional process operations can be performed. In one embodiment, the deviation from conventional lithography/dual damascene patterning (which is otherwise tolerated) will not be a factor in the resulting structure described herein. It should be understood that the above examples have focused on the formation/retention of the wire end/plug/cut. However, in other embodiments, a similar manner can be used to form vias/contacts above or below the metal line layer. It should also be understood that in subsequent manufacturing operations, the dielectric lines can be removed to provide an air gap between the resulting metal lines.

Referring again to Figures 20A-20G, in one embodiment, a patterning process for creating a grating-defining plug has been described. Advantages of this embodiment may include better dimensional control of the end-to-end feature, which reduces the chance of an end-to-end short circuit (production failure) otherwise observed under worst-case process variations. The enhanced dimensional control of the end-to-end features provides more areas under worst-case process variations (for via seating and coverage). Thus, in one embodiment, the enhanced electrical connection can be achieved from layer to layer with increased throughput and product performance. Enhanced dimensional control of the end-to-end features can result in a smaller end-to-end width, and thus, a better product density (cost per function) can be achieved.

In an embodiment, an embodiment of the invention has the advantage that all of its line end positions are defined by a single lithography operation. For example, when the plug/cut pitch becomes extremely small, a common solution is to use a multi-pass lithography with additional processing to create a composite plug/cut pattern. Conversely, in the embodiments described herein, the feature end position is a function of most lithography operations and, therefore, has a lower limit than when a single lithography operation is used to define the end of the feature (as in the case of the embodiments described herein). A bigger change.

In accordance with an embodiment of the present invention, a wire end cutting method is described. One or more embodiments described herein relate to techniques for patterning metal wire ends. Embodiments may include the form of one or more of contact fabrication, damascene processing, dual damascene processing, interconnect fabrication, and metal line trench patterning.

To provide a background, in advanced nodes in semiconductor fabrication, low-order interconnects are created by separate patterning processes for line gratings, line ends, and vias. The fidelity of the composite pattern tends to decrease as the through hole on the line end encroaches, and vice versa. The embodiments described herein provide a line end process, also known as a plug process, which eliminates the associated approximation rules. Embodiments may allow the through holes to be placed on the wire ends and the large through holes to cover the wire ends.

To provide a further background, Figure 21A illustrates a plan view of a metallization layer of a conventional semiconductor device and corresponding cross-sectional views taken along the a-a' axis of the plan view. Figure 21B illustrates a cross-sectional view of a wire end or plug made using a currently known treatment scheme. Figure 21C illustrates another cross-sectional view of a wire end or plug made using a currently known treatment scheme.

Referring to FIG. 21A, metallization layer 2100 includes metal lines 2102 formed in dielectric layer 2104. Metal line 2102 can be coupled to lower via 2103. Dielectric layer 2104 can include a wire end or plug region 2105. Referring to FIG. 21B, a conventional wire end or plug region 2105 of dielectric layer 2104 can be fabricated by patterning hard mask layer 2110 on dielectric layer 2104 and then etching exposed portions of dielectric layer 2104. The exposed portion of dielectric layer 2104 can be etched to a depth suitable to form line trench 2106 or further etched to a depth suitable to form via trench 2108. Referring to FIG. 21C, two vias adjacent the wire ends or opposite sidewalls of the plug 2105 can be fabricated in a single large exposure 2116 to ultimately form the wire trench 2112 and the via trench 2114.

However, referring again to Figures 21A-21C, fidelity issues and/or hard mask erosion problems may result in imperfect patterned states. Conversely, one or more embodiments described herein include an embodiment of a process flow involving the construction of a line-end dielectric (plug) (after trench and via patterning processes). In an exemplary processing scheme, FIGS. 21D-21J illustrate cross-sectional views showing various operations in a process for patterning metal line ends of a back end of line (BEOL) interconnect, in accordance with an embodiment of the present invention.

Referring to FIG. 21D, a method of fabricating a metallization layer for an interconnect structure of a semiconductor die includes forming a line trench 2128 over an upper portion of an interlayer dielectric (ILD) material layer 2126 formed over the underlying metallization layer 2120. (above the lower part 2130). The lower metallization layer 2120 includes metal lines 2122 disposed in the dielectric layer 2124.

Referring to Figure 21E, via trenches 2132A and 2132B are formed in portion 2130 below ILD material layer 2126 to form patterned lower portion 2130' of ILD material layer 2126. As an example embodiment, via trench 2132A exposes two metal lines 2122 of underlying metallization layer 2120, while via trench 2132B exposes one metal line 2122 of underlying metallization layer 2120.

Referring to Figure 21F, a sacrificial material 2134, such as a matrix material, is formed over the ILD material layer (portion 2130' shown in Figure 21F) and in the trench 2128 and via trenches 2132A and 2132B. In one embodiment, a patterned hard mask layer 2136 is formed over the sacrificial material 2134, as depicted in Figure 21F.

Referring to FIG. 21G, the sacrificial material 2134 is patterned to form an opening (left-hand opening of FIG. 21G) exposed between the two metal lines 2122 of the underlying metallization layer 2120 associated with the via trench 2132A of FIG. 21E. Part of the lower metallization layer 2120. In the illustrated exemplary embodiment, the sacrificial material 2134 is further patterned to form an opening (the right-hand side opening of FIG. 21G) that exposes the patterned lower portion 2130 of the ILD material layer adjacent the via trench 2132B of FIG. 2E. 'part. In one embodiment, the sacrificial material 2134 is patterned by transferring the pattern of the patterned hard mask 2136 to the sacrificial material 2134 (by an etching process).

Referring to Figure 21H, the opening of the sacrificial material 2134 (now shown as patterned and filled with sacrificial material 2134') is filled with dielectric material 2138. In one embodiment, the opening of the sacrificial material 2134 is filled with a dielectric material 2138 using a deposition process selected from the group consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD). In one embodiment, the opening of the sacrificial material 2134 is filled with a dielectric material 2138 comprised of a first dielectric material. In one such embodiment, the ILD material layer 2126 includes a second dielectric material comprised of a different composition than the first dielectric material. However, in another such embodiment, the ILD material layer 2126 is comprised of a first dielectric material.

Referring to Figure 21I, the filled sacrificial material 2134' is removed to provide dielectric plugs 2140A and 2140B. In the illustrated exemplary embodiment, dielectric plug 2140A is disposed on a portion of lower metallization layer 2120 between two metal lines 2122 of lower metallization layer 2120. The dielectric plug 2140A is adjacent to the via trench 2132A and the trench 2128', and (in the case shown in FIG. 21I) between the substantially symmetric via trench 2132A and the trench 2128' . Dielectric plug 2140B is disposed on a portion of patterned lower portion 2130' of ILD material layer 2126. The dielectric plug 2140 is adjacent to the via trench 2142B and the corresponding line trench (the right hand side of the dielectric plug 2140B). In one embodiment, the structure of FIG. 21H is subjected to a planarization process for removing the overload region of the dielectric material 2138 (the region above and above the surface on either side of the trench) for The patterned hard mask 2136 is removed and used to reduce the height of the sacrificial material 2134' and portions of the dielectric material 2138 therein. The sacrificial material 2134' is then removed by using a selective wet or dry process etch technique.

Referring to Fig. 21J, the line trench 2128' and the via trenches 2132A and 2132B are filled with a conductive material. In one embodiment, the fill line trenches 2128' and the via trenches 2132A and 2132B are formed of a conductive material to form metal lines 2142 and conductive vias 2144 in the patterned dielectric layer 2130'. In the exemplary embodiment, with reference to plug 2140A, first metal line 2142 and first conductive via 2144 are directly adjacent to the left hand side wall of dielectric plug 2140A. The second metal line 2142 and the second conductive via 2144 are directly adjacent to the right hand side wall of the dielectric plug 2140A. Referring to the plug 2140B, the first metal line 2142 is directly adjacent to the right-hand side wall of the dielectric plug 2140B, and the lower portion of the patterned lower portion 2130' of the ILD layer is directly adjacent to the first conductive via 2144 . However, on the left hand side of the dielectric plug 2140B, only the metal line 2142 (rather than the associated conductive via) is associated with the dielectric plug 2140B. In one embodiment, the metal fill process is performed by depositing and then planarizing one or more metal layers over the structure of FIG.

Referring again to Figure 21J, several different embodiments may be shown using the illustrations. For example, in one embodiment, the structure of Figure 21J represents the final metallization layer structure. In another embodiment, the dielectric plugs 2140A and 2140B are removed to provide an air gap structure. In another embodiment, the dielectric plugs 2140A and 2140B are replaced with another dielectric material. In another embodiment, the dielectric plugs 2140A and 2140B can be sacrificial patterns that are ultimately transferred to another underlying interlayer dielectric material layer.

In an exemplary embodiment, referring again to FIG. 21J (and previous processing operations), the metallization layer for the interconnect structure of the semiconductor die includes a metal line 2142 disposed in the trench of the interlayer dielectric (ILD) material layer 2126. In slot 2128'. The ILD material layer 2126 is comprised of a first dielectric material. Conductive vias 2144 are disposed in the ILD 2126 material layer, under metal lines 2142 and electrically connected to metal lines 2142. The dielectric plug 2140A (or 2140B) is directly adjacent to the metal line 2142 and the conductive via 2144. The second metal line 2142 and the conductive via 2144 may also be directly adjacent to the dielectric plug (eg, dielectric plug 2140A). In one embodiment, the dielectric plug 2140A (or 2140B) is comprised of a second dielectric material that is different from the first dielectric material.

It should be understood that filling the opening of the sacrificial material 2134 with a dielectric material can result in the formation of a seam in the dielectric material that is approximately the center of the resulting dielectric plug. For example, Figure 21K illustrates a cross-sectional view of a metallization layer of an interconnect structure of a semiconductor die including a dielectric line end or plug having a seam therein, in accordance with an embodiment of the present invention.

Referring to Figure 21K, the metallization layer of the interconnect structure of the semiconductor die includes metal lines 2140 disposed in the trenches of the interlayer dielectric (ILD) material layer (shown below portion 2130'). Conductive vias 2144 are disposed in ILD material layer 2130', below metal lines 2142 and electrically connected to metal lines 2142. Dielectric plugs 2152A and 2152B are directly adjacent to metal line 2142 and conductive via 2144. Dielectric plugs 2152A and 2152B each include a seam 2150 that is approximately the center of the dielectric plug, for example, may facilitate deposition of a dielectric plug by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

It should be understood that the wire end or plug may be associated with a wire that does not have a lower via adjacent the dielectric plug. For example, Figure 21L illustrates a cross-sectional view of a metallization layer of an interconnect structure of a semiconductor die including dielectric line ends or plugs that are not in close proximity to the conductive vias, in accordance with an embodiment of the present invention. Referring to Figure 21L, the dielectric plug 2152 is associated with a metal line 2142 that does not have a lower via (such as via 2144) that is adjacent to the dielectric plug 2152 (and over the associated patterned dielectric layer 2154').

The resulting structure, such as those associated with FIG. 21J, FIG. 21K, or FIG. 21L, can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of FIG. 21J, FIG. 21K or FIG. 21L may represent the last metal interconnect layer in the integrated circuit. In one embodiment, the deviation due to conventional lithography/dual damascene patterning (which is otherwise tolerated) is mitigated for the resulting structure described herein. It should also be understood that in subsequent manufacturing operations, the dielectric layer can be removed to provide an air gap between the resulting metal lines.

Self-aligned etching of preformed vias and plugs is described in accordance with an embodiment of the present invention. One or more embodiments described herein relate to self-aligned vias and plug patterns. The self-aligned morphology of the procedures described herein can be based on a directed self-polymerization (DSA) mechanism, as described in more detail below. However, it should be understood that its selective growth mechanism can be utilized to replace (or bind to) a DSA based approach. In one embodiment, the procedures described herein enable the implementation of self-aligned metallization for the fabrication of back-end process features.

Embodiments described herein may be directed to a self-aligned isotropic etch process for pre-formed vias or plugs (or both). For example, the processing scheme may involve the preforming of each possible via and plug in a metallization layer, such as a semiconductor structure back-end metallization layer. The lithography is then utilized to select a particular via and/or plug location to be turned on/off (eg, saved/removed). Embodiments of the embodiments described herein may relate to the use of such an etch scheme to form all of the vias/plugs in the optical barrel configuration for each respective via/metal layer in the metallization stack. As will be understood, the vias can be formed in a layer different from the layer in which the plug is formed (eg, the latter is formed in a metal line layer perpendicular to the via layer), or a plug And vias can be formed in the same layer.

One or more embodiments described herein provide a more efficient way to pattern by maximizing overlapping process windows, minimizing the size and shape of the desired pattern, and adding holes or plugs for patterning. The efficiency of the lithography process. In a more specific embodiment, the pattern used to open the pre-formed vias or plug locations can be formed to be relatively small, enabling an increase in the overlap tolerance of the lithography process. The pattern features can be made of a uniform size that reduces the scan time for direct writing of the electron beam and/or the optical proximity correction (OPC) complexity with optical lithography. The pattern features can also be formed to be shallow, which can enhance the patterning resolution. The subsequent etch process can be an isotropic chemiselective etch. This etch process mitigates the associated contours and critical dimensions and alleviates the anisotropy problems typically associated with dry etch methods. This etching process is also relatively cheaper (from the standpoint of equipment and throughput) compared to other selective removal methods.

As an exemplary general processing scheme, FIGS. 22A-22G illustrate portions of an integrated circuit layer that represent various operations in a method of self-aligned isotropic etching that pre-forms vias or plug locations, in accordance with the present invention. Example. In each of the illustrated operations, a plan view is shown on the left hand side and a corresponding cross-sectional view is displayed on the right hand side. These views will be referred to herein as corresponding cross-sectional views and plan views.

Figure 22A illustrates a plan view and corresponding cross-sectional view (taken along the a-a' axis) of the pre-patterned starting structure following the holes/grooves 2204 in the substrate or layer 2202. In one embodiment, the substrate or layer 2202 is an interlayer dielectric (ILD) material layer.

Although not depicted for simplicity, it should be understood that the apertures/trench 2204 may expose features such as underlying metal lines. Still further, in an embodiment, the starting structure can be patterned in a grating-like pattern having holes/grooves 2204 spaced at a constant pitch and having a constant width. The pattern can be manufactured, for example, by halving the pitch or reducing the pitch by a quarter. Where the via layer is fabricated, certain holes/grooves 2204 can be associated with lower lower metallization lines.

Figure 22B illustrates a plan view and corresponding cross-sectional view (taken along the b-b' axis) subsequent to the structure of Figure 22A after filling the holes/grooves 2204 with the sacrificial or permanent footprint 2206. The ILD material can be used to fill the holes/grooves 2204 where it uses a permanent placeholder material. In the case where it uses a sacrificial placeholder material, it provides more flexibility in design choices. For example, in one embodiment, a material that will not otherwise be suitable for retention in the final structure, such as a structurally weak polymer or a soft photoresist material, can be used. As depicted in the cross-sectional view of FIG. 22B, the formation of a small number of depressions 2208 of the sacrificial or permanent placeholder material 2206 in the holes/grooves 2204 can be included to aid in subsequent processing. In one embodiment, the sacrificial or permanent footprint material 2206 is a spin-on dielectric material.

Figure 22C illustrates a plan view and corresponding cross-sectional view (taken along the c-c' axis) of the structure of Figure 22B following the formation of the patterned layer 2210. In one embodiment, the patterned layer 2210 is a photosensitive material, such as a positive tone photoresist layer. In another embodiment, the patterned layer 2210 is an anti-reflective coating material. In one embodiment, the patterned layer 2210 includes a stack of material layers including one or more layers of photosensitive material and/or one or more layers of anti-reflective coating material.

Figure 22D illustrates a plan view and corresponding cross-sectional view (taken along the d-d' axis) of the structure of Figure 22C following patterning of patterned layer 2210 to form opening 2212 in patterned layer 2210. Referring to Figure 22D, opening 2212 exposes a lower portion of sacrificial or permanent placeholder material 2206. In particular, the opening 2212 exposes the lower portion of the sacrificial or permanent footprint 2206 only on the holes/grooves 2204 in which the vias or plugs are selected to be formed. In one embodiment, the opening 2212 in the patterned layer 2210 is substantially smaller than the exposed holes/trench 2204. As described briefly above, its relatively smaller formation than the opening 2212 of the exposed aperture/groove 2204 provides a significantly increased tolerance for misalignment problems. In one embodiment, the patterned layer 2210 is a photosensitive material, and the opening 2212 is formed by a lithography process such as a positive tone lithography process.

Figure 22E illustrates a plan view and corresponding cross-sectional view of the structure of Figure 22D following the removal of the sacrificial or permanent placeholder material 2206 in a position exposed by the opening 2212 to form the re-exposed hole/groove 2214. Take the e-e' axis.) In one embodiment, the sacrificial or permanent footprint material 2206 is removed by an isotropic etch process. In one such embodiment, the isotropic etch process involves the application of a wet etchant. A wet etchant is passed through the opening 2212 to access and etch the sacrificial or permanent footprint material 2206. The etch process is isotropic, as material that is not exposed by opening 2212 (but accessible through opening 2212) can be etched to selectively formed re-exposed holes/grooves 2214 for through holes or The plug is formed in the desired position. In one embodiment, the wet etch process etches the sacrificial or permanent footprint material 2206 without etching (or not substantially etching) the patterned layer 2210.

In one embodiment, the sacrificial or permanent placeholder material 2206 is a spin-on carbon hard mask material and the etch process is a TMAH based etch process. In another embodiment, the sacrificial or permanent footprint material 2206 is a spin-on bottom anti-reflective coating (BARC) material and the etching process is a TMAH-based etching process. In another embodiment, the sacrificial or permanent footprint material 2206 is a spin-on bottom glass material and the etching process is a wet etching process based on an organic solvent, acid or base. In another embodiment, the sacrificial or permanent footprint material 2206 is a spin-on metal oxide material and the etching process is a wet etch process according to commercially available cleaning chemistries. In another embodiment, the sacrificial or permanent footprint material 2206 is a CVD carbon material and the etching process is an etch process based on oxygen plasma ash.

Figure 22F illustrates a plan view and corresponding cross-sectional view (taken along the f-f' axis) of the structure of Figure 22E following removal of the patterned layer 2210. In one embodiment, the patterned layer 2210 is a photoresist layer, and the photoresist layer is removed by a wet removal or plasma ashing process. Removal of the patterned layer 2210 completely exposes the re-exposed apertures/grooves 2214.

Figure 22G illustrates a plan view and corresponding cross-sectional view (taken along the g-g' axis) of the structure of Figure 22F following the filling of the re-exposed holes/trench 2214 with the material layer 2216 and subsequent planarization. In one embodiment, the material layer 2216 is used to form a plug and is a permanent ILD material. In another embodiment, the material layer 116 is used to form a conductive via and is a metal fill layer. In one such embodiment, the metal fill layer is a single material layer or is formed from several layers, including a conductive backing layer and a fill layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, can be used to form this metal fill layer. In one embodiment, the metal fill layer is composed of a conductive material such as, but not limited to, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au. Or its alloy. In the case where the material layer 116 is planarized (continuous after deposition), a chemical mechanical polishing process can be used.

In one embodiment, material layer 2216 is a material suitable for forming conductive vias. In one such embodiment, the sacrificial or permanent placeholder material 2206 is a permanent placeholder material, such as a permanent ILD material. In another such embodiment, the sacrificial or permanent placeholder material 2206 is a sacrificial placeholder material that is subsequently removed and replaced with a material such as a permanent ILD material. In another embodiment, material layer 2216 is a material suitable for forming a dielectric plug. In one such embodiment, the sacrificial or permanent footprint material 2206 is a sacrificial footprint material that is subsequently removed or partially removed to enable metal wire formation.

It should be understood that the resulting structure of Figure 22G can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 22G can represent the last metal interconnect layer in the integrated circuit. Again, it should be understood that the above examples do not include an etch stop or metal capping layer in the pattern, which may otherwise be required for patterning. However, for clarity, these layers are not included in the drawing as it does not affect the overall concept.

In another aspect, the embodiment is directed to a process flow for performing an isotropic dry etch (along with a hole reduction process). In one such embodiment, a patterning scheme provides pinhole patterning in the mask layer, followed by filling all via locations with the organic polymer. As an example processing scheme, Figures 22H-22J illustrate oblique angle cross-sectional views of portions of an integrated circuit layer that illustrate various operations in a method of self-aligned isotropic etching that pre-forms via locations, According to an embodiment of the invention.

Figure 22H illustrates the starting structure following the filling of all possible via locations with the placeholder material. Referring to FIG. 22H, a metallization layer 2252, such as an ILD layer of a metallization layer, is formed over a substrate (not shown) and includes a plurality of metal lines 2254 therein. The ILD material (which may be two or more different ILD materials 2256 and 2258) is around the location where the vias may be formed. The sacrificial footprint material 2260 occupies a location in which all possible vias can be formed over the metal lines 2252. A mask layer 2262, such as a thin low temperature oxide mask layer, is formed on the underlying structure. It should be understood that the sacrificial footprint material 2260 does not appear on adjacent features, which may be accomplished by deposition and planarization or recess processes.

Figure 22I illustrates the structure of Figure 22H following the patterning of the mask layer 2262 to form the opening 2264 in the mask layer 2262. Referring to FIG. 22I, opening 2264 exposes a lower portion of sacrificial footprint 2260. In particular, the opening 2264 exposes the lower portion of the sacrificial footprint 2260 only at locations where the vias are selected to be formed. In one embodiment, the opening 2264 in the mask layer 2262 is substantially smaller than the exposed sacrificial footprint material 2260. As described briefly above, its relatively smaller formation than the opening 2264 of the exposed sacrificial footprint 2260 provides a significantly increased tolerance for misalignment problems. The process effectively "shrinks" the via position to the size of the "pinhole" for the selection and patterning of the actual via location. In one embodiment, the mask layer 2262 is patterned by the opening 2262 by first forming and patterning the photosensitive material on the mask layer 2262 by a lithography process (such as a positive tone lithography process), and The mask layer 2262 is then patterned by an etching process.

22J illustrates the structure of FIG. 22I following the removal of the sacrificial placeholder material 2260 in the location exposed by the opening 2264 to form the exposed via location 2266. In one embodiment, the sacrificial footprint material 2260 is removed at the via location 2266 by an isotropic etch process. In one such embodiment, the sacrificial footprint material 2260 is an organic polymer and the isotropic etch process is an isotropic plasma ash (oxygen plasma) or wet cleaning process.

Referring again to FIG. 22J, it should be understood that subsequent processing may involve removing the mask layer 2262 and filling the holes/trench 2266 with conductive via material. At the same time, the remaining sacrificial footprint material 2260 that is not exposed by the opening 2264 (ie, not selected as the via location) can be replaced with a permanent ILD material. The resulting structure can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the resulting structure can represent the last metal interconnect layer in the integrated circuit.

In accordance with one or more embodiments of the present invention, as described above, the manner described herein can be established in the use of so-called "light buckets" in which each possible feature (eg, a via or plug) is pre-patterned. Into the substrate. Next, the photoresist is filled into the patterned features and the lithographic operation is only used to select the selected vias for via opening. The light bucket mode allows for larger critical dimensions (CD) and/or errors in overlap while retaining the ability to select through holes or plugs of interest. The lithography used to select a particular light bucket may include, but is not limited to, 193 nm immersion lithography (i193), extreme ultraviolet (EUV), and/or electron beam direct writing (EBDW) lithography.

In summary, in accordance with one or more embodiments of the present invention, the DSA mode or subtractive mode is produced to be photosensitive. In one aspect, a form of light bucket is achieved in which the lithography limit can be relaxed and the misalignment tolerance can be high because the light barrel is surrounded by a non-photosolvable material. Further, in an embodiment, instead of exposure to, for example, 30 mJ/cm ² , the optical barrel may be exposed to, for example, 3 mJ/cm ² . Usually this will result in very poor CD control and roughness. In this case, however, CD and roughness control will be defined by the geometry of the barrel, which can be optimally controlled and defined. Thus, this light barrel approach can be used to prevent imaging/dosage tradeoffs, which limits the throughput of next generation lithography processes. In one embodiment, the optical barrel material that is not selected for removal is ultimately retained as a permanent ILD portion of the semiconductor structure. In another embodiment, the optical barrel material that is not selected for removal is ultimately exchanged to the permanent ILD portion of the semiconductor structure.

In one embodiment, the drum "ILD" composition is typically very different from the standard ILD, and (in one embodiment) is highly self-aligned in both directions. More generally, in one embodiment, the term light barrel as used herein relates to the use of ultrafast photoresist or electron beam resist or other photosensitive material, such as those formed in an etched opening. In this embodiment, thermal backfilling of the polymer entering the opening is followed by application after spin coating. In one embodiment, the fast photoresist is fabricated by removing the inhibitor from existing photoresist materials. In another embodiment, the light bucket is formed by an etch back process and/or a lithography/reduction/etch process. It should be understood that the light bucket need not be filled with the actual photoresist as long as the material acts as a photosensitive switch. In one embodiment, the lithography is used to expose the corresponding light bucket that it is selected for removal. However, the lithography limit can be relaxed and the misalignment tolerance can be high because the light barrel is surrounded by a non-photosolvable material. In one embodiment, the light bucket is exposed to extreme ultraviolet (EUV) light to expose the light bucket, wherein in a particular embodiment, the EUV is in the range of 5-15 nanometers. While many of the embodiments described herein relate to a light barrel material according to a polymer, in other embodiments, the light barrel material according to the nanoparticle is similarly implemented.

In accordance with an embodiment of the present invention, a light bucket mode is described. One or more embodiments described herein relate to a subtractive manner for self-aligned vias and plug patterning, and the resulting structure. In one embodiment, the procedures described herein enable the implementation of self-aligned metallization for the fabrication of back-end process features. The overlap problem expected for next generation via and plug patterning can be handled in one or more ways as described herein. More specifically, one or more of the embodiments described herein involve the use of a subtractive method to pre-form each via and plug using an etched trench. An additional operation is then used to select which vias and plugs to retain. These operations can be illustrated using a light bucket, although a more conventional resist exposure and ILD backfill can be used to perform the selection process.

In the first aspect, the through hole first and the second plug method are used. By way of example, Figures 23A-23L illustrate portions of an integrated circuit layer that represent various operations in a method of reducing self-aligned vias and plug patterning, in accordance with an embodiment of the present invention. In each of the illustrations of each of the operations, a cross-section and/or a beveled view is displayed. These views will be referred to herein as corresponding cross-sectional views and oblique views.

23A illustrates a cross-sectional view of the starting structure 2300 following deposition (but prior to patterning) of the first hard mask material layer 2304 formed over the interlayer dielectric (ILD) layer 2302, in accordance with an embodiment of the present invention. . Referring to Figure 23A, patterned mask 2306 has spacers 2308 formed on or over first hard mask material layer 2304 (along its sidewalls).

Figure 23B illustrates the structure of Figure 23A following the patterning of the first hard mask layer by doubling the pitch, in accordance with an embodiment of the present invention. Referring to FIG. 23B, the patterned mask 2306 is removed and the resulting pattern of spacers 2308 is transferred (eg, by an etch process) to the first hard mask material layer 2304 to form a first patterned hard mask 2310. In one such embodiment, the first patterned hard mask 2310 is formed in a grating pattern, as depicted in Figure 23B. In one embodiment, the grating structure of the first patterned hard mask 2310 is a tight pitch grating structure. In certain such embodiments, the tight pitch cannot be obtained directly through conventional lithography. For example, a pattern according to conventional lithography may be first formed (mask 2306), but the pitch may be halved by patterning using spacer masks, as depicted in Figures 23A and 23B. Even though not shown, the original pitch can be reduced to a quarter by the second round of spacer mask patterning. Thus, the grating-like pattern of the first patterned hard mask 2310 of Figure 23B can have a hard mask line that is separated by a constant pitch and has a constant width.

Figure 23C illustrates the structure of Figure 23B following the formation of the second patterned hard mask, in accordance with an embodiment of the present invention. Referring to FIG. 23C, a second patterned hard mask 2312 is formed to be interlaced with the first patterned hard mask 2310. In one such embodiment, the second patterned hard mask 2312 is formed by deposition of a second layer of hard mask material having a composition different from that of the first layer of hard mask material 2304. The second layer of hard mask material is then planarized (eg, by chemical mechanical polishing (CMP)) to provide a second patterned hard mask 2312.

Figure 23D illustrates the structure of Figure 23C following deposition of a hard mask cap layer in accordance with an embodiment of the present invention. Referring to FIG. 23D, a hard mask cap layer 2314 is formed on the first patterned hard mask 2310 and the first patterned hard mask 2312. In one such embodiment, the material composition and etch selectivity of the hard mask cap layer 2314 are different from the first patterned hard mask 2310 and the first patterned hard mask 2312.

Figure 23E illustrates the structure of Figure 23D following deposition of a hard mask cap layer, in accordance with an embodiment of the present invention. Referring to FIG. 23E, a patterned hard mask cap layer 2314 is formed on the first patterned hard mask 2310 and the first patterned hard mask 2312. In one such embodiment, the patterned hard mask cap layer 2314 is formed with a grating pattern orthogonal to the grating pattern of the first patterned hard mask 2310 and the first patterned hard mask 2312, as shown in the figure. Shown in 23E. In one embodiment, the grating structure formed by the patterned hard mask cap layer 2314 is a closely pitched grating structure. In this embodiment, the tight pitch cannot be obtained directly through conventional lithography. For example, a pattern according to a conventional lithography may be formed first, but the pitch may be halved by patterning using a spacer mask. Even the original pitch can be reduced to a quarter by the second round of spacer mask patterning. Thus, the rasterized pattern of the patterned hard mask cap layer 2314 of Figure 23E can have a hard mask line that is separated by a constant pitch and has a constant width.

Figure 23F illustrates the structure of Figure 23E following the further patterning of the first patterned hard mask and the subsequent formation of the plurality of light barrels, in accordance with an embodiment of the present invention. Referring to FIG. 23F, using the patterned hard mask cap layer 2314 as a mask, the first patterned hard mask 2310 is further patterned to form a first patterned hard mask 2316. The second patterned hard mask 2312 is not further patterned into this process. Thereafter, the patterned hard mask cap layer 2314 is removed and the light bucket 2318 is formed in the resulting opening above the ILD layer 2302. Light bucket 2318 (at this stage) represents all possible via locations in the resulting metallization layer.

Figure 23G illustrates the structure of Figure 23F following subsequent exposure and development of the light barrel to leave the selected via location and subsequent via opening etched into the lower ILD, in accordance with an embodiment of the present invention. Referring to Figure 23G, the selected light bucket 2318 is exposed and removed to provide a selected through hole location 2320. Via location 2320 undergoes a selective etch process (such as a selective plasma etch process) to extend the via opening into lower ILD layer 2302 to form patterned ILD layer 2302'. The etching is selective for the remaining light bucket 2318, the first patterned hard mask 2316, and the second patterned hard mask 2312.

Figure 23H illustrates the structure of Figure 23G following the removal of the remaining light bucket, the subsequent formation of the hard mask material, and the subsequent formation of the second plurality of light barrels, in accordance with an embodiment of the present invention. Referring to Figure 23H, the remaining light buckets are removed, for example, by a selective etch process. All of the formed openings (e.g., the openings formed when the light barrel 2318 and the through hole locations 2320 are removed) are then filled with a hard mask material 2322, such as a carbon based hard mask material. Thereafter, the first patterned hard mask 2316 is removed (eg, in a selective etch process) and the resulting opening is filled with a second plurality of light barrels 2324. Light bucket 2324 (at this stage) represents all possible plug locations in the resulting metallization layer. It should be understood that the second patterned hard mask 2312 is not further patterned at this stage in the process.

Figure 23I illustrates the structure of Figure 23H following the selection of the plug position, in accordance with an embodiment of the present invention. Referring to Figure 23I, the light bucket 2324 from Figure 23H is removed from a position 2326 where the plug will not be formed. In a position in which the plug is selected to form a plug, the light tub 2324 is retained. In one embodiment, to form a location 2326 in which the plug will not be formed, lithography is used to expose the corresponding light bucket 2324. The exposed light bucket can then be removed by the developer.

Figure 23J illustrates the structure of Figure 23I following the removal of the recently formed hard mask from the via and line locations, in accordance with an embodiment of the present invention. Referring to Figure 23J, the hard mask material 2322 depicted in Figure 23I is removed. In one such embodiment, the hard mask material 2322 is a carbon based hard mask material and is removed by a plasma ash process. As shown, the remaining features include a patterned ILD layer 2302', a light bucket 2324 retained for plug formation, and a via opening 2328. Although not shown, it should be understood that in one embodiment, the second hard mask layer 2312 is also retained at this stage.

Figure 23K illustrates the structure of Figure 23J following the depression of the patterned ILD layer in a position not protected by the plug forming aperture, in accordance with an embodiment of the present invention. Referring to Figure 23K, portions of the patterned ILD layer 2302' that are not protected by the light barrel 2324 are recessed to provide metal line openings 2330, except for via openings 2328.

Figure 23L illustrates the structure of Figure 23K following metal filling, in accordance with an embodiment of the present invention. Referring to Figure 23L, metallization 2332 is formed in openings 2328 and 2332. In one such embodiment, the metallization 2332 is formed by a metal fill and polishing process. Referring to the left-hand portion of Figure 23L, the structure is shown to include a lower portion including a patterned ILD layer 2302' having metal lines and vias (collectively shown as 2332) formed therein. The upper structure region 2334 includes a second patterned hard mask 2312 and a remaining (plug position) light bucket 2324. In one embodiment, the upper region 2334 is removed (eg, by CMP or etched back) prior to subsequent fabrication. However, in an alternate embodiment, the upper zone 2334 is retained in the final structure.

The structure of Figure 23L can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 23L can represent the last metal interconnect layer in the integrated circuit. It should be understood that the above-described process operations can be performed in an alternate order, not every operation needs to be performed and/or additional process operations can be performed. Referring again to Figure 23L, self-aligned fabrication by subtractive mode can be accomplished at this stage. Manufacturing the next layer in a similar manner may require the start of a complete process. Alternatively, other ways can be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene.

In the second aspect, the first plug and the second through hole are used. By way of example, Figures 23M-23S illustrate portions of an integrated circuit layer that represent various operations in a method of reducing self-aligned vias and plug patterning, in accordance with another embodiment of the present invention. In each of the illustrated operations, a plan view is shown at the top and a corresponding cross-sectional view is shown at the bottom. These views will be referred to herein as corresponding cross-sectional views and plan views.

Figure 23M illustrates a plan view and corresponding cross-sectional view of a starting orthogonal grid formed over a substrate 2351, in accordance with an embodiment of the present invention. Referring to the plan view taken along axes a-a' and b-b' and the corresponding cross-sectional views (a) and (b), the starting grid structure 2350 includes a grating ILD layer 2352 having a first hard cover. A cover layer 2354 is disposed thereon. The second hard mask layer 2356 is disposed on the first hard mask layer 2354 and patterned to have a grating structure orthogonal to the underlying grating structure. Furthermore, the opening 2358 is held between the grating structure of the second hard mask layer 2356 and the underlying grating formed by the ILD layer 2352 and the first hard mask layer 2354.

Figure 23N illustrates a plan view and corresponding cross-sectional view of the structure of Figure 23M following the opening fill and etch back, in accordance with an embodiment of the present invention. Referring to the plan view taken along axes a-a' and b-b' and the corresponding cross-sectional views (a) and (b), the opening 2358 of FIG. 23M is filled with a dielectric layer 2360 (such as a yttrium oxide layer). ). This dielectric layer 2360 can be formed with a deposited oxide film, such as by chemical vapor deposition (CVD), high density plasma deposition (HDP), or dielectric spin coating. The deposited material may need to be etched back to achieve the relative height shown in Figure 23N, leaving the upper opening 2358'.

Figure 23O illustrates a plan view and corresponding cross-sectional view of the structure of Figure 23N following the filling, exposure, and development of the light barrel to leave the selected plug position, in accordance with an embodiment of the present invention. Referring to the plan views taken individually along axes a-a' and b-b' and the corresponding cross-sectional views (a) and (b), a light bucket is formed in the opening 2358' above Fig. 23N. After that, most of the light buckets are exposed and removed. However, the selected light bucket 2362 is not exposed and thus remains to provide the selected plug position, as shown in Figure 23O.

Figure 23P illustrates a plan view and corresponding cross-sectional view of the structure of Figure 23O following removal of portions of dielectric layer 2360, in accordance with an embodiment of the present invention. Referring to the plan view taken along axes a-a' and b-b' and the corresponding cross-sectional views (a) and (b), portions of the dielectric layer 2360 that are not covered by the light barrel 2362 are removed. . However, portions of dielectric layer 2360 that are not covered by light barrel 2362 remain in the structure of Figure 23P. In one embodiment, portions of the dielectric layer 2360 that are not covered by the optical barrel 2362 are removed by a wet etch process.

Figure 23Q illustrates a plan view and corresponding cross-sectional view of the structure of Figure 23P following the filling, exposure, and development of the light barrel to leave the selected through hole locations, in accordance with an embodiment of the present invention. Referring to the plan views taken along the axes a-a' and b-b' and the corresponding cross-sectional views (a) and (b), the photobucket is formed when the portion of the dielectric layer 2360 is removed. In the opening. Thereafter, the selected light bucket is exposed and removed to provide a selected through hole location 2364, as shown in Figure 23Q.

Figure 23R illustrates a plan view and corresponding cross-sectional view of the structure of Figure 23Q following the etch of the via opening into the lower ILD, in accordance with an embodiment of the present invention. Referring to the plan view taken along axes a-a' and b-b' and the corresponding cross-sectional views (a) and (b), the via location 2364 of Figure 23Q is subjected to a selective etching process (such as selectivity). The plasma etching process) extends the via opening 2364 to the opening 2364' which is formed into the lower ILD layer 2352.

Figure 23S illustrates a plan view and corresponding cross-sectional view of the structure of Figure 23R following removal of the second hard mask layer and the remaining optical barrel material, in accordance with an embodiment of the present invention. Referring to the plan view taken along axes a-a' and b-b' and the corresponding cross-sectional views (a) and (b), the second hard mask layer 2356 and any remaining light barrel material (also That is, the optical drum material that has not been exposed and developed is removed. This removal is selectively performed for all other remaining features. In one such embodiment, the second hard mask layer 2356 is a carbon-based hard mask material and the removal is performed by an O ₂ plasma ash process. Referring again to Figure 23S, the remainder of this stage is: the ILD layer 2352 in which the via opening 2364' is formed and the portion of the dielectric layer 2360 that is retained to the plug location (e.g., retained by the upper optical barrel material) . Thus, in one embodiment, the structure of FIG. 23S includes an ILD layer 2352 patterned with via openings (for subsequent metal fill) having a location for creating a dielectric layer 2360 of the plug. The remaining openings 2366 can be filled with metal to form metal lines. It should be understood that its hard mask 2354 can be removed.

Thus, once filled with a metal interconnect material, the structure of Figure 23S can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 23S may represent the last metal interconnect layer in the integrated circuit once filled with the metal interconnect material. Referring again to Figure 23S, self-aligned fabrication by subtractive mode can be accomplished at this stage. Manufacturing the next layer in a similar manner may require the start of a complete process. Alternatively, other ways can be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene.

It should be understood that the manner described in connection with Figures 23A-23L and 23M-23S is not necessarily implemented to form vias that are aligned with the underlying metallization layer. As such, in some contexts, these process schemes can be considered to involve blind shooting from top to bottom for any underlying metallization layer. In the third aspect, the subtractive mode provides alignment with the underlying metallization layer. For example, Figures 24A-24I illustrate portions of an integrated circuit layer that represent various operations in a method of reducing self-aligned plug patterning, in accordance with another embodiment of the present invention. In each of the illustrated operations, a beveled three-dimensional cross-sectional view is provided.

Figure 24A illustrates a starting point structure 2400 for a reduced via and plug process following fabrication of a deep metal line, in accordance with an embodiment of the present invention. Referring to Figure 24A, structure 2400 includes a metal line 2402 having an intermediate interlayer dielectric (ILD) line 2404. It should also be understood that certain lines 2402 may be associated with lower vias for coupling to previous interconnect layers. In one embodiment, metal line 2402 is formed by patterning a trench into an ILD material (eg, ILD material of line 2404). The trench is then filled with metal and, if desired, planarized to the top of the ILD line 2404. In one embodiment, the metal trench and fill process are characterized by high aspect ratio features. For example, in one embodiment, the aspect ratio of the metal line height (h) to the metal line width (w) is in the range of about 5-10.

Figure 24B illustrates the structure of Figure 24A following the recess of the metal lines, in accordance with an embodiment of the present invention. Referring to Figure 24B, metal line 2402 is selectively recessed to provide first order metal line 2406. The depressions are selectively performed on the ILD line 2404. The recess can be performed by etching through dry etching, wet etching, or a combination thereof. The degree of dishing can be determined by the target thickness of the first order metal line 2406 for use as a suitable conductive interconnect within the back end of line (BEOL) interconnect structure.

Figure 24C illustrates the structure of Figure 24B following the formation of an interlayer dielectric (ILD) layer, in accordance with an embodiment of the present invention. Referring to Figure 24C, ILD material layer 2408 is deposited and, if desired, planarized to a level above recessed metal line 2406 and ILD line 2404.

Figure 24D illustrates the structure of Figure 24C following deposition and patterning of the hard mask layer, in accordance with an embodiment of the present invention. Referring to FIG. 24D, a hard mask layer 2410 is formed on the ILD layer 2408. In one such embodiment, the hard mask layer 2410 is formed with a grating pattern that is orthogonal to the grating pattern of the first order metal line 2406 / ILD line 2404, as shown in Figure 24D. In one embodiment, the grating structure formed by the hard mask layer 2410 is a closely pitched grating structure. In this embodiment, the tight pitch cannot be obtained directly through conventional lithography. For example, a pattern according to a conventional lithography may be formed first, but the pitch may be halved by patterning using a spacer mask. Even the original pitch can be reduced to a quarter by the second round of spacer mask patterning. Thus, the grating-like pattern of the second hard mask layer 2410 of Figure 24D can have a hard mask line that is separated by a constant pitch and has a constant width.

Figure 24E illustrates the structure of Figure 24D following the formation of the trenches defined by the pattern of the hard mask of Figure 24D, in accordance with an embodiment of the present invention. Referring to FIG. 24E, the exposed regions of the ILD layer 2408 (ie, not protected by 2410) are etched to form trenches 2412 and patterned ILD layers 2414. The etch stop is stopped (and thus exposed) on the top surface of the first order metal line 2406 and the ILD line 2404.

Figure 24F illustrates the structure of Figure 24E following the formation of a light bucket in all possible through-hole locations, in accordance with an embodiment of the present invention. Referring to Figure 24F, a light bucket 2416 is formed in all possible through hole locations above the exposed portions of the recessed metal lines 2406. In one embodiment, the light bucket 2416 is formed to be substantially coplanar with the top surface of the ILD line 2404, as depicted in Figure 24F. Moreover, referring again to FIG. 24F, the hard mask layer 2410 can be removed from the patterned ILD layer 2414.

Figure 24G illustrates the structure of Figure 24F following the selection of the via locations, in accordance with an embodiment of the present invention. Referring to Figure 24G, the light bucket 2416 from Figure 24F is removed when the through hole location 2418 is selected. The light barrel 2416 is retained in a position in which the through hole is not selected. In one embodiment, to form the via location 2418, lithography is used to expose the corresponding light bucket 2416. The exposed light bucket can then be removed by the developer.

Figure 24H illustrates the structure of Figure 24G following the conversion of the remaining optical barrel to the permanent ILD material, in accordance with an embodiment of the present invention. Referring to Figure 24H, the material of the optical tub 2416 is modified (e.g., by cross-linking during the baking operation) in position to form the final ILD material 2420. In one such embodiment, the cross-link provides a solubility switch upon baking. The final, crosslinked material has inter-intermediate properties and can therefore be retained in the final metallized structure.

Referring again to Figure 24H, in one embodiment, the resulting structure includes up to three different regions of dielectric material (ILD line 2404 + ILD line 2414 + crosslinked light barrel 2420) in a single plane 2450 of the metallization structure. In this embodiment, both or all of the ILD line 2404, the ILD line 2414, and the crosslinked light barrel 2420 are comprised of the same material. In another such embodiment, the ILD line 2404, the ILD line 2414, and the crosslinked light barrel 2420 are each composed of different ILD materials. In either case, in a particular embodiment, a vertical seam (eg, seam 2497) between the material such as ILD line 2404 and ILD line 2414 can be observed in the final structure and/or A vertical seam (eg, seam 2498) between the ILD wire 2404 and the crosslinked light barrel 2420 and/or a vertical seam (eg, seam 2499) between the ILD line 2414 and the crosslinked light barrel 2420, etc. the difference.

Figure 24I illustrates the structure of Figure 24H following the formation of metal lines and vias, in accordance with an embodiment of the present invention. Referring to Figure 24I, metal lines 2422 and vias 2424 are formed over the metal fill of the opening of Figure 24H. Metal line 2422 is coupled to lower metal line 2406 by via 2424. In one embodiment, the openings are filled in a damascene manner or a bottom-up filling manner to provide the structure shown in FIG. 24I. Thus, the deposition of metals (e.g., copper and associated barrier and seed layers) used to form metal lines and vias in the above manner can be typically used in standard back end processing (BEOL) processors. In an embodiment, in subsequent fabrication operations, the ILD lines 2414 can be removed to provide an air gap between the resulting metal lines 2424.

The structure of Figure 24I can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 24I can represent the last metal interconnect layer in the integrated circuit. Referring again to Figure 24I, self-aligned fabrication by subtractive mode can be accomplished at this stage. Manufacturing the next layer in a similar manner may require the start of a complete process. Alternatively, other ways can be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene.

In accordance with an embodiment of the present invention, a multi-color light bucket is described. One or more embodiments described herein relate to the use of a multi-color optical bucket as a means of handling plug and via fabrication below lithographic pitch limitations. One or more embodiments described herein relate to a subtractive manner for self-aligned vias and plug patterning, and the resulting structure. In one embodiment, the procedures described herein enable the implementation of self-aligned metallization for the fabrication of back-end process features. The overlap problem expected for next generation via and plug patterning can be handled in one or more ways as described herein.

In an exemplary embodiment, the manner described below is based on the use of a so-called light bucket in which each possible feature (eg, a via) is re-patterned into the substrate. Next, the photoresist is filled into the patterned features and the lithographic operation is only used to select the selected vias for via opening. In the specific embodiment described below, the lithography operation is used to define a relatively large aperture above a plurality of "multi-color optical buckets" that can then be opened by a large amount of exposure at a particular wavelength. The multi-color drum mode allows for large critical dimensions (CD) and/or errors in overlap while retaining the ability to select through holes of interest. In one such embodiment, the trenches are used to contain the resist itself, and a plurality of exposed wavelengths are used to selectively open vias of interest.

More specifically, one or more of the embodiments described herein involve the use of a subtractive method to pre-form each via or via opening using an etched trench. An additional operation is then used to select which vias and plugs to retain. These operations can be illustrated using a light bucket, although a more conventional resist exposure and ILD backfill can be used to perform the selection process.

In one example, a self-aligned via opening can be used. As an example processing scheme, Figures 25A-25H illustrate portions of an integrated circuit layer that illustrate various operations in a method of subtractive self-aligned via patterning using a multi-color optical barrel, in accordance with an embodiment of the present invention. In each of the illustrations of each of the operations, a cross-sectional view is displayed.

25A illustrates a cross-sectional view of a starting structure 2500 following deposition (but prior to patterning) of a first layer of hard masking material 2504 formed over an interlayer dielectric (ILD) layer 2502, in accordance with an embodiment of the present invention. . Referring to Figure 25A, patterned mask 2506 has spacers 2508 formed on or over first hard mask material layer 2504 (along its sidewalls).

Figure 25B illustrates the structure of Figure 25A following the first patterning of the first hard mask layer and subsequent filling of the first color light barrel, in accordance with an embodiment of the present invention. Referring to FIG. 25B, patterned mask 2506 and corresponding spacers 2508 are used together as a mask during etching to form trenches 2510 through first hard mask material layer 2504 and partially into ILD layer 2502. The trench 2510 is then filled with a first color light bucket 2512.

Figure 25C illustrates the structure of Figure 25B following the second patterning of the first hard mask layer and subsequent filling of the second color light barrel, in accordance with an embodiment of the present invention. Referring to FIG. 25C, the patterned mask 2506 is removed and the second plurality of trenches 2514 are etched through the first hard mask material layer 2504 and partially into the ILD layer 2502, between the spacers 2508. Thereafter, the trench 2514 is filled with a second color photobubble material layer 2516.

Referring again to FIG. 25C, the negative pattern of spacers 2508 is thus transferred (eg, by two etching processes that form trenches 2510 and 2514) to first hard mask material layer 2504. In one such embodiment, spacers 2508 (and thus trenches 2510 and 2514) are formed in a grating pattern, as depicted in Figure 25C. In one embodiment, the grating pattern is a tight pitch grating pattern. In certain such embodiments, the tight pitch cannot be obtained directly through conventional lithography. For example, a pattern according to conventional lithography may first be limited to mask 2506, but the pitch may be halved by masking using a negative spacer mask, as depicted in Figures 25A-25C. Even though not shown, the original pitch can be reduced to a quarter by the second round of spacer mask patterning. Therefore, the grating patterns (collectively) of the light barrels 2512 and 2516 are separated by a constant pitch and have a constant width.

Figure 25D illustrates the structure of Figure 25C following the planarization of the first and second color light barrels from each other, in accordance with an embodiment of the present invention. Referring to FIG. 25D, the second color photobucket material layer 2516 and the top portion of the spacer 2508 are planarized, for example, by chemical mechanical polishing (CMP) until the top surface of the first color light barrel 2512 is exposed to form discrete The second color light bucket 2518 is from the light bucket material layer 2516. In one embodiment, the combination of the first color light bucket 2512 and the second color light bucket 2518 represents all possible through hole locations in the subsequently formed metallization structure.

Figure 25E illustrates the structure of Figure 25D following the exposure and development of the first color light barrel to leave the selected via location, in accordance with an embodiment of the present invention. Referring to Figure 25E, a second hard mask 2520 is formed and patterned on the structure of Figure 25D. The patterned second hard mask 2520 reveals the selected first color light bucket 2512A. The selected light bucket 2512A is exposed to light illumination and removed (i.e., developed) to provide a selected through hole opening 2513A. It should be understood that the description in relation to forming and patterning the hard mask layer involves (in one embodiment) the mask being formed over a later covered hard mask. Mask formation may involve the use of one or more layers suitable for lithography processing. When patterning one or more lithographic layers, the pattern is transferred to the hard mask layer by an etching process to provide a patterned hard mask layer.

Referring again to FIG. 25E, it may not be possible to reveal only the selected light bucket 2512A during patterning of the second hard mask layer 2520. For example, one or more adjacent (or nearby) second color light buckets 2518 may also be exposed. These additional exposed light buckets may not be the desired location for the final via formation. However, any of the exposed second color light buckets 2518 (in one embodiment) are not modified for exposure to the illumination that they use to pattern the group of first color light buckets 2512. For example, in one embodiment, the first color light bucket 2512 is susceptible to a large amount of red exposure 2521 and can be developed to remove the first color light bucket 2512, as shown in Figure 25E. In this embodiment, the second color light bucket 2518 is less susceptible to a large amount of red exposure and, therefore, cannot be developed and removed, even when exposed to a large amount of red exposure, as shown in Figure 25E. In one embodiment, larger patterns and/or deviation tolerances may be provided to relax the limitations associated with patterning the second hard mask layer 2520 by adjacent optical barrels having different illumination susceptibility.

Figure 25F illustrates the structure of Figure 25E following the exposure and development of the second color light barrel to leave an additional selected via location, in accordance with an embodiment of the present invention. Referring to Figure 25F, a third hard mask 2522 is formed and patterned on the structure of Figure 25E. The third hard mask 2522 can also fill the selected through hole opening 2513A as depicted in Figure 25F. The patterned third hard mask 2522 reveals selected second color light buckets 2518A and 2518B. Selected light buckets 2518A and 2518B are exposed to light illumination and removed (i.e., developed) to individually provide selected via openings 2519A and 2519B.

Referring again to FIG. 25F, it may not be possible to reveal only the patterning of the selected light buckets 2518A and 2518B to the third hard mask layer 2522. For example, one or more adjacent (or nearby) first color light buckets 2512 may also be exposed. These additional exposed light buckets may not be the desired location for the final via formation. However, any of the revealed first color light buckets 2512 (in one embodiment) are not modified for exposure to the illumination that they use to pattern the group of second color light buckets 2518. For example, in one embodiment, the second color light bucket 2518 is susceptible to a large amount of green exposure 2523 and can be developed to remove the second color light bucket 2518, as shown in Figure 25F. In this embodiment, the first color light bucket 2512 is less susceptible to a large amount of green exposure and, therefore, cannot be developed and removed, even though it is exposed during a large amount of green exposure, as shown in Figure 25F. In one embodiment, larger patterns and/or deviation tolerances may be provided to relax the limits associated with the patterned third hard mask layer 2522 by adjacent optical barrels having different illumination susceptibility.

Figure 25G illustrates the structure of Figure 25F following the removal and etching of the third hard mask layer to form the via locations, in accordance with an embodiment of the present invention. Referring to Figure 25G, the third hard mask layer 2522 is removed. In one such embodiment, the third hard mask layer 2522 is a carbon-based hard mask layer and is removed by an ashing process. Next, the patterns of via openings 2519A, 2513A, and 2519B are subjected to a selective etch process (such as a selective plasma etch process) to extend the via openings deeper into the lower ILD layer 2502 to form a via pattern having via locations 2524. The ILD layer 2502'. The etch is selective for the remaining light barrels 2512 and 2518 and for the spacer 2508.

Figure 25H illustrates the structure of Figure 25G prior to metal filling, in accordance with an embodiment of the present invention. Referring to Figure 25H, all remaining first color and second color light buckets 2512 and 2518 are removed. The remaining first and second color light buckets 2512 and 2518 can be removed directly or can be exposed and developed first to enable removal. The removal of the remaining first color and second color light buckets 2512 and 2518 provides a wire trench 2526 that is partially coupled to the via location 2524 in the patterned ILD layer 2502'. Subsequent processes may include removal of spacer 2508 and hard mask layer 2504, and metal fill of metal line trench 2526 and via location 2504. In one such embodiment, the metallization is formed by metal filling and polishing back to the process.

The structure of Figure 25H (when filled with metal) can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 25H (when filled with metal) may represent the last metal interconnect layer in the integrated circuit. Referring again to Figure 25H, self-aligned fabrication by subtractive mode can be accomplished at this stage. Manufacturing the next layer in a similar manner may require the start of a complete process. Alternatively, other ways can be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene.

Referring again to Figures 25A-25H, several options are contemplated for providing the first color light bucket 2512 and the second color light bucket 2518. For example, in one embodiment, two different positive tone organic photoresists are used. It should be understood that in one such embodiment, materials having different chemical structures may be selected for the first color light bucket 2512 and the second color light bucket 2518 to allow for different coating, photoactivation, and development processes to be used. . As an example embodiment, a conventional 193 nm lithography polymethacrylate resist system is selected for the first color light bucket 2512, while a conventional 248 nm polyhydroxystyrene photoresist system is selected for the second color light. Bucket 2518. A significant chemical difference between the two types of resins allows two different organic casting solvents to be used; this may be necessary because the material of the second color light bucket 2518 is coated with its existing first color light The material of the barrel 2512. The casting solvent for the first color light bucket 2512 is not limited; for the second color light bucket 2518, an alcohol solvent can be used because it still dissolves the PHS material but does not dissolve the less polar polymethacrylate.

The combination of the polymethacrylate resin as the material of the first color light bucket 2512 and the polyhydroxystyrene resin as the material of the second color light bucket 2518 can (in one embodiment) enable the two to be used Different exposure wavelengths. A typical 193 nm lithographic polymer is based on a polymethacrylate having a 193 nm absorption photoacid generator (PAG) because the polymer does not strongly absorb this wavelength. Polyhydroxystyrene, on the other hand, may not be suitable because it strongly absorbs 193 nm and prevents activation of the PAG throughout the film. Next, in an embodiment, the material of the first color light bucket 2512 can be selectively activated and developed in the presence of 193 nm photons. To emphasize the difference in optical velocity between the first color light barrel 2512 and the second color light barrel 2518, factors such as PAG absorbance at 193 nm, PAG loading, and photoacid strength can be tuned for each. Additionally, a strong 193 nm absorber can be added to the second color light bucket 2518 (or selectively deposited on top of the second color light bucket 2518) to reduce PAG activation within the bulk film. Following exposure, in a particular embodiment, development of the first color light bucket 2512 is selectively performed with a standard TMAH developer, wherein minimal development of the second color light bucket 2518 will occur.

In an embodiment, to selectively remove the second color light bucket 2518 (when the first color light bucket 2512 is present), a second lower energy wavelength is used that activates only the second color light bucket 2518 Instead of the PAG in the first color light bucket 2512. This can be achieved in two ways. First, in one embodiment, PAGs having different absorption characteristics are used. For example, the trihydrocarbyl phosphonium salt has an extremely low absorbance at a wavelength such as 248 nm, and the triarylsulfonium has an extremely high absorptivity. Thus, selectivity is achieved by using a triaryl sulfonium or other 248 nm absorbing PAG in the second color light bucket 2518, while using a trihydrocarbyl hydrazine or other non-248 nm absorbing PAG in the first color light bucket 2512. Alternatively, the sensitizer can be incorporated into the second color light bucket 2518, which absorbs the low energy photon transfer energy selectively in the second color light bucket 2518 to the PAG without activation occurring in the first color light bucket 2512 Medium (because no sensitizer is present).

In another embodiment, FIG. 25I illustrates an exemplary two-tone resist for one light bucket type and an exemplary single tone resist for another light bucket type, in accordance with an embodiment of the present invention. Referring to Figure 25I, in one embodiment, a two-tone photoresist system (PB-1) is used for the material of the first color light bucket 2512. A monochromatic (slow) photoresist system (PB-2) is used for the material of the second color light bucket 2518. A two-tone photoresist can be characterized as having a photoresponse that is effectively shut down to a higher dose due to activation of the photo-based generator included in the system. The light-generating system neutralizes the photoacid and prevents the polymer from deprotecting. In one embodiment, during exposure of the first color light bucket 2512, the dose is selected such that its two-tone resist (PB-1) operates as a fast positive tone system, while the single tone resist (PB-2) ) enough photons have not been received for the soluble switching to be activated. This allows PB-1 to be removed with TMAH developer without removing PB-2. In order to selectively remove PB-2 without removing PB-1, a higher dose is used for the second exposure (ie, exposure of the second color light bucket 2518). The selected dose must activate sufficient PAG in PB-2 to allow for dissolution in TMAH and to activate PB-2 to move PB-2 into the negative tone response domain. In this scheme, the same PAG can be used for PB-1 and PB-2 and the same exposure wavelength can be used for exposures 1 and 2. It will be appreciated that PB-1 may require the incorporation of a photo-based generator (PBG); however, it is likely that it will require a different type of polymer to allow for the coating of PB-2 (once PB-1 has been coated). As noted above, the use of a polymethacrylate type resist for PB-1 and a PHS type for PB-2 meets this need.

It should be understood that the materials specified above for the first and second color light buckets 2512 and 2518, respectively, may be exchanged in accordance with embodiments of the present invention. Meanwhile, the above multi-color light bucket method may be referred to as 1-D. A similar approach can be applied to a 2-D system using crossed gratings, although the optical barrel material will have to withstand etching and cleaning from the crossed gratings described above. The result will be a checkerboard type pattern with smaller through holes/plugs in the vertical direction, relative to those in the above manner. In addition, it should be understood that the manner described in connection with Figures 25A-25H is not necessarily performed to form a via that is aligned to the underlying metallization layer, although it must be implemented as such. In other contexts, these process schemes can be considered to involve blind shooting from top to bottom for any underlying metallization layer.

In accordance with an embodiment of the present invention, a light bucket for a conductive sheet is described.

For example, Figure 26A illustrates a plan view of a conventional back end of line (BEOL) metallization layer. Referring to FIG. 26A, a conventional BEOL metallization layer 2600 is shown with conductive lines or routings 2604 disposed in the interlayer dielectric layer 2602. The metal lines may generally extend parallel to each other and may include a cut, interrupt or plug 2606 in the continuity of one or more of the conductive lines 2604. To electrically couple two or more of the parallel metal lines, the upper or lower layer routing 2608 is included in the previous or next metallization layer. The upper or lower routing 2608 can include a conductive line 2610 that couples the conductive vias 2612. It should be understood that because the upper or lower routing 2608 is included in the previous or next metallization layer, the upper or lower routing 2608 may consume vertical real estate of its semiconductor structure including the metallization layer.

Conversely, Figure 26B illustrates a plan view of a back end of line (BEOL) metallization layer having conductive sheets to couple metal lines of the metallization layer, in accordance with an embodiment of the present invention. Referring to FIG. 26B, BEOL metallization layer 2650 is shown with conductive lines or routing 2654 disposed in interlayer dielectric layer 2652. The metal lines may generally extend parallel to each other and may include a cut, interrupt or plug 2656 in the continuity of one or more of the conductive lines 2654. To electrically couple two or more of the parallel metal lines, a conductive sheet 158 is included in the metallization layer 2650. It should be understood that because the conductive sheet 2658 is included in the same metallization layer as the conductive line 2654, the vertical real-life conductive sheet 2658 consumption of the semiconductor structure including the metallization layer can be reduced, relative to the structure of FIG. 26A.

One or more embodiments described herein relate to a light bucket mode for metal damascene plugs and sheet patterning. These patterning schemes can be implemented to enable bidirectional spacer based interconnections. Embodiments may be particularly suitable for electrically connecting two parallel lines of a metallization layer, wherein the two metal lines are fabricated using a spacer-based manner, the spacer being base-based and otherwise confined in the same metallization layer The inclusion of electrically conductive connections between two adjacent lines. In general, one or more embodiments are related to a manner that utilizes a damascene technique to form a conductive sheet and a non-conductive spacing or interruption (plug) between the metals.

More specifically, one or more embodiments described herein relate to the use of a damascene method to form sheets and plugs. Initially, each possible patch and plug location is first patterned into the hard mask layer. An additional operation is then used to select which slices and plug locations to retain. The locations are then transferred into the underlying interlayer dielectric layer. These operations can be illustrated using a light bucket. In a particular embodiment, a method for tessellation patterning of vias, plugs, and sheets is provided for self-alignment, using a light barrel approach and a selective hard mask.

In accordance with an embodiment of the present invention, optical barrel patterning is used to fabricate plugs and sheets in a self-aligning manner. A general overview of the process flow may involve (1) fabrication of a cross-grating, followed by (2) plugging and changing the photoresist to a barrel of a "hard" material that can withstand downstream processing, followed by ( 3) by backfilling with the fillable material, recessing the fillable material, and removing the grating tonal inversion of the original cross-grating, followed by (4) the barreling for the "slice" definition, followed by (5) The pattern is etched into the underlying interlayer dielectric (ILD) layer and the additional hard mask material is polished away. It should be understood that while the general process flow does not include vias, in one embodiment, the manner described herein can be implemented to extend to multiple plugs, vias, and sheets using the same self-aligned grating.

For example, Figures 27A-27K illustrate oblique cross-sectional views showing various operations in a method of fabricating a back end of line (BEOL) metallization layer having a conductive sheet to couple the metal of the metallization layer Line, in accordance with an embodiment of the invention.

Referring to FIG. 27A, a first operation in the cross-raster patterning scheme is performed over an interlayer dielectric (ILD) layer 2702, which is formed over the substrate 2700. A cover hard mask 2704 is first formed on the ILD layer 2702. The first grating hard mask 2706 is formed along a first direction overlying the hard mask 2704. In one embodiment, the first grating hard mask 2706 is formed in a grating pattern, as depicted in Figure 27A. In one embodiment, the grating structure of the first grating hard mask 2706 is a tight pitch grating structure. In certain such embodiments, the tight pitch cannot be obtained directly through conventional lithography. For example, a pattern according to a conventional lithography may be formed first, but the pitch may be halved by patterning using a spacer mask. Even the original pitch can be reduced to a quarter by the second round of spacer mask patterning. Thus, the grating-like pattern of the first grating hard mask 2706 of Figure 27A can have a hard mask line that is closely spaced at a constant pitch and has a constant width.

Referring to FIG. 27B, a second operation in the cross-raster patterning scheme is performed over the interlayer dielectric (ILD) layer 2702. The second grating hard mask 2708 is formed along a second direction overlying the hard mask 2704. The second direction is orthogonal to the first direction. The second grating hard mask 2708 has an overlying hard mask 2710. In one embodiment, the second grating hard mask 2710 is fabricated in a patterning process using an overlying hard mask 2710. The continuity of the second grating hard mask 2708 is interrupted by the line of the first grating hard mask 2706, and as such, portions of the first grating hard mask 2706 extend below the overlying hard mask 2710. In one embodiment, the second grating hard mask 2708 is formed to be interleaved with the first grating hard mask 2706. In one such embodiment, the second grating hard mask 2708 is formed by deposition of a second layer of hard mask material having a composition different from that of the first grating hard mask 2706. The second layer of hard mask material is then planarized (eg, by chemical mechanical polishing (CMP)) and then patterned using an overlying hard mask 2710 to provide a second grating hard mask 2708. As in the case of the first grating hard mask 2706, in one embodiment, the grating structure of the second grating hard mask 2708 is a tight pitch grating structure. In certain such embodiments, the tight pitch cannot be obtained directly through conventional lithography. For example, a pattern according to a conventional lithography may be formed first, but the pitch may be halved by patterning using a spacer mask. Even the original pitch can be reduced to a quarter by the second round of spacer mask patterning. Thus, the grating-like pattern of the second grating hard mask 2708 of Figure 27A can have a hard mask line that is closely spaced at a constant pitch and has a constant width.

Referring to FIG. 27C, the plug light barrel patterning scheme is implemented as a first light barreling process. In one embodiment, a light bucket 2712 is formed over all exposed openings between the first grating hard mask 2706 and the second grating hard mask 2708. In one embodiment, the via patterning process is selectively performed prior to the plug light barrel patterning process. The via patterning can be direct patterning or can involve a separate light barreling process.

Referring to Figure 27D, the selected one of the light buckets 2712 is removed while the other light buckets 2712 are retained, for example, by exposing the selected light buckets 2712 to a lithography and development process for opening all other light buckets 2712. . The exposed portion of the overlay hard mask 2704 of FIG. 27A is then etched to provide a first patterned hard mask 2714. The retained light bucket 2712 (at this stage) represents the plug location in the final metallization layer. That is, in the first light drum process, the light bucket is removed from a position where no plug will be formed. In one embodiment, in order to form a location in which the plug will not be formed, lithography is used to expose the corresponding light bucket. The exposed light bucket can then be removed by the developer.

Referring to Figure 27E, a raster tone inversion process is performed. In one embodiment, dielectric region 2716 is formed in all exposed regions of the structure of Figure 27D. In one embodiment, dielectric region 2716 is formed by deposition of a dielectric layer and etching back to form dielectric region 2716.

Referring to Figure 27F, portions of the first grating hard mask 2706 that are not covered by the overlying hard mask 2710 are then removed to leave only the first grating hard mask remaining under the overlying hard mask 2710. Part 2706' of 2706.

Referring to FIG. 27G, the sheet light bucket patterning scheme is implemented as a second light barreling process. In one embodiment, the light barrel 2718 is formed in all of the exposed openings formed when the exposed portions of the first grating hard mask 2706 are removed.

Referring to Figure 27H, the selected one of the light buckets 2718 is removed while the other light buckets 2718 are retained, for example, by not exposing the light bucket 2718 to a lithography and development process for opening other light buckets. The exposed portions of the first patterned hard mask 2714 of Figures 27D-27G are then etched to provide a second patterned hard mask 2715. The retained light bucket 2718 (at this stage) represents where the conductive sheets will not be in the final metallization layer. That is, in the second light drum process, the light bucket is removed from the position where the conductive sheets will eventually be formed. In one embodiment, in order to form a location in which the conductive sheets are to be formed, lithography is used to expose the corresponding light bucket. The exposed light bucket can then be removed by the developer.

Referring to FIG. 27I, the overlying hard mask 2710, the second grating hard mask 2708, and the dielectric region 2716 are removed. Thereafter, a portion of the second patterned hard mask 2715 exposed when the overlying hard mask 2710 is removed is removed to provide a third patterned hard mask 2720, a second grating hard mask 2708, And the dielectric region 2716 is removed. In one embodiment, the remainder of the light barrels 2712 and 2718 are first hardened (eg, by a baking process), and the overlying hard mask 2710, the second grating hard mask 2708, and the dielectric region 2716 are removed. prior to. At this stage, the selected one of the light bucket 2712, the selected one of the light buckets 2718, and the remaining portion 2706' of the first grating hard mask 2706 remain on the third patterned hard mask 2720. In one embodiment, the overlying hard mask 2710, the second grating hard mask 2708, and the dielectric region 2716 are removed using a selective wet etch process, while the overlying hard mask 2710 is removed. The portion of the second patterned hard mask 2715 that is exposed is removed using a dry etch process to provide a third patterned hard mask 2720.

Referring to FIG. 27J, the pattern of the third patterned hard mask 2720 is transferred to the upper portion of the ILD layer 2702 to form a patterned ILD layer 2722. In one embodiment, the plug and sheet pattern of the third patterned hard mask 2720 are then transferred to the ILD layer 2702 to form a patterned ILD layer 2722. In one embodiment, an etch process is used to transfer the pattern into the ILD layer 2702. In one such embodiment, the selected one of the light buckets 2712 remaining over the third patterned hard mask 2720, the selected one of the light buckets 2718, and the retained portion 2706' of the first grating hard mask 2706 It is removed or lost during the etching it uses to form the patterned ILD layer 2722. In another embodiment, the selected one of the light buckets 2712 remaining over the third patterned hard mask 2720, the selected one of the light buckets 2718, and the retained portion 2706' of the first grating hard mask 2706 are It is removed before or after the etching it uses to form the patterned ILD layer 2722.

Referring to FIG. 27K, after the formation of the patterned ILD layer 2732, a conductive line 2724 is formed. In one embodiment, the conductive lines 2724 are formed using a metal fill and polish back process. During the formation of the conductive lines 2724, conductive sheets 2728 that couple the two metal lines 2724 are also formed. Thus, in one embodiment, the conductive coupling (slice 2728) between the conductive lines 2724 is formed at the same time as the conductive lines 2724, in the same ILD layer 2722, and in the same plane as the conductive lines 2724. . Moreover, the plug 2726 can be formed as a break or break in one or more of the conductive lines 2724, as depicted in Figure 27K. In one such embodiment, the plug 2726 is retained in the region of the ILD layer 2702 during pattern transfer to form the patterned ILD layer 2722. In one embodiment, the third patterned hard mask 2720 is removed, as depicted in Figure 27K. In one such embodiment, the third patterned hard mask 2720 is removed after forming the conductive lines 2724 and 2728, for example, using a post-metallization chemical mechanical planarization (CMP) process.

Referring again to FIG. 27K, in an embodiment, a semiconductor structure back end of line (BEOL) metallization layer includes an interlayer dielectric (ILD) layer 2722 disposed over the substrate 2700. A plurality of conductive lines 2724 are disposed in the ILD layer 2722 along the first direction. The conductive sheet 2728 is disposed in the ILD layer 2722. The conductive sheet couples both of the plurality of conductive lines 2724 along a second direction orthogonal to the first direction.

This configuration as shown in Figure 27K cannot be achieved by conventional lithography (small pitch, small width, or both). At the same time, self-alignment cannot be achieved using traditional processes. Moreover, the configuration as shown in FIG. 27K cannot be otherwise achieved in the case where the pitch division scheme is used to finally provide the pattern of the conductive lines 2724.

In one embodiment, the conductive strip 2728 and the plurality of conductive lines are continuous rather than contiguous, as depicted in Figure 27K. In one embodiment, the conductive strip 2728 and the plurality of conductive lines 2724 are coplanar, as depicted in Figure 27K. In one embodiment, the BEOL metallization layer further includes a dielectric plug 2726 disposed on the end of one of the plurality of conductive lines 2724, as depicted in Figure 27K. In one embodiment, the dielectric plug 2726 is continuous with the ILD layer, rather than contiguous, as depicted in Figure 27K. In one embodiment, although not shown, the BEOL metallization layer further includes conductive vias disposed under and electrically coupled to one of the plurality of conductive lines 2724.

The structure of Figure 27K can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 3K can represent the last metal interconnect layer in the integrated circuit. Referring to Figure 27K, this self-aligned fabrication by a damascene light bucket approach can be continued to fabricate the next metallization layer. Alternatively, other ways can be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene. It should also be understood that although not depicted, one or more of the conductive lines 2724 can be coupled to the lower conductive vias, which can be formed using an additional light bucket operation. In one embodiment, as an alternative to the two-dimensional approach described above, a one-dimensional raster approach can also be implemented in the plug and slice (and possibly via) patterning. This one-dimensional approach is limited to only one direction. In this way, the pitch can be "tight" in one direction and "loose" in one direction.

One or more embodiments described herein relate to a light bucket mode for subtracting plugs and sheet patterning. These patterning schemes can be implemented to enable bidirectional spacer based interconnections. Embodiments may be particularly suitable for electrically connecting two parallel lines of a metallization layer, wherein the two metal lines are fabricated using a spacer-based manner, the spacer being base-based and otherwise confined in the same metallization layer The inclusion of electrically conductive connections between two adjacent lines. In general, one or more embodiments are related to a manner that utilizes a subtractive technique to form a conductive sheet and a non-conductive spacing or interruption between the metal (plug).

One or more embodiments described herein provide a means for patterning self-aligned vias, cuts, and/or sheets for subtractive use using a light barreling mode and a selective hard mask. Embodiments may involve the use of so-called fabric patterning to reduce patterned self-aligned interconnects, plugs, and vias. The fabric approach may involve an embodiment of a hard masked fabric pattern that utilizes etch selectivity between the various hard mask materials. In the particular embodiment described herein, the fabric treatment scheme is implemented to subtractively pattern interconnects, cuts, and through holes.

As a summary of one or more embodiments described herein, a general summary process flow can refer to the following programming sequence: (1) using a fabric process that utilizes four "color" hard masks with etch selectivity between each other. Manufacturing of the flow, (2) removing the first of the hard mask types for the light barreling of the through holes, (3) backfilling the first hard mask material, and (4) removing the light bucket for the cut (or plug) The second of the hard mask types, (5) backfilling the second hard mask material, (6) removing the third type of hard mask type for the light barrel of the conductive sheet, (7) reducing the ground Etching the metal of the cut and sheet, and (8) removing the hard mask and subsequent backfilling and polishing back with permanent ILD material.

28A-28T illustrate oblique cross-sectional views showing various operations in a method of fabricating a back end of line (BEOL) metallization layer having a conductive sheet to couple metal lines of the metallization layer, in accordance with the present invention. Embodiments of the invention.

Referring to FIG. 28A, a grating patterning scheme is implemented over the overlying hard mask layer 2802 formed over the metal layer 2800, the metal layer 2800 being formed over a substrate (not shown) . The first grating hard mask 2804 is formed along a first direction that covers the hard mask 2802. The second grating hard mask 2806 is formed along the first direction and alternates with the first grating hard mask 2804. In one embodiment, the first grating hard mask 2804 is formed from a material having an etch selectivity different from that of the second grating hard mask 2806.

In one embodiment, the first and second grating hard masks 2804 and 2806 are formed in a grating pattern, as depicted in Figure 28A. In one embodiment, the grating structures of the first and second grating hard masks 2804 and 2806 are closely spaced grating structures. In certain such embodiments, the tight pitch cannot be obtained directly through conventional lithography. For example, a pattern according to a conventional lithography may be formed first, but the pitch may be halved by patterning using a spacer mask. Even the original pitch can be reduced to a quarter by the second round of spacer mask patterning. Thus, the grating-like pattern of the first and second grating hard masks 2804 and 2806 of FIG. 28A can have hard mask lines that are closely spaced at a constant pitch and have a constant width.

Referring to Figure 28B, the sacrificial cross-raster patterning process is performed. The overlying hard mask 2808 is formed in a grating pattern, along the second direction, orthogonal to the first direction, that is, orthogonal to the first and second grating hard masks 2804 and 2806.

In one embodiment, the overlying hard mask 2808 is formed with a tight pitch grating structure. In certain such embodiments, the tight pitch cannot be obtained directly through conventional lithography. For example, a pattern according to a conventional lithography may be formed first, but the pitch may be halved by patterning using a spacer mask. Even the original pitch can be reduced to a quarter by the second round of spacer mask patterning. Thus, the grating-like pattern of the overlying hard mask 2808 of Figure 28B can have a hard mask line that is closely spaced at a constant pitch and has a constant width.

Referring to Figure 28C, fabric pattern formation is performed. The area of the first hard mask 2804 exposed between the gratings overlying the hard mask 2808 is selectively etched and replaced with the area of the third hard mask 2810. The area of the second hard mask 2806 exposed between the gratings overlying the hard mask 2808 is selectively etched and replaced with the area of the fourth hard mask 2812. In one embodiment, the third grating hard mask 2810 is formed from a material having an etch selectivity different from that of the first hard mask 2804 and the second hard mask 2806. In a further embodiment, the fourth hard mask 2812 is formed from a material having an etch selectivity different from that of the first hard mask 2804, the second hard mask 2806, and the third hard mask 2810. .

Referring to Figure 28D, the overlying hard mask 2808 is removed. In one embodiment, the overlying hard mask 2808 uses a selective etch for the first hard mask 2804, the second hard mask 2806, the third hard mask 2810, and the fourth hard mask 2812, The ashing or cleaning process is removed to leave a fabric pattern, as shown in Figure 28D.

Figures 28E-28H are associated with a via patterning process. Referring to FIG. 28E, the third hard mask 2810 is removed, selective for the first hard mask 2804, selective for the second hard mask 2806, and selective for the fourth hard mask 2812 to provide It exposes an opening 2814 that covers a portion of the hard mask 2802. In one embodiment, the third hard mask 2810 is removed, selective for the first hard mask 2804, selective for the second hard mask 2806, and selective for the fourth hard mask 2812, Use a selective etch or cleaning process.

Referring to FIG. 28F, the through-hole light barrel patterning scheme is implemented as a first light barreling process. In one embodiment, a light bucket is formed in all of the exposed openings 2814 of Figure 28E. The selector of the light bucket is removed to re-expose the opening 2814 while the other light buckets 2816 are retained, for example, by not exposing the light bucket 2816 to a lithography and development process for opening all of the first light bucket. (In the particular case shown, three light buckets are retained and one is removed).

Referring to FIG. 28G, the exposed portion of the overlying hard mask 2802 is then etched to provide a first patterned hard mask 2820. Additionally, a metal layer 2800 is etched through the opening to provide an etched trench 2818 in the first patterned metal layer 2822. The first patterned metal layer 2822 includes conductive vias 2824. After the subtractive metal etch, the remaining light bucket 2816 is removed to re-expose the associated opening 2814.

Referring to Figure 28H, trench 2818 and opening 2814 are backfilled with a hard mask material. In one embodiment, a material similar or identical to the material of the third hard mask 2810 is formed on the structure of FIG. 28G and planarized or etched back to provide a deep hard mask region 2826 and a shallow hard mask region. 2828. In one embodiment, the deep hard mask region 2826 and the shallow hard mask region 2828 are of a third material type (ie, the material type of the third hard mask 2810).

Figures 28I-28L are related to wire cutting or plug forming a patterning process. Referring to FIG. 28I, the first hard mask 2804 is removed, selective for the second hard mask 2806, selective for the deep hard mask region 2826 of the third material type and the shallow hard mask region 2828, and for The fourth hard mask 2812 is selective to provide an opening 2830 that exposes a portion of the first patterned hard mask 2820. In one embodiment, the first hard mask 2804 is removed, selective for the second hard mask 2806, selective for the deep hard mask region 2826 of the third material type and the shallow hard mask region 2828, And for the fourth hard mask 2812, a selective etching or cleaning process is used.

Referring to Figure 28J, the cut or plug light bucket patterning scheme is implemented as a second light barreling process. In one embodiment, a light bucket is formed in all of the exposed openings 2830 of Figure 28I. The selector of the light bucket is removed to re-expose the opening 2830 while the other light buckets 2832 are retained, for example, by not exposing the light bucket 2832 to a lithography and development process for opening all of the other of the second light buckets. (In the particular case shown, three light buckets are retained and one is removed). The removed light bucket (at this stage) represents where the cut or plug will be in the final metallization layer. That is, in the second light drum process, the light bucket is removed from the position where the plug or cut will ultimately be formed.

Referring to Figure 28K, the exposed portion of the first patterned hard mask 2820 is then etched to provide a second patterned hard mask 2834 having trenches 2836 formed therein. After this etch, the remaining light bucket 2832 is removed to re-expose the associated opening 2830.

Referring to Figure 28L, trench 2834 and opening 2830 are backfilled with a hard mask material. In one embodiment, a material similar or identical to the material of the first hard mask 2804 is formed on the structure of FIG. 28K and planarized or etched back to provide a deep hard mask region 2838 and a shallow hard mask region. 2840. In one embodiment, the deep hard mask region 2838 and the shallow hard mask region 2840 are of the first material type (ie, the material type of the first hard mask 2804).

Referring to Figure 28M, the fourth hard mask 2812 is removed, selective for the deep hard mask region 2838 and the shallow hard mask region 2840 of the first material type, selective for the second hard mask 2806, and The deep hard mask region 2826 of the third material type and the shallow hard mask region 2828 are selective. In one embodiment, the fourth hard mask 2812 is removed, selective for the deep hard mask region 2838 of the first material type and the shallow hard mask region 2840, and selective for the second hard mask 2806, And for the third material type deep hard mask region 2826 and shallow hard mask region 2828, selective etching or cleaning processes are used. The deep etch process is performed through the resulting opening and completely through the second patterned hard mask 2834 to form a third patterned hard mask 2842; and completely through the first patterning of the metal layer 2822 to form a second time The metal layer 2844 is patterned. Although not depicted, at this stage, a second cutting or plug patterning process can be performed.

Referring to Figure 28N, the deep opening formed in association with Figure 28M is backfilled with a hard mask material. In one embodiment, a material similar or identical to the material of the fourth hard mask 2812 is formed on the structure of FIG. 28M and planarized or etched back to provide a deep hard mask region 2846. In one embodiment, the deep hard mask region 2846 is of the fourth material type (ie, the material type of the fourth hard mask 2812). In an alternative embodiment, as shown in association with 2899 of FIG. 28S, as described below, the ILD layer (such as a low-k dielectric layer) may be first filled and etched back to the level of the second patterned metal layer 2844. . A fourth type of hard mask material (i.e., a shallow version of 2846) is then formed on the ILD layer.

28O-28R are associated with the formation of a patterning process for the conductive sheets. Referring to Figure 28O, the second hard mask 2806 is removed, selective for the deep hard mask region 2838 of the first material type and the shallow hard mask region 2840, for the deep hard mask region 2826 of the third material type and The shallow hard mask region 2828 is selective and selective for the deep hard mask region 2846 of the fourth material type to provide an opening 2848 that exposes a portion of the third patterned hard mask 2842. In one embodiment, the second hard mask 2806 is removed, selective for the deep hard mask region 2838 of the first material type and the shallow hard mask region 2840, and for the deep hard mask region of the third material type The 2826 and shallow hard mask regions 2828 are selective and selective for the deep hard mask region 2846 of the fourth material type, using a selective etching or cleaning process.

Referring to FIG. 28P, the conductive sheet light barrel patterning scheme is implemented as a third light barreling process. In one embodiment, a light bucket is formed in all of the exposed openings 2848 of Figure 28O. The selector of the light bucket is removed to re-expose the opening 2848 while the other light bucket 2850 is retained, for example, by not exposing the light bucket 2850 to a lithography and development process for opening all other third light drums. (In the particular case shown, one light bucket 2850 is retained and three are removed). The removed light bucket (at this stage) represents where the conductive sheets will not be formed in the final metallization layer. That is, in the third light drum process, the light barrel 2850 is retained at a position where the conductive sheets will eventually be formed.

Referring to Figure 28Q, the exposed portion of the third patterned hard mask 2842 is then etched through opening 2848 to provide a fourth patterned hard mask 2852 having trenches 2854 formed therein. After this etching, the remaining light barrel 2850 is removed.

Referring to Figure 28R, the deep hard mask region 2838 of the first material type and the shallow hard mask region 2840 are removed, selective for the deep hard mask region 2826 and the shallow hard mask region 2828 of the third material type and for The deep hard mask region 2846 of the fourth material type is selective to further expose portions of the fourth patterned hard mask 2852. In one embodiment, the deep hard mask region 2838 of the first material type and the shallow hard mask region 2840 are removed, selective for the deep hard mask region 2826 and the shallow hard mask region 2828 of the third material type. And for the deep hard mask region 2846 of the fourth material type, a selective etching or cleaning process is used.

Referring to FIG. 28S, a deep etch process is performed through the resulting opening and completely through the second patterned metal layer 2844 to form a third patterned metal layer 2856. At this stage, in the case where its ILD layer 2899 is formed in the operation associated with FIG. 28N, as described above in the alternative embodiment, portions of this ILD layer 2899 are viewable in the structure of FIG. 28S. .

Referring to part (a) of Figure 28T, in one embodiment, the hard mask removal of the remaining hard mask portions 2828, 2846, 2852 of Figure 28S is performed and the structure is subsequently planarized. In one embodiment, the height of the deep hard mask region 2826 is reduced, but the regions are not all removed together to form the via cover 2858 and the ILD 2860. Further, a plug region 2862 is formed. In one embodiment, ILD 2899 is formed in association with FIG. 28N; and in one such embodiment, plug region 2862 includes material other than ILD 2899. In another embodiment, ILD 2899 is not formed in association with FIG. 28N; and ILD 2860 and the entire portion of plug 2862 are formed simultaneously and in the same material, for example, using an ILD backfill process. In one embodiment, the metallization portion of the structure includes a metal line 2864, a conductive via 2824 (having a via cover 2858 thereon), and a conductive strip 2866, as depicted in part (a) of Figure 28T.

Referring to part (a) of Figure 28T, in one embodiment, ILD backfill 2861 is formed on the structure of Figure 28S. In one such embodiment, the ILD film is deposited and then etched back to provide the structure of part (b) of Figure 28T. In one embodiment, the hard mask of FIG. 28S is left in place to perform the templating of the next metallization layer. That is, the appearance of the remaining hard mask can be used to template the next layer of the patterning process.

In either case, whether part (a) or (b) of Figure 28T, the embodiments described herein include the conduction of the remaining hard mask material (2858 or 2826) in the final metallization layer of the semiconductor structure. Above the through hole 2824. Moreover, referring again to Figures 28A-28T, it should be understood that the order of patterning for cuts, vias, and sheets may be interchangeable. At the same time, although the example process flow shows a cut, a through hole, and a pass, it can also perform a majority pass of each type of patterning.

Referring again to portion (a) of FIG. 28T, in one embodiment, the semiconductor structure back end of line (BEOL) metallization layer includes an interlayer dielectric (ILD) layer 2860. A plurality of conductive lines 2864 are disposed in the ILD layer 2860 along the first direction. The conductive sheet 2866 couples both of the plurality of conductive lines 2864 along a second direction orthogonal to the first direction.

This configuration, as shown in Figure 28T, cannot be achieved by conventional lithography (at small pitches, small widths, or both). At the same time, self-alignment cannot be achieved using traditional processing schemes. Moreover, the configuration as shown in FIG. 28T cannot be otherwise achieved in the case where the pitch division scheme is used to ultimately provide the pattern of the conductive lines 2864.

In one embodiment, both the conductive strip 2866 and the plurality of conductive lines 2864 are continuous rather than contiguous. In one embodiment, the conductive strip 2866 and the plurality of conductive lines 2866 are coplanar. In one embodiment, the BEOL metallization layer further includes a plug of dielectric material 2862 disposed on an end of one of the plurality of conductive lines 2866. In an embodiment, the BEOL metallization layer further includes a conductive via.

The structure of Figure 28T can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 28T can represent the last metal interconnect layer in the integrated circuit. Referring again to Figure 28T, this self-aligned fabrication by subtractive light barrel mode can be continued to fabricate the next metallization layer. Alternatively, other ways can be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene.

In accordance with an embodiment of the invention, resist adaptation for tolerance for exposure misalignment is described. Resist adaptation can include one or more of internal inhibition, graft layer inhibition, or top layer inhibition. One or more embodiments described herein relate to a two-stage baking photoresist having a releasable inhibitor. Applications can point to extreme ultraviolet (EUV) lithography, general lithography applications, solutions to overlapping problems, and general photoresist technology. In one embodiment, a material is described that is adapted to enhance the performance of the drum-based approach. In one aspect, the resist material is limited to a pre-patterned hard mask. The light bucket selector is then removed using a high resolution lithography tool (eg, EUV lithography tool). Particular embodiments can be implemented to enhance the consistency of the response of the resist material across a given optical barrel.

To provide a background, one of the objectives in the light bucket mode may be to first diffuse any EUV release acid across the exposed light barrel to enhance the consistency of the resist response across the selected light barrel. In past methods, this goal has been achieved by the use of special materials that enable the acid to diffuse across the barrel at a low temperature to avoid soluble switching reactions excited by these acids. However, the activity of another resist component (i.e., an inhibitor) may prevent this advantage from being fully realized. In particular, the inhibitor neutralizes the acids before they can diffuse or spread across a given light barrel. In response to such problems, in accordance with one or more of the embodiments described herein, the standard inhibitor is replaced with an inhibitor that can be released by extreme ultraviolet (UV) exposure or the like, which provides for avoiding premature acid And the ability.

More particularly, in accordance with one or more embodiments described herein, a light bucket resist material comprising a UV release inhibitor is implemented to effectively provide a "2-stage PEB" wherein the EUV exposure effect is effectively averaged horizontally Cross the established light bucket. These embodiments enable a "digital" bucket response in which the entire light bucket is cleared or not cleared. In a particular embodiment, this response is more tolerant of edge layout errors where the aerial image is not perfectly aligned with the light bucket grid.

To exemplify one or more concepts involved herein, FIGS. 29A-29C illustrate cross-sectional views and corresponding plan views of various operations in a method of patterning using a light barrel including a two-stage baking photoresist According to an embodiment of the invention.

Referring to FIG. 29A, a pre-patterned hard mask 2904 is disposed over the substrate 2902. The pre-patterned hard mask 2904 has an opening filled with a two-stage baked photoresist 2906. The two-stage bake photoresist 2906 is limited to openings in the pre-patterned hard mask 2904, for example, to provide a grid of potential via locations.

Referring to Figure 29B, the selected person of the light bucket is subjected to exposure 2907 from the lithography tool. The two-stage bake photoresist 2906 is exposed with a lithography tool (eg, an EUV lithography tool) to select which vias should be opened. In one embodiment, the alignment between the lithography tool and the pre-patterned hard mask 2904 grid is imperfect, resulting in asymmetry in exposure in the target light bucket and/or in adjacent light buckets. Partial exposure. Exposure 2907 is a shifted aerial image 2908 as seen in plan view.

Referring to Figure 29C, although the exposure of Figure 29B may have involved misalignment and partial exposure of the unselected light buckets, only the selected light buckets are cleared to form openings 2920, leaving the unselected light buckets closed to the light drums 2912. In one embodiment, the process is used to ensure that only the selected photocell is finally opened, followed by exposure 2907 of the selected area of the two-stage bake photoresist 2906, all two-stage bake photoresist 2906 was first baked to promote acid diffusion. Extreme ultraviolet (UV) inhibited release is then performed to neutralize the acid. The second bake is then performed to facilitate soluble switching, as described in more detail below. In a particular embodiment, the photoacid released from the first bake operation is diffused throughout the photocell. A large amount of UV exposure releases the inhibitor and then the final soluble switching bake is fulfilled. This process is detailed below in conjunction with Figures 30A-30E.

As a result, the selected location that receives the larger exposure is eventually cleared to provide an open light bucket position 2920, subsequent to development. The unselected position that is not exposed (or only partially exposed but to a lesser extent, in the event of misalignment) remains at the closed barrel position 2912, following the development.

To demonstrate the opposite situation in which a conventional photoresist is used, FIG. 1D illustrates a cross-sectional view of a conventional resist photobucket structure following development of a bare barrel after misalignment exposure. The light bucket area 2954 is shown to only partially remove 2950, leaving some residual photoresist 2952. In the event that its light bucket 2954 is a selected light bucket, the misalignment exposure 2907 only partially clears the light bucket, which can result in subsequent poor quality manufacturing of the conductive structures in such locations. In the event that its light bucket 2954 is a non-selected light bucket, an unwanted opening 2950 occurs, potentially resulting in subsequent formation of conductive structures in unwanted locations.

In a more detailed process description, Figures 30A-30E illustrate a schematic view of various operations in a method of patterning using a light bucket that includes a two-stage baked photoresist, in accordance with an embodiment of the present invention.

Referring to FIG. 30A, the first 3002 and second 3004 optical barrels each include a photodegradable composition including an acid deprotectable photoresist material, a photoacid generating (PAG) component 3010, and a photobase generating component 3012. The misaligned EUV or electron beam exposure 3006 is performed in a selected light bucket 3002 and a non-selected light bucket 3004 that exposes a plurality of selected light buckets 3002 and partially exposes the unselected light buckets 3004 (but to a lesser extent). In a particular embodiment, the photobase generating component 3012 is a UV releasable inhibitor.

Referring to Figure 30B, the first bake is fulfilled. In one embodiment, the first bake is performed at too low a temperature to cause a soluble switch. In one such embodiment, the bake is diffusion only, resulting in diffused materials 3020 and 3022 of light barrels 3002 and 3004, individually.

Referring to Figure 30C, inhibitor 3014 is released to individually form materials 3024 and 3026 of light barrels 3002 and 3004. In one embodiment, inhibitor 3014 is an inhibitor of UV release. In certain such embodiments, the inhibitor of UV release is released by extensive UV exposure (eg, 365 nm exposure). In one embodiment, both of the optical barrels 3002 and 3004 are exposed to a large amount of exposure to the same extent.

Referring to Figure 30D, a second bake is performed to individually provide materials 3028 and 3030 of light buckets 3002 and 3004. In one embodiment, the second bake system produces a soluble switch wherein the secondary critical acid concentration is inhibited. In this way, there is substantially no local acid concentration. That is, the deprotection of the portion of the optical barrel that is not only partially exposed does not occur.

Referring to FIG. 30E, the optical tubs 3002 and 3004 are subjected to a developing process. The selected light bucket 3002 is removed during development to provide a cleared light bucket 3032. The unselected light bucket 3004 is not removed during development and remains in the blocked light bucket 3034. In this way, even in the event of misalignment exposure, a digital light bucket response (only open or closed, no partial open) is achieved.

It should be understood that not all embodiments require a single composition to achieve a two-stage baked photoresist. In a first alternative, Figure 30A' illustrates a schematic view of another operation in a method of patterning using a light bucket, in accordance with an embodiment of the present invention. Referring to Figure 30A', the first 3002' and second 3004' optical barrels each include a grafted light-based generating component 3050 along the bottom and sidewalls of the first 3002' and second 3004' light buckets. The photobleachable composition is formed in the grafted light-based generating component 3050. The photobleachable composition includes an acid deprotectable photoresist material and a photoacid generating (PAG) component 3010'. The exposure 3006' and the multi-stage development process can then be performed, similar to the manner described above.

In a second alternative, Figure 30A" illustrates a schematic view of another operation in a method of patterning using a light bucket, in accordance with an embodiment of the present invention. Referring to Figure 30A", first 3002" and second 3004" light The barrels each comprise a photodegradable composition comprising an acid deprotectable photoresist material and a photoacid generating (PAG) component 3010". After performing the first bake, a layer 3060 comprising a base generating component is formed in the first 3002" and second 3004". The light barrels 3002" and 3004" are then exposed to ultraviolet (UV) illumination. In this case, the base component does not need to be introduced via a photo-based generator, but can be deposited later. The process operation, for example, by vapor deposition or exposure to the base atmosphere NMP.

The application of the above-described photoresist composition and manner can be implemented to produce a regular structure that covers all possible vias (or plugs) locations, followed by selective patterning with only the desired features. To provide further material details, in one embodiment, referring again to Figures 30A-30E, light buckets 3002 and 3004 comprise a photodegradable composition. The photobleachable composition comprises an acid deprotectable photoresist material having substantially transparency at a certain wavelength. The photobleachable composition also includes a photoacid generating (PAG) component having substantially transparency at that wavelength. The photobleachable composition comprises a radical generating component that is substantially absorptive to the wavelength. In an alternate embodiment, the acid deprotectable photoresist material is not substantially transparent at this wavelength.

In one embodiment, the group generating component is one selected from the group consisting of a photo-based generating component, an electron-based generating component, a chemical-based generating component, and a UV-based generating component. In one embodiment, the base generating component is a sonic basis generating component. In one embodiment, the base generating component is UV absorbing. In one embodiment, the base generating component comprises a low energy UV chromophore. In a particular such embodiment, the low energy UV chromophore is selected from the group consisting of anthracenylcarbamates, naphthalenylcarbamates, 2-nitrobenzene 2-nitrophenylcarbamates, arylcarbamates, coumarins, phenylglyoxylic acid, acetophenones, and diphenyl ketone Benzophenones). In one embodiment, the low energy UV chromophore is a light releasing amine. In one embodiment, the base generating component comprises a material selected from the group consisting of N,N-dicyclohexyl-2-nitrophenylcarbamate (N,N-dicyclohexyl-2-nitrophenylcarbamate) , N,N-disubstituted carbamates and mono-substituted carbamates.

In one embodiment, the PAG component comprises a material selected from the group consisting of triethyl, trimethyl, and other trialkylsulfonates, wherein the sulfonate group The group is selected from the group consisting of trifluoromethylsulfonate, nonanfluorobutanesulfonate, and p-tolylsulfonate, or limited to organic Other examples of groups containing -SO ₃ sulfonate anions. In one embodiment, the acid deprotectable photoresist material is an acid deprotectable material selected from the group consisting of polymers, molecular glasses, carbon decane, and metal oxides. In one embodiment, a metal oxide is used and the release group is not required. In one embodiment, the acid deprotectable photoresist material comprises a material selected from the group consisting of polyhydroxystyrene, polymethyl methacrylate, polyhydroxystyrene, or polymethyl methacrylate. The small molecule weight molecular glass version (which contains acid catalyzed deprotection for the carboxylic acid is ester functional), the carbon decane, and the metal oxide processing function (which is sensitive to acid catalyzed deprotection or crosslinking).

In one embodiment, the wavelength is about 365 nm. In one embodiment, the acid deprotects the photoresist material to be substantially absorptive at a wavelength of about 13.5 nanometers. In one embodiment, the acid deprotects the photoresist material from substantially absorbed energy in the range of about 5-150 keV. In one embodiment, the molar ratio of the PAG component to the base generating component is at least 50:1.

Referring again to FIGS. 30A-30E, 30A' and 30A", in accordance with an embodiment of the present invention, a method of selecting a light bucket for semiconductor processing includes providing a structure having a first light adjacent to a second light bucket 3004 Bucket 3002. The structure is exposed to extreme ultraviolet (EUV) or electron beam illumination 3006, wherein the first light barrel 3002 is exposed to EUV or electron beam illumination 3006 to a greater extent than the second light barrel 3004. The structure is exposed to After EUV or electron beam irradiation 3006, the first bake of the first and second bale is performed as described in connection with Figure 30B. After performing the first bake, the structure is exposed to ultraviolet (UV) illumination, wherein The first light barrel is exposed to UV radiation to the same extent as the second light barrel, as described in connection with Figure 30C. After exposing the structure to UV illumination, the second baking of the first and second light barrels is Fulfillment, as described in connection with Figure 30 D. After the second bake is performed, the structure is developed. The development system opens the first light bucket and leaves the second light bucket closed, as described in association with Figure 30E.

In one embodiment, exposing the structure to extreme ultraviolet (EUV) or electron beam illumination comprises exposing the structure to an energy having a wavelength of about 13.5 nanometers. In another embodiment, exposing the structure to extreme ultraviolet (EUV) or electron beam illumination comprises exposing the structure to energy in the range of 5-150 keV. In one embodiment, exposing the structure to UV radiation comprises exposing the structure to energy having a wavelength of about 365 nm. In one embodiment, the first bake is performed over a period of time in the range of about 50-120 degrees Celsius in the range of about 0.5-5 minutes. In one embodiment, the second bake is performed over a period of time in the range of about 100-180 degrees Celsius in the range of about 0.5-5 minutes.

In an embodiment, referring specifically to FIG. 30A, the first and second optical barrels each comprise a photodegradable composition comprising an acid deprotectable photoresist material, a photoacid generating (PAG) component, and a photobase generation. ingredient. In one such embodiment, exposing the structure to extreme ultraviolet (EUV) or electron beam illumination includes activating the PAG component. The first bake spreads the acid formed from the activated PAG component throughout the first and second optical barrels. Exposing the structure to UV irradiation includes activating the photobase generating component. The second baking utilizes a radical generated from the photobase generating component to suppress the total amount of acid formed in the second optical barrel, but does not inhibit the total amount of acid formed in the first optical barrel.

In another embodiment, referring specifically to FIG. 30A', the first and second optical barrels each include a grafted light-based generating component (along the bottom and sidewalls of the first and second optical barrels) and photodegradable (formed) In the grafted photobase generating component). The photodegradable composition includes an acid deprotectable photoresist material and a photoacid generating (PAG) component. In one such embodiment, exposing the structure to extreme ultraviolet (EUV) or electron beam illumination includes activating the PAG component. The first bake spreads the acid formed from the activated PAG component throughout the first and second optical barrels. Exposing the structure to UV irradiation includes activating the grafted light-based generating component. The second baking utilizes a radical generated from the photobase generating component to suppress the total amount of acid formed in the second optical barrel, but does not inhibit the total amount of acid formed in the first optical barrel.

In another embodiment, referring specifically to FIG. 30A", the first and second optical barrels each comprise a photodegradable composition comprising an acid deprotectable photoresist material and a photoacid generating (PAG) component. Further included, after performing the first bake and prior to exposing the structure to ultraviolet (UV) illumination, forming a layer comprising a base generating component on the first and second optical barrels. In one such embodiment, exposing The structure of extreme ultraviolet (EUV) or electron beam irradiation includes activating the PAG component. The first baking diffuses the acid formed from the activated PAG component throughout the first and second optical barrels. Exposing the structure to UV irradiation includes activating the substrate. The second baking system utilizes a base generated from the base generating component to suppress the total amount of acid formed in the second optical drum, but does not inhibit the total amount of acid formed in the first optical drum.

In any of the above, in one embodiment, developing the structure comprises (in the case of positive tone development) a standard aqueous TMAH developer (eg, in a concentration range from 0.1 M to 1 M) or The other aqueous or alcoholic developer of tetramethylammonium hydroxide is immersed or coated for 30-120 seconds, followed by DI water cleaning. In another embodiment, in the case of negative tone development, developing the structure comprises immersing or coating with an organic solvent such as cyclohexanone, 2-heptanone, propylene glycol methyl ethyl acetate or the like, followed by Wash with another organic solvent such as hexane, heptane, cyclohexane, and the like.

In an exemplary embodiment, the manner described above is established using a so-called light bucket wherein each possible feature (eg, a via) is pre-patterned into the substrate. Next, the photoresist is filled into the patterned features and the lithographic operation is only used to select the selected vias for via opening. In a particular embodiment, lithography operations are used to define a relatively large aperture above a plurality of optical barrels comprising a two-stage baked photoresist, as described above. The two-stage bake photoresist bath mode allows for large critical dimensions (CD) and/or errors in overlap while retaining the ability to select vias of interest.

In accordance with an embodiment of the present invention, image tonal reversal of the resist (e.g., for a light bucket) is described. One or more embodiments described herein relate to a class of materials having particular properties to enable pattern reversal (e.g., hole reversal to the column), and associated processing and structure resulting from the class of materials. The material category can be a soft material category, such as a photoresist-like material. As a general approach, a resist-like material is deposited in a pre-patterned hard mask. The resist material can then be selected using a high resolution lithography tool, such as an extreme ultraviolet (EUV) processing tool. On the other hand, a resist-like material may alternatively be left to remain permanently in the last fabricated structure, for example, it forms an interlaminar dielectric (ILD) material or structure that breaks between metal lines ("plug Plug"). The overlap (edge layout) problem expected for the next generation plug patterning can be solved by one or more of the ways described herein.

More specifically, one or more embodiments described herein relate to the use of a spin-on dielectric (eg, ILD) having a fill that enables holes ("barrels") in the patterned photoresist layer. Without destroying the special properties of the photoresist layer pattern. First, the spin-on dielectric material is introduced into a solvent that does not dissolve or cause intermixing of the photoresist and the dielectric material. It should be understood that good fillability of the holes is required. The initial crosslinking (or setting) of the spin-on dielectric film is accomplished under conditions in which the photoresist and the spin-on dielectric are not miscible and lose pattern information. Once the pattern is reversed, the material within the barrel is then converted (through baking/hardening) to a dielectric having desirable properties such as k-value, modulus, etch selectivity, and the like. Although not limited to such materials, spin-on dielectric materials that build blocks based on 1,3,5-trisilacyclohexane can be implemented to meet the above criteria. Crosslinking of the solubility loss of such a material (or other ruthenium based dielectric) can be initiated (either thermally or at a lower temperature) by using an acid, base or Lewis acid catalyst process. In one embodiment, this low temperature catalysis is critical to the manner of the modes described herein.

In one embodiment, the manner described herein relates to the use of optimal imaging performance (eg, from a positive tone material) to produce a negative tone pattern, with the final film process pursuing material properties. The final material properties can be approximated for those high performance low k dielectric/ILD materials. Conversely, the most advanced options for direct patterning of dielectric films are limited and are not expected to exhibit the necessary lithographic properties for future generations of shrinking technology generation.

As described in greater detail below in conjunction with Figures 31 and 32A-32H, in accordance with embodiments described herein, the trench pre-patterning in the ILD material is filled with a chemically amplified photoresist. Using high resolution lithography (eg, EUV), selected holes within the trenches are exposed and removed via conventional positive tone processing. At this stage, empty holes are treated with a pre-catalyst layer. In one such embodiment, the precatalyst layer is a self-polymerizing monolayer (SAM) containing an additional catalyst layer. The resulting decorative aperture is then filled with a dielectric precursor with concomitant overload. Localization (or proximity) of the catalyst in the pores results in selective crosslinking and setting of only the dielectric in the pores. The overload and photoresist are removed, followed by the dielectric (if needed) and the final hardening of the metallization process.

In accordance with an embodiment of the present invention, a key feature of the manner described herein relates to the adaptation of varying pattern density and varying thickness of an overload. In one embodiment, this adaptation is enabled because cross-linking only occurs in/near the hole and the overload is eventually removed by planarization (eg, by chemical mechanical polishing). In one embodiment, selective crosslinking of the dielectric material in the pores is achieved without incurring selective crosslinking in the region of the overload. In a particular embodiment, following the patterning and development of the positive tone lithography, the hydrophilic Si-OH termination surface is exposed to the holes and any locations where the photoresist has been removed. The hydrophilic surface may be present prior to coating of the photoresist or during, for example, tetramethylammonium hydroxide (TMAH) development or subsequent cleaning. It should be understood that photoresists that have not been exposed and developed will remain mildly or strongly hydrophobic in nature, and thus, the patterning process effectively produces hydrophilic and hydrophobic domains.

In one embodiment, the exposed hydrophilic surface is functionalized with a surface grafting agent that carries the catalyst or precatalyst required to crosslink the dielectric material. Subsequent coating of the dielectric results in the filling of the holes using the overload, as described above, and as explained in more detail below. Upon activation and controlled diffusion of, for example, a low temperature baked precatalyst, the dielectric material is selectively crosslinked into the pores with minimal cross-linking occurring in the overload, ie, directly in the pores on. The overloaded dielectric material can then be removed using dissolution in a casting solvent or another solvent. It should be understood that the removal process may also remove the photoresist, or the photoresist may be removed using another solvent or by an ashing process. In one embodiment, as the hue is reversed, the dielectric material can be baked/hardened to a relatively high temperature prior to metallization or other processing.

In one or more embodiments described herein, there are several ways to place the catalyst or precatalyst in the pores. For certain dielectric materials, strong Brinell is required. In other cases, a strong Lewis acid can be utilized. For the sake of simplicity in the description, the term "acid" is used to refer to both situations. In one embodiment, direct absorption of the catalyst or precatalyst is utilized. In this context, the catalyst is coated onto a hydrophilic surface and held securely via H-bonding or other electrostatic interaction. Subsequent coating of the dielectric material causes the acid and dielectric precursors to be localized in the pores where heat or other activation initiates the desired crosslinking chemistry. In the exemplary embodiment, the reaction of the Si-OH rich surface with the strong Lewis acid B (C ₆ F ₅ ) ₃ results in the formation of Si-OB(C ₆ F ₅ ) ₃ H ⁺ . The resulting Lewis acid is used to catalyze the crosslinking of hydrosilane precursor molecules at relatively lower temperatures than the non-catalytic process. In one embodiment, the large catalyst utilized minimizes diffusion into the overload zone.

In another embodiment, the manner relates to covalent bonding of a catalyst or precatalyst via a decane chemistry, such as chlorine, alkoxy, and amine decane or other surface grafting groups, which may include oxoxane, hydrazine Base chloride, alkene, alkyne, amine, phosphine, thiol, phosphonic acid or carboxylic acid. In this context, the catalyst or precatalyst is covalently linked to the grafting agent. For example, a well-known acid generator (for example, light or heat) according to a cerium salt may be adhered to a siloxane (for example, [(MeO) ₃ Si-CH ₂ CH ₂ CH ₂ SR ₂ ] [X], where R = alkyl or aryl group and X = a weakly coordinating anion, such as trifluoromethanesulfonate, nonafluorobutanesulfonate _{(nonaflate), HB (C 6} F 5) 3, BF 4, etc.) . The catalyst or precatalyst can be selectively adhered to the ILD of interest, or selectively removed from the resist, using a thermal, dry etch, or wet etch process. In yet another embodiment, the catalyst or precatalyst is introduced prior to photoresist coating using similar techniques. In this context, in order to be effective, the grafting material must not interfere with lithography and must withstand subsequent processing.

Figure 31 illustrates an oblique view of an alternating pattern of interlayer dielectric (ILD) lines and resist lines, which is formed in one of the resist lines, as an exemplary means of acting to demonstrate the concepts described herein. Holes, in accordance with embodiments of the present invention. Referring to FIG. 31, pattern 3100 includes alternating ILD lines 3102 and resist lines 3104. Holes 3106 are formed in one of the resist lines 3104, for example, by conventional lithography. As described below, in association with Figures 32A-32H, a pattern such as pattern 3100 can undergo hue inversion.

In the example process flow, Figures 32A-32H illustrate a cross-sectional view in a fabrication process involving the use of a bottom-up cross-linked dielectric image inversion of a dielectric, in accordance with an embodiment of the present invention.

Figure 32A illustrates a cross-sectional view of the starting structure after pre-patterning of trenches 3204 in ILD material 3202. The selected one of trenches 3204 is filled with chemically amplified photoresist 3206, while others have been processed to provide unfilled trenches (or unfilled trench portions, as shown in FIG. 31). For example, in one embodiment, using high resolution lithography (eg, extreme ultraviolet (EUV) lithography), selected apertures within the trenches 3204 are exposed and removed via conventional positive tone processing.

Although not depicted for simplicity, it should be understood that the unfilled trenches (or holes formed in the filled trenches) may expose underlying features, such as underlying metal lines, in region 3208. Furthermore, in an embodiment, the starting structure can be patterned in a grating-like pattern having grooves spaced at a constant pitch and having a constant width. The pattern, for example, can be manufactured by halving the pitch or reducing the pitch by a quarter. Some trenches can be associated with lower vias or lower order metallization lines.

Figure 32B illustrates a cross-section of the structure of Figure 32A following the disposal of a blank trench or hole having a pre-catalyst layer 3210 (which, in one embodiment, a self-polymerizing monolayer (SAM) containing a catalyst material). view. In one such embodiment, as shown, pre-catalyst layer 3210 is formed on the exposed portion of ILD 3202, but not on the exposed portion of resist 3206 or any exposed metal (such as above region 3208). . In one embodiment, the pre-catalyst layer 3210 is formed by exposing the structure of FIG. 32A to a pre-catalyst-forming molecule in a gas phase, or a molecule dissolved in a solvent. In one embodiment, the pre-catalyst layer is a layer of catalyst or pre-catalyst formed by direct adsorption, as described above. In another embodiment, the pre-catalyst layer 3210 is a layer of a catalyst or pre-catalyst formed by covalent adhesion.

Figure 32C illustrates a cross-sectional view of the structure of Figure 32B following the use of dielectric material 3212 to fill the resulting decorative aperture. It should be understood that the dielectric material 3212 has portions 3212A that fill the trenches or holes and portions 3212B that are located above the trenches or holes. Section 3212B is referred to herein as overloading. In one embodiment, the dielectric material 3212 is a spin-on dielectric material.

In one embodiment, the dielectric material 3212 is selected from the group consisting of hydroquinone precursor molecules, wherein the catalyst mediates Si-H bonds with crosslinkers (such as water, tetraethoxy decane (TEOS), hexaethoxylate). The reaction of hexaethoxytrisilacyclohexane or a similar multifunctional crosslinking agent. In one such embodiment, the dielectric material 3212 includes triterpene cyclohexane, which can be subsequently linked together by groups of O. In other embodiments, an alkoxydecane-based dielectric precursor or semi-aluminoxane (SSQ) is used for the dielectric material 3212.

Figure 32D illustrates a cross-sectional view of the structure of Figure 32C following the crosslinking of portion 3212A of dielectric material 3212. In one embodiment, localization (or proximity) of the unfilled trench or catalyst (eg, pre-catalyst layer 3210) results in selective cross-linking to form cross-linking region 3214 and portion 3212A of dielectric material 3212. , only in these holes. That is, in one embodiment, portion 3212B of dielectric material 3212 is not crosslinked. In one embodiment, the intersection used to form region 3214 is accomplished by a thermal hardening process (ie, by heating).

In one embodiment, the dielectric material 3212 includes triterpene cyclohexane, and the crosslinking used to form the region 3214 includes crosslinking the triterpene cyclohexane together by groups of O. Referring to Figure 33A, triterpene cyclohexane 3300 is illustrated. Referring to Figure 33B, two crosslinked (XL) triterpene cyclohexane molecules 3300 form a crosslinked material 3320. Figure 33C illustrates an idealized representation of a chain triterpene cyclohexane structure 3340. It should be understood that, in practice, structure 3340 is used to indicate the mixing of the oligomer composites, but in common is the H-capped triterpene cyclohexane ring.

Figure 32E illustrates a cross-sectional view of the structure of Figure 32D following removal of the overload region 3212B of the dielectric material 3212. Figure 32F illustrates a cross-sectional view of the structure of Figure 32E following removal of resist 3206 selective to cross-linking region 3214. In one embodiment, as depicted, the resist 3206 is removed in subsequent and different processing operations, such as a second wet chemical development operation, relative to the overload region 3212B used to remove the dielectric material 3212. Processing operations (such as a first wet chemical development operation). However, in another embodiment, the resist 3206 is removed in the same processing operation (such as a wet chemical development operation) to remove the overload region 3212B of the dielectric material 3212. In one embodiment, the remaining cross-linking zone 3214 is subjected to an additional hardening process (eg, additional heating subsequent to the cross-linking hardening process). In one embodiment, additional hardening is performed following the removal of the resist 3206 and the overload region 3212B.

Figure 32G illustrates a cross-sectional view of the structure of Figure 32F following the formation of the metal fill layer 3216. Metal fill layer 3216 can be formed in the open trenches (or holes) from Figure 32F, as well as in the overload region. The metal fill layer can be a single material layer or can be formed from several layers, including a conductive backing layer and a fill layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, can be used to form the metal fill layer 3216. In one embodiment, the metal fill layer 3216 is composed of a conductive material such as, but not limited to, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au or its alloy.

Figure 32H illustrates a cross-sectional view of the structure of Figure 32G following planarization of a metal fill layer used to form metal features 3218 (e.g., metal lines or vias). In one embodiment, the planarization of the metal fill layer 3216 used to form the metal features 3218 is performed using a chemical mechanical polishing process. The resulting structure is shown in FIG. 32H in which metal features 3218 are alternately disposed with cross-linked (dielectric) regions 3214 in ILD material 3202.

It should be understood that the resulting structure of Figure 32H can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 32H can represent the last metal interconnect layer in the integrated circuit. Again, it should be understood that the above examples do not include an etch stop or metal capping layer in the pattern, which may otherwise be required for patterning. However, for the sake of clarity, these layers are not included in the graph because they do not affect the overall bottom-up fill concept.

Referring again to Figures 32A-32H, this patterning scheme can be implemented as an integrated patterning approach involving the creation of a regular structure covering all possible locations, followed by selective patterning of only the desired features. Crosslinking region 3214 represents a material that may remain in the final structure to become an ILD (eg, become a plug) between the ends of the metal lines.

In accordance with an embodiment of the invention, a diagonal mask patterning is described. One or more embodiments described herein are directed to diagonal hard mask patterning for overlay improvement, particularly in the fabrication of semiconductor integrated circuit back end of line (BEOL) features. Patterning applications based on diagonal hard masks may include, but are not limited to, the following embodiments: 193 nm immersion lithography, extreme ultraviolet (EUV) lithography, interconnect fabrication, overlay improvement, overlay budget, plug pattern Patterning and through-hole patterning. Embodiments may be particularly useful for self-aligned fabrication of BEOL structures.

In one embodiment, the manner described herein relates to an integrated solution that allows for increased via and plug overlap tolerances relative to existing modes. In one such embodiment, all of the potential vias and plugs are pre-patterned and filled with a resist to form a plurality of light barrels. Thereafter, in a particular embodiment, EUV or 193 nm lithography is used to select certain via and plug locations for the actual (final) via and plug fabrication. In one embodiment, diagonal patterning is used to increase the nearest neighbor distance, which results in an increase in the factor of the square root of the overlap budget. More specifically, one or more of the embodiments described herein involve the use of a subtractive method to pre-form each via and plug using an etched trench. An additional operation is then used to select which vias and plugs to retain. These operations are illustrated using a light barrel, although a more conventional resist exposure and ILD backfilling method can be used to perform the selection process.

In one form, a diagonal hard masking approach can be implemented. By way of example, Figures 34A-34X illustrate portions of an integrated circuit layer that illustrate various operations in a method of using self-aligned vias and plug patterning of diagonal hard masks, in accordance with an embodiment of the present invention. . In each of the illustrated figures, a cross-section and/or a plane and/or a beveled view are displayed. These views will be referred to herein as corresponding cross-sectional views, plan views, and beveled views.

Figure 34A illustrates a cross-sectional view of the starting structure 3400 following deposition (but prior to patterning) of the first hard mask material layer 3404 formed over the interlayer dielectric (ILD) layer 3402, in accordance with an embodiment of the present invention. . Referring to Figure 34A, patterned mask 3406 has spacers 3408 formed on or over first hard mask material layer 3404 (along its sidewalls).

Figure 34B illustrates a cross-sectional view of the structure of Figure 34A following the patterning of the first hard mask layer by doubling the pitch, in accordance with an embodiment of the present invention. Referring to FIG. 34B, the patterned mask 3406 is removed and the resulting pattern of spacers 3408 is transferred (eg, by an etch process) to the first hard mask material layer 3404 to form a first patterned hard mask 3410. In one such embodiment, the first patterned hard mask 3410 is formed in a grating pattern, as depicted in Figure 34B. In one embodiment, the grating structure of the first patterned hard mask 3410 is a tight pitch grating structure. In certain such embodiments, the tight pitch cannot be obtained directly through conventional lithography. For example, a pattern according to conventional lithography may be formed first (mask 3406), but the pitch may be halved by patterning using spacer masks, as depicted in Figures 34A and 34B. Even though not shown, the original pitch can be reduced to a quarter by the second round of spacer mask patterning. Thus, the grating-like pattern of the first patterned hard mask 3410 of Figure 34B can have a hard mask line that is separated by a constant pitch and has a constant width.

Figure 34C illustrates a cross-sectional view of the structure of Figure 34B following the formation of the second patterned hard mask, in accordance with an embodiment of the present invention. Referring to FIG. 34C, a second patterned hard mask 3412 is formed to be interlaced with the first patterned hard mask 3410. In one such embodiment, the second patterned hard mask 3412 is formed by deposition of a second layer of hard mask material (eg, having a composition different from the first layer of hard mask material 3404). The second layer of hard mask material is then planarized (eg, by chemical mechanical polishing (CMP)) to provide a second patterned hard mask 3412.

Figure 34D illustrates a cross-sectional view of the structure of Figure 34C following deposition of a hard mask cap layer (third hard mask layer), in accordance with an embodiment of the present invention. Referring to FIG. 34D, a hard mask cap layer 3414 is formed on the first patterned hard mask 3410 and the first patterned hard mask 3412. In one such embodiment, the material composition and etch selectivity of the hard mask cap layer 3414 is different from the first patterned hard mask 3410 and the first patterned hard mask 3412.

Figure 34E illustrates a perspective view of the structure of Figure 34D following the patterning of the hard mask cap layer, in accordance with an embodiment of the present invention. Referring to FIG. 34E, a patterned hard mask cap layer 3414 is formed over the first patterned hard mask 3410 and the first patterned hard mask 3412. In one such embodiment, the patterned hard mask cap layer 3414 is formed with a grating pattern orthogonal to the grating pattern of the first patterned hard mask 3410 and the first patterned hard mask 3412, as shown in the figure. Shown in 34E. In one embodiment, the grating structure formed by the patterned hard mask cap layer 3414 is a closely pitched grating structure. In this embodiment, the tight pitch cannot be obtained directly through conventional lithography. For example, a pattern according to a conventional lithography may be formed first, but the pitch may be halved by patterning using a spacer mask. Even the original pitch can be reduced to a quarter by the second round of spacer mask patterning. Thus, the rasterized pattern of the patterned hard mask cap layer 3414 of Figure 34E can have a hard mask line that is separated by a constant pitch and has a constant width. It should be understood that the description herein relates to forming and patterning a hard mask layer (or hard mask layer, such as hard mask cap layer 3414) involving (in one embodiment) masking formed over a covered hard mask or hard mask. Above the cover layer. Mask formation may involve the use of one or more layers suitable for lithography processing. When patterning one or more lithographic layers, the pattern is transferred to a hard mask or hard mask cap layer by an etch process to provide a patterned hard mask or hard mask cap layer.

Figure 34F illustrates an oblique angle view and corresponding plan view of the structure of Figure 34E following further patterning of the first patterned hard mask, in accordance with an embodiment of the present invention. Referring to FIG. 34F, using the patterned hard mask cap layer 3414 as a mask, the first patterned hard mask 3410 is further patterned to form a first patterned hard mask 3416. The second patterned hard mask 3412 is not further patterned into this process. In one embodiment, the first patterned hard mask 3410 is patterned to a depth sufficient to expose regions of the ILD layer 3402, as depicted in Figure 34F.

Figure 34G illustrates a plan view of the structure of Figure 34F following the removal of the hard mask cap layer and the formation of the fourth hard mask layer, in accordance with an embodiment of the present invention. Referring to FIG. 34G, a hard mask cap layer (third hard mask layer) 3414 is removed, for example, by a wet etching process, a dry etching process, or a CMP process. A fourth hard mask layer 3418 is formed over the resulting structure by (in one embodiment) a deposition and CMP process. In one such embodiment, the fourth hard mask layer 3418 is formed by deposition of a layer of material different from the material of the second patterned hard mask layer 3412 and the first patterned hard mask layer 3416.

Figure 34H illustrates a plan view of the structure of Figure 34G following deposition and patterning of the first diagonal hard mask layer, in accordance with an embodiment of the present invention. Referring to FIG. 34H, a first diagonal hard mask layer 3420 is formed on the fourth hard mask layer 3418, the second patterned hard mask layer 3412, and the first patterned hard mask layer 3416 of FIG. 34G. . In one embodiment, the first diagonal hard mask layer 3420 has a substantially or highly symmetric diagonal pattern (eg, 45 degrees relative to the grating structure of the second pattern hard mask layer 3412). An alternating line of the fourth hard mask layer 3418 is covered. In one embodiment, the diagonal pattern of the first diagonal hard mask layer 3420 is printed with a minimum critical dimension (CD), ie, the pitch is not halved or the pitch is reduced by a quarter. . It should be understood that the individual lines can be printed to be even larger than the minimum CD as long as some area of the adjacent columns of the fourth hard mask layer 3418 remain exposed. In any event, the raster pattern of the first diagonal hard mask layer 3420 of Figure 34H can have a hard mask line that is separated by a constant pitch and has a constant width. It should be understood that the description herein relates to forming and patterning a diagonal hard mask layer, such as first diagonal hard mask layer 3420, involving (in one embodiment) a mask formed over the overlying hard mask layer. . Mask formation may involve the use of one or more layers suitable for lithography processing. When patterning one or more lithographic layers, the pattern is transferred to the hard mask layer by an etching process to provide a diagonally patterned hard mask layer. In a particular embodiment, the first diagonal hard mask layer is a carbon based hard mask layer.

Figure 34I illustrates a plan view of the structure of Figure 34H following removal of the exposed regions of the fourth hard mask layer, in accordance with an embodiment of the present invention. Referring to FIG. 34I, using the first diagonal hard mask layer 3420 as a mask, the exposed area of the fourth hard mask layer 3418 is removed. In one such embodiment, the exposed regions of the fourth hard mask layer 3418 are removed by an isotropic etch process (eg, a wet etch process or a non-anisotropic plasma etch process) such that any Partial exposure results in complete removal of a portion of the exposed portion of the fourth hard mask material. In one embodiment, the region in which the fourth hard mask layer 3418 has been removed reveals portions of the ILD layer 3402, as depicted in FIG. 34I.

Figure 34J illustrates a plan view of the structure of Figure 34I following removal of the first diagonal hard mask layer, in accordance with an embodiment of the present invention. Referring to FIG. 34J, the first diagonal hard mask layer 3420 is removed to reveal the first patterned hard mask layer 3416 and the second patterned hard mask layer 3412. Also shown is a portion of the fourth hard mask layer 3418 that is protected from being etched by the first diagonal hard mask layer 3420. Therefore, the alternate rows of the resulting grid-like pattern of FIG. 34J or the alternate rows of the resulting grid-like pattern of FIG. 34J are downward, and the fauna of the fourth hard mask layer 3418 and the lower ILD layer 3402 are revealed. The area is alternately configured. That is, the result is a checkerboard pattern of the ILD layer 3402 area and the fourth hard mask layer area 3418. As a result, the increase in the square root factor of two is achieved closest to the adjacent distance 3422 (shown as the distance in direction b). In a particular embodiment, the first diagonal hard mask layer 3420 is a carbon based hard mask material and is removed by a plasma ashing process.

Figure 34K illustrates a plan view of the structure of Figure 34J following the formation of the first plurality of optical barrels, in accordance with an embodiment of the present invention. Referring to Figure 34K, a first plurality of optical barrels 3424 are formed in the openings above the ILD layer 3402 such that portions of the ILD layer 3402 are left unexposed. Light bucket 3424 (at this stage) represents the first half of all possible via locations in the resulting metallization layer.

Figure 34L illustrates a plan view and corresponding cross-sectional view (along a-a' of the structure of Figure 34K following exposure and development of the drum to form selected via locations, and subsequent via opening etched into the lower ILD. The shaft is taken according to an embodiment of the invention. Referring to Figure 34L, the selected light bucket 3424 is exposed and removed to provide a selected through hole location 3426. Via location 3426 is subjected to a selective etch process (such as a selective plasma etch process) to extend the via opening into the underlying ILD layer 3402 to form a patterned ILD layer 3402'. The etch is selective for the remaining (unexposed) light bucket 3424, the first patterned hard mask layer 3416, the second patterned hard mask layer 3412, and the fourth hard mask layer 3418.

Figure 34M illustrates a plan view and corresponding cross-sectional view (taken along the b-b' axis) of the structure of Figure 34L following the removal of the remaining light barrel and subsequent formation of the fifth hard mask material, according to Embodiments of the invention. Referring to Figure 34M, the remainder of the first plurality of optical buckets 3424 are removed, for example, by selective etching or ashing. All of the exposed openings (e.g., the openings formed when the light bucket 3424 is removed along with the through hole locations 3426) are then filled with a hard mask material 3428, such as a carbon based hard mask material.

Figure 34N illustrates a plan view and corresponding cross-sectional view (taken along the c-c' axis) of the structure of Figure 34M following removal of the remaining region of the fourth hard mask layer, in accordance with the practice of the present invention example. Referring to Figure 34N, all of the remaining areas of the fourth hard mask layer 3418 are removed, for example, by selective etching or ashing. In one embodiment, the region in which the fourth hard mask layer 3418 has been removed reveals portions of the patterned ILD layer 3402', as depicted in Figure 34N.

Figure 34O illustrates a plan view and corresponding cross-sectional view (taken along the d-d' axis) of the structure of Figure 34N following the formation of the second plurality of optical barrels, in accordance with an embodiment of the present invention. Referring to Figure 34O, a second plurality of optical barrels 3430 are formed in the openings above the patterned ILD layer 3402' such that portions of the patterned ILD layer 3402' that are not left are revealed. Light bucket 3430 (at this stage) represents the second half of all possible via locations in the resulting metallization layer.

Figure 34P illustrates a plan view and corresponding cross-sectional view of the structure of Figure 34O following exposure and development of the photobucket to form selected via locations, and subsequent via openings etched into the underlying ILD (along e-e' The shaft is taken according to an embodiment of the invention. Referring to Figure 34P, the selected light bucket 3430 is exposed and removed to provide a selected through hole location 3432. The via location 3432 is subjected to a selective etch process (such as a selective plasma etch process) to extend the via opening into the underlying patterned ILD layer 3402' to form a further patterned ILD layer 3402". The etch is selective for each of the following The remaining (unexposed) light bucket 3430, the first patterned hard mask layer 3416, the second patterned hard mask layer 3412, and the hard mask material 3428.

Figure 34Q illustrates a plan view and corresponding cross-sectional view (taken along the f-f' axis) of the structure of Figure 34P following the removal of the fifth hard mask material, the trench etch, and the subsequent formation of the sacrificial layer. According to an embodiment of the invention. Referring to Figure 34Q, the hard mask material layer 3428 is removed to reveal all of the original first and second halves of the potential via location. The patterned ILD layer 3402" is then patterned to form an ILD layer 3402"" that includes via openings 3432 and 3426, along with a trench 3436 in which the via opening is not formed. The trench 3436 will ultimately be used Metal wire fabrication, as described below. Upon completion of the trench etch, all openings (including via openings 3426 and 3432 and trench 3436) are filled with sacrificial material 3434. In one such embodiment, a hard mask Material layer 3428 is a carbon-based hard mask material and is removed by a plasma ashing process. In one embodiment, sacrificial material 3434 is a flowable organic or inorganic material, such as a sacrificial light absorbing material (SLAM). The sacrificial material 3434 is formed (or planarized) to the level of the first patterned hard mask 3416 and the second patterned hard mask 3412, as depicted in Figure 34Q.

Figure 34R illustrates a plan view of the structure of Figure 34Q following deposition and patterning of the second diagonal hard mask layer, in accordance with an embodiment of the present invention. Referring to FIG. 34R, a second diagonal hard mask layer 3438 is formed over the sacrificial material 3434, the second patterned hard mask layer 3412, and the first patterned hard mask layer 3416 configuration of FIG. 34Q. In one embodiment, the second diagonal hard mask layer 3438 has a pattern of substantially or highly symmetric diagonal lines (eg, 45 degrees relative to the grating structure of the second pattern hard mask layer 3412). The alternating lines of the first patterned hard mask layer 3416 are covered. In one embodiment, the diagonal pattern of the second diagonal hard mask layer 3438 is printed with a minimum critical dimension (CD), ie, the pitch is not halved or the pitch is reduced by a quarter. . It should be understood that the individual lines can be printed to be even larger than the minimum CD as long as certain areas of adjacent columns of the first hard mask layer 3416 remain exposed. In any event, the raster pattern of the second diagonal hard mask layer 3438 of Figure 34R can have a hard mask line separated by a constant pitch and having a constant width. It should be understood that the description herein relates to forming and patterning a diagonal hard mask layer, such as second diagonal hard mask layer 3438, involving (in one embodiment) a mask formed over the overlying hard mask layer . Mask formation may involve the use of one or more layers suitable for lithography processing. When patterning one or more lithographic layers, the pattern is transferred to the hard mask layer by an etching process to provide a diagonally patterned hard mask layer. In a particular embodiment, the second diagonal hard mask layer 3438 is a carbon based hard mask layer.

Figure 34S illustrates the structure of Figure 34R following the removal of the exposed area of the first patterned hard mask layer, the removal of the second diagonal hard mask layer, and the subsequent formation of the third plurality of light barrels. Plan view and corresponding cross-sectional view (taken along the g-g' axis) in accordance with an embodiment of the present invention. Referring to Figure 34S, using the second diagonal hard mask layer 3438 as a mask, the exposed areas of the first hard mask layer 3416 are removed. In one such embodiment, the exposed regions of the first patterned hard mask layer 3416 are removed by an isotropic etch process (eg, a wet etch process or a non-anisotropic plasma etch process). That is, any partial exposure results in complete removal of a portion of the exposed portions of the first patterned hard mask layer 3416. Referring again to FIG. 34S, the second diagonal hard mask layer 3438 is removed to reveal the sacrificial material 3434 and the second patterned hard mask layer 3412. Also shown is a portion of the first hard mask layer 3416 that is protected from being etched by the equal direction of the second diagonal hard mask layer 3438. In a particular embodiment, the second diagonal hard mask layer 3438 is a carbon based hard mask material and is removed by a plasma ashing process. Referring again to Figure 34S, a third plurality of optical barrels 3440 are formed in the resulting openings above the patterned ILD layer 3402''' such that portions of the patterned ILD layer 3402'' that remain unexposed. Light bucket 3440 (at this stage) represents the first half of all possible plug locations in the resulting metallization layer. Therefore, the alternate rows of the resulting grid-like pattern of FIG. 34S or the alternate rows of the resulting grid-like pattern of FIG. 34S are downward, and the zoning of the first patterned hard mask layer 3416 alternates with the light barrel 3440. Configuration. That is, the result is a checkerboard pattern of the light barrel 3440 area and the first patterned hard mask layer 3416 area. As a result, the increase in the square root factor of two is achieved closest to the adjacent distance 3442 (shown as the distance in direction b).

Figure 34T illustrates a plan view and corresponding cross-sectional view (taken along the h-h' axis) of the structure of Figure 34S following the plug position selection and trench etch, in accordance with an embodiment of the present invention. Referring to Figure 34T, the light bucket 3440 from Figure 34S is removed from a position 3442 where no plug will be formed. In a position in which the plug is selected to form a plug, the optical tub 3440 is retained. In one embodiment, to form a location 3442 in which the plug will not be formed, lithography is used to expose the corresponding light bucket 3440. The exposed light bucket can then be removed by the developer. The patterned ILD layer 3402''' is then patterned to form an ILD layer 3402''', which includes a trench 3444 formed at location 3442. The trench 3444 will ultimately be used for metal wire fabrication as described below.

Figure 34U illustrates a plan view and corresponding cross-sectional view (taken along the i-i' axis) of the structure of Figure 34T following the removal of the remaining third light bucket and subsequent formation of the hard mask, according to the present Embodiments of the invention. Referring to Figure 34U, all remaining optical barrels 3440 are removed, for example, by an ashing process. All of the openings (including the grooves 3444) are filled with a hard mask material layer 3446 when all of the remaining light barrels 3440 are removed. In one embodiment, the hard mask material layer 3446 is a carbon based hard mask material.

Figure 34V illustrates a plan view and corresponding cross-sectional view (taken along the j-j' axis) following the structure of Figure 34V after the first patterned hard mask removal and the fourth plurality of light barrels are formed, according to the present Embodiments of the invention. Referring to FIG. 34V, the first patterned hard mask layer 3416 is removed (eg, by a selective dry or wet etch process), and the fourth plurality of light barrels 3448 are formed in the patterned ILD layer 3402"" The resulting opening in the upper portion is such that it does not have a portion of the patterned ILD layer 3402"" that remains. Light bucket 3448 (at this stage) represents the second half of all possible plug locations in the resulting metallization layer.

Figure 34W illustrates a plan view and corresponding cross-sectional view (taken along the k-k' axis) of the structure of Figure 34V following plug position selection and trench etch, in accordance with an embodiment of the present invention. Referring to Figure 34W, the light bucket 3448 from Figure 34V is removed from position 3450 where the plug will not be formed. In a position in which the plug is selected to form a plug, the optical tub 3448 is retained. In one embodiment, to form a location 3450 in which the plug will not be formed, lithography is used to expose the corresponding light bucket 3448. The exposed light bucket can then be removed by the developer. The patterned ILD layer 3402'''' is then patterned to form an ILD layer 3402'''', which includes a trench 3452 formed at location 3450. The trench 3452 will ultimately be used for metal wire fabrication as described below.

Figure 34X illustrates a plan view and corresponding first cross-sectional view of the structure of Figure 34W following the removal of the remaining fourth light bucket, the hard mask material layer and the sacrificial material, and subsequent metal filling (along the l- The l'axis is taken) and the second cross-sectional view (taken along the m-m' axis) in accordance with an embodiment of the present invention. Referring to Figure 34X, the remaining fourth light bucket 3448, hard mask material layer 3446, and sacrificial material 3434 are removed. In one such embodiment, the hard mask material layer 3446 is a carbon-based hard mask material, and both the hard mask material layer 3446 and the remaining fourth light barrel 3448 are removed to a plasma ashing. Process. In one embodiment, the sacrificial material 3434 is removed in a different etch process. Referring to the plan view of FIG. 34X, metallization 3454 is formed to be interleaved and coplanar with the second patterned hard mask layer 3412. Referring to the first cross-sectional view taken along the 1-1' axis of the plan view of FIG. 34X, the metallization 3454 is filled with trenches 3452 and 3454 formed in the patterned interlayer dielectric layer 3402"". (i.e., as corresponding to the cross-sectional view taken along the k-k' axis of Fig. 34W). Referring to the second cross-sectional view taken along the m-m' axis of the plan view of FIG. 34X, the metallization 3454 also fills the trench 3436 formed in the patterned interlayer dielectric layer 3402"" Hole openings 3432 and 3426 (i.e., as viewed in cross-section corresponding to the f-f' axis along Figure 34Q). Thus, metallization 3454 is used to form a plurality of conductive lines and conductive vias in an interlayer dielectric layer for a metallized structure, such as a BEOL metallization.

In one embodiment, the metallization 3454 is formed by metal filling and polishing back to the process. In one such embodiment, the second patterned hard mask layer 3412 is reduced in thickness during the polishing back process. In certain such embodiments, while reducing its thickness, a portion of the second patterned hard mask 3412 is retained, as depicted in Figure 34X. Thus, the metal features 3456 (which are not the conductive lines or conductive vias formed in the patterned interlayer dielectric layer 3402'"" are maintained interleaved with the second patterned hard mask layer and are located in the interlayer dielectric layer 3402. '''''Up or above (but not), as also depicted in Figure 34X. In an alternative embodiment (not shown), the second patterned hard mask 3412 is completely removed during the polishing back. Therefore, metal features 3456 (which are not conductive lines or conductive vias) are not retained in the final structure. In either case, the structure of Figure 34X can then be used as the basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figure 34X can represent the last metal interconnect layer in the integrated circuit.

It should be understood that the above-described process operations can be performed in an alternate order, not every operation needs to be performed and/or additional process operations can be performed. Referring again to Figure 34X, fabrication can be accomplished at this stage by using a metallization layer of diagonal hard mask. Manufacturing the next layer in a similar manner may require the start of a complete process. Alternatively, other ways can be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene.

In one embodiment, an interlayer dielectric (ILD) material is comprised of (or includes) a layer of dielectric or insulating material, as used throughout the specification. Examples of suitable dielectric materials include, but are not limited to, oxides of cerium (eg, cerium oxide (SiO ₂ )), oxides doped with cerium, fluorinated oxides of cerium, carbon doped with cerium Oxides, various low k dielectric materials known in the art, and combinations thereof. This interlayer dielectric material can be formed by conventional techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In one embodiment, as also throughout the specification, the metal wire or interconnect material (and via material) is comprised of one or more metals or other conductive structures. A common example is the use of copper wires and structures that may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of several metals. For example, the metal interconnects can include a barrier layer (eg, a layer comprising one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, and the like. Thus, the interconnects can be a single layer of material, or can be formed from several layers, including a conductive liner layer and a fill layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, can be used to form the interconnect. In one embodiment, the interconnect is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au. Or its alloy. Interconnect lines are also sometimes referred to (in the art) as trajectories, wiring, wires, metals, or just interconnects.

In one embodiment, as also throughout the specification, the hard mask material is comprised of a dielectric material that is different from the interlayer dielectric material. In one embodiment, different hard mask materials can be used in different regions to provide different growth and etch selectivity from the underlying dielectric and metal layers. In some embodiments, the hard mask layer comprises a layer of tantalum nitride (eg, tantalum nitride) or a layer of tantalum oxide, or both, or a combination thereof. Other suitable materials may include carbon based materials. In another embodiment, the hard mask material comprises a metal. For example, a hard mask or other overlying material may comprise a layer of titanium or other metal nitride (eg, titanium nitride). Potentially lesser amounts of other materials, such as oxygen, can be included in one or more of these layers. Alternatively, other hard mask layers known in the art can be used in accordance with certain embodiments. The hard mask layer can be formed by CVD, PVD, or by other deposition methods.

In one embodiment, as used throughout this specification, the lithography operation is performed using 193 nm immersion lithography (i193), EUV and/or EBDW lithography, and the like. A positive tone or negative tone resist can be used. In one embodiment, the lithographic mask is a three-layer mask consisting of a topographical masking portion, an anti-reflective coating (ARC), and a photoresist layer. In a particular such embodiment, the terrain shielding portion is a carbon hard mask (CHM) layer and the anti-reflective coating is a 矽ARC layer.

Optical and SEM metrology for light drums are described in accordance with the embodiments described herein. It should be understood that the use of a pre-patterned hard mask to define a lithographic pattern can make overlay measurements challenging, as the response to such patterned exposure is digital (binary) and the feature size is Quantized. Thus, the size of the underlying mask pattern becomes the smallest measurable unit of overlap, which is too large for effective process control. The manner described below not only enables an overlay measurement that is much smaller than the size of the underlying pre-patterned hard mask, but also provides a signal response that is magnified to multiple times the overlap shift, which enables extremely accurate overlap measurements.

In order to provide a structural framework for the concepts described herein, Figures 35A-35D illustrate cross-sectional views and corresponding top-down views representing various operations in a patterned processing scheme using pre-patterned hard masks. According to an embodiment of the invention.

Referring to FIG. 35A, a first pre-patterned hard mask 3502 and a second pre-patterned hard mask 3504 are formed over the lower layer 3506. All possible via or plug locations are exposed as openings 3508 in the pre-patterned hard mask 3502 and the second pre-patterned hard mask 3504.

Referring to Figure 35B, a plurality of photoresist layer portions 3510 are formed in opening 3508 of Figure 35A.

Referring to Figure 35C, the selected 3512 of the plurality of photoresist layer portions 3510 is exposed by lithographic exposure 3514. The selector 3512 of the plurality of photoresist layer portions 3510 exposed by the lithographic exposure 3514 can represent the via or plug locations that will ultimately be opened or selected.

However, in accordance with an embodiment of the present invention, lithographic exposure 3514 has an overlay error in the X direction of Figure 35C. For example, the exposed photoresist layer 3512 on the left hand side of the cross-sectional view is shifted to the right to the extent that one portion of the photoresist is not exposed by the lithographic exposure 3514. All exposed photoresist layers 3512 from the top down view are shifted to the right to the extent that one portion of the photoresist is not exposed by the lithographic exposure 3514. Again, the shift can be substantially sufficient to partially expose adjacent locations, as depicted in Figure 35C.

Referring to Figure 35D, the selected location 3512 has cleared the exposed photoresist to provide an opening 3516. Opening 3516 can be used for subsequent via or plug fabrication, depending on the particular layer of the semiconductor structure.

However, in the event that insufficient exposure of its location 3512 is fulfilled due to overlay errors, certain openings 3516 may be catastrophically not fully opened. Typically, exposure 3514 is provided with a critical number of electrons or photons to completely remove selected 3512 of complex photoresist layer portion 3510 to provide opening 3516. Some overlap errors can be tolerated, but significant overlap errors cannot be tolerated. Moreover, as described in more detail below, even in the event that all of the openings 3516 are fully opened, successful fabrication of the next layer may require at least some degree of overlap measurement based on the openings 3516.

One or more embodiments described herein relate to a manner of using a multi-pitch grating structure on a layer to extract overlapping information relative to the underlying layer. Embodiments described herein can be implemented to address pre-patterned layers and pre-patterned on top of a pre-patterned hard mask (eg, via or plug) by using an optical metrology tool The problem of measurement overlap between hard mask layers (eg, light buckets). In one embodiment, the grating is patterned at two or more pitches that are different from the underlying pre-patterned grating but parallel to one of the underlying gratings. The current shift of the layer relative to the overlap of the hard mask pattern results in an optical signal that moves with the overlap and is proportional to the overlay error. In contrast, optical overlap typically involves real features and therefore provides an analog response. Here, the movement is quantized differently than the movement in the analog action. That is, the response is digital (eg, digitized and amplified actions) because it is based on steps. In one embodiment, the "edge" pattern is measured.

Figures 36A-36E, described below, show the generation of an optical signal using a light bucket that responds to changes in overlap. It should be understood that conventional optical metrology tools measure a relatively large target (eg, 20-30 microns). For the embodiments described herein, the structure is generated from an array of lines/spaces that is below the resolution limit of the viewing tool and that utilizes the light bucket concept to produce movements that can be detected/measured using conventional overlay measurement algorithms. edge. The final pattern seen by the metrology tool shows measurable optical edges due to diffraction and scattering of light from the sub-resolution pattern that it moves with overlap. Figure 36F shows possible optical metrology indicia used in conjunction with Figures 36A-36E.

Figure 36A illustrates a top down view of an overlay scenario in which the current layer is overlaid on the underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.

Referring to FIG. 36A, the lower layer includes a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604. A plurality of photoresist layer portions 3610 and a plurality of openings 3616 (which have been exposed and developed) are positioned between the first pre-patterned hard mask 3602 and the second pre-patterned hard mask 3604 structure. The current layer is represented by the overlay image 3650A. The overlay image 3650A has a zero overlap shift and a P/4 pitch difference. The pitch of the overlay image 3650A of the current layer is shown to be 25% larger (in the upper half 3652A) and 25% smaller (in the lower half 3654A) as an example embodiment. Wide unexposed features 3656A and 3658A are included in the current layer, as depicted in Figure 36A.

Figure 36B illustrates a top down view of the overlay context, wherein the current layer has a positive overlap with respect to a quarter pitch of the underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.

Referring to FIG. 36B, the lower layer includes a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604. A plurality of photoresist layer portions 3610 and a plurality of openings 3616 (which have been exposed and developed) are positioned between the first pre-patterned hard mask 3602 and the second pre-patterned hard mask 3604 structure. The current layer is represented by the overlay image 3650B. Overlapping image 3650B has a positive (+ve) overlap shift of P/4. Wide unexposed features 3656B and 3658B are included in the current layer, with the movement of the wide unexposed features 3656B and 3658B as depicted in Figure 36B.

Figure 36C illustrates a top down view of the overlap context, wherein the current layer has a positive overlap with a half pitch of the underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.

Referring to FIG. 36C, the lower layer includes a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604. A plurality of photoresist layer portions 3610 and a plurality of openings 3616 (which have been exposed and developed) are positioned between the first pre-patterned hard mask 3602 and the second pre-patterned hard mask 3604 structure. The current layer is represented by the overlay image 3650C. The overlay image 3650C has a positive (+ve) overlap shift of P/2. Wide unexposed features 3656C and 3658C are included in the current layer, with the movement of the wide unexposed features 3656C and 3658C as depicted in Figure 36C.

Figure 36D illustrates a top down view of the overlap context, wherein the current layer has a positive overlap of any value Δ relative to the underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.

Referring to FIG. 36D, the lower layer includes a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604. A plurality of photoresist layer portions 3610 and a plurality of openings 3616 (which have been exposed and developed) are positioned between the first pre-patterned hard mask 3602 and the second pre-patterned hard mask 3604 structure. The current layer is represented by the overlay image 3650D. The overlay image 3650D has a zero overlap shift and a P+Δ pitch difference. Wide unexposed features 3656D and 3658D are included in the current layer, as depicted in Figure 36D.

Figure 36E illustrates a top-down view of the overlap context, where the current layer has a positive overlap of any value Δ relative to the underlying pre-patterned hard mask grid, wherein the measurable Δ system is changed by resist sensitivity and/or Or the feature size has been depicted and changed to be as small as desired, in accordance with an embodiment of the present invention.

Referring to FIG. 36E, the lower layer includes a first pre-patterned hard mask 3602 and a second pre-patterned hard mask 3604. A plurality of photoresist layer portions 3610 and a plurality of openings 3616 (which have been exposed and developed) are positioned between the first pre-patterned hard mask 3602 and the second pre-patterned hard mask 3604 structure. The current layer is represented by the overlay image 3650E. The superimposed image 3650E has an overlap shift of +Δ and a pitch difference of P+Δ. Wide unexposed features 3656E and 3658E are included in the current layer, with the movement of the wide unexposed features 3656E and 3658E as depicted in Figure 36E. In one embodiment, for small overlap shifts of Δ, the measurement signal is amplified to a level of P, and Δ can be as small as desired.

Figure 36F illustrates an exemplary metrology structure suitable for the manner described above in relation to Figures 36A-36E, in accordance with an embodiment of the present invention. Referring to Figure 36F, the weights and measures structure 3697 includes layer 1 features 3698 (e.g., lower layers) and layer 2 features 3699 (e.g., current layers). In one embodiment, each of the features has a width of about 20-30 microns, as depicted in Figure 36F. This structure can be included in the scribe line or on the die in the plug-in unit, for example. In one embodiment, the completed die may include a region having a beat frequency of a wide feature formed by an array of vias or plugs in the set of narrow features. The presence of two different beat frequencies in either direction may imply the use of the above techniques to measure overlap. The above manner can result in an accurate measurement of the overlap in the optical barrel for each via or plug patterned layer for which the technique is used. Embodiments can improve the accuracy of future generations of technology while using overlapping measurement tools of current technology.

One or more embodiments described herein are related to the use of critical dimension scanning electron microscope (CDSEM) techniques to measure the overlap on a pre-patterned hard mask (eg, a light bucket). Embodiments described herein can be implemented to address patterned vias on top of a pre-patterned hard mask (eg, a light bucket layer) by using a scanning electron microscope (eg, CDSEM) / or the problem of measurement overlap between the plug layer and the underlying pre-patterned hard mask layer. In one embodiment, the via or plug locations are patterned to a pitch that is slightly different than the pitch of the underlying pre-patterned hard mask. Due to the overlap mismatch, the position of the light bucket that it clears depends on the amount of overlap mismatch.

Figure 37A illustrates a top down view of an overlay scenario in which the current layer is overlaid on the underlying pre-patterned hard mask, in accordance with an embodiment of the present invention.

Referring to FIG. 37A, the lower layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704. A plurality of photoresist layer portions 3710 and a plurality of openings 3716 (which have been exposed and developed) are positioned between the first pre-patterned hard mask 3702 and the second pre-patterned hard mask 3704 structure. The current layer is represented by the overlay image 3750A. Overlapping image 3750A has an overlap shift of zero X and a zero of zero. The pitch of the overlay image 3750A of the current layer is 25% greater, relative to the underlying layer as an example embodiment, i.e., patterned at a pitch of +[Delta], where Δ = P/4. Zone 3760A emphasizes the position of the "light bucket cluster" and shifts at zero overlap (PB _0,0 ).

37B illustrates a top-down view of an overlay context in which the current layer has a positive overlap shift relative to a quarter pitch of the underlying pre-patterned hard mask grid in the X direction, in accordance with an embodiment of the present invention. .

Referring to FIG. 37B, the lower layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704. A plurality of photoresist layer portions 3710 and a plurality of openings 3716 (which have been exposed and developed) are positioned between the first pre-patterned hard mask 3702 and the second pre-patterned hard mask 3704 structure. The current layer is represented by the overlay image 3750B. Overlapping image 3750B has an overlap shift of X of P _X /4 and Y of zero. The pitch of the overlay image 3750B of the current layer is 25% greater, relative to the underlying layer as an example embodiment, i.e., patterned at a pitch + Δ, where Δ = P / 4. Zone 3760B emphasizes the locations of X=-2P _X and Y=0 for the light bucket cluster of PB _0,0 . Zone 3760B and the corresponding open/closed vertical train are moved to the left by an amount equal to twice the pitch. It should be understood that the open/closed rows will have a different contrast than the other rows due to the fact that the exposed light barrel density is different from the other rows in the zone.

Figure 37C illustrates a top down view of the overlap context, wherein the current layer has a negative overlap with respect to a quarter pitch of the underlying pre-patterned hard mask grid in the X direction, in accordance with an embodiment of the present invention.

Referring to FIG. 37C, the lower layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704. A plurality of photoresist layer portions 3710 and a plurality of openings 3716 (which have been exposed and developed) are positioned between the first pre-patterned hard mask 3702 and the second pre-patterned hard mask 3704 structure. The current layer is represented by the overlay image 3750C. Overlapping image 3750C has an overlap of X of -P _X /4 and Y of zero. The pitch of the overlay image 3750C of the current layer is 25% larger, relative to the underlying layer as an example embodiment, i.e., patterned at a pitch + Δ, where Δ = P / 4. The zone 3760C emphasizes the position of X=+2P _X and Y=0 for the light bucket cluster of PB _0,0 . Zone 3760C and the corresponding open/closed vertical train are moved to the right by an amount equal to twice the pitch.

Figure 37D illustrates a top down view of the overlap context, wherein the current layer has a positive overlap with respect to a quarter pitch of the underlying pre-patterned hard mask grid in the Y direction, in accordance with an embodiment of the present invention.

Referring to FIG. 37D, the lower layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704. A plurality of photoresist layer portions 3710 and a plurality of openings 3716 (which have been exposed and developed) are positioned between the first pre-patterned hard mask 3702 and the second pre-patterned hard mask 3704 structure. The current layer is represented by the overlay image 3750D. Overlapping image 3750D has an overlap shift of zero X and _{Y of} P _Y /4. The pitch of the overlay image 3750D of the current layer is 25% larger, relative to the underlying layer as an example embodiment, i.e., patterned at a pitch + Δ, where Δ = P / 4. The zone 3760D emphasizes the position of X=0 and Y=-2P _Y for the light bucket cluster of PB _0,0 . Zone 3760D and the corresponding open/closed horizontal column are moved downward by an amount equal to twice the pitch.

Figure 37E illustrates a top down view of the overlap context, wherein the current layer has a positive overlap with respect to a quarter pitch of the lower pre-patterned hard mask grid in the X direction and has a lower relative to the Y direction The positive overlap of the quarter pitch of the pre-patterned hard mask grid is in accordance with an embodiment of the present invention.

Referring to FIG. 37E, the lower layer includes a first pre-patterned hard mask 3702 and a second pre-patterned hard mask 3704. A plurality of photoresist layer portions 3710 and a plurality of openings 3716 (which have been exposed and developed) are positioned between the first pre-patterned hard mask 3702 and the second pre-patterned hard mask 3704 structure. The current layer is represented by the overlay image 3750E. Overlapping image 3750E has an overlap shift of X of P _X /4 and _{Y of} P _Y /4. The pitch of the overlay image 3750E of the current layer is 25% greater, relative to the underlying layer as an example embodiment, i.e., patterned at a pitch + Δ, where Δ = P / 4. Zone 3760E emphasizes the locations of X=-2P _X and Y=-2P _Y for the light bucket cluster of PB _0,0 . Zone 3760E and the corresponding open/closed horizontal column are moved downward by an amount equal to twice the pitch. In addition, zone 3760E and the corresponding open/closed vertical line are moved to the left by an amount equal to twice the pitch.

Referring again to Figures 37A-37E, it will be understood that cross-sectional analysis of a semiconductor wafer can reveal alignment marks that include vertical and horizontal arrays of vias and/or plugs in a plurality of grid vias and plugs. An application of one or more embodiments as described in the specification. Such structures can be included in the scribe line or on the dies in the plug-in unit, for example. The application of this approach can result in an accurate measurement of the overlap in the aperture barrel of each via and/or plug patterned layer that it is intended to use in conjunction with the CDSEM metrology. It should also be understood that traditional overlay techniques cannot work with this patterning.

In accordance with an embodiment of the present invention, a new structure for high resolution phase shift mask (PSM) fabrication for lithography, such as extreme ultraviolet lithography (EUV), is described. These PSM masks can be used for general (direct) lithography or complementary lithography.

Photolithography is often used in manufacturing processes to form patterns in the layers of photoresist. In the photolithography process, a photoresist layer is deposited over the underlying layer to be etched. Typically, the underlying layer is a semiconducting layer, but can be any type of hard mask or dielectric material. The photoresist layer is then selectively exposed to illumination by passing through a light mask or reticle. The photoresist is subsequently developed and those portions of the photoresist that are exposed to the illuminating light are removed, in the case of "positive" photoresist.

The light mask or reticle used to pattern the wafer is placed in a photolithographic exposure tool, commonly known as a "stepper" or "scanner." In a stepper or scanner machine, a light mask or reticle is placed between the illumination source and the wafer. A light mask or reticle is typically formed from a patterned chromaticity (absorber layer) that is placed on a quartz substrate. The illumination passes through the quartz section of the light mask or reticle substantially without attenuation, in a position where there is no chromaticity. In contrast, the illumination does not pass through the chromaticity portion of the mask. This type of mask is referred to as a binary mask because the illumination incident on the mask does not completely pass through the quartz segment or is completely blocked by the chrominance segment. After the illumination selectively passes through the mask, the pattern on the mask is transferred to the photoresist, and the image of the mask is projected into the photoresist by passing through a series of lenses.

As the features on the light mask or reticle become closer together, the diffraction effect begins (when the size of the features on the mask is equivalent to the wavelength of the source). Diffraction causes the image projected on the photoresist to become blurred, resulting in poor resolution.

One of the most advanced methods of preventing the diffraction pattern from interfering with the desired patterning of the photoresist is to cover a selected opening in the light mask or reticle with a transparent layer (known as a shifter). The shifter shifts one of the set of exposure rays into a different phase from another adjacent set, which counteracts the interference pattern from the diffraction. This method is called phase shift mask (PSM) mode. However, alternative mask manufacturing solutions that reduce defects and increase throughput during mask production are an important focus area for lithography process development.

One or more embodiments of the present invention relate to a method for fabricating a lithographic mask and the resulting lithographic mask. In order to provide a background, the need to meet the aggressive device expansion targets proposed by the semiconductor industry depends on its ability to pattern lithographic masks of smaller features with high fidelity. However, the way to pattern smaller and smaller features creates a huge challenge for mask manufacturing. In this regard, the lithographic masks that are widely used today rely on the concept of phase shift mask (PSM) technology for patterning features. However, reducing defects while producing smaller and smaller patterns remains one of the biggest obstacles in mask manufacturing. The use of phase shift masks can have several drawbacks. First, the design of the phase shift mask is a rather complicated procedure that requires a lot of resources. Second, due to the nature of the phase shift mask, it is difficult to check if no defects are present in the phase shift mask. These defects in the phase shifting mask are derived from the current integration scheme utilized to create the mask itself. Conventional phase shifting masks pattern a thick light absorbing material in a cumbersome and somewhat flawed manner and then transfer the pattern to its secondary layer that assists in phase shifting. Complicating things, the absorber layer is subjected to plasma etching twice, and therefore, the adverse effects of plasma etching (such as load effects, reactive ion etching delay, charging, and regenerative effects) result in mask production. defect.

Innovative and novel integration techniques for fabricating defect-free lithographic masks are still a high priority for device expansion. Therefore, in order to take advantage of all the advantages of the phase shift masking technique, a novel integration scheme utilizing the following: (i) patterning the shifter layer with high fidelity and (ii) patterning the absorber only once and During the final phase of manufacturing. In addition, this manufacturing solution can provide other advantages such as flexibility in material selection, reduced substrate damage during manufacturing, and increased throughput during mask manufacture.

Figure 38 illustrates a cross-sectional view of a lithographic mask structure 3801 in accordance with an embodiment of the present invention. The lithography mask 3801 includes a die intermediate region 3810, a frame region 3820, and a die frame interface region 3830. The die frame interface region 3830 includes adjacent regions of the die middle region 3810 and the frame region 3820. The mid-die region 3810 includes a patterned shifter layer 3806 disposed directly on the substrate 3800, wherein the patterned shifter layer has features including sidewalls. The frame region 3820 surrounds the mid-grain region 3810 and includes a patterned absorber layer 3802 disposed directly on the substrate 3800.

The die frame interface region 3830 (disposed on the substrate 3800) includes a two-layer stack 3840. The two-layer stack 3840 includes an upper layer 3804 disposed on the lower patterned shifter layer 3806. The upper layer 3804 of the double layer stack 3840 is comprised of the same material as the patterned absorber layer 3802 of the frame area 3820.

In one embodiment, the uppermost surface 3808 of the features of the patterned shifter layer 3806 has a height that is different from the uppermost surface 3812 of the features of the die box interface region and that is different from the uppermost surface 3814 of the features in the frame region. . Moreover, in one embodiment, the height of the uppermost surface 3812 of the features of the die-frame interface region is different from the height of the uppermost surface 3814 of the features of the frame region. The typical thickness of the patterned shifter layer 3806 ranges from 40 to 100 nm, while the typical thickness of the absorber layer ranges from 30 to 100 nm. In one embodiment, the thickness of the absorber layer 3802 in the frame region 3820 is 50 nm, and the thickness of the absorber layer 3804 disposed on the shifter layer 3806 in the die frame interface region 3830 is 120 nm. The thickness of the absorbent in the medium is 70 nm. In one embodiment, the substrate 3800 is quartz, and the patterned shifter layer includes materials such as, but not limited to, molybdenum molybdenum, molybdenum oxynitride, molybdenum nitride, hafnium oxynitride, or tantalum nitride. And the absorbent material is chromium.

Complementary electron beam lithography is described in accordance with an embodiment of the present invention. One or more embodiments described herein relate to lithographic methods and tools that relate to or are suitable for complementary electron beam lithography (CEBL), including semiconductor processing considerations when implementing such methods and tools.

Complementary lithography utilizes the capabilities of two lithography techniques (cooperating) to reduce the cost of critical layers in patterned logic devices at 20 nm half pitch and below, in mass production (HVM). The most cost-effective way to implement complementary lithography is to combine optical lithography with electron beam lithography (EBL). The procedure for transferring an integrated circuit (IC) design to a wafer is detailed as follows: optical lithography for printing unidirectional lines at a predefined pitch (strictly unidirectional or predominantly unidirectional); pitch segmentation techniques, To increase the line density; and EBL, to "cut" the line. EBL is also used to pattern other key layers, especially contacts and vias. Optical lithography can be used alone to pattern other layers. When used to supplement optical lithography, the EBL is referred to as CEBL, or a complementary EBL. CEBL is for cutting lines and holes. By not attempting to pattern all layers, CEBL plays a complementary but critical role to meet industrial patterning needs at advanced (smaller) technology nodes (eg, 10 nm or less, such as 7nm or 5nm technology nodes). on. CEBL also extends the use of current optical lithography technologies, tools and facilities.

The embodiments disclosed herein can be used to fabricate a variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, a semiconductor memory can be fabricated. In addition, integrated circuits or other microelectronic devices can be used with a variety of electronic devices known in the art. For example, in computer systems (eg, desktop, laptop, server), mobile phones, personal electronic devices, and the like. The integrated circuit can be coupled to a bus or other component in the system. For example, a processor can be coupled to a memory, a group of chips, and the like by one or more bus bars. Each processor, memory, chipset can potentially be fabricated in the manner disclosed herein.

As noted above, electron beam (ebeam) lithography can be implemented to complement standard lithography techniques to achieve desired scaling of the features of integrated circuit fabrication. An electron beam lithography tool can be used to perform electron beam lithography. In an exemplary embodiment, FIG. 39 is a schematic cross-sectional view of an electron beam of an electron beam lithography apparatus.

Referring to Figure 39, electron beam row 3900 includes an electron source 3902 for providing a beam 3904 of electrons. The electron beam 3904 passes through the aperture 3906, and then the optical device 3908 is illuminated by the high aspect ratio. Output beam 3910 then passes through slit 3912 and can be controlled by thin lens 3914 (eg, which can be magnetic). Finally, beam 3904 passes through a shaped aperture 3916 (which may be a one-dimensional (1-D) shaped aperture) and then passed through a eliminator aperture array (BAA) 3918. The BAA 3918 includes a plurality of physical apertures therein, such as openings formed in a sheet of tantalum. It is possible that only a portion of the BAA 3918 is exposed to the electron beam at a given time. Alternatively, or in combination, only a portion 3920 of the electron beam 3904 passing through the BAA 3918 is allowed to pass through the final aperture 3922 (eg, the beam portion 3921 is shown as blocked) and (possibly) the level feedback deflector 3924.

Referring again to Figure 39, the resulting electron beam 3926 ultimately impacts a point 3928 on the surface of the wafer 3930, such as a germanium wafer for IC fabrication. Specifically, the resulting electron beam may impinge on the photoresist layer on the wafer, but the embodiment is not limited thereto. Stage scan 3932 moves wafer 3930 relative to beam 3926, along the direction of arrow 3934 shown in FIG. It should be understood that the electron beam tool may completely include a plurality of rows 3900 of the type shown in FIG. At the same time, the electron beam tool can have an associated basic computer, and each line can further have a corresponding line computer.

In one embodiment, all or part of the opening or aperture of the BAA may be switched on or off (eg, by beam deflection) when referring to an opening or aperture in the eliminator aperture array (BAA) The wafer/die moves underneath the wafer in the direction of travel or scanning. In one embodiment, the BAA can be independently controlled, whether each opening passes the electron beam to the sample or deflects the electron beam into, for example, a Faraday cup or a mask aperture. An electron beam or device comprising the BAA can be built to deflect the entire beam cover to only a portion of the BAA, and then individual openings in the BAA are electrically configured to pass ("on") or not (by) the electron beam ( "turn off"). For example, undeflected electrons pass to the wafer and expose the resist layer while the deflected electrons are trapped in the Faraday cup or the masking aperture. It should be understood that reference to "opening" or "opening height" refers to the point size impacted on the receiving wafer rather than the physical opening in the BAA, since the physical opening is substantially larger (eg, micron grade) ultimately from the BAA. The resulting point size (eg, nanometer rating). Therefore, when the pitch described in the text as BAA or the opening in the BAA is said to be "corresponding to" the pitch of the metal line, this description actually refers to the pitch between the impact points as produced from the BAA. The relationship between the pitch of the line being cut. As exemplified below, the points produced from BAA 4310 have the same pitch as the pitch of line 4300 (when two rows of BAA openings are considered together). At the same time, the points produced from only one row of the interleaved array of BAA 4310 have a pitch that is twice the pitch of line 4300.

In one embodiment, an interleaved beam aperture array is implemented to address the flux of the electron beam machine while also enabling a minimum wiring pitch. If there is no interleaving, the edge layout error (EPE) considerations indicate that the minimum pitch of twice the width of the wiring cannot be cut because it is impossible to stack vertically in a single stack. For example, FIG. 40 illustrates the aperture 4000 of the BAA relative to the line 4002 to be cut or having a through hole in the target position, when the line is scanned below the aperture 4000 in the direction of the arrow 4004. Referring to Figure 40, for a given line 4002 to be cut or a through hole to be placed, the EPE 4006 of the cutter opening (aperture) results in a rectangular opening in the BAA grid of the pitch of the line.

Figure 41 illustrates two non-interlaced apertures 4100 and 4102 individually with respect to the BAA of the two wires 4104 and 4106 to be cut or having through holes in the target position, when the wire is in the direction of arrow 4108 When scanned below the apertures 4100 and 4102. Referring to Figure 41, when the rectangular opening 4000 of Figure 40 is placed in a vertical single row having other such rectangular openings (e.g., now 4100 and 4102), the allowable pitch of the line to be cut is limited by: The 2x EPE 4110 plus the distance requirement 4112 between the BAA openings 4100 and 4102 plus the width of a wiring 4104 or 4106. The resulting interval 4114 is shown by the arrow on the right side of Figure 41. This line array may severely limit the pitch of the wiring to be substantially 3-4 times the width of the wiring, which may be unacceptable. Another alternative that may be unacceptable would be to cut a tighter pitch wiring with two (or more) paths with slightly offset routing locations; this approach can severely limit the flux of the electron beam machine.

With respect to Figure 41, Figure 42 illustrates two rows 4202 and 4204 staggered apertures 4206 of the BAA 4200 relative to the plurality of lines 4208 to be cut or having through holes in the target position, when the line 4208 is scanned along the direction 4210. When the aperture 4206 is below, the scanning direction is indicated by an arrow, in accordance with an embodiment of the present invention. Referring to Figure 41, the interleaved BAA 4200 includes two linear arrays 4202 and 4204 that are spatially staggered as shown. The two interleaved arrays 4202 and 4204 cut (or place through holes) alternating lines 4208. Line 4208 (in one embodiment) is placed on a tight grid with twice the width of the wiring. As used throughout the present disclosure, the term "interlaced array" may refer to the interlacing of openings 4206 that are staggered in one direction (eg, vertical) and either have no overlap or have some overlap, when When scanning in an orthogonal direction (for example, a horizontal direction) while viewing. In the latter case, effective overlap provides tolerance for misalignment.

It should be understood that although the interleaved array is shown as two vertical rows in the text for simplicity, the opening or aperture of a single "row" need not be linear in the vertical direction. For example, in an embodiment, the interleaving is obtained as long as the first array collectively has a pitch in the vertical direction and the second array interlaced with the first array in the scanning direction has a pitch in the vertical direction. Array. Thus, a reference or description of a vertical line in the text may actually consist of one or more lines unless specified as a single line of openings or apertures. In one embodiment, where a "row" opening is not a single row opening, any offset within the "row" can be compensated for by a strobe timing. In one embodiment, the key point is that the openings or apertures of the interleaved array of BAAs are located at a particular pitch in the first direction, but are offset in the second direction to allow them to place cuts or through holes without any gaps. Between the cut or the through hole in the first direction.

Thus, one or more embodiments are directed to an interlaced beam aperture array in which the openings are staggered to allow for EPE cut and/or via requirements, unlike an inline arrangement that does not address EPE technology requirements. Conversely, if there is no interleaving, the problem of edge layout error (EPE) means that the minimum pitch twice the width of the wiring cannot be cut because it is impossible to stack vertically in a single stack. Alternatively, in one embodiment, the use of interleaved BAAs enables more than 4000 times faster than the individual electron beam writes to each of the wiring locations. Furthermore, the interleaved array allows the wiring pitch to be twice the width of the wiring. In a particular embodiment, the array has 4096 staggered openings above two rows such that EPE for each of the cutting and via locations can be performed. It should be understood that an interlaced array (as contemplated herein) may include two or more rows of staggered openings.

In one embodiment, the use of an interleaved array preserves space to include metal around the aperture of the BAA containing one or two electrodes for transferring or directing electron beams to the wafer or to the Faraday cup or to mask the aperture. That is, each opening can be controlled by the separation of the electrodes to pass or deflect the electron beam. In one embodiment, the BAA has 4096 openings and the electron beam apparatus covers a complete array of 4096 openings, each of which is electrically controlled. The flux is increased by sweeping the wafer under the opening (as indicated by the bold black arrow).

In a particular embodiment, the interleaved BAA has two columns of staggered BAA openings. This array allows tight pitch routing where the wiring pitch can be twice the width of the wiring. Furthermore, all wiring can be cut in a single pass (or through holes can be formed in a single pass), thereby enabling flux on the electron beam machine. Figure 21A illustrates two rows of staggered apertures (left) of a BAA with respect to a complex line (right) of a through hole (filled into a square box) patterned with a cut (break in the horizontal line) or a staggered BAA, in the scanning direction Arrows are shown in accordance with embodiments of the present invention.

Referring to Figure 43A, the lines resulting from a single interlaced array can be as previously described, wherein the lines are single pitched with their cuts and vias patterned. In particular, Figure 43A depicts a plurality of lines 4300 or an open line location 4302 in which wireless is present. Vias 4304 and cuts 4306 can be formed along line 4300. Line 4300 is shown relative to a BAA 4310 having a scan direction 4312. Thus, Figure 43A can be viewed as a typical pattern produced by a single interlaced array. The dashed line shows where the cut occurred in the patterned line (including the total cut used to remove the full line or line portion). The via location 4304 is a patterned via that falls on top of the wiring 4300.

It should be understood that the electron beam rows including the interlaced beam aperture array (interlaced BAA) as described above may also include other features than those described in conjunction with FIG. For example, in one embodiment, the sample level can be rotated 90 degrees to accommodate alternating metallization layers that can be printed orthogonally to each other (eg, rotated between the X and Y scan directions). In another embodiment, the electron beam tool can rotate the wafer 90 degrees before loading the wafer onto the stage.

Figure 43B illustrates a cross-sectional view of a stack 4350 of metallization layers 4352 in an integrated circuit, in accordance with an embodiment of the present invention, in accordance with the metal line layout of the type illustrated in Figure 43A. Referring to Figure 43B, in an exemplary embodiment, the metal cross-section of interconnect stack 4350 is taken from a single BAA array of eight matching metal layers 4354, 4356, 4358, 4360, 4362, 4364, 4366, and 4368. It should be understood that the thicker/wider wires 4370 and 4372 above will not be formed as a single BAA. Via location 4374 is depicted as connecting the eight matching metal layers 4354, 4356, 4358, 4360, 4362, 4364, 4366, and 4368 below.

In summary, in one embodiment, the complementary lithography as described herein involves the fabrication of a grid-like layout by conventional or state-of-the-art lithography, such as 193 nm immersion lithography (193i). Pitch segmentation can be implemented to increase the density of the lines in the grid layout by a factor of n. The grid layout formation using 193i lithography plus pitch division by a factor of n can be specified as 193i+P/n pitch division. The patterning of the pitch-divided grid layout can then be patterned using electron beam direct writing (EBDW) "cutting". In one such embodiment, the 193 nm immersion calibration can be extended to many generations using cost effective pitch segmentation. In one embodiment, the complementary EBL is used to interrupt grating continuity and pattern the vias. In another embodiment, a complementary EUV is used to interrupt grating continuity and pattern the vias.

Figure 44 illustrates a computing device 4400 in accordance with an embodiment of the present invention. Computing device 4400 includes a circuit board 4402. Circuit board 4402 can include a number of components including, but not limited to, processor 4404 and at least one communication chip 4406. Processor 4404 is physically and electrically coupled to circuit board 4402. In some embodiments, at least one communication chip 4406 is also physically and electrically coupled to the circuit board 4402. In a further embodiment, communication chip 4406 is part of processor 4404.

Depending on its application, computing device 4400 can include other components that may or may not be physically and electrically coupled to circuit board 4402. These other components include, but are not limited to, volatile memory (eg, DRAM), non-volatile memory (eg, ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chips Group, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, Cameras, and mass storage devices (such as hard drives, compact discs (CDs), digital compact discs (DVDs), etc.).

The communication chip 4406 enables wireless communication for the transfer of data to and from the computing device 4400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, and the like, which may convey data via the use of modulated electromagnetic radiation transmitted through a non-solid medium. The term does not imply that its associated device does not contain any wiring, although in some embodiments it may not. The communication chip 4406 can implement any of several wireless standards or protocols including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G, and above. Computing device 4400 can include a plurality of communication chips 4406. For example, the first communication chip 4406 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth; and the second communication chip 4406 can be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE. , Ev-DO and others.

The processor 4404 of the computing device 4400 includes integrated circuit dies that are packaged within the processor 4404. In some embodiments of embodiments of the invention, the integrated circuit die of the processor includes one or more devices, such as a MOS-FET transistor constructed in accordance with an embodiment of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from a register and/or memory to convert the electronic data into storage that can be stored in a register and/or memory. Other electronic materials.

The communication chip 4406 also includes integrated circuit dies that are packaged in the communication chip 4406. In accordance with another embodiment of the present invention, an integrated circuit die of a communication chip is constructed in accordance with an embodiment of the present invention.

In further embodiments, another component included within computing device 4400 can include integrated circuit dies constructed in accordance with embodiments of embodiments of the present invention.

In various embodiments, the computing device 4400 can be a laptop, a small notebook, a notebook, a thin and light notebook, a smart phone, an input pad, a personal digital assistant (PDA), an ultra-light mobile PC, a mobile phone. , desktop computers, servers, printers, scanners, monitors, set-top boxes, entertainment control units, digital cameras, portable music players, or digital video recorders. In further embodiments, computing device 4400 can be any other electronic device that processes data.

Figure 45 illustrates an inserter 4500 that includes one or more embodiments of the present invention. The interposer 4500 is an intermediate substrate for bridging the first substrate 4502 to the second substrate 4504. The first substrate 4502 can be, for example, an integrated circuit die. The second substrate 4504 can be, for example, a memory module, a computer motherboard, or other integrated circuit die. Typically, the purpose of the interposer 4500 is to extend the connection to a wider pitch or to reroute the connection to a different connection. For example, the interposer 4500 can couple the integrated circuit die to a ball grid array (BGA) 506 that can be subsequently coupled to the second substrate 4504. In some embodiments, the first and second substrates 4502/4504 are mounted to the opposite side of the interposer 4500. In other embodiments, the first and second substrates 4502/4504 are mounted to the same side of the interposer 4500. And in further embodiments, three or more substrates are interconnected via interposer 4500.

The inserter 4500 can be formed from epoxy, fiberglass reinforced epoxy, ceramic materials, or polymeric materials such as polyimine. In further embodiments, the interposer can be formed as an alternative hard or resilient material that can include the same materials described above for the semiconductor substrate, such as tantalum, niobium, and other III-V or Group IV materials.

The interposer can include a metal interconnect 4508 and a via 4510 including, but not limited to, a through via (TSV) 4512. The interposer 4500 can further include an embedded device 4514, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, inductors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices can also be formed on the interposer 4500. In accordance with embodiments of the present invention, the apparatus or process disclosed herein can be used in the manufacture of the interposer 4500.

Thus, embodiments of the invention include sub-10 nm pitch patterning and self-polymerization devices.

Example Embodiment 1 An integrated circuit structure includes a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a grating pattern interrupted by a portion of the body portion. a trench isolation layer between the plurality of semiconductor bodies and adjacent to the lower portion of the plurality of semiconductor bodies, but not adjacent to the upper portion of the plurality of semiconductor bodies, wherein the trench isolation layer is located in the portion Above the body part. One or more gate electrode stacks are attached to the top surface of the upper portions of the plurality of semiconductor bodies and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies, and the trench isolation layer Part of it. a back end of line (BEOL) metallization layer over the one or more gate electrode stacks, the BEOL metallization layer comprising a plurality of alternating first and second conductive line types along the same direction, wherein the first conductive The total composition of the line type is different from the total composition of the second conductive line type.

Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein the lines of the first conductive line type are isolated by a pitch, and wherein the line of the second conductive line type is isolated by the pitch.

Example Embodiment 3: The integrated circuit structure of the example embodiment 1 or 2, wherein the plurality of alternating first and second conductive line types are located in an interlayer dielectric (ILD) layer.

EMBODIMENT 4: The integrated circuit structure of the example embodiment 1 or 2, wherein the plurality of alternating first and second conductive line types are separated by an air gap.

EMBODIMENT 5: The integrated circuit structure of the example embodiment 1, 2, 3 or 4, wherein the total composition of the first conductive line type substantially comprises copper, and wherein the total composition of the second conductive line type is substantially The material includes a material selected from the group consisting of Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au, and alloys thereof.

Example Embodiment 6: The integrated circuit structure of the example embodiment 1, 2, 3, 4 or 5, wherein the plurality of alternating first and second conductive line types each comprise a bottom along the line and The barrier layer of the side wall.

EMBODIMENT 7: The integrated circuit structure of the example embodiment 1, 2, 3, 4 or 5, wherein the plurality of alternating first and second conductive line types each comprise a bottom along the line but A barrier layer that is not along the sidewall of the line.

Example Embodiment 8: The integrated circuit structure of the example embodiment 1, 2, 3, 4, 5, 6 or 7, wherein the plurality of alternate first and second conductive line types of the one or more of the lines Connected to the lower via, which is connected to the underlying metallization layer, between the one or more gate electrode stacks and the BEOL metallization layer, and the plurality of alternating One or more of the lines of the first and second conductive line types are interrupted by a dielectric plug.

Example Embodiment 9: The integrated circuit structure of the example embodiment 1, 2, 3, 4, 5, 6, 7, or 8, wherein the grating pattern has a constant pitch.

Example Embodiment 10: The integrated circuit structure of the example embodiment 1, 2, 3, 4, 5, 6, 7, 8, or 9 further includes a source on both sides of the one or more gate electrode stacks Or a drain region, wherein the source or drain regions are adjacent to the upper portions of the plurality of semiconductor bodies and include semiconductor materials different from the semiconductor material of the semiconductor bodies.

Example Embodiment 11: The integrated circuit structure of the example embodiment 1, 2, 3, 4, 5, 6, 7, 8, or 9 further includes a source on both sides of the one or more gate electrode stacks Or a drain region, wherein the source or drain regions are located in the upper portions of the plurality of semiconductor bodies.

Example Embodiment 12: The integrated circuit structure of the example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11, wherein each of the one or more gate electrode stacks comprises High-k gate dielectric layer and metal gate electrode.

Example Embodiment 13: The integrated circuit structure of the example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12, wherein the first conductive line types have an upper surface, A metal composition having a metal composition different from the surface of the second conductive line type.

Example Embodiment 14: An integrated circuit structure includes a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a grating pattern interrupted by a portion of the body portion. a trench isolation layer between the plurality of semiconductor bodies and adjacent to the lower portion of the plurality of semiconductor bodies, but not adjacent to the upper portion of the plurality of semiconductor bodies, wherein the trench isolation layer is located in the portion Above the body part. One or more gate electrode stacks are attached to the top surface of the upper portions of the plurality of semiconductor bodies and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies, and the trench isolation layer Part of it. a back end of line (BEOL) metallization layer over the one or more gate electrode stacks, the BEOL metallization layer comprising a plurality of alternating first and second conductive line types along the same direction, wherein the plurality of alternating lines alternate The lines of the first and second conductive line types each include a barrier layer along the bottom of the line but not along the side walls of the line.

Example Embodiment 15: The integrated circuit structure of Example Embodiment 14, wherein the lines of the first conductive line type are isolated by a pitch, and wherein the line of the second conductive line type is isolated by the pitch.

EMBODIMENT 16: The integrated circuit structure of the example embodiment 14 or 15, wherein the plurality of alternating first and second conductive line types are in an interlayer dielectric (ILD) layer.

EMBODIMENT 17: The integrated circuit structure of the example embodiment 14 or 15, wherein the plurality of alternating first and second conductive line types are separated by an air gap.

EMBODIMENT 18: The integrated circuit structure of the example embodiment 14, 15, 16 or 17, wherein the total composition of the first conductive line type is the same as the total composition of the second conductive line type.

EMBODIMENT 19: The integrated circuit structure of Example 14, 14, 16, or 17, wherein the total composition of the first conductive line type substantially comprises copper, and wherein the total composition of the second conductive line type substantially comprises A material selected from the group consisting of Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au, and alloys thereof.

EMBODIMENT 20: The integrated circuit structure of the example embodiment 14, 15, 16, 17, 18 or 19, wherein one or more of the plurality of alternating first and second conductive line types are Connected to a lower via that is connected to a lower metallization layer between the one or more gate electrode stacks and the BEOL metallization layer, and wherein the plurality of alternating layers One or more of the lines of a second and second conductive line type are interrupted by a dielectric plug.

Example Embodiment 21: The integrated circuit structure of the example embodiment 14, 15, 16, 17, 18, 19 or 20, wherein the grating pattern has a constant pitch.

Example Embodiment 22: The integrated circuit structure of the example embodiment 14, 15, 16, 17, 18, 19, 20 or 21, further comprising a source or a drain on both sides of the one or more gate electrode stacks a polar region, wherein the source or drain regions are adjacent to the upper portions of the plurality of semiconductor bodies and include semiconductor materials different from the semiconductor material of the semiconductor bodies.

Example Embodiment 23: The integrated circuit structure of the example embodiment 14, 15, 16, 17, 18, 19, 20 or 21, further comprising a source or a drain on both sides of the one or more gate electrode stacks a polar region, wherein the source or drain regions are located in the upper portions of the plurality of semiconductor bodies.

Example Embodiment 24: The integrated circuit structure of the example embodiment 14, 15, 16, 17, 18, 19, 20, 21, 22 or 23, wherein each of the one or more gate electrode stacks comprises a high k Gate dielectric layer and metal gate electrode.

Example Embodiment 25: An integrated circuit structure includes a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a first grating pattern interrupted by a portion of the body portion. a trench isolation layer between the plurality of semiconductor bodies and adjacent to the lower portion of the plurality of semiconductor bodies, but not adjacent to the upper portion of the plurality of semiconductor bodies, wherein the trench isolation layer is located in the portion Above the body part. One or more gate electrode stacks are attached to the top surface of the upper portions of the plurality of semiconductor bodies and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies, and the trench isolation layer Part of it. A first back end of line (BEOL) metallization layer is over the one or more gate electrode stacks, the first BEOL metallization layer comprising a second grating of alternating metal lines and dielectric lines in a first direction. A second BEOL metallization layer is over the first BEOL metallization layer, the second BEOL metallization layer comprising a third grating of alternating metal lines and dielectric lines in a second direction. The second direction is orthogonal to the first direction. Each metal line of the third grating of the second BEOL metallization layer is on a dielectric layer, the dielectric layer including a first dielectric material and a first dielectric material corresponding to the alternating metal line and the dielectric layer of the first BEOL metallization layer Two alternating regions of dielectric material. Each of the dielectric lines of the third grating of the second BEOL metallization layer includes a continuous region of a third dielectric material that is different from the alternating regions of the first dielectric material and the second dielectric material.

EMBODIMENT 26: The integrated circuit structure of example 25, wherein the metal line of the second BEOL metallization layer is electrically coupled to the metal line of the first BEOL metallization layer by a via hole, the via hole There is a center of the metal line of the first BEOL metallization layer and a center directly aligned with the center of the metal line of the second BEOL metallization layer.

EMBODIMENT 27: The integrated circuit structure of the example embodiment 25 or 26, wherein the metal line of the second BEOL metallization layer is interrupted by a plug having a first BEOL metallization layer The center of the dielectric line is directly aligned with the center.

EMBODIMENT 28: The integrated circuit structure of example embodiment 25, 26 or 27, wherein the first dielectric material, the second dielectric material, and the third dielectric material are all non-identical materials.

EMBODIMENT 29: The integrated circuit structure of example embodiment 25, 26 or 27, wherein only the first dielectric material, the second dielectric material, and the third dielectric material are the same material.

EMBODIMENT 30: The integrated circuit structure of the example embodiment 25, 26, 27, 28 or 29, wherein the alternating different regions of the first dielectric material and the second dielectric material are separated by a seam, and wherein The continuum of the third dielectric material is separated from the alternating regions of the first dielectric material and the second dielectric material by a seam.

EMBODIMENT 31: The integrated circuit structure of the example embodiment 25, 26, 27 or 30, wherein the first dielectric material, the second dielectric material, and the third dielectric material are all the same material.

Example Embodiment 32: The integrated circuit structure of the example embodiment 25, 26, 27, 28, 29, 30 or 31, wherein the first grating pattern has a constant pitch.

Example Embodiment 33: The integrated circuit structure of the example embodiment 25, 26, 27, 28, 29, 30, 31 or 32 further comprising a source or a drain on both sides of the one or more gate electrode stacks a polar region, wherein the source or drain regions are adjacent to the upper portions of the plurality of semiconductor bodies and include semiconductor materials different from the semiconductor material of the semiconductor bodies.

Example Embodiment 34: The integrated circuit structure of the example embodiment 25, 26, 27, 28, 29, 30, 31 or 32 further comprising a source or a drain on both sides of the one or more gate electrode stacks a polar region, wherein the source or drain regions are located in the upper portions of the plurality of semiconductor bodies.

Example Embodiment 35: The integrated circuit structure of the example embodiment 25, 26, 27, 28, 29, 30, 31, 32, 33 or 34, wherein each of the one or more gate electrode stacks comprises a high k Gate dielectric layer and metal gate electrode.

Example Embodiment 36: The integrated circuit structure of the example embodiment 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 or 35, wherein the etch stop layer or the additional dielectric layer separates the first BEOL metal And a second BEOL metallization layer.

Example Embodiment 37: A method of fabricating an integrated circuit structure includes forming a plurality of backbone features over a substrate, forming a first set of spacers along sidewalls of each of the plurality of backbone features, the first set of spacers having different Forming a first material composition of materials of the plurality of backbone features, forming a second set of spacers along sidewalls of each of the first set of spacers, the second set of spacers having a different from the first material Forming a second material composition of the material different from the plurality of backbone features, forming a third set of spacers along sidewalls of each of the second set of spacers, the third set of spacers having a different a third material composition of the first material composition, different from the second material composition, and different from the plurality of backbone features, forming a fourth group along sidewalls of each of the third set of spacers a spacer, the fourth set of spacers having the second material composition forming a fifth set of spacers laterally adjacent to sidewalls of each of the fourth set of spacers, the fifth set of spacers having the spacer First Material composition, after forming the fifth set of spacers, removing the plurality of backbone features, after removing the plurality of backbone features, along a sidewall of each of the first set of spacers and along the plurality of The sidewalls of each of the five sets of spacers form a sixth set of spacers, the sixth set of spacers having the second material composition, forming a final feature between each of the adjacent pairs of spacers of the sixth set of spacers Flattening the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers, and the sixth group The spacers, and the final features, form a target base layer, and the target base layer is used to form a metallization layer of the semiconductor structure.

</ RTI> The method of example 37, wherein forming the plurality of backbone features comprises using standard lithography operations.

The method of embodiment 37 or 38, wherein forming the plurality of backbone features comprises forming a plurality of features comprising a material selected from the group consisting of tantalum nitride, tantalum oxide, and tantalum carbide.

The method of example 37, 38 or 39, wherein forming the first set of spacers comprises using an atomic layer deposition (ALD) process to deposit the first groups conformal to the plurality of backbone features A material of the spacer anisotropically etching the material of the first set of spacers to form the first set of spacers along the sidewalls of each of the plurality of backbone features.

The method of example 37, 38 or 39, wherein forming the first set of spacers comprises selectively growing the first set of intervals along the sidewalls of each of the plurality of backbone features Material of matter.

The method of example 37, 38, 39, 40 or 41, wherein each final feature has a greater than the first set of spacers, the second set of spacers, and the third set of spacers The side widths of the side widths of the fourth set of spacers, the fifth set of spacers, and the spacers of the sixth set of spacers.

</ RTI> The method of example 37, 38, 39, 40, 41 or 42 wherein each of the final features is grown by a material formed along adjacent pairs of spacers of the sixth set of spacers Merged to form.

The method of example 37, 38, 39, 40, 41, 42 or 43 wherein each final feature comprises the third material composition.

The method of example 37, 38, 39, 40, 41, 42, 43 or 44, wherein using the target base layer to form the metallization layer of the semiconductor structure comprises removing the first material composition All of the portions are formed to form a first plurality of trenches, and a first plurality of conductive lines are formed in the first plurality of trenches.

The method of example 45, wherein the using the target base layer to form the metallization layer of the semiconductor structure further comprises removing all portions of the third material composition to form a second plurality of trenches, and forming The second plurality of conductive lines are in the second plurality of trenches.

The method of example 46, wherein the first plurality of conductive lines are the same composition as the second plurality of conductive lines.

The method of example 46, wherein the first plurality of conductive lines are different from the second plurality of conductive lines.

Exemplary Embodiment 49: The method of Exemplary Embodiment 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47 or 48, further comprising forming an additional 20-200 sets of spacers in forming the fifth The group spacer is between the sixth group of spacers and before the plurality of backbone features are removed.

Example Embodiment 50: A target structure for fabricating an integrated circuit structure includes a first set of spacers over a hard mask layer over a substrate, the first set of spacers having a first material composition. A second set of spacers is along an outer sidewall of each of the first set of spacers, the second set of spacers having a second material composition different from the first material composition. a third set of spacers is along a sidewall of each of the second set of spacers, the third set of spacers having a third material composition different from the first material composition and different from the second material composition . A fourth set of spacers is along the sidewalls of each of the third set of spacers, the fourth set of spacers having the second material composition. A fifth set of spacers is laterally adjacent to sidewalls of each of the fourth set of spacers, the fifth set of spacers having the first material composition. a sixth set of spacers along an inner sidewall of each of the first set of spacers and along a sidewall of each of the fifth set of spacers, the sixth set of spacers having the second material composition . The final feature is in each opening between adjacent pairs of spacers of the sixth set of spacers.

Example 51: The target structure of example embodiment 50, wherein the first group of spacers, the second group of spacers, the third group of spacers, the fourth group of spacers, and the fifth The set of spacers, the sixth set of spacers, and the final features are substantially coplanar with each other.

Example embodiment 52: The target structure of example embodiment 50 or 51, wherein each final feature has a greater than the first set of spacers, the second set of spacers, the third set of spacers, and the fourth The side width of the side width of each of the spacers, the fifth set of spacers, and the spacers of the sixth set of spacers.

Exemplary Embodiment 53: The target structure of Example Embodiment 52, wherein the side width of each of the final features is in the range of 6-12 nm.

Example Embodiment 54: The object structure of the example embodiment 50, 51, 52 or 53 wherein each final feature has a seam that is approximately concentrated within the last feature.

Exemplary Embodiment 55: The target structure of Exemplary Embodiment 50, 51, 52, 53 or 54 wherein each final feature comprises the third material composition.

100‧‧‧ starting structure

102‧‧‧Interlayer dielectric (ILD) layer

104‧‧‧ hard mask material layer

106‧‧‧patterned mask

108‧‧‧ spacers

110‧‧‧ patterned hard mask

402‧‧‧Big semiconductor substrate

404‧‧‧First patterned hard mask

406‧‧ ‧ pitch

408‧‧‧Second hard mask layer

410‧‧‧Selective brush material layer

414‧‧‧First polymer block

416‧‧‧Second polymer block

Section 416A‧‧‧

Section 416B‧‧‧

418,418’, 418”‧‧‧Fins

420‧‧‧ patterned substrate

422‧‧‧ surface

424‧‧‧Second patterned hard mask layer

426‧‧‧ obtained pitch

428,428',428"‧‧‧Interlayer dielectric (ILD) layer

430‧‧‧ patterned mask

432‧‧‧ openings

434‧‧‧Edge layout error (EPE)

436‧‧‧ cutting size

438‧‧‧Location

440‧‧‧

442‧‧‧

444‧‧‧

446‧‧‧ highlight

448‧‧‧ dent

450‧‧‧patterned mask

452‧‧‧ openings

454‧‧‧ position

456‧‧‧

458‧‧‧

460‧‧‧

462‧‧‧

464‧‧‧ highlight

466‧‧‧ dent

468,468’,468”‧‧‧Interlayer dielectric (ILD) layer

472‧‧‧ highlight

474‧‧‧ Lower fin section

476‧‧‧ recess height

600‧‧‧Semiconductor structures or devices

602‧‧‧Base

604‧‧‧ protruding fins

604A, 604B‧‧‧ source and bungee areas

605‧‧‧Sub-fin area

606‧‧‧Isolated Area

608‧‧‧ gate line

614‧‧ ‧ gate contact

616‧‧‧Upper gate contact through hole

650‧‧‧gate electrode

652‧‧‧gate dielectric layer

654‧‧‧ dielectric cover

660‧‧‧Overlying metal interconnects

670‧‧‧Interlayer dielectric stack or layer

680‧‧‧ interface

699‧‧‧ Remnant highlights

700‧‧‧ Target base layer

702‧‧‧ patterned layer

704‧‧‧hard mask layer

706‧‧‧Transfer layer

708‧‧‧Base

710‧‧‧ backbone features

712‧‧‧Intermediate group

714‧‧‧Small features of the second material type

716‧‧‧Small features of the first material type

718‧‧‧Small features of the third material type

750‧‧‧ Target base layer

752‧‧‧patterned layer

754‧‧‧hard mask layer

756‧‧‧Transfer layer

758‧‧‧Base

760‧‧‧ backbone features

762‧‧‧Intermediate group

764‧‧‧Small features of the first material type

766‧‧‧Small features of the second material type

768‧‧‧Small features of the third material type

802‧‧‧Base

804‧‧‧Transfer layer

806‧‧‧hard mask layer

808‧‧‧ backbone features

810‧‧‧First set of small features

812‧‧‧Second set of small features

814‧‧‧ third set of small features

816‧‧‧Fourth set of small features

818‧‧‧Additional spacer layer

820‧‧‧ openings

822‧‧‧ openings

824‧‧‧ spacers

826‧‧‧ spacers

828‧‧‧Last wide feature

830‧‧‧Metal line patterning features

830’‧‧‧Metal wire

832‧‧‧ below through hole patterning features

834‧‧ layer

836‧‧‧Overlay hard cover

838‧‧‧Second metal wire patterning features

840‧‧‧Second through hole patterning features

842‧‧‧Overlay hard cover

850‧‧‧ plug material

900‧‧‧ starting point structure

902‧‧‧hard mask layer

904‧‧‧ Sacrifice layer

906‧‧‧Interlayer dielectric (ILD) layer

908‧‧‧ patterned hard mask layer

910‧‧‧ patterned sacrificial layer

912‧‧‧First line opening

914‧‧‧Line end zone

916‧‧‧through opening

918‧‧‧ patterned ILD layer

920‧‧‧Interconnection lines

922‧‧‧ conductive through holes

924‧‧‧Line end opening

926‧‧‧ spacer material layer

928‧‧‧ spacers

930‧‧‧Line-end placeholder

932‧‧‧ plug socket

934‧‧‧ Plug seat

936‧‧‧interconnection line

938‧‧‧Electrical through hole

940‧‧‧ patterned ILD layer

942‧‧‧Line end opening

946/948‧‧‧Interlayer dielectric (ILD) layer

999‧‧‧Semiconductor structure

1000‧‧‧ starting structure

1002‧‧‧metal wire

1002’‧‧‧ line

1004‧‧‧Interlayer dielectric line (ILD)

1006‧‧‧ extra film

1008‧‧‧ extra film

1010‧‧‧Interlayer dielectric (ILD) line

1012‧‧‧hard mask

1014‧‧‧Surface modification layer

1016‧‧‧ middle line

1016A‧‧‧ polymer

1016B‧‧‧ polymer

1018‧‧‧ permanent interlayer dielectric (ILD) layer

1020‧‧‧hard mask layer

1022A, 1022B, 1022C‧‧‧ Through Hole Location

1024A, 1024B, 1024C‧‧‧through hole

1026‧‧‧ILD layer

1026'‧‧‧ recessed ILD layer

1028A, 1028B, 1028C‧‧‧ Plug position

1030‧‧‧Metal wire

1032‧‧‧through hole

1090‧‧‧First material type

1092‧‧‧Second material type

1097‧‧‧Seam

1099‧‧‧Seam

1100‧‧‧ starting structure

1102‧‧‧Metal wire

1102’‧‧‧ line

1104‧‧‧Interlayer dielectric line (ILD)

1106‧‧‧ extra film

1108‧‧‧ extra film

1110‧‧‧ structure

1112‧‧‧ structure

1114‧‧‧ Structure

1116‧‧‧ conformal layer

1118‧‧‧ structure

1119‧‧‧ILD material layer

1120‧‧‧ permanent interlayer dielectric (ILD) line

1120'‧‧‧ recessed ILD line

1122‧‧‧ Structure

1123‧‧‧Conformal material layer

1124‧‧‧hard mask layer

1126‧‧‧structure

1128‧‧‧Permanent ILD line

1128’‧‧‧ recessed ILD line

1130‧‧‧ structure

1132‧‧‧ trench

1134‧‧‧Material layer

1136‧‧‧ mask

1136A‧‧‧Photoresist layer

1136B‧‧‧Anti-reflective coating (ARC)

1136C‧‧‧ terrain masking

1137‧‧‧ openings

1138‧‧‧ second mask

1140‧‧‧Metal wire

1142, 1144‧‧‧ Reserved plug

1199‧‧‧Seam

1200‧‧‧Semiconductor structural layer

1202‧‧‧Metal wire

1204‧‧‧Interlayer dielectric (ILD) line

1206‧‧‧First molecular species

1208‧‧‧Second molecular species

1210‧‧‧A/B surface

1212‧‧‧C surface

1214‧‧‧Three-block copolymer

1220‧‧‧Separate structure

1222‧‧‧First District

1224‧‧‧Second District

1226‧‧‧ Third District

1250‧‧‧Separate three-block BCP

1252‧‧‧Axis

1260‧‧‧ starting structure

1262‧‧‧Metal wire

Line 1262’‧‧

1264‧‧‧Interlayer dielectric lines

1266‧‧‧ extra film

1268‧‧‧ extra film

1270‧‧‧Three-block copolymer layer

District 1272‧‧

1274‧‧‧Second District

1276‧‧‧ Third District

1280‧‧ layer

1282‧‧ layer

1290‧‧‧ lithography

1292‧‧‧some

District 1294‧‧

1302‧‧‧Metal wire

1304‧‧‧Dielectric layer

1306‧‧‧Example

1308, 1310‧‧‧ plug

1314‧‧‧Dielectric line

1400‧‧‧ starting point structure

1402‧‧‧Metal wire

1404‧‧‧Intermediate interlayer dielectric (ILD) line

1406‧‧‧ plug cap

1408‧‧‧first-order metal wire

1410‧‧‧hard mask layer

1412‧‧‧Second hard mask layer

1414‧‧‧ trench

1416‧‧‧second ILD line

1418‧‧‧ openings

1420‧‧‧ light barrel

1422‧‧‧through hole location

1424‧‧‧ District

1426‧‧‧hard mask layer

1428‧‧‧ light barrel

1430‧‧‧ Non-plug position

1432‧‧‧ District

1434‧‧‧through opening

1436‧‧‧Metal wire

1438‧‧‧through hole

1496‧‧‧Seam

1497‧‧‧Seam

1498‧‧‧Seam

1499‧‧‧Seam

1500‧‧‧Start plug grid structure

1502‧‧‧ILD layer

1504‧‧‧First hard mask layer

1506‧‧‧ Third hard mask layer

1508‧‧‧Second hard mask layer

1510‧‧‧ openings

1512‧‧‧ light barrel

1514‧‧‧ Plug position

1516‧‧‧ Plug

1600‧‧‧ starting point structure

1602‧‧‧Interlayer dielectric (ILD) layer

1604‧‧‧hard mask layer

1606‧‧‧First metal wire

1607‧‧‧ conductive through holes

1608‧‧‧ trench

1608A‧‧‧ side wall

1608B‧‧‧ bottom

1610‧‧‧Non-conformal dielectric cap

1610A‧‧‧Part 1

1610B‧‧‧Part II

1612‧‧‧second metal wire

1613‧‧‧through hole

1614‧‧‧First hard mask layer

1616‧‧‧Second hard mask layer

1630‧‧‧ starting point structure

1632‧‧‧Interlayer dielectric (ILD) layer

1634‧‧‧hard mask layer

1636‧‧‧First metal wire

1636A‧‧‧ highlight

1637‧‧‧Electrical through holes

1638‧‧‧Dielectric spacers

1640‧‧‧ Sacrificial hard mask

1642‧‧‧ trench

1644‧‧‧Sacrificial materials

1646‧‧‧Non-conformal dielectric cap

1648‧‧‧ Sacrifice cover

1650‧‧‧Location

1652‧‧‧through hole location

1654‧‧‧second metal wire

1656‧‧‧ conductive vias

1658‧‧‧First placeholder

1660‧‧‧Second placeholder

1662‧‧‧First hard mask layer

1664‧‧‧Second hard mask layer

1666‧‧‧Upper ILD layer

1668‧‧‧ openings

1670‧‧‧ conductive through holes

Section 1672‧‧‧

1700‧‧‧ starting point structure

1702‧‧‧Interlayer dielectric (ILD) layer

1704‧‧‧hard mask layer

1706‧‧‧First metal wire

1706A‧‧‧ highlight

1707‧‧‧ conductive vias

1708‧‧‧Dielectric spacers

1710‧‧‧ Sacrificial hard mask

1712‧‧‧ trench

1714‧‧‧Sacrificial materials

1715‧‧‧ Sag sacrificial material

1716‧‧‧Non-conformal dielectric cap

1716A‧‧‧上上

1722‧‧‧through hole location

1724‧‧‧second metal wire

1726‧‧‧ conductive vias

1728‧‧‧First placeholder

1730‧‧‧Second placeholder

1732‧‧‧First hard mask layer

1734‧‧‧Second hard mask layer

1736‧‧‧Upper ILD layer

1738‧‧‧ openings

1740‧‧‧Electrical through holes

Section 1742‧‧‧

1800‧‧‧ starting point structure

1802‧‧‧Metal wire

1804‧‧‧Dielectric line

1806‧‧‧etch stop layer

1808‧‧‧Interlayer dielectric layer

1810‧‧‧ patterned hard mask

1812‧‧‧ patterned interlayer dielectric layer

1814‧‧‧Metal line area

1816‧‧‧hard mask layer

1818‧‧‧etch stop layer

1820‧‧‧ pattern accumulation layer

1822‧‧‧ patterned hard mask

1824‧‧‧hard mask

1826‧‧‧One patterned memory layer

1828‧‧‧Block line

1830‧‧‧Insulation spacer forming material layer

1832‧‧‧ spacers

1834‧‧‧Second patterned memory layer

1836‧‧‧patterned etch stop layer

1838‧‧‧ patterned hard mask layer

1840‧‧‧Second patterned interlayer dielectric layer

1842‧‧‧patterned etch stop layer

1844‧‧‧through hole location

1846‧‧‧ position

1848‧‧‧Metal through hole

1850‧‧‧Metal wire

1900‧‧‧ starting point structure

1900’‧‧‧ structure

1900"‧‧‧ structure

1902‧‧‧Metal wire

1904‧‧‧Dielectric line

1906‧‧‧hard mask layer

1908‧‧‧Next patterned layer

1910‧‧‧etch stop layer

1912‧‧‧ dielectric layer

1914‧‧‧Grating structure

1916‧‧‧ patterned dielectric layer

1918‧‧‧ patterned etch stop layer

1920‧‧‧through hole location

1922‧‧‧ patterned hard mask

1924‧‧‧ District

1926‧‧‧ patterned lithographic mask

1928‧‧‧ District

1930‧‧‧ below structure

1932‧‧‧Metal through hole

1934‧‧‧Metal wire

1936‧‧‧Metal wire

1938‧‧‧Metal wire

1940‧‧‧hard mask layer

2000‧‧‧ starting point structure

2002‧‧‧Interlayer dielectric (ILD) material layer

2004‧‧‧First hard mask layer

2006‧‧‧Second hard mask layer

2008‧‧‧ Third hard mask layer

2010‧‧‧ lithographic patterned mask

2012‧‧‧ patterned hard mask layer

2014‧‧‧ patterned ILD layer

2016‧‧‧ patterned hard mask layer

2018‧‧‧Metal wire

2020‧‧‧ conductive vias

2100‧‧‧metallization

2102‧‧‧Metal wire

2103‧‧‧ below the through hole

2104‧‧‧Dielectric layer

2105‧‧‧Line end or plug area

2106‧‧‧Line trench

2108‧‧‧through hole trench

2110‧‧‧hard mask layer

2112‧‧‧Line groove

2114‧‧‧through hole trench

2120‧‧‧lower metallization layer

2122‧‧‧Metal wire

2124‧‧‧Dielectric layer

2126‧‧‧Interlayer dielectric (ILD) material layer

2128, 2128'‧‧‧ line trench

2130‧‧‧下下

2130’‧‧‧ patterned lower part

2132A, 2132B‧‧‧through hole trench

2134‧‧‧Sacrificial materials

2134'‧‧‧ patterned and filled with sacrificial materials

2136‧‧‧ patterned hard mask

2138‧‧‧Dielectric materials

2140A, 2140B‧‧‧ dielectric plug

2142‧‧‧Metal wire

2144‧‧‧ conductive vias

2150‧‧‧ seams

2152‧‧‧ dielectric plug

2152A, 2152B‧‧‧ dielectric plug

2154'‧‧‧ patterned dielectric layer

2202‧‧‧Base or layer

2204‧‧‧ holes/grooves

2206‧‧‧ Placeholders

2208‧‧‧Small depression

2210‧‧‧ patterned layer

2212‧‧‧ openings

2214‧‧‧Re-exposing holes/grooves

2216‧‧‧Material layer

2252‧‧‧metallization

2254‧‧‧Metal wire

2256, 2258‧‧‧ILD materials

2260‧‧‧ Sacrifice placeholders

2262‧‧‧mask layer

2264‧‧‧ openings

2266‧‧‧through hole location

2300‧‧‧ starting structure

2302‧‧‧Interlayer dielectric (ILD) layer

2302'‧‧‧ patterned ILD layer

2304‧‧‧First hard mask material layer

2306‧‧‧ patterned mask

2308‧‧‧ spacers

2310‧‧‧First patterned hard mask

2312‧‧‧Second patterned hard mask

2314‧‧‧hard mask cover

2316‧‧‧First patterned hard mask

2318‧‧‧Light barrel

2320‧‧‧through hole location

2322‧‧‧hard mask material

2324‧‧‧ light barrel

2326‧‧‧Location

2328‧‧‧through opening

2330‧‧‧Metal wire opening

2332‧‧‧metallization

2334‧‧‧Upper District

2350‧‧‧Start grid structure

2351‧‧‧Base

2352‧‧‧Grating ILD layer

2354‧‧‧First hard mask layer

2356‧‧‧Second hard mask layer

2358‧‧‧ openings

2358’‧‧‧Opening

2360‧‧‧ dielectric layer

2362‧‧‧Light barrel

2364‧‧‧through hole location

2364’‧‧‧ openings

2366‧‧‧ remaining openings

2400‧‧‧ starting point structure

2402‧‧‧Metal wire

2404‧‧‧Intermediate interlayer dielectric (ILD) line

2406‧‧‧first-order metal wire

2408‧‧‧ILD material layer

2410‧‧‧hard mask layer

2412‧‧‧ trench

2414‧‧‧ patterned ILD layer

2416‧‧‧ light barrel

2418‧‧‧through hole location

2420‧‧‧Last ILD material

2422‧‧‧Metal wire

2424‧‧‧through hole

2450‧‧‧ single plane

2497‧‧‧Seam

2498‧‧‧Seams

2499‧‧‧Seam

2500‧‧‧ starting structure

2502‧‧‧Interlayer dielectric (ILD) layer

2502'‧‧‧ patterned ILD layer

2504‧‧‧First hard mask material layer

2506‧‧‧ patterned mask

2508‧‧‧ spacers

2510‧‧‧ trench

2512‧‧‧First color light bucket

2512A‧‧‧Selected first color light bucket

2513A‧‧‧Selected through hole opening

2514‧‧‧ trench

2516‧‧‧Second color light barrel material layer

2518‧‧‧Second color light bucket

2518A, 2518B‧‧‧Selected second color light bucket

2519A, 2519B‧‧‧through opening

2520‧‧‧Second hard mask

2521‧‧‧Red exposure

2522‧‧‧ Third hard mask

2523‧‧‧Green exposure

2524‧‧‧through hole location

2526‧‧‧Metal wire trench

2600‧‧‧Traditional BEOL metallization

2602‧‧‧Interlayer dielectric layer

2604‧‧‧Flexed wire or route

2606‧‧‧Cut, interrupt or plug

2608‧‧‧Upper or lower route

2610‧‧‧Flexible wire

2612‧‧‧Electrical through hole

2650‧‧‧BEOL metallization

2652‧‧‧Interlayer dielectric layer

2654‧‧‧Flexed wire or route

2656‧‧‧Cut, interrupt or plug

2658‧‧‧Electrical sheet

2700‧‧‧Base

2702‧‧‧Interlayer dielectric (ILD) layer

2704‧‧‧Overlay hard mask

2706‧‧‧First grating hard mask

Section 2706’‧‧‧

2708‧‧‧Second grating hard mask

2710‧‧‧Overlay hard mask

2712‧‧‧ light barrel

2714‧‧‧First patterned hard mask

2715‧‧‧Second patterned hard mask

2716‧‧‧Dielectric zone

2718‧‧‧ light barrel

2720‧‧‧ Third patterned hard mask

2722‧‧‧ patterned ILD layer

2724‧‧‧Flexible wire

2726‧‧‧ Plug

2728‧‧‧Conductor

2800‧‧‧ metal layer

2802‧‧‧ Covering the hard mask layer

2804‧‧‧First grating hard mask

2806‧‧‧Second grating hard mask

2808‧‧‧Overlay hard mask

2810‧‧‧ Third hard mask

2812‧‧‧Fourth hard mask

2814‧‧‧ openings

2816‧‧‧Light barrel

2818‧‧‧ etching trench

2820‧‧‧The first patterned hard mask

2822‧‧‧First patterned metal layer

2824‧‧‧ conductive vias

2826‧‧‧Deep hard mask area

2828‧‧‧Shallow hard mask area

2830‧‧‧ openings

2832‧‧‧ light barrel

2834‧‧‧Second patterned hard mask

2836‧‧‧ trench

2838‧‧‧Deep hard mask area

2840‧‧‧Shallow hard mask area

2842‧‧‧The third patterned hard mask

2844‧‧‧Second patterned metal layer

2846‧‧‧Deep hard mask area

2848‧‧‧ openings

2850‧‧‧Light barrel

2852‧‧‧ Fourth patterned hard mask

2854‧‧‧ trench

2856‧‧‧ Third patterned metal layer

2858‧‧‧through hole cover

2860‧‧‧ILD

2861‧‧‧ILD backfill

2862‧‧‧ Plug area

2864‧‧‧Flexible wire

2866‧‧‧Conductor

2899‧‧‧ILD layer

2902‧‧‧Base

2904‧‧‧Pre-patterned hard mask

2906‧‧‧Two-stage baking photoresist

2907‧‧‧ exposure

2908‧‧‧Displaced aerial imagery

2912‧‧‧closed light barrel

2920‧‧‧ openings

2950‧‧‧ partially cleared

2952‧‧‧Residual photoresist

2954‧‧‧ light barrel

3002,3002’, 3002”‧‧‧ first light barrel

3004,3004’,3004”‧‧‧second light barrel

3006,3006’‧‧‧ exposure

3010, 3010', 3010" ‧ ‧ Photoacid Production (PAG)

3012‧‧‧Light-based ingredients

3014‧‧‧Inhibitor

3020, 3022‧‧‧ diffused materials

3024, 3026‧‧‧Materials

3028, 3030‧‧‧Materials

3032‧‧‧Cleaned light bucket

3034‧‧‧ Blocked light bucket

3050‧‧‧Grafting light-based production components

3060‧‧ layer

3100‧‧‧ pattern

3102‧‧‧ILD line

3104‧‧‧resist line

3106‧‧‧ hole

3202‧‧‧ILD materials

3204‧‧‧ trench

3206‧‧‧Chemical amplified photoresist

District 3208‧‧‧

3210‧‧‧Pre-catalyst layer

3212‧‧‧Dielectric materials

3212A, part 3212B‧‧‧

3214‧‧‧Linking Area

3216‧‧‧ metal filled layer

3218‧‧‧Metal characteristics

3300‧‧‧Three Hexane Heterocyclohexane

3320‧‧‧ cross-linking materials

3340‧‧‧ Linked triterpene heterocyclohexane structure

3400‧‧‧ starting structure

3402‧‧‧Interlayer dielectric (ILD) layer

3402', 3402", 3402''', 3402'''', 3402''''' ‧‧‧ patterned ILD layer

3404‧‧‧First hard mask material layer

3406‧‧‧ patterned mask

3408‧‧‧ spacers

3410‧‧‧First patterned hard mask

3412‧‧‧Second patterned hard mask

3414‧‧‧hard mask cover

3416‧‧‧First patterned hard mask

3418‧‧‧4th hard mask layer

3420‧‧‧First diagonal hard mask

3422‧‧‧ closest to adjacent distance

3424‧‧‧ light barrel

3426‧‧‧through hole location

3428‧‧‧hard mask material

3430‧‧‧ light barrel

3432‧‧‧through hole location

3434‧‧‧Sacrificial materials

3436‧‧‧ trench

3438‧‧‧Second diagonal hard mask

3440‧‧‧Light barrel

3442‧‧‧ closest to adjacent distance

3444‧‧‧ trench

3446‧‧‧ hard mask material layer

3448‧‧‧Light barrel

3450‧‧‧Location

3452‧‧‧ trench

3454‧‧‧metallization

3456‧‧‧Metal characteristics

3502‧‧‧First pre-patterned hard mask

3504‧‧‧Second pre-patterned hard mask

3506‧‧‧Under layer

3508‧‧‧ openings

3510‧‧‧Photo resist layer

3512‧‧‧Selected

3514‧‧‧ lithography exposure

3516‧‧‧ openings

3602‧‧‧First pre-patterned hard mask

3604‧‧‧Second pre-patterned hard mask

3610‧‧‧Photo resist layer

3616‧‧‧ openings

3650A, 3650B, 3650C, 3650D, 3650E‧‧‧ overlay images

3652A‧‧‧ Upper half

3654A‧‧‧ Lower half

3656A, 3656B, 3656C, 3656D, 3656E‧‧‧ Wide unexposed features

3658A, 3658B, 3658C, 3658D, 3658E‧‧‧ Wide unexposed features

3697‧‧‧ Weights and Measures Structure

3698‧‧‧ Layer 1 features

3699‧‧‧ Layer 2 features

3702‧‧‧First pre-patterned hard mask

3704‧‧‧Second pre-patterned hard mask

3710‧‧‧Photo resist layer

3716‧‧‧ openings

3750A, 3750B, 3750C, 3750D, 3750E‧‧‧ overlay images

3760A, 3760B, 3760C, 3760D, 3760E‧‧‧

3800‧‧‧Base

3801‧‧‧ lithography mask structure

3802‧‧‧ patterned absorbent layer

3804‧‧‧Upper

3806‧‧‧ patterned shifter layer

3808‧‧‧ top surface

3810‧‧‧ Middle grain area

3812‧‧‧ top surface

3814‧‧‧ top surface

3820‧‧‧Box area

3830‧‧‧die box interface area

3840‧‧‧Double-layer stacking

3900‧‧‧Electronic beam

3902‧‧‧Electronic source

3904‧‧‧Electronic bundle

3906‧‧‧Restricted aperture

3908‧‧‧Lighting optics

3910‧‧‧ Output beam

3912‧‧‧Slit

3914‧‧‧ Thin lens

3916‧‧‧Molded aperture

3918‧‧‧Remove Aperture Array (BAA)

Section 3920‧‧‧

3921‧‧‧ bundle part

3922‧‧‧Last aperture

3924‧‧ level feedback deflector

3926‧‧‧ electron beam obtained

3928‧‧ points

3930‧‧‧ wafer

3932‧‧ level scan

3934‧‧‧Arrow

4000‧‧‧ aperture

4002‧‧‧ line

4004‧‧‧Arrow

4006‧‧‧Edge layout error (EPE)

4100, 4102‧‧‧ aperture

Line 4104, 4106‧‧

4108‧‧‧Arrow

4110‧‧‧EPE

4112‧‧‧ Distance demand

4114‧‧‧ interval

4200‧‧‧BAA

4202, 4204‧‧‧

4206‧‧‧ aperture

4208‧‧‧ line

4210‧‧‧ Direction

4300‧‧‧ line

4302‧‧‧Opening position

4304‧‧‧through hole

4306‧‧‧Cutting

4310‧‧‧BAA

4312‧‧‧Scanning direction

4350‧‧‧Stacking

4352‧‧‧metallization layer

4354, 4356, 4358, 4360, 4362, 4364, 4366, 4368‧‧‧ metal layers

4370,4372‧‧‧Metal wire

4374‧‧‧through hole location

4400‧‧‧ Computing device

4402‧‧‧Circuit board

4404‧‧‧ Processor

4406‧‧‧Communication chip

4500‧‧‧ Inserter

4502‧‧‧First substrate

4504‧‧‧Second substrate

4506‧‧‧Ball Grid Array (BGA)

4508‧‧‧Metal interconnection

4510‧‧‧through hole

4512‧‧‧Through through hole (TSV)

4514‧‧‧Embedded device

Figure 1A illustrates a cross-sectional view of the starting structure following deposition of a layer of hard masking material formed on an interlayer dielectric (ILD) layer (but prior to patterning).

Figure 1B illustrates a cross-sectional view of the structure of Figure 1A following the patterning of the hard mask layer halved by the pitch.

2 illustrates a cross-sectional view of a spacer-based six-times patterning (SBSP) processing scheme involving a pitch factor of six.

Figure 3 illustrates a cross-sectional view of a nine-times patterning (SBNP) processing scheme based on a spacer segmentation pitch factor of nine.

4A-4N illustrate cross-sectional views of various operations in a method of fabricating a non-planar semiconductor device, in accordance with an embodiment of the present invention, wherein:

Figure 5 illustrates the structure of Figure 4N following exposure of portions above the plurality of fins, in accordance with an embodiment of the present invention.

Figure 6A illustrates a cross-sectional view of a non-planar semiconductor device in accordance with an embodiment of the present invention.

Figure 6B illustrates a plan view taken along the a-a' axis of the semiconductor device of Figure 6A, in accordance with an embodiment of the present invention.

7A and 7B illustrate cross-sectional views of a target infrastructure for enabling a very tight pitch final pattern of a semiconductor layer, in accordance with an embodiment of the present invention.

8A-8H illustrate cross-sectional views showing various operations in a method of fabricating a target infrastructure for enabling a very tight pitch final pattern of a semiconductor layer, in accordance with an embodiment of the present invention.

Figures 8H' and 8H" illustrate cross-sectional views of exemplary structures following the patterning of vias and plugs, in accordance with an embodiment of the present invention.

9A-9L illustrate oblique cross-sectional views of portions of an integrated circuit layer representing various operations in a method of pitch segmentation patterning for increased overlap tolerance for back end of line (BEOL) interconnect fabrication. According to an embodiment of the invention.

Figures 10A-10M illustrate portions of an integrated circuit layer that illustrate various operations in a method of self-aligned vias and metal patterning, in accordance with an embodiment of the present invention.

Figures 11A-11M illustrate portions of an integrated circuit layer that illustrate various operations in a method of self-aligned vias and metal patterning, in accordance with an embodiment of the present invention.

12A-12C illustrate oblique cross-sectional views showing various operations in a method of using a three-block copolymer to form self-aligned vias or contacts of a back end of line (BEOL) interconnect, in accordance with the present invention. Example.

Figure 12D illustrates a beveled cross-sectional view showing the operation in a method of using a three-block copolymer to form a self-aligned via or junction of a back end of line (BEOL) interconnect, in accordance with an embodiment of the present invention.

Figure 12E illustrates a beveled cross-sectional view showing another operation in a method of using a three-block copolymer to form a self-aligned via or junction of a back end of line (BEOL) interconnect, in accordance with another aspect of the present invention Example.

Figure 12F illustrates a three-block copolymer used to form self-aligned vias or contacts of a back end of line (BEOL) interconnect, in accordance with an embodiment of the present invention.

12G and 12H illustrate plan views and corresponding cross-sectional views showing various operations in a method of using a three-block copolymer to form self-aligned vias or contacts of a back end of line (BEOL) interconnect, Embodiments of the invention.

12I-12L illustrate plan views and corresponding cross-sectional views showing various operations in a method of using a three-block copolymer to form self-aligned vias or contacts of a back end of line (BEOL) interconnect, Embodiments of the invention.

Figure 13 illustrates a plan view and corresponding cross-sectional view of a self-aligned via structure following the formation of metal lines, vias and plugs, in accordance with an embodiment of the present invention.

Figures 14A-14N illustrate portions of an integrated circuit layer that represent various operations in a method of subtracting self-aligned vias and plug patterning, in accordance with an embodiment of the present invention.

Figures 15A-15D illustrate portions of an integrated circuit layer that represent various operations in a method of subtracting self-aligned plug patterning, in accordance with another embodiment of the present invention.

16A-16D illustrate cross-sectional views of portions of an integrated circuit layer showing various operations in a method of forming a dielectric helmet for use in back end of line (BEOL) interconnect fabrication, in accordance with an embodiment of the present invention.

16E-16P illustrate cross-sectional views of portions of an integrated circuit layer showing another operation in a method involving dielectric helmet formation for back end of line (BEOL) interconnect fabrication, in accordance with an embodiment of the present invention.

17A-17J illustrate cross-sectional views of portions of an integrated circuit layer showing another operation in a method involving dielectric helmet formation for back end of line (BEOL) interconnect fabrication, in accordance with an embodiment of the present invention.

18A-18W illustrate plan views and corresponding oblique and cross-sectional views showing various operations in a metal via processing scheme for a back end of line (BEOL) interconnect, in accordance with an embodiment of the present invention.

19A-19L illustrate plan views and corresponding oblique cross-sectional views showing various operations in a grid self-aligned metal via processing scheme for back end of line (BEOL) interconnects, in accordance with implementations of the present invention example.

20A-20G illustrate plan views and corresponding cross-sectional views showing various operations in a method of fabricating a grating-based plug and cutting for forming a characteristic end of a back end of line (BEOL) interconnect, in accordance with the present invention An embodiment.

Figure 21A illustrates a plan view and corresponding cross-sectional view taken along the a-a' axis of a plan view of a metallization layer of a currently known semiconductor device.

Figure 21B illustrates a cross-sectional view of a wire end or plug made using a currently known treatment scheme.

Figure 21C illustrates another cross-sectional view of a wire end or plug made using a currently known treatment scheme.

21D-21J illustrate cross-sectional views showing various operations in a process for patterning metal wire ends of a back end of line (BEOL) interconnect, in accordance with an embodiment of the present invention.

Figure 21K illustrates a cross-sectional view of a metallization layer of an interconnect structure of a semiconductor die including a dielectric line end or plug having a seam therein, in accordance with an embodiment of the present invention.

Figure 21L illustrates a cross-sectional view of a metallization layer of an interconnect structure of a semiconductor die including dielectric line ends or plugs that are not in close proximity to the conductive vias, in accordance with an embodiment of the present invention.

22A-22G illustrate portions of an integrated circuit layer that are representative of various operations in a self-aligned isotropic etch process that pre-forms vias or plug locations, in accordance with an embodiment of the present invention.

22H-22J illustrate oblique angle cross-sectional views of portions of an integrated circuit layer showing various operations in a method of self-aligned isotropic etching involving pre-formed via locations, in accordance with an embodiment of the present invention. .

Figures 23A-23L illustrate portions of an integrated circuit layer that represent various operations in a method of subtracting self-aligned vias and plug patterning, in accordance with an embodiment of the present invention.

Figures 23M-23S illustrate portions of an integrated circuit layer that represent various operations in a method of reducing self-aligned via patterning, in accordance with an embodiment of the present invention.

Figures 24A-24I illustrate portions of an integrated circuit layer that represent various operations in a method of subtracting self-aligned vias and plug patterning, in accordance with an embodiment of the present invention.

Figures 25A-25H illustrate portions of an integrated circuit layer that illustrate various operations in a method of subtractive self-aligned via patterning using a multi-color optical barrel, in accordance with an embodiment of the present invention.

Figure 25I illustrates an exemplary two-tone resist for one light barrel type and an example single tone resist for another light barrel type, in accordance with an embodiment of the present invention.

Figure 26A illustrates a plan view of a conventional back end of line (BEOL) metallization layer.

Figure 26B illustrates a plan view of a back end of line (BEOL) metallization layer having conductive sheets to couple metal lines of the metallization layer, in accordance with an embodiment of the present invention.

27A-27K illustrate oblique cross-sectional views showing various operations in a method of fabricating a back end of line (BEOL) metallization layer having a conductive sheet to couple metal lines of the metallization layer, in accordance with the present invention. Embodiments of the invention.

28A-28T illustrate oblique cross-sectional views showing various operations in a method of fabricating a back end of line (BEOL) metallization layer having a conductive sheet to couple metal lines of the metallization layer, in accordance with the present invention. Embodiments of the invention.

29A-29C illustrate cross-sectional views and corresponding plan views of various operations in a method of patterning a light bucket including a two-stage baking photoresist, in accordance with an embodiment of the present invention.

Figure 29D illustrates a cross-sectional view of a conventional resist photobleak structure following development of a bare barrel after misalignment exposure.

Figures 30A-30E illustrate a schematic view of various operations in a method of patterning using a light bucket comprising a two-stage baked photoresist, in accordance with an embodiment of the present invention.

Figure 30A' illustrates a schematic view of another operation in a method of patterning using a light bucket, in accordance with an embodiment of the present invention.

Figure 30A'' illustrates a schematic view of another operation in a method of patterning using a light bucket, in accordance with an embodiment of the present invention.

Figure 31 illustrates an oblique angle view of an alternating pattern of interlayer dielectric (ILD) lines and resist lines having apertures formed in one of the resist lines, in accordance with an embodiment of the present invention.

Figures 32A-32H illustrate a cross-sectional view in a fabrication process involving the use of a bottom-up cross-linked optical image inversion of a dielectric, in accordance with an embodiment of the present invention.

Figure 33A illustrates a trisilacyclohexane molecule, in accordance with an embodiment of the invention.

Figure 33B illustrates two crosslinked (XL) trioxane heterocyclohexane molecules used to form a crosslinked material, in accordance with an embodiment of the present invention.

Figure 33C illustrates an idealized representation of the structure of a chain triterpene heterocyclohexane, in accordance with an embodiment of the present invention.

Figures 34A-34X illustrate portions of an integrated circuit layer that illustrate various operations in a method of using a diagonal hard mask self-aligned via and plug patterning, in accordance with an embodiment of the present invention.

Figures 35A-35D illustrate cross-sectional views and corresponding top-down views showing various operations in a patterning scheme using a pre-patterned hard mask, in accordance with an embodiment of the present invention.

Figure 36A illustrates a top down view of an overlay scenario in which the current layer is overlaid on the underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.

Figure 36B illustrates a top down view of the overlay context, wherein the current layer has a positive overlap with respect to a quarter pitch of the underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.

Figure 36C illustrates a top down view of the overlap context, wherein the current layer has a positive overlap with a half pitch of the underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.

Figure 36D illustrates a top down view of the overlap context, wherein the current layer has a positive overlap of any value Δ relative to the underlying pre-patterned hard mask grid, in accordance with an embodiment of the present invention.

Figure 36E illustrates a top-down view of the overlap context, where the current layer has a positive overlap of any value Δ relative to the underlying pre-patterned hard mask grid, wherein the measurable Δ system is changed by resist sensitivity and/or Or the feature size has been depicted and changed to be as small as desired, in accordance with an embodiment of the present invention.

Figure 36F illustrates an exemplary metrology structure suitable for the manner described above in relation to Figures 36A-36E, in accordance with an embodiment of the present invention.

Figure 37A illustrates a top down view of an overlay scenario in which the current layer is overlaid on the underlying pre-patterned hard mask, in accordance with an embodiment of the present invention.

Figure 37B illustrates a top down view of the overlap context, wherein the current layer has a positive overlap with respect to a quarter pitch of the underlying pre-patterned hard mask grid in the X direction, in accordance with an embodiment of the present invention.

Figure 37C illustrates a top down view of the overlap context, wherein the current layer has a negative overlap with respect to a quarter pitch of the underlying pre-patterned hard mask grid in the X direction, in accordance with an embodiment of the present invention.

Figure 37D illustrates a top down view of the overlap context, wherein the current layer has a positive overlap with respect to a quarter pitch of the underlying pre-patterned hard mask grid in the Y direction, in accordance with an embodiment of the present invention.

Figure 37E illustrates a top down view of the overlap context, wherein the current layer has a positive overlap with respect to a quarter pitch of the lower pre-patterned hard mask grid in the X direction and has a lower relative to the Y direction The positive overlap of the quarter pitch of the pre-patterned hard mask grid is in accordance with an embodiment of the present invention.

Figure 38 illustrates a cross-sectional view of a lithographic mask structure in accordance with an embodiment of the present invention.

Figure 39 is a schematic cross-sectional view of an electron beam column of an electron beam lithography apparatus.

Figure 40 illustrates the aperture (left) of the shadow aperture array (BAA) relative to the line (right) to be cut or having a via placed in the target location, when the line is scanned below the aperture.

Figure 41 illustrates two non-interlaced apertures (left) relative to the BAA of the two lines (right) to be cut or having through holes in the target position, when the line is scanned below the aperture.

Figure 42 illustrates two rows of staggered apertures (left) relative to the BAA of the complex line (right) to be cut or having a through hole placed in the target position, when the line is scanned below the aperture, in the scanning direction by the arrow Shown in accordance with an embodiment of the present invention.

Figure 43A illustrates two rows of staggered apertures (left) of a BAA with respect to a complex line (right) of a through hole (filled into a square box) having a cut (break in the horizontal line) or a staggered BAA, in the scanning direction Arrows are shown in accordance with embodiments of the present invention.

Figure 43B illustrates a cross-sectional view of a metallization layer stack in an integrated circuit, in accordance with an embodiment of the present invention, in accordance with the metal line layout of the type illustrated in Figure 21A.

Figure 44 illustrates a computing device in accordance with an embodiment of the present invention.

Figure 45 illustrates an inserter that includes one or more embodiments of the present invention.

Claims (55)

An integrated circuit structure comprising: a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a grating pattern interrupted by a portion of the body portion; and a trench isolation layer interposed between the plurality of semiconductor bodies And adjacent to the lower portion of the plurality of semiconductor bodies, but not adjacent to the upper portion of the plurality of semiconductor bodies, wherein the trench isolation layer is located over the portion of the body portion; one or more gate electrode stacks And the sidewalls of the upper portions of the upper portions of the plurality of semiconductor bodies and laterally adjacent to the upper portions of the plurality of semiconductor bodies, and portions of the trench isolation layer; and the rear portion a BEOL metallization layer over the one or more gate electrode stacks, the BEOL metallization layer comprising a plurality of alternating first and second conductive line types along the same direction, wherein the first The total composition of the type of conductive line is different from the total composition of the second type of conductive line. The integrated circuit structure of claim 1, wherein the line of the first conductive line type is isolated by a pitch, and wherein the line of the second conductive line type is isolated by the pitch. The integrated circuit structure of claim 1, wherein the plurality of alternating first and second conductive line types are in an interlayer dielectric (ILD) layer. The integrated circuit structure of claim 1, wherein the plurality of alternating first and second conductive line types are separated by an air gap. The integrated circuit structure of claim 1, wherein the total composition of the first conductive line type substantially comprises copper, and wherein the total composition of the second conductive line type substantially comprises an element selected from the group consisting of Al, Ti, A material consisting of Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au, and alloys thereof. The integrated circuit structure of claim 1, wherein the plurality of alternating first and second conductive line types each comprise a barrier layer along a bottom and a sidewall of the line. The integrated circuit structure of claim 1, wherein the plurality of alternating first and second conductive line types each include a barrier layer along a bottom of the line but not along a side wall of the line. . The integrated circuit structure of claim 1, wherein one or more of the plurality of alternating first and second conductive line types are connected to the lower via, which is connected to the underlying metal a lower metallization layer between the one or more gate electrode stacks and the BEOL metallization layer, and the plurality of alternating first and second conductive line types of the lines One or more are interrupted by a dielectric plug. The integrated circuit structure of claim 1, wherein the grating pattern has a constant pitch. The integrated circuit structure of claim 1, further comprising: a source or a drain region on both sides of the one or more gate electrode stacks, wherein the source or drain regions are adjacent to each other The upper portions of the plurality of semiconductor bodies and comprising semiconductor materials different from the semiconductor material of the semiconductor bodies. The integrated circuit structure of claim 1, further comprising: a source or a drain region on both sides of the one or more gate electrode stacks, wherein the source or drain regions are located Within the upper portions of the plurality of semiconductor bodies. The integrated circuit structure of claim 1, wherein each of the one or more gate electrode stacks comprises a high-k gate dielectric layer and a metal gate electrode. The integrated circuit structure of claim 1, wherein the first conductive line types have an upper surface having a metal composition different from a metal composition of the upper surface of the second conductive line types. An integrated circuit structure comprising: a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a grating pattern interrupted by a portion of the body portion; and a trench isolation layer interposed between the plurality of semiconductor bodies And adjacent to the lower portion of the plurality of semiconductor bodies, but not adjacent to the upper portion of the plurality of semiconductor bodies, wherein the trench isolation layer is located over the portion of the body portion; one or more gate electrode stacks And the sidewalls of the upper portions of the upper portions of the plurality of semiconductor bodies and laterally adjacent to the upper portions of the plurality of semiconductor bodies, and portions of the trench isolation layer; and the rear portion a BEOL metallization layer over the one or more gate electrode stacks, the BEOL metallization layer comprising a plurality of alternating first and second conductive line types along the same direction, wherein the plurality The alternating first and second electrically conductive line types each comprise a barrier layer along the bottom of the line but not along the side walls of the line. The integrated circuit structure of claim 14, wherein the line of the first conductive line type is isolated by a pitch, and wherein the line of the second conductive line type is isolated by the pitch. The integrated circuit structure of claim 14, wherein the plurality of alternating first and second conductive line types are in an interlayer dielectric (ILD) layer. The integrated circuit structure of claim 14, wherein the plurality of alternating first and second conductive line types are separated by an air gap. The integrated circuit structure of claim 14, wherein the total composition of the first conductive line type is the same as the total composition of the second conductive line type. The integrated circuit structure of claim 14, wherein the total composition of the first conductive line type substantially comprises copper, and wherein the total composition of the second conductive line type substantially comprises selected from the group consisting of Al, Ti, Zr, A material of a group consisting of Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au, and alloys thereof. The integrated circuit structure of claim 14, wherein one or more of the plurality of alternating first and second conductive line types are connected to the lower via, which is connected to the lower metal a lower metallization layer between the one or more gate electrode stacks and the BEOL metallization layer, and the plurality of alternating first and second conductive line types of the lines One or more are interrupted by a dielectric plug. The integrated circuit structure of claim 14, wherein the grating pattern has a constant pitch. The integrated circuit structure of claim 14, further comprising: a source or a drain region on both sides of the one or more gate electrode stacks, wherein the source or drain regions are adjacent The upper portions of the plurality of semiconductor bodies and comprising semiconductor materials different from the semiconductor material of the semiconductor bodies. The integrated circuit structure of claim 14, further comprising: a source or a drain region on both sides of the one or more gate electrode stacks, wherein the source or drain regions are located Within the upper portions of the plurality of semiconductor bodies. The integrated circuit structure of claim 14, wherein each of the one or more gate electrode stacks comprises a high-k gate dielectric layer and a metal gate electrode. An integrated circuit structure comprising: a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a first grating pattern interrupted by a portion of the body portion; and a trench isolation layer interposed between the plurality of semiconductors Between the bodies and adjacent to the lower portion of the plurality of semiconductor bodies, but not adjacent to the upper portion of the plurality of semiconductor bodies, wherein the trench isolation layer is located over the portion of the body portion; one or more gates An electrode stack on a top surface of the upper portions of the plurality of semiconductor bodies and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies, and on portions of the trench isolation layer; a first back end of line (BEOL) metallization layer over the one or more gate electrode stacks, the first BEOL metallization layer comprising a second grating of alternating metal lines and dielectric lines in a first direction; And a second BEOL metallization layer over the first BEOL metallization layer, the second BEOL metallization layer comprising an alternating metal in the second direction And a third grating of the dielectric line, the second direction is orthogonal to the first direction, wherein each metal line of the third grating of the second BEOL metallization layer is on the dielectric layer, the dielectric layer comprising An alternating metal line of the first BEOL metallization layer and an alternating different region of the first dielectric material and the second dielectric material of the dielectric layer, and wherein the dielectric lines of the third grating of the second BEOL metallization layer comprise A continuous region of three dielectric materials different from the alternating regions of the first dielectric material and the second dielectric material. The integrated circuit structure of claim 25, wherein the metal line of the second BEOL metallization layer is electrically coupled to the metal line of the first BEOL metallization layer by a via, the via having one A center directly aligned with a center of the metal line of the first BEOL metallization layer and a center of the metal line of the second BEOL metallization layer. The integrated circuit structure of claim 25, wherein the metal line of the second BEOL metallization layer is interrupted by a plug having a center of a dielectric line with the first BEOL metallization layer Directly centered. The integrated circuit structure of claim 25, wherein the first dielectric material, the second dielectric material, and the third dielectric material are not the same material. The integrated circuit structure of claim 25, wherein only the first dielectric material, the second dielectric material, and the third dielectric material are the same material. The integrated circuit structure of claim 25, wherein the alternating different regions of the first dielectric material and the second dielectric material are separated by a seam, and wherein the continuous region of the third dielectric material Separating from the alternating regions of the first dielectric material and the second dielectric material by a seam. The integrated circuit structure of claim 25, wherein the first dielectric material, the second dielectric material, and the third dielectric material are all the same material. The integrated circuit structure of claim 25, wherein the first grating pattern has a constant pitch. The integrated circuit structure of claim 25, further comprising: a source or a drain region on both sides of the one or more gate electrode stacks, wherein the source or drain regions are adjacent The upper portions of the plurality of semiconductor bodies and comprising semiconductor materials different from the semiconductor material of the semiconductor bodies. The integrated circuit structure of claim 25, further comprising: a source or a drain region on both sides of the one or more gate electrode stacks, wherein the source or drain regions are located Within the upper portions of the plurality of semiconductor bodies. The integrated circuit structure of claim 25, wherein each of the one or more gate electrode stacks comprises a high-k gate dielectric layer and a metal gate electrode. The integrated circuit structure of claim 25, wherein the etch stop layer or the additional dielectric layer separates the first BEOL metallization layer from the second BEOL metallization layer. A method of fabricating an integrated circuit structure, the method comprising: forming a plurality of backbone features over a substrate; forming a first set of spacers along sidewalls of each of the plurality of backbone features, the first set of spacers having a different Forming a first material composed of materials of the plurality of backbone features; forming a second set of spacers along sidewalls of each of the first set of spacers, the second set of spacers having a different composition than the first material And a second material composition of the material different from the plurality of backbone features; forming a third set of spacers along sidewalls of each of the second set of spacers, the third set of spacers having a different a first material composition, a third material composition different from the second material composition and different from the plurality of backbone features; forming a fourth set of spaces along sidewalls of each of the third set of spacers The fourth set of spacers has the second material composition; forming laterally adjacent to the fourth set of spacers a fifth set of spacers of the sidewalls, the fifth set of spacers having the first material composition; after forming the fifth set of spacers, removing the plurality of backbone features; removing the plurality of backbone features Forming a sixth set of spacers along sidewalls of each of the first set of spacers and sidewalls of each of the fifth set of spacers, the sixth set of spacers having the second material Forming; forming a final feature in each opening between adjacent pairs of spacers of the sixth set of spacers; planarizing the first set of spacers, the second set of spacers, and the third set of spacers And the fourth set of spacers, the fifth set of spacers, the sixth set of spacers, and the final features to form a target base layer; and using the target base layer to form a metallization of the semiconductor structure Floor. The method of claim 37, wherein forming the plurality of backbone features comprises using standard lithography operations. The method of claim 37, wherein forming the plurality of backbone features comprises forming a plurality of features comprising a material selected from the group consisting of tantalum nitride, tantalum oxide, and tantalum carbide. The method of claim 37, wherein forming the first set of spacers comprises: using an atomic layer deposition (ALD) process to deposit materials of the first set of spacers conformal to the plurality of backbone features; And anisotropically etching the material of the first set of spacers to form the first set of spacers along the sidewalls of each of the plurality of backbone features. The method of claim 37, wherein forming the first set of spacers comprises selectively growing the first set of spacers along the sidewalls of each of the plurality of backbone features. The method of claim 37, wherein each of the final features has a greater than the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, The side widths of the side widths of the fifth set of spacers and the spacers of the sixth set of spacers. The method of claim 37, wherein each of the final features is formed by a combination of material growth formed by adjacent pairs of spacers of the sixth set of spacers. The method of claim 37, wherein each of the final features comprises the third material composition. The method of claim 37, wherein the using the target base layer to form the metallization layer of the semiconductor structure comprises: removing all portions of the first material composition to form a first plurality of trenches; and forming the first A plurality of conductive lines are in the first plurality of trenches. The method of claim 45, wherein the using the target base layer to form the metallization layer of the semiconductor structure further comprises: removing all portions of the third material composition to form a second plurality of trenches; Two complex conductive lines are in the second plurality of trenches. The method of claim 46, wherein the first plurality of conductive lines are the same composition as the second plurality of conductive lines. The method of claim 46, wherein the first plurality of conductive lines are different from the second plurality of conductive lines. The method of claim 37, further comprising forming an additional 20-200 sets of spacers between the formation of the fifth set of spacers and the sixth set of spacers, and prior to removing the plurality of backbone features . A target structure for fabricating an integrated circuit structure, the target structure comprising: a first set of spacers above the hard mask layer above the substrate, the first set of spacers having a first material composition; along the a second set of spacers on an outer sidewall of each of the set of spacers, the second set of spacers having a second material composition different from the first material composition; each of the second set of spacers a third set of spacers of the sidewalls, the third set of spacers having a third material composition different from the first material composition and different from the second material composition; along each of the third set of spacers a fourth set of spacers of the sidewalls of the person, the fourth set of spacers having the second material composition; a fifth set of spacers laterally adjacent to the sidewalls of each of the fourth set of spacers, a fifth set of spacers having the first material composition; an inner sidewall along each of the first set of spacers and a sixth set of spacers along a sidewall of each of the fifth set of spacers, Sixth set of spacers There the second material; and a sixth set of the plurality of adjacent spacers final characteristics of each of the openings between the spacers. The target structure of claim 50, wherein the first group of spacers, the second group of spacers, the third group of spacers, the fourth group of spacers, and the fifth group of spacers The sixth set of spacers, and the final features are substantially coplanar with each other. The target structure of claim 50, wherein each of the final features has a larger than the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, The side widths of the side widths of the fifth set of spacers and the spacers of the sixth set of spacers. For example, the target structure of claim 52, wherein the side width of each final feature is in the range of 6-12 nm. The target structure of claim 50, wherein each final feature has a seam that is approximately concentrated within the final feature. For example, the target structure of claim 50, wherein each final feature comprises the third material composition.