CN102437090B - Copper back channel interconnecting process without metal blocking layer - Google Patents
Copper back channel interconnecting process without metal blocking layer Download PDFInfo
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- CN102437090B CN102437090B CN201110194242.5A CN201110194242A CN102437090B CN 102437090 B CN102437090 B CN 102437090B CN 201110194242 A CN201110194242 A CN 201110194242A CN 102437090 B CN102437090 B CN 102437090B
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Abstract
The invention relates to a copper back channel interconnecting process without a metal blocking layer, which solves the problems that in the prior art, the residue of a metal layer etching blocking layer exists in the metal wire connecting process, so the integral capacitance is increased, and the long capacitance delay time is further caused. After the metal layer etching blocking layer is deposited, the excessive metal layer etching blocking layer in a non-metal conducting wire region is firstly removed through photoetching and etching, then, metal insulation media are deposited, a metal conducting wire groove is photoetched and etched again, in addition, the rest metal layer etching blocking layer at the lower part of the metal conducting wire groove is removed, and finally, the copper interconnecting process without the metal layer etching blocking layer is realized.
Description
Technical field
The present invention relates to a kind of metal interconnected technique, particularly relate to a kind of copper subsequent interconnection technique without metal barrier.
Background technology
Along with the continuous progress of integrated circuit fabrication process, the volume of semiconductor device is just becoming more and more less, they be coupled together also more difficult.In in the past 30 years, semi-conductor industry circle is all the material using aluminium as interface unit, but reducing along with chip, industrial quarters needs thinner, thinner connection, and the high-ohmic of aluminium is also more and more difficult to meet demand.And when high density ultra large scale integrated circuit, high resistance easily causes electronics that " wire jumper " occurs, and causes neighbouring device to produce the on off state of mistake.That is, may produce using aluminium as the chip of wire cannot with the function situation predicted, Simultaneous Stabilization is also poor.On so trickle circuit, the signal transmission speed of copper is faster and more stable than aluminium.
The metal connecting line of traditional integrated circuit is with the etching mode of metal level to make plain conductor, then carries out the filling of dielectric layer, the chemico-mechanical polishing of dielectric layer, repeats above-mentioned operation, and then successfully carry out multiple layer metal superposition.But when the material of plain conductor converts the lower copper of resistance aluminium to by aluminium time, because the dry quarter of copper is comparatively difficult, therefore new embedding technique is concerning just very necessary the processing procedure of copper.
Embedding technique is also called Damascus technics, and this technology etches metallic channel first on the dielectric layer, and then fills metal, then carries out metal machinery polishing to metal, repeats above-mentioned operation, and then successfully carries out multiple layer metal superposition.The main feature of embedding technique is the etching technics not needing to carry out metal level, and this is very important to the promotion and application of process for copper.
Ic manufacturing technology has striden into the epoch of 130nm.Current most thin copper film are in 180 to 130nm operation stage, and the logical circuit production line of about 40% can use thin copper film technique.Arrive 90nm operation stage, then have the semiconductor production line of 90% to adopt thin copper film technique.Damascus mosaic technology of employing Cu-CMP is current unique ripe copper patterning process with being successfully applied in IC manufacture.
The computing formula of multilayer interconnection electric capacity:
(formula 1)
Wherein, k is dielectric constant; L is metal guide line length; T is the plain conductor degree of depth; W is plain conductor width;
for permittivity of vacuum, from formula 1, dielectric constant is lower, and electric capacity is less.
Multilayer interconnection resistance-capacitance time Delay computing formula:
(formula 2)
Wherein, (k is dielectric constant; L is metal guide line length; T is the plain conductor degree of depth; W is plain conductor width;
for permittivity of vacuum;
for metallic resistance rate) from formula 2, dielectric constant is lower, and resistivity is little, and multilayer interconnection resistance-capacitance time postpones also shorter.
Metal level dielectric and metal level etching barrier layer is depended on by the integral capacitor of the visible device of formula.Usual metal level etching barrier layer is the material such as silicon nitride or carborundum, damages underlying components or metal when they can provide higher etching selection ratio to prevent plain conductor groove etched.But these materials are because its dielectric constant is far above metal level dielectric, and then overall capacitance values is caused to rise.
Summary of the invention
The invention discloses a kind of copper subsequent interconnection technique without metal barrier, carry out remaining owing to there is metal level etching barrier layer the integral capacitor rising caused in metal connecting line process in order to solve in prior art, and then the problem causing the capacitance delays time long.
Above-mentioned purpose of the present invention is achieved through the following technical solutions:
Without a copper subsequent interconnection technique for metal barrier, in a substrate, be formed with the source/drain doped region of MOS (metal-oxide-semiconductor) memory, substrate is formed the grid of MOS (metal-oxide-semiconductor) memory; One contact hole etching barrier layer covers substrate and is arranged on the grid on substrate, and the top on contact hole etching barrier layer is also coated with one deck contact hole insulating oxide layer film, and form the multiple through holes running through contact hole insulating oxide layer film and contact hole etching barrier layer, partial through holes contact grid, partial through holes contact source/drain doped region, and be also filled with metal material in through hole; Deposit one metal level etching barrier layer on contact hole insulating oxide layer film, wherein, comprises the following steps:
Step a: etch metal level etching barrier layer, only retains the residual region being positioned at the metal level etching barrier layer contacted above through hole and with through hole, and remaining metal level etching barrier layer etching is removed;
Step b: deposit one metallic channel insulating barrier and a hard mask layer on contact hole insulating oxide layer film, metallic channel insulating barrier covers the top of the residual region of metal level etching barrier layer simultaneously, and deposit one hard mask layer covers on metallic channel insulating barrier more afterwards;
Step c: form the opening in hard mask layer, and utilize the opening in hard mask layer to etch metallic channel insulating barrier, the metallic channel insulating barrier above the residual region of metal level etching barrier layer is etched away, to form metallic channel in metallic channel insulating barrier; Steps d: etching removes residual metal level etching barrier layer, to be filled with the through hole of metal material in the bottom-exposed of metallic channel, depositing metal copper in metallic channel more afterwards;
Step e: carry out copper metal machinery glossing, removes the hard mask on metallic channel insulating barrier.
Copper subsequent interconnection technique without metal barrier as above, wherein, also comprises before step a: spin coating photoresist on metal level etching barrier layer, and carries out photoetching.
Copper subsequent interconnection technique without metal barrier as above, wherein, also comprises before step c: spin coating photoresist on hard mask layer, and photoetching forms metallic channel figure.
Copper subsequent interconnection technique without metal barrier as above, wherein, is also deposited with one deck contact hole etching barrier layer between contact hole insulating oxide layer film and substrate.
Copper subsequent interconnection technique without metal barrier as above, wherein, by passing contact hole insulating oxide.
Copper subsequent interconnection technique without metal barrier as above, wherein, is formed with device side wall in the side of transistor gate.
In sum, owing to have employed technique scheme, the present invention to solve in prior art in metal connecting line process without the copper subsequent interconnection technique of metal barrier and remains the integral capacitor caused rise owing to there is metal level etching barrier layer, and then the problem causing the capacitance delays time long, after deposited metal etching barrier layer, rely on photoetching, first etching removes the excess metal layer etching barrier layer of nonmetal conductor area, depositing metal dielectric subsequently, photoetching again, etching metallic channel, and remove the residual metallic layer etching barrier layer being placed in metallic channel bottom, the final copper wiring technique realized without metal level etching barrier layer.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more obvious.
Fig. 1 is that the present invention is without the cross-sectional device views after the rear road metal etch barrier deposit of the copper subsequent interconnection technique of metal barrier;
Fig. 2 is the present invention without the cutaway view after the photoetching completing metal etch barrier of the copper subsequent interconnection technique of metal barrier, etching;
Fig. 3 is the cutaway view that complete metallic channel insulating material and hard mask deposition after of the present invention without the copper subsequent interconnection technique of metal barrier;
Fig. 4 be the present invention without the copper subsequent interconnection technique of metal barrier complete plain conductor groove etched after cutaway view;
Fig. 5 removing metal level etching barrier layer and completing the cutaway view of metal level metallic copper plating without the copper subsequent interconnection technique of metal barrier that be the present invention;
Fig. 6 is that the present invention removes the cutaway view after surface hard mask without the copper metal machinery polishing that completes of the copper subsequent interconnection technique of metal barrier.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Fig. 1 is that the present invention is without the cross-sectional device views after the rear road metal etch barrier deposit of the copper subsequent interconnection technique of metal barrier, refer to Fig. 1, a kind of copper subsequent interconnection technique without metal barrier, in a substrate 10, be formed with the source/drain doped region of MOS (metal-oxide-semiconductor) memory, be formed with the grid 20 of MOS (metal-oxide-semiconductor) memory over the substrate 10; One contact hole etching barrier layer 30 covers substrate 10 and arranges on grid 20 over the substrate 10, and the top on contact hole etching barrier layer 30 is also coated with one deck contact hole insulating oxide layer film 40, and form the multiple through holes running through contact hole insulating oxide layer film 40 and contact hole etching barrier layer 30, partial through holes contact grid 20, partial through holes contact source/drain doped region, and be also filled with metal material in through hole 401; Deposit one metal level etching barrier layer 50 on contact hole insulating oxide layer film 40, wherein, comprises the following steps:
Fig. 2 is the present invention without the cutaway view after the photoetching completing metal etch barrier of the copper subsequent interconnection technique of metal barrier, etching, refer to Fig. 2, step a: metal level etching barrier layer 50 is etched, only retain the residual region being positioned at the metal level etching barrier layer 50 contacted above through hole 401 and with through hole 401, remaining metal level etching barrier layer 50 etching is removed, and the upper end open of through hole 401 is blocked by metal level etching barrier layer 50 that it retains completely;
Further, also comprise before step a: spin coating photoresist on metal level etching barrier layer 50, and carry out photoetching, form etched features, and, after step a, need photoresist to remove.
Fig. 3 is the cutaway view that complete metallic channel insulating material and hard mask deposition after of the present invention without the copper subsequent interconnection technique of metal barrier, refer to Fig. 3, step b: deposit one metallic channel insulating barrier 60 and a hard mask layer 70 successively from down to up on contact hole insulating oxide layer film 40, residual metal level etching barrier layer 50 covers by metallic channel insulating barrier 60 and hard mask layer 70 simultaneously, that is, metallic channel insulating barrier 60 covers the top of the residual region of metal level etching barrier layer 50 simultaneously, deposit one hard mask layer 70 covers on metallic channel insulating barrier 60 more afterwards,
Fig. 4 be the present invention without the copper subsequent interconnection technique of metal barrier complete plain conductor groove etched after cutaway view, refer to Fig. 4, step c: form the opening in hard mask layer 70, and utilize the opening in hard mask layer 70 to etch metallic channel insulating barrier 60, metallic channel insulating barrier 60 above the residual region of metal level etching barrier layer 50 is etched away, to form metallic channel in metallic channel insulating barrier 60;
Further, also comprise before step c: spin coating photoresist on hard mask layer 70, photoetching forms metallic channel figure.
Fig. 5 removing metal level etching barrier layer and completing the cutaway view of metal level metallic copper plating without the copper subsequent interconnection technique of metal barrier that be the present invention, refer to Fig. 5, steps d: etching removes residual metal level etching barrier layer 50, the through hole 401 of metal material is filled with, afterwards depositing metal copper 80 in metallic channel again with the bottom-exposed of metallic channel; The photoresist of spin coating before step c is removed after removing residual metal level etching barrier layer 50 by etching, and after above-mentioned processing step, metal level etching barrier layer 50 is completely removed, thus achieves the copper subsequent interconnection technique without metal level etching barrier layer 50.
Fig. 6 is that the present invention removes the cutaway view after surface hard mask without the copper metal machinery polishing that completes of the copper subsequent interconnection technique of metal barrier, refer to Fig. 6, after steps d, also comprise step e: carry out copper metal machinery glossing, the hard mask on metallic channel insulating barrier 60 is removed.
Between contact hole insulating oxide layer film 40 and substrate 10, one deck contact hole etching barrier layer 30 is also deposited with, by passing contact hole insulating oxide in the present invention.
Device side wall 201 is formed with in the side of transistor gate 20 in the present invention.
In sum, owing to have employed technique scheme, the present invention to solve in prior art in metal connecting line process without the copper subsequent interconnection technique of metal barrier and remains the integral capacitor caused rise owing to there is metal level etching barrier layer, and then the problem causing the capacitance delays time long, after deposited metal etching barrier layer, rely on photoetching, first etching removes the excess metal layer etching barrier layer of nonmetal conductor area, depositing metal dielectric subsequently, photoetching again, etching metallic channel, and remove the residual metallic layer etching barrier layer being placed in metallic channel bottom, the final copper wiring technique realized without metal level etching barrier layer.
It should be appreciated by those skilled in the art that those skilled in the art can realize described change case in conjunction with prior art and above-described embodiment, do not repeat them here.Such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned particular implementation, any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (4)
1., without a copper subsequent interconnection technique for metal barrier, in a substrate, be formed with the source/drain doped region of MOS (metal-oxide-semiconductor) memory, substrate is formed the grid of MOS (metal-oxide-semiconductor) memory; One contact hole etching barrier layer covers substrate and is arranged on the grid on substrate, and the top on contact hole etching barrier layer is also coated with one deck contact hole insulating oxide layer film, and form the multiple through holes running through contact hole insulating oxide layer film and contact hole etching barrier layer, partial through holes contact grid, partial through holes contact source/drain doped region, and be also filled with metal material in through hole; Deposit one metal level etching barrier layer on contact hole insulating oxide layer film, is characterized in that, comprise the following steps:
Step a: etch metal level etching barrier layer, only retains the residual region being positioned at the metal level etching barrier layer contacted above through hole and with through hole, and remaining metal level etching barrier layer etching is removed;
Step b: deposit one metallic channel insulating barrier and a hard mask layer on contact hole insulating oxide layer film, metallic channel insulating barrier covers the top of the residual region of metal level etching barrier layer simultaneously, and deposit one hard mask layer covers on metallic channel insulating barrier more afterwards;
Step c: form the opening in hard mask layer, and utilize the opening in hard mask layer to etch metallic channel insulating barrier, the metallic channel insulating barrier above the residual region of metal level etching barrier layer is etched away, to form metallic channel in metallic channel insulating barrier; Steps d: etching removes residual metal level etching barrier layer, to be filled with the through hole of metal material in the bottom-exposed of metallic channel, depositing metal copper in metallic channel more afterwards;
Step e: carry out copper metal machinery glossing, removes the hard mask on metallic channel insulating barrier;
Wherein, described metal level etching barrier layer has higher etching selection ratio relative to described metallic channel insulating barrier, and the dielectric constant of this metal level etching barrier layer is greater than the dielectric constant of described metallic channel insulating barrier.
2. the copper subsequent interconnection technique without metal barrier according to claim 1, is characterized in that, also comprise before step a: spin coating photoresist on metal level etching barrier layer, and carry out photoetching.
3. the copper subsequent interconnection technique without metal barrier according to claim 1, is characterized in that, also comprise before step c: spin coating photoresist on hard mask layer, and photoetching forms metallic channel figure.
4. the copper subsequent interconnection technique without metal barrier according to claim 1, is characterized in that, be formed with device side wall in the side of transistor gate.
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| CN201110194242.5A CN102437090B (en) | 2011-07-12 | 2011-07-12 | Copper back channel interconnecting process without metal blocking layer |
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| CN201110194242.5A CN102437090B (en) | 2011-07-12 | 2011-07-12 | Copper back channel interconnecting process without metal blocking layer |
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| US9461143B2 (en) * | 2012-09-19 | 2016-10-04 | Intel Corporation | Gate contact structure over active gate and method to fabricate same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5854124A (en) * | 1997-02-04 | 1998-12-29 | Winbond Electronics Corp. | Method for opening contacts of different depths in a semiconductor wafer |
| US6380084B1 (en) * | 2000-10-02 | 2002-04-30 | Chartered Semiconductor Manufacturing Inc. | Method to form high performance copper damascene interconnects by de-coupling via and metal line filling |
| CN1893020A (en) * | 2005-07-06 | 2007-01-10 | 株式会社瑞萨科技 | Semiconductor device and a method of manufacturing the same |
| CN101202244A (en) * | 2006-12-15 | 2008-06-18 | 中芯国际集成电路制造(上海)有限公司 | Method for removing photoresist graphical in forming process of dual embedded structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6770570B2 (en) * | 2002-11-15 | 2004-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a semiconductor device with a substantially uniform density low-k dielectric layer |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5854124A (en) * | 1997-02-04 | 1998-12-29 | Winbond Electronics Corp. | Method for opening contacts of different depths in a semiconductor wafer |
| US6380084B1 (en) * | 2000-10-02 | 2002-04-30 | Chartered Semiconductor Manufacturing Inc. | Method to form high performance copper damascene interconnects by de-coupling via and metal line filling |
| CN1893020A (en) * | 2005-07-06 | 2007-01-10 | 株式会社瑞萨科技 | Semiconductor device and a method of manufacturing the same |
| CN101202244A (en) * | 2006-12-15 | 2008-06-18 | 中芯国际集成电路制造(上海)有限公司 | Method for removing photoresist graphical in forming process of dual embedded structure |
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