CN102569176A - Method for preparing dual Damascene structure - Google Patents
Method for preparing dual Damascene structure Download PDFInfo
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- CN102569176A CN102569176A CN201210014790XA CN201210014790A CN102569176A CN 102569176 A CN102569176 A CN 102569176A CN 201210014790X A CN201210014790X A CN 201210014790XA CN 201210014790 A CN201210014790 A CN 201210014790A CN 102569176 A CN102569176 A CN 102569176A
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Abstract
The invention provides a method for preparing a dual Damascene structure. The method comprises the following steps of: sequentially forming an etching barrier layer, a medium layer and a first metal hard mask on a semiconductor substrate; etching the substrate to open the first metal hard mask until a part of the medium layer is removed to form a ditch; depositing a second metal hard mask; etching the substrate to open the second metal hard mask until the medium layer and the etching barrier layer are removed to form a through hole; and filling metal into the ditch and the through hole. According to the method, the metal hard masks are adopted, so the sizes of the ditch and the through hole can be well controlled, leakage current is reduced, and the electric performance and the reliability are obviously improved.
Description
Technical field
The present invention relates to a kind of method for preparing Damascus, relate in particular to a kind of method for preparing double damask structure.
Background technology
Along with the continuous development of ic manufacturing technology, the characteristic size of semiconductor chip is constantly dwindled; Simultaneously, along with the number of transistors in the chip constantly increases, function is more and more stronger, and the metal connecting line of chip is in more and more thinner, and level is more and more.This just makes by resistance-capacitance (Rc) delay of dielectric layer electric capacity generation between connection resistances and line increasing to the influence of chip speed, very strives to have surpassed the brilliant grid delay of stopping the speed of pipe own of decision.Therefore manage to reduce connection resistances and reduce electric capacity between line, become the key of further raising chip speed.
In order to solve the problem that resistance-capacitance postpones (Rc delay); The measure of taking in the industry is: the dielectric materials (dielectric constant is less than 3.0) that meets IC technology is used in (1); Make the permittivity ratio silicon of the dielectric layer between the multi-metal intra-connection lower, thereby reduce parasitic capacitance; (2) adopt copper to replace aluminium, reduce resistance as partly leading the electric conducting material of stopping interconnection line in the element; Compare with aluminium, the resistance coefficient of copper is little, and fusing point is high, and anti-electromigration ability is strong, and can carry higher current density, and because copper can be done carefullyyer, therefore adopts copper wiring can also reduce electric capacity and power consumption, can improve the packaging density of element simultaneously.
Because copper is difficult to be etched, the lithographic technique that therefore is used to form the aluminum metal wiring traditionally is inapplicable for copper.For this reason, a kind of new wire laying mode that is called as dual damascene (Dual Damascene) structure is sent by liter.So-called double damask structure technology is meant: in dielectric layer, leave earlier interconnection channel and through hole, then through electroplating or electroless copper cement copper in interconnection channel and through hole, utilize chemico-mechanical polishing (CMP) to grind off crossing the copper of filling out again.
The common method of making double damask structure generally has following several kinds: 1, all-pass hole precedence method (Full VIA First); 2, half via-first method (Partial VIA First); 3, plain conductor precedence method (Full Trench First); 4, self aligned approach (self-alignment) etc.
Above-mentioned several method all exists advantage and deficiency separately, and especially for advanced person's back segment copper wiring, along with size is more and more littler, the control of critical size (CD) becomes key.In addition, the requirement of electric property such as leakage current (leakage current), and reliability also becomes challenging problem gradually; Existing method is having limitation aspect the control via CD, and the space between the via to via is very little, causes one of electrical parameter, and the leakage current between the via to via is very big, even can connect together between the via, influences the reliability of copper-connection;
Therefore, those skilled in the art is devoted to develop a kind of the improvement electrically and the method for preparing double damask structure of reliability.
Summary of the invention
In view of above-mentioned the problems of the prior art, technical problem to be solved by this invention is existing.
A kind of method for preparing double damask structure provided by the invention may further comprise the steps:
Step 1 forms etching barrier layer, dielectric layer and first metal hard mask successively on Semiconductor substrate;
In a preferred embodiments of the present invention, said step 7 comprises:
Bottom and side-walls growing metal barrier layer and copper seed layer at said groove and through hole;
In said groove and through hole, form interconnect materials; And
Utilize CMP process to remove the interconnect materials on the said dielectric layer, stay the interconnect materials in said groove and the through hole.
In another preferred embodiments of the present invention, the material of the metal barrier in the said step 7 is TaN or Ta.
In another preferred embodiments of the present invention, said step 1 is included in and forms etching barrier layer, dielectric layer, dielectric layer protective layer and first metal hard mask on the Semiconductor substrate successively.
In another preferred embodiments of the present invention, under second photoresist, also apply bottom antireflective coating in the said step 5; Also comprise in the step 6 and remove said bottom antireflective coating.
In another preferred embodiments of the present invention, said dielectric layer is a low dielectric coefficient medium layer.
In another preferred embodiments of the present invention, the material of said dielectric layer is a silsesquioxane.
In another preferred embodiments of the present invention, the material of said etching barrier layer is silicon nitride or carborundum.
In another preferred embodiments of the present invention, the material of said first metal hard mask is TiN or TaN.
In another preferred embodiments of the present invention, the material of the said second hard mask is TaN, Ta, TiN or Ti.
The method for preparing dual damascene of the present invention has been used the hard mask of bimetallic, therefore can well control the size of groove and through hole, thereby reduce leakage current, and electric property and reliability significantly improve.
Description of drawings
Fig. 1 is the sketch map of the double damask structure in the step 1 of embodiments of the invention;
Fig. 2 is the sketch map of the double damask structure in the step 2 of embodiments of the invention;
Fig. 3 is the sketch map of the double damask structure in the step 3 of embodiments of the invention;
Fig. 4 is the sketch map of the double damask structure in the step 4 of embodiments of the invention;
Fig. 5 is the sketch map of the double damask structure in the step 5 of embodiments of the invention;
Fig. 6 is the sketch map of the double damask structure in the step 6 of embodiments of the invention;
Fig. 7 is the sketch map of the double damask structure in the step 7 of embodiments of the invention;
Fig. 8 is the sketch map of the double damask structure of embodiments of the invention formation.
Embodiment
Below will combine accompanying drawing that the present invention is done concrete explaination.
The method for preparing double damask structure of embodiments of the invention may further comprise the steps:
Step 1, as shown in fig. 1, on Semiconductor substrate 1, form etching barrier layer 2, dielectric layer 3, dielectric layer protective layer 4 and first metal hard mask 5 successively; Preferably, the material of etching barrier layer is silicon nitride or carborundum; The material of first metal hard mask is TiN or TaN.
In said groove and through hole, form interconnect materials 12; And
As shown in Figure 8, utilize CMP process to remove the interconnect materials on the said dielectric layer, stay the interconnect materials 12 in said groove and the through hole.
The method for preparing double damask structure of the present invention has been used the hard mask of bimetallic, therefore can well control the size of groove and through hole, thereby reduce leakage current, and electric property and reliability significantly improve.
In an embodiment of the present invention, dielectric layer is a low dielectric coefficient medium layer.Preferred material is a silsesquioxane.
In an embodiment of the present invention, can adopt the chemical gas-phase method deposition to form etching barrier layer, dielectric layer, dielectric layer protective layer; Adopt chemical gas-phase method or physical vapor method to deposit first metal hard mask or second metal hard mask.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (10)
1. a method for preparing double damask structure is characterized in that, may further comprise the steps:
Step 1 forms etching barrier layer, dielectric layer and first metal hard mask successively on Semiconductor substrate;
Step 2, spin coating first photoresist on first metal hard mask, and photoetching forms first photoengraving pattern;
Step 3, etching are opened first metal hard mask and until removing the part dielectric layer to form groove, are removed first photoresist;
Step 4, deposit second metal hard mask;
Step 5, spin coating second photoresist on said second metal hard mask, and photoetching forms second photoengraving pattern;
Step 6, etching are opened second metal hard mask and until removing dielectric layer and etching barrier layer with the formation through hole, and remove second photoresist;
Step 7 is filled metal in said groove and through hole.
2. the method for preparing double damask structure as claimed in claim 1 is characterized in that, said step 7 comprises:
Bottom and side-walls growing metal barrier layer and copper seed layer at said groove and through hole;
In said groove and through hole, form interconnect materials; And
Utilize CMP process to remove the interconnect materials on the said dielectric layer, stay the interconnect materials in said groove and the through hole.
3. the method for preparing double damask structure as claimed in claim 2 is characterized in that, the material of the metal barrier in the said step 7 is TaN or Ta.
4. the method for preparing double damask structure as claimed in claim 1 is characterized in that, said step 1 is included in and forms etching barrier layer, dielectric layer, dielectric layer protective layer and first metal hard mask on the Semiconductor substrate successively.
5. the method for preparing double damask structure as claimed in claim 1 is characterized in that, under second photoresist, also applies bottom antireflective coating in the said step 5; Also comprise in the step 6 and remove said bottom antireflective coating.
6. the method for preparing double damask structure as claimed in claim 1 is characterized in that, said dielectric layer is a low dielectric coefficient medium layer.
7. the method for preparing double damask structure as claimed in claim 6 is characterized in that, the material of said dielectric layer is a silsesquioxane.
8. the method for preparing double damask structure as claimed in claim 1 is characterized in that, the material of said etching barrier layer is silicon nitride or carborundum.
9. the method for preparing double damask structure as claimed in claim 1 is characterized in that, the material of said first metal hard mask is TiN or TaN.
10. the method for preparing double damask structure as claimed in claim 1 is characterized in that, the material of the said second hard mask is TaN, Ta, TiN or Ti.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210014790XA CN102569176A (en) | 2012-01-18 | 2012-01-18 | Method for preparing dual Damascene structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210014790XA CN102569176A (en) | 2012-01-18 | 2012-01-18 | Method for preparing dual Damascene structure |
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| CN102569176A true CN102569176A (en) | 2012-07-11 |
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| CN201210014790XA Pending CN102569176A (en) | 2012-01-18 | 2012-01-18 | Method for preparing dual Damascene structure |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066088A (en) * | 2012-12-21 | 2013-04-24 | 豪威科技(上海)有限公司 | Manufacturing method of backside illuminated complementary metal-oxide-semiconductor transistor (CMOS) image sensor |
| CN103681463B (en) * | 2012-09-12 | 2016-12-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of preparation method of double damask structure |
| CN109755108A (en) * | 2017-11-07 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of semiconductor devices |
| CN110660778A (en) * | 2018-06-28 | 2020-01-07 | 台湾积体电路制造股份有限公司 | Semiconductor structure and forming method thereof |
| CN110890315A (en) * | 2018-09-07 | 2020-03-17 | 长鑫存储技术有限公司 | Semiconductor structure with Damascus structure and preparation method thereof |
| CN115020225A (en) * | 2022-08-08 | 2022-09-06 | 广州粤芯半导体技术有限公司 | Method and device for integrally etching metal hard mask |
| US11532511B2 (en) | 2018-06-28 | 2022-12-20 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for forming semiconductor structure |
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| US6017817A (en) * | 1999-05-10 | 2000-01-25 | United Microelectronics Corp. | Method of fabricating dual damascene |
| US6211061B1 (en) * | 1999-10-29 | 2001-04-03 | Taiwan Semiconductor Manufactuirng Company | Dual damascene process for carbon-based low-K materials |
| CN1493087A (en) * | 2000-12-26 | 2004-04-28 | ����Τ�����ʹ�˾ | Method for eliminating reaction between photoresist and organosilicate glass (OSG) |
| CN102082114A (en) * | 2009-12-01 | 2011-06-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of dual damascene structure |
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2012
- 2012-01-18 CN CN201210014790XA patent/CN102569176A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6017817A (en) * | 1999-05-10 | 2000-01-25 | United Microelectronics Corp. | Method of fabricating dual damascene |
| US6211061B1 (en) * | 1999-10-29 | 2001-04-03 | Taiwan Semiconductor Manufactuirng Company | Dual damascene process for carbon-based low-K materials |
| CN1493087A (en) * | 2000-12-26 | 2004-04-28 | ����Τ�����ʹ�˾ | Method for eliminating reaction between photoresist and organosilicate glass (OSG) |
| CN102082114A (en) * | 2009-12-01 | 2011-06-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of dual damascene structure |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681463B (en) * | 2012-09-12 | 2016-12-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of preparation method of double damask structure |
| CN103066088A (en) * | 2012-12-21 | 2013-04-24 | 豪威科技(上海)有限公司 | Manufacturing method of backside illuminated complementary metal-oxide-semiconductor transistor (CMOS) image sensor |
| CN103066088B (en) * | 2012-12-21 | 2015-08-19 | 豪威科技(上海)有限公司 | The manufacture method of back-illuminated type CMOS |
| CN109755108A (en) * | 2017-11-07 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of semiconductor devices |
| CN109755108B (en) * | 2017-11-07 | 2021-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN110660778A (en) * | 2018-06-28 | 2020-01-07 | 台湾积体电路制造股份有限公司 | Semiconductor structure and forming method thereof |
| US11532511B2 (en) | 2018-06-28 | 2022-12-20 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for forming semiconductor structure |
| CN110890315A (en) * | 2018-09-07 | 2020-03-17 | 长鑫存储技术有限公司 | Semiconductor structure with Damascus structure and preparation method thereof |
| CN115020225A (en) * | 2022-08-08 | 2022-09-06 | 广州粤芯半导体技术有限公司 | Method and device for integrally etching metal hard mask |
| CN115020225B (en) * | 2022-08-08 | 2022-12-13 | 广州粤芯半导体技术有限公司 | Method and device for integrally etching metal hard mask |
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Application publication date: 20120711 |