CN102082118A - Method for producing dual-damascene structure - Google Patents
Method for producing dual-damascene structure Download PDFInfo
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- CN102082118A CN102082118A CN2010102972419A CN201010297241A CN102082118A CN 102082118 A CN102082118 A CN 102082118A CN 2010102972419 A CN2010102972419 A CN 2010102972419A CN 201010297241 A CN201010297241 A CN 201010297241A CN 102082118 A CN102082118 A CN 102082118A
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Abstract
The invention discloses a method for producing a dual-damascene structure, which comprises the following steps of: providing a semiconductor substrate; forming an etching barrier layer and a graphic photoresist layer on the semiconductor substrate in sequence, wherein the graphic photoresist defines a through-hole structure; forming a medium layer covering the etching barrier layer and the graphic photoresist layer; photoetching and etching on the medium layer until the graphic photoresist layer is exposed so as to form a groove; removing the graphic photoresist layer and the etching barrier layer under the graphic photoresist layer to form a through hole which is communicated with the groove; and filling metals into the through hole and the groove. With the method for producing the dual-damascene structure, the steps of through-hole filling and etching in the traditional dual-damascene technique are greatly simplified.
Description
Technical field
The present invention relates to technical field of semiconductor device, relate in particular to a kind of method for preparing double damask structure.
Background technology
Along with the continuous development of ic manufacturing technology, the characteristic size of semiconductor chip is constantly dwindled; Simultaneously, along with the number of transistors in the chip constantly increases, function is more and more stronger, and the metal connecting line of chip is in more and more thinner, and level is more and more.This just makes by resistance-capacitance (RC) delay of dielectric layer electric capacity generation between connection resistances and line increasing to the influence of chip speed, even has surpassed the grid delay of the speed of decision transistor own.Therefore manage to reduce connection resistances and reduce electric capacity between line, become the key of further raising chip speed.
In order to solve the problem that resistance-capacitance postpones (RC delay), the measure of taking in the industry is: (1) uses the dielectric materials (dielectric constant is less than 3.0) that meets IC technology, make the permittivity ratio silicon of the dielectric layer between the multi-metal intra-connection lower, thereby reduce parasitic capacitance; (2) adopt copper to replace the electric conducting material of aluminium, reduce resistance as interconnection line in the semiconductor element; Compare with aluminium, the resistance coefficient of copper is little, the fusing point height, and anti-electromigration ability is strong, and can carry higher current density, and because copper can be done carefullyyer, therefore adopts copper wiring can also reduce electric capacity and power consumption, can improve the packaging density of element simultaneously.
Because copper is difficult to be etched, the lithographic technique that therefore is used to form the aluminum metal wiring traditionally is inapplicable for copper.For this reason, a kind of new wire laying mode that is called as dual damascene (Dual Damascene) structure is developed.So-called double damask structure technology is meant: leave earlier interconnection channel and through hole in dielectric layer, then by electroplating or electroless copper cement copper in interconnection channel and through hole, utilize chemico-mechanical polishing (CMP) to grind off crossing the copper of filling out again.
The common method of making double damask structure generally has following several: 1, all-pass hole precedence method (Full VIA First); 2, half via-first method (Partial VIA First); 3, plain conductor precedence method (Full Trench First); 4, self aligned approach (self-alignment) etc.
Above-mentioned several method all exists advantage and deficiency separately, assessed improve after, at present, all-pass hole precedence method (Full VIA First) is most widely used in industrial quarters.Preferential (the Full VIA First) technology in all-pass hole is insensitive to the alignment problem of groove, therefore be difficult for causing through hole to lose efficacy, process window is bigger, but on the step that through hole is filled, the inhomogeneous bad reaction that must cause post-order process is filled or filled to the through hole of failure, even failure, and conventional filling reagent and subsequent optical carving technology use number of different types chemical substance, technology is loaded down with trivial details, and road, back etching technics complexity.In a word, the through hole that traditional dual damascene process relates to is filled and etch step, complex process and various.
Summary of the invention
The object of the present invention is to provide a kind of method for preparing double damask structure, to solve the problem that existing dual damascene process faces on through hole filling and etching.
For addressing the above problem, the present invention proposes a kind of method for preparing double damask structure, and this method comprises the steps: to provide Semiconductor substrate; Form etching barrier layer and patterned photoresist layer on described Semiconductor substrate successively, described patterned photoresist layer has defined through-hole structure; Form the dielectric layer that covers described etching barrier layer and described patterned photoresist layer; The described dielectric layer of photoetching and etching is to exposing described patterned photoresist layer, to form groove; Remove the etching barrier layer of described patterned photoresist layer and described patterned photoresist layer below, to form the through hole that is communicated with described groove; In described through hole and groove, fill metal.
Optionally, described dielectric layer utilizes the spin coating mode to form.
Optionally, to the step that exposes described patterned photoresist layer, also comprise: toast described Semiconductor substrate, so that the reaction of described dielectric layer generation heat cross-linking at the described dielectric layer of etching.
Optionally, the step of filling metal comprises in described through hole and groove: at bottom and the side-walls growing metal barrier layer and the adhesion layer of described through hole and groove; On described dielectric layer and in described through hole and the groove, form interconnect materials; And utilize CMP (Chemical Mechanical Polishing) process to remove interconnect materials on the described dielectric layer, the metal in remaining described through hole and the groove.
Optionally, forming interconnect materials on described dielectric layer and in through hole and the groove realizes by physical vapour deposition (PVD) and electrochemistry depositing process.
Optionally, between described Semiconductor substrate and described etching barrier layer, be formed with the substrate dielectric layer.
Optionally, the material of described substrate dielectric layer is a silicon dioxide.
Optionally, described dielectric layer is a low dielectric coefficient medium layer.
Optionally, the material of described dielectric layer is the organic polymer that contains silicon.
Optionally, the described material that contains the organic polymer of silicon is a silsesquioxane.
Optionally, the described dielectric layer of dry etching is to exposing described patterned photoresist layer to form described groove.
Optionally, the material of described etching barrier layer is silicon nitride or carborundum.
Optionally, dry etching is removed the etching barrier layer of described patterned photoresist layer and patterned photoresist layer below.
Compared with prior art, the method for preparing double damask structure provided by the invention forms the dielectric layer that covers described etching barrier layer and patterned photoresist layer earlier, the described dielectric layer of etching is to exposing described patterned photoresist layer to form groove afterwards, again by removing the etching barrier layer of described patterned photoresist layer and described patterned photoresist layer below, form the through hole that is communicated with described groove, thereby simplified the processing step in traditional double Damascus.
In addition, utilize the spin coating mode to form described dielectric layer,, avoided that the dielectric layer air spots is smooth to have a negative impact to postchannel process because the flowability that the material of dielectric layer has makes the planarization dielectric layer of formation preferable.
In addition, adopt the dielectric layer of low-k to effectively reduce the parasitic capacitance of intraconnections, thereby reduce the RC delay, and alleviate the interference between the intraconnections, and then improve the speed of the operation of device.
Description of drawings
The method step flow chart of the preparation double damask structure that Fig. 1 provides for the embodiment of the invention;
The cross-sectional view of the device of each step correspondence in the method for preparing double damask structure that Fig. 2 A to Fig. 2 G provides for the embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments the method for preparing double damask structure that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only be used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is, a kind of method for preparing double damask structure is provided, this method forms the dielectric layer that covers described etching barrier layer and patterned photoresist layer earlier, the described dielectric layer of photoetching afterwards and etching is to exposing described patterned photoresist layer to form groove, again by removing the etching barrier layer of described patterned photoresist layer and described patterned photoresist layer below, forming the through hole be communicated with described groove, thereby simplified the processing step in traditional double Damascus.
Please refer to Fig. 1, the method step flow chart of the preparation double damask structure that it provides for the embodiment of the invention, in conjunction with this Fig. 1, this method may further comprise the steps:
Step S101 provides Semiconductor substrate;
Step S102 forms etching barrier layer and patterned photoresist layer successively on Semiconductor substrate, described patterned photoresist layer has defined through-hole structure;
Step S103 forms the dielectric layer that covers described etching barrier layer and patterned photoresist layer;
Step S104, the described dielectric layer of photoetching and etching is to exposing described patterned photoresist layer, to form groove;
Step S105 removes the etching barrier layer of described patterned photoresist layer and described patterned photoresist layer below, forms the through hole that is communicated with described groove;
Step S106 fills metal in described through hole and groove.
Below in conjunction with generalized section the method for preparing double damask structure of the present invention is described in more detail, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.
Shown in Fig. 2 A, and integrating step S101 and step S102, at first, provide Semiconductor substrate 200.Described Semiconductor substrate 200 can be the substrate (part that comprises integrated circuit and other elements) of multi layer substrate (silicon substrate that for example, has covering dielectric and metal film), classification substrate, silicon-on-insulator substrate (SOI), epitaxial silicon substrate, section processes.
Then, form etching barrier layer 202 and patterned photoresist layer 203 successively on described Semiconductor substrate 200, described patterned photoresist layer 203 has defined the through hole 206 of follow-up formation.
Preferably, described photoresist layer 203 is realized graphical by photoetching and developing technique.Between described etching barrier layer 202 and described Semiconductor substrate 200, be formed with substrate dielectric layer (not shown), in the present embodiment, described substrate dielectric layer material adopts silicon dioxide, and wherein silicon dioxide plays the effect of regulating stress between etching barrier layer 202 and the Semiconductor substrate 200.In the present embodiment, described etching barrier layer 202 adopts silicon nitride material.
Shown in Fig. 2 B, and integrating step S103, then, spin-on dielectrics material on described etching barrier layer 202 and patterned photoresist layer 203, to form dielectric layer 204, described dielectric layer 204 covers described patterned photoresist layer 203 and etching barrier layer 202.Can utilize the spin coating mode to form described dielectric layer 204,, avoid that dielectric layer 204 air spotss are smooth to have a negative impact to post-order process because the flowability that the material of dielectric layer 204 has makes dielectric layer 204 flatness of formation preferable.
Preferable, described dielectric layer 204 is selected advanced low-k materials for use, with the parasitic capacitance of reduction intraconnections, thereby reduces the RC delay, and alleviates the interference between the intraconnections, and then improve the speed of the operation of device.Described dielectric layer 204 materials can be the organic polymers that contains silicon, and in the present embodiment, described dielectric layer 204 materials adopt silsesquioxane.
Shown in Fig. 2 C, by aiming at the photoresist figure of below, photoetching forms patterned photoresist 201 on described dielectric layer 204.
Shown in Fig. 2 D, and integrating step S104, be mask with patterned photoresist 201, adopt the described dielectric layer 204 of mode etching of dry etching, to form groove 205, described groove 205 exposes described patterned photoresist layer 203.
Shown in Fig. 2 E, and integrating step S105, subsequently, adopt dry etching to remove the etching barrier layer 202 of described patterned photoresist layer 203 and described patterned photoresist layer 203 belows successively, forming the through hole 206 be communicated with described groove 205, and remove patterned photoresist 201.It will be appreciated by persons skilled in the art that stating can be by repairing the through hole 206 that (trimming) obtains smaller szie to patterned photoresist layer 203 after forming described patterned photoresist layer 203.
Shown in Fig. 2 F and Fig. 2 G, and integrating step S106, last, in described through hole 206 and groove 205, fill metal 207.
In the present embodiment, the step of filling metal 207 specifically comprises in described through hole 206 and groove 205: at bottom and the side-walls growing metal barrier layer (not shown) and the adhesion layer (not shown) of described through hole 206 and groove 205; Form interconnect materials 208 on described dielectric layer 204 and in described through hole 206 and the groove 205; And utilize CMP (Chemical Mechanical Polishing) process to remove interconnect materials 208 on the described dielectric layer 204, stay the metal 207 of in described through hole 206 and groove 205, filling.
Optionally, forming interconnect materials 208 on described dielectric layer 204 and in described through hole 206 and the groove 205 realizes by physical vapour deposition (PVD) and electrochemistry depositing process.
Optionally, to the step that exposes described patterned photoresist layer 203, also comprise: toast described Semiconductor substrate 200, so that the heat cross-linkings reaction takes place described dielectric layer 204 at the described dielectric layer 204 of etching.
In the present embodiment, the temperature that described Semiconductor substrate 200 is toasted is 350 ℃～400 ℃, and stoving time is 2 minutes～3 minutes, in the process of toasting, the heat cross-linking reaction takes place in described dielectric layer 204, becomes solid by having mobile colloid before the reaction.
In sum, the invention provides a kind of method for preparing double damask structure, this method forms the dielectric layer 204 that covers described etching barrier layer 202 and patterned photoresist layer 203 earlier, the described dielectric layer 204 of etching is to exposing described patterned photoresist layer 203 to form groove 205 afterwards, remove the etching barrier layer 202 of described patterned photoresist layer 203 and described patterned photoresist layer 203 belows again, form the through hole 206 that is communicated with described groove 205, simplified the through hole of traditional double Damascus technics greatly and filled and etch step.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (13)
1. a method for preparing double damask structure is characterized in that, comprising:
Semiconductor substrate is provided;
Form etching barrier layer and patterned photoresist layer on described Semiconductor substrate successively, described patterned photoresist layer has defined through-hole structure;
Form the dielectric layer that covers described etching barrier layer and described patterned photoresist layer;
The described dielectric layer of photoetching and etching is to exposing described patterned photoresist layer, to form groove;
Remove the etching barrier layer of described patterned photoresist layer and described patterned photoresist layer below, to form the through hole that is communicated with described groove;
In described through hole and groove, fill metal.
2. the method for preparing double damask structure as claimed in claim 1 is characterized in that, described dielectric layer utilizes the spin coating mode to form.
3. the method for preparing double damask structure as claimed in claim 2, it is characterized in that, the described dielectric layer of etching also comprises to the step that exposes described patterned photoresist layer: toast described Semiconductor substrate, so that the reaction of described dielectric layer generation heat cross-linking.
4. the method for preparing double damask structure as claimed in claim 1 is characterized in that, the step of filling metal in described through hole and groove comprises:
Bottom and side-walls growing metal barrier layer and adhesion layer at described through hole and groove;
In described through hole and groove and on the dielectric layer, form interconnect materials; And
Utilize CMP (Chemical Mechanical Polishing) process to remove interconnect materials on the described dielectric layer, stay the metal in described through hole and the groove.
5. the method for preparing double damask structure as claimed in claim 4 is characterized in that, forms interconnect materials on described dielectric layer and in through hole and the groove and realizes by physical vapour deposition (PVD) and electrochemistry depositing process.
6. the method for preparing double damask structure as claimed in claim 1 is characterized in that, is formed with the substrate dielectric layer between described Semiconductor substrate and described etching barrier layer.
7. the method for preparing double damask structure as claimed in claim 6 is characterized in that, the material of described substrate dielectric layer is a silicon dioxide.
8. the method for preparing double damask structure as claimed in claim 1 is characterized in that, described dielectric layer is a low dielectric coefficient medium layer.
9. the method for preparing double damask structure as claimed in claim 8 is characterized in that, the material of described dielectric layer is the organic polymer that contains silicon.
10. the method for preparing double damask structure as claimed in claim 9 is characterized in that, the described material that contains the organic polymer of silicon is a silsesquioxane.
11. the method for preparing double damask structure as claimed in claim 1 is characterized in that, the described dielectric layer of dry etching is to exposing described patterned photoresist layer to form described groove.
12. the method for preparing double damask structure as claimed in claim 1 is characterized in that, the material of described etching barrier layer is silicon nitride or carborundum.
13. the method for preparing double damask structure as claimed in claim 1 is characterized in that, dry etching is removed the etching barrier layer of described patterned photoresist layer and patterned photoresist layer below.
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| CN2010102972419A CN102082118A (en) | 2010-09-29 | 2010-09-29 | Method for producing dual-damascene structure |
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| CN2010102972419A CN102082118A (en) | 2010-09-29 | 2010-09-29 | Method for producing dual-damascene structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105390435A (en) * | 2014-08-20 | 2016-03-09 | 格罗方德半导体公司 | Self-aligned back end of line cut |
| CN106054519A (en) * | 2016-07-07 | 2016-10-26 | 中国科学院深圳先进技术研究院 | Method for preparing three-dimensional microelectrode array by using photoresist |
| CN112701080A (en) * | 2019-10-22 | 2021-04-23 | 珠海格力电器股份有限公司 | Through hole forming method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20080064213A1 (en) * | 2006-09-12 | 2008-03-13 | Hynix Semiconductor Inc. | Method for forming a fine pattern of a semiconductor device |
| US20080079153A1 (en) * | 2006-09-29 | 2008-04-03 | Seong-Hee Jeong | Method for forming semiconductor device |
| CN101188209A (en) * | 2006-11-21 | 2008-05-28 | 台湾积体电路制造股份有限公司 | Semiconductor device, mosaic structure and method forming inter-connection |
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2010
- 2010-09-29 CN CN2010102972419A patent/CN102082118A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080064213A1 (en) * | 2006-09-12 | 2008-03-13 | Hynix Semiconductor Inc. | Method for forming a fine pattern of a semiconductor device |
| US20080079153A1 (en) * | 2006-09-29 | 2008-04-03 | Seong-Hee Jeong | Method for forming semiconductor device |
| CN101188209A (en) * | 2006-11-21 | 2008-05-28 | 台湾积体电路制造股份有限公司 | Semiconductor device, mosaic structure and method forming inter-connection |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105390435A (en) * | 2014-08-20 | 2016-03-09 | 格罗方德半导体公司 | Self-aligned back end of line cut |
| CN105390435B (en) * | 2014-08-20 | 2019-03-15 | 格罗方德半导体公司 | Self aligned last part technology notch |
| CN106054519A (en) * | 2016-07-07 | 2016-10-26 | 中国科学院深圳先进技术研究院 | Method for preparing three-dimensional microelectrode array by using photoresist |
| CN112701080A (en) * | 2019-10-22 | 2021-04-23 | 珠海格力电器股份有限公司 | Through hole forming method |
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Application publication date: 20110601 |