CN102364673A - Method for forming copper interconnection structure - Google Patents
Method for forming copper interconnection structure Download PDFInfo
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- CN102364673A CN102364673A CN2011103554532A CN201110355453A CN102364673A CN 102364673 A CN102364673 A CN 102364673A CN 2011103554532 A CN2011103554532 A CN 2011103554532A CN 201110355453 A CN201110355453 A CN 201110355453A CN 102364673 A CN102364673 A CN 102364673A
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Abstract
The invention relates to a method for forming a copper interconnection structure. The method comprises the following steps of: depositing a dielectric layer on a semiconductor substrate; forming a through hole and/or a groove in the dielectric layer by photoetching and etching processes; depositing a metal barrier layer at the bottom and the side wall of the through hole and/or the groove; depositing a copper seed crystal layer on the metal barrier layer, and filling metal copper into the through hole and/or the groove to ensure that the surface of the metal copper is lower than the surface of the dielectric layer, so that a copper metal layer and a copper groove on the copper metal layer are formed in the through hole and/or the groove; depositing a barrier layer capable of preventing copper from diffusing on the surface of the copper metal layer and the surface of the dielectric layer; removing the barrier layer capable of preventing the copper from diffusing on the dielectric layer by chemical and mechanical grinding methods; simultaneously, reserving the barrier layer capable of preventing the copper from diffusing on the surface of the copper metal layer. The method can be used for manufacturing a plurality of copper interconnection layers.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of formation method of copper-connection.
Background technology
Along with the semiconductor integrated technology constantly develops; The continuing of the characteristic size of semiconductor integrated circuit reduces; The density of interconnection line presents ever-increasing trend; The RC (R refers to resistance, and C refers to parasitic capacitance) that resistance that these metal interconnecting wires produce and parasitic capacitance are brought postpones can compare with the device gate delay time, becomes the principal element of limit ic speed.
Postpone in order to reduce RC, copper wiring technique replaces the aluminium interconnection process becomes main flow technology, and introduces the dielectric of low-k (low-k) material as metal interlevel.Copper has reduced the resistance between metal connecting line, has strengthened the stability of circuit simultaneously; Advanced low-k materials has then reduced the parasitic capacitance between the metal connecting line.Because copper can not form the chloride of volatile, can not realize through conventional aluminum interconnection wiring technology, so the technical scheme that present copper interconnect wiring generally adopts is a Damascus technics; In Damascus technics; At first dielectric layer is carried out etching, produce the groove and the through hole that are used for technology, secondly barrier layer; Copper seed layer; Be deposited on copper in groove or the through hole through electroplating technology once more, use chemical mechanical milling tech (CMP) that copper is planarized to the surface of metal interlamination medium layer at last, so just formed copper-connection.
Yet; Copper atom has very high mobility in dielectric material and silicon; Being easy to diffuse in dielectric material and the silicon to influence the minority carrier lifetime of device and the leakage current of knot, causes circuit malfunction, reliability decrease; Therefore, must can prevent that the dielectric barrier layer (also as etching barrier layer) of copper diffusion can suppress the diffusion of copper atom in dielectric layer of lower floor's copper metal in deposit on the wafer after the metallic copper planarization.In traditional copper-connection method; The deposit that can prevent copper diffusion dielectric barrier layer is the anti-copper diffusion barrier layer film of deposit one deck on the whole plane at copper interconnect surfaces place; Yet owing to can prevent that the dielectric constant of copper diffusion dielectric barrier layer is big than the low-k material, making increases between the double layer of metal and with electric capacity between the layer metal; The RC that has increased circuit postpones to increase, and has limited the speed of integrated circuit.
Summary of the invention
The present invention proposes a kind of formation method of copper interconnection structure; Selectively depositedly prevent that copper diffusion dielectric barrier layer can improve the big shortcoming of interconnection capacitance that can prevent that copper diffusion barrier layer causes; Promote the performance of semiconductor chip, help the development of very lagre scale integrated circuit (VLSIC).
For solving the problems of the technologies described above, the present invention provides a kind of formation method of copper interconnection structure, comprises the steps:
The semiconductor substrate is provided, deposit one dielectric layer on the said semiconductor-based end;
Adopt photoetching, etching technics, in said dielectric layer, form through hole and/or groove;
Bottom and sidewall deposit one metal barrier at said through hole and/or groove;
At cement copper inculating crystal layer on the metal barrier and in said through hole and/or groove, fill metallic copper, make the surface of metallic copper be lower than the surface of said dielectric layer, thereby in through hole and/or groove, form the copper groove on copper metal layer and the copper metal layer;
Deposit one deck can be prevented copper diffusion barrier layer on the surface of said copper metal layer and said dielectric layer surface;
Adopt cmp to remove the copper the prevented diffusion dielectric barrier layer of dielectric layer top, on the copper metal layer surface, remain with a part and can prevent copper diffusion dielectric barrier layer.
As preferably, the step of the copper groove on said formation copper metal layer and the copper metal layer comprises:
Adopt electroplating technology that said through hole and/or groove are carried out the copper filling;
Adopt cmp to remove the metallic copper on the dielectric layer, and directly form the copper groove that is lower than said dielectric layer surface at the top of through hole and/or groove.
As preferably, the step of the copper groove on said formation copper metal layer and the copper metal layer comprises:
Adopt electroplating technology that said through hole and/or groove are carried out the copper filling;
Adopt cmp to remove the metallic copper on the dielectric layer;
Adopt the reverse electrolysis electroplating technology to remove a part of metallic copper at through hole and/or groove top, form the copper groove that is lower than said dielectric layer surface.
As preferably, the step of the copper groove on said formation copper metal layer and the copper metal layer comprises:
Adopt electroplating technology that said through hole and/or groove are carried out the copper filling;
Adopt cmp to remove the metallic copper on the dielectric layer;
Adopt wet processing to remove the metallic copper of the part at through hole and/or groove top, form the copper groove that is lower than said dielectric layer surface.
As preferably, said dielectric layer adopts chemical vapor deposition or spin coating process to form, and said dielectric layer adopts advanced low-k materials.
As preferably, the advanced low-k materials that said dielectric layer adopted is SiOCH.
As preferably, saidly prevent that the material of copper diffusion barrier layer is SiN, SiC, SiOC, SiOCN or SiCN.
As preferably, the method on said depositing metal barrier layer is: adopt among physical vapor deposition, chemical vapor deposition or atomic layer deposition TiN, Ti, TaN, Ta, WN or the W one or more.
As preferably, the degree of depth of said copper groove is 10～100nm
As preferably, the said degree of depth of preventing the thickness of copper diffusion barrier layer more than or equal to said copper groove.
As preferably, the copper the prevented diffusion dielectric barrier layer thickness that keeps on the said copper metal layer surface is equal to or less than the degree of depth of said copper groove.
As preferably, adopt Damascus etching technics in said dielectric layer, to form through hole and/or groove.
Only realized that through formation method of the present invention deposit can be prevented copper diffusion dielectric barrier layer on the copper metal layer surface; Not only having removed on the dielectric layer the unnecessary copper diffusion barrier layer prevented has reduced and can prevent the interconnection capacitance that copper diffusion barrier layer causes; Thereby the RC that improves entire circuit postpones, and can be widely used in semiconductor fabrication process.
Description of drawings
Fig. 1 is a formation method flow diagram of the present invention;
Fig. 2 a-Fig. 2 o is the profile that one embodiment of the invention forms each processing step in the method flow.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
The formation method of a kind of copper interconnection structure of the present invention may further comprise the steps: the semiconductor substrate is provided, deposit one dielectric layer on the said semiconductor-based end; Adopt photoetching, etching technics, in said dielectric layer, form through hole and/or groove; Bottom and sidewall deposit one metal barrier at said through hole and/or groove; At cement copper inculating crystal layer on the metal barrier and in said through hole and/or groove, fill metallic copper, make the surface of metallic copper be lower than the surface of said dielectric layer, thereby in through hole and/or groove, form the copper groove on copper metal layer and the copper metal layer; Deposit one deck can be prevented copper diffusion barrier layer on the surface of said copper metal layer and said dielectric layer surface; Adopt cmp to remove the copper the prevented diffusion dielectric barrier layer of dielectric layer top, and remain with a part on the copper metal layer surface and can prevent copper diffusion dielectric barrier layer, form copper-connection.
To combine generalized section that the manufacturing approach of a kind of copper interconnection structure of the present invention is described in more detail below; The preferred embodiments of the present invention have wherein been represented; Should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing to those skilled in the art, and not as limitation of the present invention.
Fig. 2 a-Fig. 2 o shows one embodiment of the invention, and is as shown in Figure 1, and the formation method of said copper interconnection structure is following:
In step 101, shown in Fig. 2 a, semiconductor substrate 200 is provided; Deposit first dielectric layer 201 on the said semiconductor-based end; The said semiconductor-based end 200 can be the silicon chip that is formed with device layer and/or metal interconnecting layer, and said first dielectric layer 201 adopts chemical vapor deposition or spin coating process to form, and said first dielectric layer 201 adopts advanced low-k materials; Preferably, adopt SiOCH.
In step 102, shown in Fig. 2 b, adopt photoetching, etching technics, in said first dielectric layer 201, form first groove 202, in the present embodiment, preferably adopt single Damascus technics etching first groove 202.
In step 103; Shown in Fig. 2 c; Bottom and sidewall deposit first metal barrier 203 at said first groove 202; The method of said deposit first metal barrier 203 is: adopt physical vapor deposition, chemical vapor deposition or atomic layer deposition, the material of said first metal barrier 203 is one or more among TiN, Ti, TaN, Ta, WN or the W.Said first metal barrier 203 can prevent that metallic copper from spreading and pollute in said first dielectric layer 201 and substrate 200.
In step 104; Shown in Fig. 2 d and 2e; Fill metallic copper at cement copper inculating crystal layer on said first metal barrier 203 and in said first groove 202; Make the surface of metallic copper be lower than the surface of said first dielectric layer 201, thereby in first groove, form the first bronze medal groove 205 on first copper metal layer 204 and first copper metal layer.In the present embodiment; Step 104 can specifically comprise: adopt electroplating technology that first groove 202 is carried out metallic copper and fill; Yet, because in electroplate filling the process of metallic copper, have part copper and overflow first groove 202 and cover said first dielectric, 201 laminar surfaces; Therefore; Adopt cmp to remove the metallic copper on first dielectric layer 201 again, and on the surface of said metallic copper, directly form the first bronze medal groove 205 and first copper metal layer 204 that is lower than said first dielectric layer 201 surfaces, and the degree of depth of the said first bronze medal groove 205 is 10～100nm.
As optional execution mode, step 104 can comprise: adopt electroplating technology that said first groove 202 is carried out metallic copper and fill; Adopt cmp to remove the metallic copper on first dielectric layer, 201 surfaces; Adopt reverse electrolysis electroplating technology (reverse-electrochemical plating process) to remove a part of metallic copper at ditch first groove 202 tops, form the first bronze medal groove 205 and first copper metal layer 204 that are lower than said first dielectric layer 201 surfaces.
As optional execution mode, step 104 can comprise: adopt electroplating technology that said first groove 202 is carried out metallic copper and fill; Adopt cmp to remove the metallic copper on first dielectric layer, 201 surfaces; Adopt wet processing to remove a part of metallic copper at first groove, 202 tops, form the first bronze medal groove 205 and first copper metal layer 204 that are lower than said first dielectric layer 201 surfaces.
In step 105, shown in Fig. 2 f, deposit one deck first can be prevented copper diffusion barrier layer 206 on the surface of said first copper metal layer 204 and said first dielectric layer 201 surfaces.Said first can prevent that the material of copper diffusion barrier layer 206 is SiN, SiC, SiOC, SiOCN or SiCN, and said first can prevent the degree of depth of the thickness of copper diffusion barrier layer more than or equal to the said first bronze medal groove.In the present embodiment, said first can prevent that the thickness of copper diffusion barrier layer 206 is preferably the degree of depth that equals the said first bronze medal groove 205.
In step 106; Of Fig. 2 g; Adopt cmp to remove said first dielectric layer 201 lip-deep first and can prevent copper diffusion dielectric barrier layer 206; On the surface of said first copper metal layer 204; Promptly remain with a part first in the first bronze medal groove 205 and can prevent copper diffusion dielectric barrier layer 206a, first can prevent that copper diffusion dielectric barrier layer 206a thickness is equal to or less than the degree of depth of the said first bronze medal groove, and first of said reservation can be prevented protective layer and the etching barrier layer of copper diffusion dielectric barrier layer 206a as first copper-connection.Final first copper interconnection layer that forms.
Then return step 101; Second dielectric layer 211 of deposit low-k on said first copper interconnection layer; Shown in Fig. 2 h, said second dielectric layer 211 adopts chemical vapor deposition or spin coating process to form, and said second dielectric layer 211 adopts advanced low-k materials; Preferably, adopt SiOCH.
In step 102, shown in Fig. 2 i, adopt photoetching, etching technics, in said second dielectric layer 211, form the through hole 212 and second groove 213, said through hole 212 connects said first groove 202 and second groove 213.In the present embodiment, preferably adopt the dual damascene etching technics to form the through hole 212 and second groove 213.
In step 103, shown in Fig. 2 j, remove first of through hole 212 bottoms and can prevent copper diffusion dielectric barrier layer 206a, make through hole 212 bottom-exposed go out said first copper metal layer 204.Shown in Fig. 2 k, at the bottom and sidewall deposit second metal barrier 214 of the said through hole 212 and second groove 213, the method for said deposit second metal barrier 214 is for another example: adopt physical vapor deposition, chemical vapor deposition or atomic layer deposition.The material of said second metal barrier 214 is one or more among TiN, Ti, TaN, Ta, WN or the W.Said second metal barrier 214 can prevent that metallic copper from spreading and pollute in said second dielectric layer 211 and first copper interconnection layer.
In step 104; Shown in Fig. 2 l and 2m; Fill metallic copper at cement copper inculating crystal layer on said second metal barrier 214 and in the said through hole 212 and second groove 213; Make the surface of metallic copper be lower than the surface of said second dielectric layer 211, thereby in the through hole 212 and second groove 213, form the second bronze medal groove 216 on second copper metal layer 215 and second copper metal layer.In the present embodiment; Step 104 can specifically comprise: adopt electroplating technology that the through hole 212 and second groove 213 are carried out the metallic copper filling; Because in electroplating the process of filling metallic copper; Have that part copper overflows through hole 212 and second groove 213 covers said second dielectric, 211 laminar surfaces; Adopt cmp to remove the metallic copper on second dielectric layer 211, and on the surface of said metallic copper, directly form the second bronze medal groove 216 and second copper metal layer 215 that is lower than said second dielectric layer surface 211, the degree of depth of the said second bronze medal groove 216 is 10～100nm.
As optional execution mode, step 104 can comprise: adopt electroplating technology that the said through hole 212 and second groove 213 are carried out the metallic copper filling; Adopt cmp to remove the metallic copper on second dielectric layer, 211 surfaces; Adopt the reverse electrolysis electroplating technology to remove a part of metallic copper at through hole 212 and second groove, 213 tops, form the second bronze medal groove 216 and second copper metal layer 215 that are lower than said second dielectric layer 211 surfaces.
As optional execution mode, step 104 can comprise: adopt electroplating technology that the said through hole 212 and second groove 213 are carried out the metallic copper filling; Adopt cmp to remove the metallic copper on second dielectric layer, 211 surfaces; Adopt wet processing to remove a part of metallic copper at through hole 212 and second groove, 213 tops, form the second bronze medal groove 216 and second copper metal layer 215 that are lower than said second dielectric layer 211 surfaces.
In step 105, shown in Fig. 2 n, deposit one deck second can be prevented copper diffusion barrier layer 217 on the surface of said second copper metal layer 215 and said second dielectric layer 211 surfaces.Said second can prevent that the material of copper diffusion barrier layer 217 is SiN, SiC, SiOC, SiOCN or SiCN, and said second can prevent the degree of depth of the thickness of copper diffusion barrier layer more than or equal to the said second bronze medal groove.In the present embodiment, said second can prevent that the thickness of copper diffusion barrier layer 217 is preferably the degree of depth that equals the said second bronze medal groove 216.
In step 106; Of Fig. 2 g; Adopt cmp to remove that said second dielectric layer 211 is lip-deep prevents copper diffusion dielectric barrier layer 217; On said second copper metal layer 215 surfaces; Promptly remain with a part second in the second bronze medal groove 216 and can prevent copper diffusion dielectric barrier layer 217a, second can prevent that copper diffusion dielectric barrier layer 217a thickness is equal to or less than the degree of depth of the said first bronze medal groove, and second of said reservation can be prevented protective layer and the etching barrier layer of copper diffusion dielectric barrier layer 217a as second copper-connection.Final second copper interconnection layer that forms.
Though embodiments of the invention show two-layer copper-connection; But the invention is not restricted to this; Can only form the layer of copper interconnection; Perhaps also can be on second copper interconnection layer the 3rd dielectric layer of deposit one low-k, and the manufacturing approach that repeats first or second copper interconnection layer forms the 3rd copper interconnection layer, even more metal levels.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (12)
1. the formation method of a copper interconnection structure is characterized in that, may further comprise the steps:
The semiconductor substrate is provided, deposit one dielectric layer on the said semiconductor-based end;
Adopt photoetching, etching technics, in said dielectric layer, form through hole and/or groove;
Bottom and sidewall deposit one metal barrier at said through hole and/or groove;
At cement copper inculating crystal layer on the metal barrier and in said through hole and/or groove, fill metallic copper, make the surface of metallic copper be lower than the surface of said dielectric layer, thereby in through hole and/or groove, form the copper groove on copper metal layer and the copper metal layer;
Deposit one deck can be prevented copper diffusion barrier layer on the surface of said copper metal layer and said dielectric layer surface;
Adopt cmp to remove the copper the prevented diffusion dielectric barrier layer of dielectric layer top, on the copper metal layer surface, remain with a part and can prevent copper diffusion dielectric barrier layer.
2. method according to claim 1 is characterized in that, the step of the copper groove on said formation copper metal layer and the copper metal layer comprises:
Adopt electroplating technology that said through hole and/or groove are carried out the copper filling;
Adopt cmp to remove the metallic copper on the dielectric layer, and directly form the copper groove that is lower than said dielectric layer surface at the top of said through hole and/or groove.
3. method according to claim 1 is characterized in that, the step of the copper groove on said formation copper metal layer and the copper metal layer comprises:
Adopt electroplating technology that said through hole and/or groove are carried out the copper filling;
Adopt cmp to remove the metallic copper on the dielectric layer;
Adopt the reverse electrolysis electroplating technology to remove a part of metallic copper at through hole and/or groove top, form the copper groove that is lower than said dielectric layer surface.
4. method according to claim 1 is characterized in that, the step of the copper groove on said formation copper metal layer and the copper metal layer comprises:
Adopt electroplating technology that said through hole and/or groove are carried out the copper filling;
Adopt cmp to remove the metallic copper on the dielectric layer;
Adopt wet processing to remove a part of metallic copper at through hole and/or groove top, form the copper groove that is lower than said dielectric layer surface.
5. method according to claim 1 is characterized in that, said dielectric layer adopts chemical vapor deposition or spin coating process to form, and said dielectric layer adopts advanced low-k materials.
6. according to claim 1 or 5 described methods, it is characterized in that the advanced low-k materials that said dielectric layer adopted is SiOCH.
7. method according to claim 1 is characterized in that, saidly prevents that the material of copper diffusion barrier layer is SiN, SiC, SiOC, SiOCN or SiCN.
8. method according to claim 1 is characterized in that, the method on said depositing metal barrier layer is: one or more among employing physical vapor deposition, chemical vapor deposition or atomic layer deposition TiN, Ti, TaN, Ta, WN or the W.
9. according to each described method among the claim 1-4, it is characterized in that the degree of depth of said copper groove is 10～100nm.
10. according to claim 1 or 7 described methods, it is characterized in that the said degree of depth of preventing the thickness of copper diffusion barrier layer more than or equal to said copper groove.
11. method according to claim 1 is characterized in that, the copper the prevented diffusion dielectric barrier layer thickness that keeps on the said copper metal layer surface is equal to or less than the degree of depth of said copper groove.
12. method according to claim 1 is characterized in that, adopts Damascus etching technics in said dielectric layer, to form through hole and/or groove.
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| CN103390576A (en) * | 2012-05-09 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Copper interconnection structure and forming method thereof |
| CN104134629A (en) * | 2014-08-15 | 2014-11-05 | 上海华力微电子有限公司 | Method for reducing RC delay of integrated circuit |
| CN108735797A (en) * | 2017-04-25 | 2018-11-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109560103A (en) * | 2017-09-27 | 2019-04-02 | 中电海康集团有限公司 | Magnetic random access memory and preparation method thereof |
| CN109713006A (en) * | 2017-10-25 | 2019-05-03 | 上海磁宇信息科技有限公司 | A method of making magnetic RAM cell array and its peripheral circuits |
| CN110211989A (en) * | 2018-02-28 | 2019-09-06 | 台湾积体电路制造股份有限公司 | Novel electric resistive RAM device, storage unit and its manufacturing method |
| CN110364502A (en) * | 2014-05-15 | 2019-10-22 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its manufacturing method with the composite barrier being located at below redistribution layer |
| CN111211094A (en) * | 2020-01-10 | 2020-05-29 | 四川豪威尔信息科技有限公司 | Method for manufacturing copper interconnection structure of integrated circuit |
| CN111584383A (en) * | 2020-05-14 | 2020-08-25 | 深圳市华星光电半导体显示技术有限公司 | Method for judging blocking capability of copper diffusion blocking layer and structure thereof |
| CN111936902A (en) * | 2018-04-02 | 2020-11-13 | 埃尔瓦有限公司 | Fabrication of metallic optical super-surfaces |
| CN112786525A (en) * | 2019-11-07 | 2021-05-11 | 长鑫存储技术有限公司 | Semiconductor device and method of forming the same |
| CN115036270A (en) * | 2022-08-11 | 2022-09-09 | 广州粤芯半导体技术有限公司 | Method for manufacturing copper interconnection structure |
| US20220336267A1 (en) * | 2019-09-27 | 2022-10-20 | Intel Corporation | Interconnect structures and methods of fabrication |
| US12027462B2 (en) | 2020-05-14 | 2024-07-02 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Method and structure for determining blocking ability of copper diffusion blocking layer |
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| CN103390576B (en) * | 2012-05-09 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Copper interconnection structure and forming method thereof |
| CN103390576A (en) * | 2012-05-09 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Copper interconnection structure and forming method thereof |
| CN110364502A (en) * | 2014-05-15 | 2019-10-22 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its manufacturing method with the composite barrier being located at below redistribution layer |
| CN104134629A (en) * | 2014-08-15 | 2014-11-05 | 上海华力微电子有限公司 | Method for reducing RC delay of integrated circuit |
| CN108735797A (en) * | 2017-04-25 | 2018-11-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109560103B (en) * | 2017-09-27 | 2020-11-13 | 中电海康集团有限公司 | Magnetoresistive random access memory and preparation method thereof |
| CN109560103A (en) * | 2017-09-27 | 2019-04-02 | 中电海康集团有限公司 | Magnetic random access memory and preparation method thereof |
| CN109713006A (en) * | 2017-10-25 | 2019-05-03 | 上海磁宇信息科技有限公司 | A method of making magnetic RAM cell array and its peripheral circuits |
| CN110211989A (en) * | 2018-02-28 | 2019-09-06 | 台湾积体电路制造股份有限公司 | Novel electric resistive RAM device, storage unit and its manufacturing method |
| CN111936902B (en) * | 2018-04-02 | 2023-02-28 | 埃尔瓦有限公司 | Fabrication of metallic optical super-surfaces |
| CN111936902A (en) * | 2018-04-02 | 2020-11-13 | 埃尔瓦有限公司 | Fabrication of metallic optical super-surfaces |
| US11887887B2 (en) * | 2019-09-27 | 2024-01-30 | Intel Corporation | Interconnect structures and methods of fabrication |
| US20220336267A1 (en) * | 2019-09-27 | 2022-10-20 | Intel Corporation | Interconnect structures and methods of fabrication |
| CN112786525A (en) * | 2019-11-07 | 2021-05-11 | 长鑫存储技术有限公司 | Semiconductor device and method of forming the same |
| CN112786525B (en) * | 2019-11-07 | 2023-07-07 | 长鑫存储技术有限公司 | Semiconductor device and method of forming the same |
| CN111211094A (en) * | 2020-01-10 | 2020-05-29 | 四川豪威尔信息科技有限公司 | Method for manufacturing copper interconnection structure of integrated circuit |
| CN111584383A (en) * | 2020-05-14 | 2020-08-25 | 深圳市华星光电半导体显示技术有限公司 | Method for judging blocking capability of copper diffusion blocking layer and structure thereof |
| US12027462B2 (en) | 2020-05-14 | 2024-07-02 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Method and structure for determining blocking ability of copper diffusion blocking layer |
| CN115036270A (en) * | 2022-08-11 | 2022-09-09 | 广州粤芯半导体技术有限公司 | Method for manufacturing copper interconnection structure |
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