478107 五、發明說明（1) 發明領域： 本發明揭露一種有關於半導體元件製程，特別是有關 於一種銅雙鑲嵌製程，以防止孔洞（vo i d)形成於介層洞 (v i a )之製程。 發明背景： 積體電路之製程除了使得晶片内元件的體積小，以達 到南雄、度及降低單位成本之目的外，元件之最後的性能更 是關鍵’而除了電晶體元件本身之設計外，最後之内連接 金屬導線乃至内連線間介電層都是重要影響元件速度表現 的重要因素，這是因導線之阻值R，與上層導線和下層導 線及相鄰導線之間會有電容C存在，一如熟悉相關技術之 人士所共知，此RC值愈低代表較低之時間延遲，因此目前 内連線使用銅製程代替鋁製程已成為一種趨勢。另外，將 内連線間介電層改用低介電常數之介電層以使寄生電容降 低，以提高速度。已成目前半導體業共同追求的目標。 傳統的銅雙鑲嵌製程多利用大馬士革的方法，在形成478107 V. Description of the invention (1) Field of the invention: The present invention discloses a process related to the fabrication of semiconductor devices, in particular, a copper dual damascene process to prevent holes (vo i d) from being formed in via holes (v i a). Background of the Invention: In addition to the process of making integrated circuits, in addition to making the components in the chip small, in order to achieve Nanxiong, degrees and reduce unit costs, the final performance of the components is more critical. In addition to the design of the transistor component itself, Finally, the inter-connected metal wires and even the dielectric layer between the interconnects are important factors that affect the speed performance of the device. This is because the resistance R of the wire has a capacitance C between the upper wire and the lower wire and adjacent wires. Existence. As everyone familiar with the related technology knows, the lower the RC value, the lower the time delay. Therefore, it has become a trend to use copper process instead of aluminum process for the interconnect. In addition, the dielectric layer between interconnects was changed to a low-constant dielectric layer to reduce parasitic capacitance and increase speed. Has become a common goal of the current semiconductor industry. The traditional copper double inlay process uses Damascus methods to form
沉積 J用無電鍍銅法或PVD法形成 側壁f底部，再利用電鍍銅 一種最新的技術則是在形成 478107 五、發明說明（2) 雙鑲嵌圖案後利用PVD法形成金屬阻障層，再浸入活化溶 液促使金屬阻障層上具有銅晶種，再以電鍍銅方式形成金 屬銅。上述不管是以PVD法形成銅晶種，或以CVD法，甚或 以活化溶液的方法，均係使電鍍銅的沉積方式由介層洞側 壁及底部成長。 請參考圖一的說明，其中金屬導線1 1係待連接的導 線，一介層洞1 5形成於介電層1 2中，用以連接金屬導線 11，1 4係姓刻終止層，例如氮化石夕層。1 8係利用活化液使 金屬阻障層1 6活化後的銅晶種層。由橫截面示意圖可以發 現電鍍銅將由三個方向成長填滿介層洞1 5，對孔徑小的介 層洞而言，預期將有孔洞產生於介層洞之中。 有鑑於如上所述的問題，本發明將提供一銅雙鑲嵌的 方法以加以解決。 發明目的及概述： 本發明之目的在提供一銅之雙鑲嵌製程以防止有孔洞 產生於介層洞之中。 本發明為一種銅之雙鑲嵌製程方法，本發明方法主要 是利用由介層洞底部待連接之金屬表層活化，以產生銅成 長的晶種’再措由下向上並以無電鐘銅方式成長’而在導Deposition J uses electroless copper method or PVD method to form the bottom of the side wall f, and then uses copper electroplating. The latest technology is to form 478107 V. Description of the invention (2) After the double damascene pattern, a metal barrier layer is formed by PVD method, and then immersed The activation solution promotes copper seeds on the metal barrier layer, and then forms metal copper by electroplating copper. Regardless of whether the copper seed is formed by the PVD method, the CVD method, or even the activation solution method, the deposition method of the electroplated copper is grown from the side wall and the bottom of the via hole. Please refer to the description of FIG. 1, in which the metal wire 11 is a wire to be connected, and a via hole 15 is formed in the dielectric layer 12 to connect the metal wire 11, 14 to a stop layer such as a nitride. Evening floor. The 18 series is a copper seed layer after the metal barrier layer 16 is activated by using an activating solution. From the schematic diagram of the cross-section, it can be found that the electroplated copper will grow from three directions to fill the interstitial holes 15. For the interstitial holes with small pore diameters, it is expected that there will be holes in the interstitial holes. In view of the problems described above, the present invention will provide a copper dual damascene method to solve the problem. OBJECTS AND SUMMARY OF THE INVENTION The object of the present invention is to provide a copper dual damascene process to prevent holes from being generated in via holes. The present invention is a copper dual damascene process method. The method of the present invention mainly utilizes the metal surface layer to be connected at the bottom of the via hole to activate the seed crystals for copper growth. On guide
478107 ——~~-__-—-—1— — ---- 五、發明說明（3) __ 線溝渠的部分則利用PVD法填入銅或者利用pvD法形 種再利用電鍍達到無孔洞之目的。主要包含以下步；銅首曰曰 先在已形成雙鑲嵌圖案之基板，先利用活化溶液使欲連接 之導線上方之金屬層活化，再利用無電鍍銅方式成長填滿 整個介層洞。再上一層金屬阻障層於導線溝渠，最後則利 用P V D法填入銅或者利用電鍵法鍍銅直到銅金屬層填滿導 線溝渠；最後再施化學機械式研磨的製程。 發明詳細說明： 鑑於上述發明背景所述，傳統之銅雙鑲嵌製程中介層 洞及導線溝渠係先以銅晶種層形成於導線溝渠及介層洞 上’再藉由電鍍銅方法自側壁銅晶種以向内及底部銅晶種 以向上等方向而成長，這樣就很容易造成介層洞内有孔洞 (void)產生。 本發明的方法係設法使介層洞底部待連接之金屬表層 活化以形成銅晶種層，再由介層洞底部向上以無電鍍銅的 方式成長銅金屬層，而使得尺寸小的介層洞由底部單一方 向成長銅金屬層而達到無孔洞產生之目的。 以下之製程詳細說明，將佐以圖示說明。說明如下： 首先請參考圖二所示之橫截面示意圖。首先圖案化一形成 於一基板100上的鋁銅合金105A/TiN 105B的金屬導線 478107 五、發明說明（4) 1 0 5。其中T i N層1 0 5 B除了做為抗反射塗層外，並可以做為 後續進行銅轉位法（copper di'splacement)的介面金屬 層0 接著，再以CVD法形成一具有良好散熱功能之内襯層 (1 i n i n g 1 a y e r ) 1 1 0以覆蓋金屬導線1 0 5及基板1 〇 〇上，以 一較佳的實施例而言，内概層11 0至少包含一厚度約為 100-800埃的氮化銘層。 隨後，形成一第一介電層120於該内襯層11〇上，第一 介電層1 2 0可以係利用旋塗式玻璃法所形成的低介電常數 (low-k)之有機介電層，例如p〇lymer或者Flare、H0SP等 皆可，當然，以化學氣相沉積法所沉積之1 ow — k ，例如黑 鑽石或者Coral也是可以選用的low-k介電材料。 第一介電層1 2 0形成後，再形’成一第一蝕刻終止層1 2 5 於該第一介電層1 2 〇上；第一蝕刻終止層1 2 5以一較佳的實 施例而言，係氮化矽。一光阻圖案（未圖示）接著以微影技 術塗佈於第一餘刻終止層1 2 5上，用·以定義介層洞位置， 此光阻圖案需適當的對準以使介層洞和金屬線1 〇 5可以連 接。接著再進行乾式蝕刻以形成介層洞開口 1 2 5 A於第一蝕 刻終止層1 2 5之中，在去光阻圖案後緊接著再沉積第二介 電層130，第二介電層130為簡化製程起見，以和第一介電 層相同材質為最佳，當然，也可以自上述第一介電層材料 478107 五、發明說明（5) 中選用不同的材質。 、之後，再形成一氮化硼層1 4 0於該第二介電層1 3 0上以 做為硬式罩幕層，其他的材料例如氮化矽也同樣可以選用 以做為硬式罩幕層之材料。再接著以光阻圖案145形成 於硬式罩幕層140上以定義導線溝渠開口 146的位置。 请參考圖三所示的橫截面示意圖，接著進行乾蝕刻以 移轉光阻圖案145至硬式罩幕層14〇後，光阻圖案145即予 以移除。並以硬式罩幕層i 4 〇為蝕刻罩幕，蝕刻第二介電 層1 3 0 ’以第一蝕刻終止層丄2 5為終止層，形成導線溝渠 140A。其中蝕刻氣體並藉由介層洞開口 125A钱刻第一介電 層1 2 0而停止於内襯層i丨〇。再更換蝕刻混合氣體以蝕穿内 襯層1 1 0而停止於T i N 1 0 5 BJi。 明參考圖四A所示的橫截面示意圖，接著以化學氣相 >儿積法沉積厚度約為2 0 0 - 1 5 0 0埃的氮化石夕層，此氮化石夕層 的功能係防止銅原子向介電層擴散，並隨後施以一非等向 性蝕刻方法，形成氮化矽間隙壁層.丨4 8、1 4 7，分別形成於 導線溝渠1 4 0 A及介層洞1 2 5 B的側壁上。氮化石夕間隙壁層 1 4 8、1 4 7亦具有阻擋有機介電層受電漿損傷所釋放的水氣 擴散至導線溝渠1 4 0 A及介層洞1 2 5 B内。以一較佳的實施例 而言，此步驟的進行可以以反應離子蝕刻法（R丨E )進行。 478107 五、發明說明（6) ' —一一: 接著利用金屬導線1 〇 5上的T i N 1 0 5B表面進行銅轉位 -· 法（copper displacement)，銅轉位法係將基板1〇〇浸入使 銅活化的溶液，而使得銅原子可以附著在T i N丨〇 5β上表面 上。銅活化的溶液主要以去離子水為主，去離子水中並至 . 少包含有〇· 01至2莫耳/公升的銅Cu+雔子，〇· 〇1至5莫耳/ 公升的氟F離子及表面活性劑，〇.01至10公克/公升界面 活性劑。界面活性劑包含RH0DAFAC re 610(製造商為 Rhone-Poulenc)、聚乙烯（p〇iye1：hy lene，乙二醇 (glycol)及 Triton X-1〇〇 (製造商為 Aldrich)。基板 1〇〇在 上述的銅活化溶液中以18至40(rc浸約3〇 —1〇〇〇秒，就可以〇 使得T i N 1 0 5B上形成一銅活化層1 5 〇 A，請同時參考圖四 B (圖四A的一局部放大圖）。 利用這一層銅活化層1 5 0 A就可以以習知技術進行無電 鍍銅程序。由於銅活化層150A僅存在於介層洞125B的底 部，側壁並沒有任何的銅活化層，因此無電鑛銅的成長方 -向是單一的，即銅金屬層由下而上成長形成，習知技術的 孔洞問題因而可以迎刃而解。 請參考圖五所示的橫截面示意圖。當無電鑛銅填滿整 個介電層洞1 2 5 B後，再接著形成一金屬阻障層1 5 5於氮化 矽間隙壁1 48及第一蝕刻終止層1 25上，。對於尺寸較大的 導線溝渠1 4 0 A有兩個方法可以填入銅金屬層，第一個方法 是利用金屬阻障層1 5 5的電導性，施以電鑛法沉積銅金屬 478107 五、發明說明（7) 層1 6 0至導線溝渠1 4 0 A内。第二個方法是以物理氣相沉積 法直接沉積銅金屬層至導線溝渠1 4 0 A内。 最後請參考圖六，施以化學/機械式研磨製程以移除 部分之銅金屬層，以硬式罩幕層1 4 0為研磨終止層。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。478107 —— ~~ -__-—-— 1— — ---- V. Description of the invention (3) The __ part of the line trench is filled with copper by PVD method or by electroplating using pvD method to achieve no holes. purpose. It mainly includes the following steps: firstly, the copper layer is formed on the substrate with the double damascene pattern, the activation solution is used to activate the metal layer above the wires to be connected, and then the electroless copper is used to grow and fill the entire via hole. Then add a metal barrier layer to the wire trench, and finally use the P V D method to fill the copper or use the bond method to plate copper until the copper metal layer fills the wire trench. Finally, a chemical mechanical polishing process is applied. Detailed description of the invention: In view of the above background of the invention, in the conventional copper dual damascene process, the interposer holes and the lead trenches are first formed on the lead trenches and the via holes with a copper seed layer, and then copper is crystallized from the side wall by a copper plating method. The seeds grow inward and at the bottom, the copper seed crystals grow in upward directions, so that it is easy to cause voids in the vias. The method of the invention is to try to activate the metal surface layer to be connected at the bottom of the via hole to form a copper seed layer, and then grow the copper metal layer from the bottom of the via hole upward in an electroless copper manner, so that the small-sized via hole is formed by The copper metal layer is grown in a single direction at the bottom to achieve the purpose of no holes. The detailed description of the following process will be illustrated with illustrations. The explanation is as follows: First, please refer to the cross-sectional diagram shown in Figure 2. First, a metal wire of aluminum-copper alloy 105A / TiN 105B formed on a substrate 100 is patterned 478107 V. Description of the invention (4) 105. The TiN layer 1 0 5B can be used as an anti-reflection coating and can also be used as an interface metal layer for copper di'splacement. Next, a CVD method is used to form a layer with good heat dissipation. A functional inner lining layer (1 ining 1 ayer) 1 10 covers the metal wire 105 and the substrate 100. In a preferred embodiment, the inner layer 1 10 includes at least a thickness of about 100 -800 Angstrom nitride layer. Subsequently, a first dielectric layer 120 is formed on the inner lining layer 110. The first dielectric layer 120 can be a low-k organic dielectric formed by a spin-on glass method. The electrical layer, for example, polymer or Flare, HOSP, etc. may be used. Of course, 1 ow-k deposited by chemical vapor deposition, such as black diamond or Coral, is also a low-k dielectric material that can be selected. After the first dielectric layer 12 is formed, a first etch stop layer 1 2 5 is formed on the first dielectric layer 1 2 0. The first etch stop layer 1 2 5 is a preferred embodiment. In terms of silicon nitride. A photoresist pattern (not shown) is then applied on the first remaining stop layer 1 2 5 by lithography technology to define the position of the via hole. This photoresist pattern needs to be properly aligned to make the interlayer The hole and the metal wire 105 can be connected. Next, dry etching is performed to form a dielectric hole opening 1 2 5 A in the first etch stop layer 12 25. After removing the photoresist pattern, a second dielectric layer 130 and a second dielectric layer 130 are then deposited. In order to simplify the manufacturing process, it is best to use the same material as the first dielectric layer. Of course, different materials can be selected from the above-mentioned first dielectric layer material 478107 V. Description of Invention (5). After that, a boron nitride layer 140 is formed on the second dielectric layer 130 as a hard mask layer. Other materials such as silicon nitride can also be used as a hard mask layer. Of materials. Then, a photoresist pattern 145 is formed on the hard mask layer 140 to define the position of the wire trench opening 146. Please refer to the schematic cross-sectional view shown in FIG. 3, and then perform dry etching to transfer the photoresist pattern 145 to the hard mask layer 140, and then the photoresist pattern 145 is removed. And using the hard mask layer i 4 o as an etching mask, the second dielectric layer 1 3 0 ′ is etched, and the first etching stop layer 丄 25 is used as a stop layer to form a wire trench 140A. The etching gas stops the first dielectric layer 120 through the opening 125A of the interlayer hole, and stops at the inner layer i0. The etching gas mixture is replaced to etch through the inner liner 1 10 and stop at T i N 1 0 5 BJi. Referring to the schematic diagram of the cross-section shown in FIG. 4A, a chemical vapor phase deposition method is then used to deposit a nitride layer with a thickness of about 200-1500 angstroms. The function of this nitride layer is to prevent Copper atoms diffuse into the dielectric layer, and then an anisotropic etching method is applied to form a silicon nitride spacer layer. 4 8 and 1 4 7 are respectively formed in the wire trench 1 4 0 A and the dielectric hole 1 2 5 B on the side wall. Nitrogen stone gap wall layers 1 4 8 and 1 4 7 also prevent the water vapor released from the organic dielectric layer from being damaged by the plasma to diffuse into the wire trench 1 40 A and the dielectric hole 1 2 5 B. In a preferred embodiment, this step can be performed by a reactive ion etching method (R 丨 E). 478107 V. Description of the invention (6) '-One by one: Then use copper surface T i N 1 0 5B on metal wire 1 0 5 to perform copper displacement-copper displacement method, the copper displacement method is to substrate 1 〇 Immerse in a solution that activates copper so that copper atoms can attach to the upper surface of T i N0 5β. The copper-activated solution is mainly deionized water, and it does not contain at least 0.01 to 2 mol / L of copper Cu + ions, and 0.001 to 5 mol / L of fluorine F ions. And surfactants, 0.01 to 10 g / L of surfactant. Surfactants include RHODAFAC re 610 (manufacturer Rhone-Poulenc), polyethylene (poiye1: hylene, glycol), and Triton X-100 (manufacturer: Aldrich). Substrate 100 Immerse the copper activation solution in the above-mentioned copper activation solution at 18 to 40 (rc for about 30 to 10,000 seconds, so that a copper activation layer 15 OA can be formed on T i N 105 B, please refer to FIG. 4 at the same time. B (a partial enlarged view of FIG. 4A). Using this copper activation layer 150 A, the electroless copper plating process can be performed by conventional techniques. Because the copper activation layer 150A exists only at the bottom of the via 125B, the sidewalls There is no copper activation layer, so the growth direction of electroless ore copper is single, that is, the copper metal layer grows from bottom to top, and the hole problem of the conventional technology can be solved. Please refer to the horizontal diagram shown in Figure 5. A schematic cross-sectional view. After the entire dielectric layer hole 12 5 B is filled with electroless copper, a metal barrier layer 15 is then formed on the silicon nitride spacer wall 148 and the first etch stop layer 125. For larger wire trenches 1 4 0 A, there are two ways to fill the copper metal layer. The first One method is to use the electrical conductivity of the metal barrier layer 1 5 to deposit copper metal 478107 by electro-mineral method. 5. Description of the invention (7) The layer 1 60 to the wire channel 1 40 A. The second method is to The physical vapor deposition method directly deposits the copper metal layer into the wire trench 1 40 A. Finally, referring to FIG. 6, a chemical / mechanical grinding process is performed to remove a portion of the copper metal layer, and a hard cover layer 1 4 0 It is a grinding stop layer. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention, All should be included in the scope of patent application described below.
第10頁 478107 圖式簡單說明 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述： 圖一顯示依據傳統方法於介層洞側壁及底部形成銅晶 種後再以無電鍍銅沉積銅層的橫截面示意圖。 圖二顯示依據本發明之方法形成圖案化的蝕刻終止 層，再沉積介電層與硬式罩幕層後以光阻定義導線溝渠的 橫截面示意圖。 圖三顯示依據本發明之方法形成導線溝渠及介層洞之 雙鑲嵌圖案並裸露TiN的橫截面示意圖。 圖四A顯示依據本發明之方法在阻障層形成後以無電 鍍銅法填滿介層洞的橫截面示意圖，圖四B則顯示無電鍍 銅沉積的方向係單方向由下向上成長的橫截面示意圖。 圖五顯示依據本發明之方法沉積金屬阻障層後再以 PVD或電鍍銅方式沉積銅於導線溝渠的橫截面示意圖。 圖六顯示依據本發明之方法施以化學機械式研磨以去 除 多 餘 之 金屬 的橫截面示 意圖。 圖 號 對 昭 ο、、 表： • 金 屬 導 線 11 介 電 層 12 刻 終 止 層 14 介 層 洞 15 金 屬 阻 障 層 16 晶 種 層 18 基 板 100 金 屬 導線 105 雀呂 銅 合 金 105A/TiN105B 内 概 層 110 〇Page 478107 The diagram simply illustrates the preferred embodiment of the present invention and will be explained in more detail in the following explanatory texts. Figure 1 shows the formation of copper seeds on the sidewall and bottom of the via hole according to the traditional method. A schematic cross-sectional view of a copper layer deposited by electroless copper. Figure 2 shows a schematic cross-sectional view of a conductive trench defined by photoresist after a patterned etch stop layer is formed according to the method of the present invention, and then a dielectric layer and a hard mask layer are deposited. FIG. 3 is a schematic cross-sectional view of forming a dual damascene pattern of a wire trench and a via hole and exposing TiN according to the method of the present invention. FIG. 4A shows a schematic cross-sectional view of filling a via hole with an electroless copper method after the barrier layer is formed according to the method of the present invention, and FIG. 4B shows a direction in which the electroless copper is deposited in a single direction from bottom to top. Schematic cross-section. FIG. 5 is a schematic cross-sectional view of depositing a metal barrier layer according to the method of the present invention and then depositing copper on the wire trench by PVD or electroplated copper. Fig. 6 shows a schematic cross-sectional view of a method for removing excess metal by chemical mechanical grinding according to the method of the present invention. Drawing numbers: • Table: • Metal wire 11 dielectric layer 12 etch stop layer 14 via hole 15 metal barrier layer 16 seed layer 18 substrate 100 metal wire 105 copper copper alloy 105A / TiN105B inner layer 110 〇
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第12頁 圖 式簡單說明 第 一 介 電 層 120 第 一 刻 終止層 125 介 層 洞 開 V 125A 介 層 洞 125B 第 二 介 電 層 130 硬 式 罩 幕 層 140 導 線 溝 渠 140A 光 阻 圖 案 145 氮 化 矽 間 隙 壁 147、 148 銅 活 化 層 150A 介 層 洞 内 之 銅 金屬> 層150 金 屬 阻 障 層 155 導 線 溝 渠 内 之 銅金, 饜層160導 線 溝 渠 開口 146The diagram on page 12 briefly explains the first dielectric layer 120, the first etch stop layer 125, the interlayer hole V 125A, the interlayer hole 125B, the second dielectric layer 130, the hard mask layer 140, the wire channel 140A, the photoresist pattern 145, and the silicon nitride gap. Walls 147, 148 Copper activation layer 150A Copper metal in via hole > Layer 150 Metal barrier layer 155 Copper and gold in wire trench, sacrificial layer 160 Wire trench opening 146