CN103390576B - Copper interconnection structure and forming method thereof - Google Patents
Copper interconnection structure and forming method thereof Download PDFInfo
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- CN103390576B CN103390576B CN201210142957.0A CN201210142957A CN103390576B CN 103390576 B CN103390576 B CN 103390576B CN 201210142957 A CN201210142957 A CN 201210142957A CN 103390576 B CN103390576 B CN 103390576B
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Abstract
The invention provides a kind of copper interconnection structure and forming method thereof, wherein, described method comprises: provide substrate; Form structure sheaf over the substrate, described structure sheaf comprises: low K dielectric layer, be positioned at the groove of described low K dielectric layer and be positioned at barrier layer and the metal copper layer of described groove; Etch described structure sheaf, to form groove on described structure sheaf; Described structure sheaf forms dielectric capping layer, described dielectric capping layer by described groove and described structure sheaf card with.By forming groove on structure sheaf, make dielectric capping layer by described groove and described structure sheaf card and, namely pass through card physically and make described dielectric capping layer and described structure sheaf compact siro spinning technology, namely the adhesive force between dielectric capping layer and metal copper layer is improved, avoid copper to diffuse in low K dielectric layer, improve the reliability of device.
Description
Technical field
The present invention relates to field of IC technique, particularly a kind of copper interconnection structure and forming method thereof.
Background technology
Along with the development of semiconductor technology, the integrated level of VLSI (very large scale integrated circuit) chip is up to several hundred million and even the scale of tens devices, and two-layer above multiple layer metal interconnection technique widely uses.Traditional to be metal interconnectedly made up of aluminum metal, but along with the continuous reduction of device feature size in integrated circuit (IC) chip, current density in metal interconnecting wires constantly increases, the response time required constantly reduces, conventional aluminum interconnection line can not meet the demands, after process is less than 130nm, copper interconnecting line technology instead of aluminum interconnecting technology.Compared with aluminium, the resistivity of metallic copper is lower, and the resistance capacitance (RC) that copper interconnecting line can reduce interconnection line postpones, and improves electromigration, improves the reliability of device.
But metallic copper also has shortcoming as interconnect material, copper easily diffuses in substrate or dielectric layer, for this reason, after copper interconnecting line is formed, needs to form dielectric capping layer thereon and spreads to prevent it.But the adhesive force between copper and conventional dielectric capping layer material is poor, in the dielectric layer that copper therefore still can be caused to diffuse into around it, make puncture voltage (the Voltage Breakdown between adjacent interconnection line, VBD) reduce, cause the reliability decrease of device, simultaneously due to the electron transfer (Electromigration) of copper atom, the useful life of device is caused to reduce.
Please refer to Fig. 1, it is the structural representation of existing copper interconnection structure.As shown in Figure 1, copper interconnection structure 1 comprises: substrate 10; Be positioned at the low K dielectric layer 11 on described substrate 10, described low K dielectric layer 11 has groove (not shown in figure 1); Be positioned at barrier layer 12 and the metal copper layer 13 of described groove, wherein, described metal copper layer 13 is positioned at described barrier layer 12; And cover the dielectric capping layer 14 of described low K dielectric layer 11, barrier layer 12 and metal copper layer 13.
At this, adhesive force between described dielectric capping layer 14 and metal copper layer 13 is poor, thus will cause still having copper to diffuse in low K dielectric layer 11, cause the reliability decrease of device, and the electron transfer of copper atom (Electromigration), cause the useful life of device to reduce.
Summary of the invention
The object of the present invention is to provide a kind of copper interconnection structure and forming method thereof, poor with the adhesive force solved between existing technique medium cap and metal copper layer, thus copper will be caused to diffuse in low K dielectric layer, cause the problem of the reliability decrease of device.
For solving the problems of the technologies described above, the invention provides a kind of formation method of copper interconnection structure, comprising:
Substrate is provided;
Form structure sheaf over the substrate, described structure sheaf comprises: low K dielectric layer, be positioned at the groove of described low K dielectric layer and be positioned at barrier layer and the metal copper layer of described groove;
Etch described structure sheaf, to form groove on described structure sheaf;
Described structure sheaf forms dielectric capping layer, described dielectric capping layer by described groove and described structure sheaf card with.
Optionally, in the formation method of described copper interconnection structure, the technique forming structure sheaf over the substrate comprises the steps:
Form low K dielectric layer over the substrate;
Etch described low K dielectric layer, to form groove in described low K dielectric layer;
Form barrier layer, described barrier layer covers diapire and the sidewall of described low K dielectric layer surface and groove;
Described barrier layer forms metal copper layer;
Chemical mechanical milling tech is performed to described barrier layer and metal copper layer, removes the barrier layer outside described groove and metal copper layer.
Optionally, in the formation method of described copper interconnection structure, described groove is positioned on described low K dielectric layer, and described groove presses close to described groove.
Optionally, in the formation method of described copper interconnection structure, by low K dielectric layer described in DHF solution etches, form described groove.
Optionally, in the formation method of described copper interconnection structure, the degree of depth of described groove is 50 dust ~ 150 dusts.
Optionally, in the formation method of described copper interconnection structure, the cross-sectional width of described groove is 50 dust ~ 150 dusts.
Optionally, in the formation method of described copper interconnection structure, the material of described dielectric capping layer is one or more in SiC, SiN and SiCN.
Optionally, in the formation method of described copper interconnection structure, the material on described barrier layer is one or more in Ta, TaN, Ti and TiN.
Accordingly, the present invention also provides a kind of copper interconnection structure, comprising:
Substrate;
Be positioned at the structure sheaf on described substrate, described structure sheaf comprises: low K dielectric layer, be positioned at the groove of described low K dielectric layer and be positioned at barrier layer and the metal copper layer of described groove; Wherein, described structure sheaf is formed with groove; And
Be positioned at the dielectric capping layer on described structure sheaf, described dielectric capping layer by described groove and described structure sheaf card with.
In copper interconnection structure provided by the invention and forming method thereof, by forming groove on structure sheaf, make dielectric capping layer by described groove and described structure sheaf card and, namely pass through card physically and make described dielectric capping layer and described structure sheaf compact siro spinning technology, namely the adhesive force between dielectric capping layer and metal copper layer is improved, avoid copper to diffuse in low K dielectric layer, improve the reliability of device.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing copper interconnection structure;
Fig. 2 is the schematic flow sheet of the formation method of the copper interconnection structure of the embodiment of the present invention;
Fig. 3 a ~ 3d is the generalized section of the formation method of the copper interconnection structure of the embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, copper interconnection structure that the present invention proposes and forming method thereof is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2, it is the schematic flow sheet of the formation method of the copper interconnection structure of the embodiment of the present invention.As shown in Figure 2, the formation method of shown copper interconnection structure comprises following processing step:
S20: substrate is provided;
S21: form structure sheaf over the substrate, described structure sheaf comprises: low K dielectric layer, be positioned at the groove of described low K dielectric layer and be positioned at barrier layer and the metal copper layer of described groove;
S22: etch described structure sheaf, to form groove on described structure sheaf;
S23: form dielectric capping layer on described structure sheaf, described dielectric capping layer by described groove and described structure sheaf card with.
Concrete, please refer to Fig. 3 a ~ 3d, it is the generalized section of the formation method of the copper interconnection structure of the embodiment of the present invention.
As shown in Figure 3 a, substrate 30 is provided, at this, described substrate 30 comprise semiconductor base 31 and the layer dielectric cap 32 that is positioned on described semiconductor base 31 (for distinguish with the dielectric capping layer of follow-up formation, at this, this layer of dielectric capping layer is called layer dielectric cap 32).Concrete, described semiconductor base 31 can be formed with classes of semiconductors device and metal (copper) interconnection line, the application is not construed as limiting this.
Then, as shown in Figure 3 b, described substrate 30 forms structure sheaf 40, described structure sheaf 40 comprises: low K dielectric layer 41, is positioned at the groove 42 of described low K dielectric layer 41, is positioned at barrier layer 43 and the metal copper layer 44 of described groove 42.Concrete, form described structure sheaf 40 by following processing step:
First, as shown in Fig. 3 b-1, described substrate 30 forms low K dielectric layer 41, the material of described low K dielectric layer 41 can for organic polymer, amorphous chlorination carbon, microminiature foamed plastics, include organic polymer Silicon On Insulator, be doped with the Si oxide of carbon and be doped with the Si oxide etc. of chlorine.
Then, as shown in Fig. 3 b-2, etch described low K dielectric layer 41, to form groove 42 in described low K dielectric layer 41, described groove 42 exposes substrate 30, at this, exposes semiconductor base 31.Concrete, described groove 42 is formed by dual damascene process or single Damascus technics.Wherein, due to the characteristic of etching technics, the part low K dielectric layer near described groove 42 will be subject to certain damage.Concrete, the part low K dielectric layer near described groove 42 will become relative to the part low K dielectric layer away from described groove 42 and more loosen, has more gap etc.Wherein, the cross-sectional width of the part low K dielectric layer (the part low K dielectric layer of the close described groove 42 namely mentioned above) of damaged is generally 50 dust ~ 150 dusts, and the width namely from the sidewall of groove 42 is the low K dielectric layer of 50 dust ~ 150 dusts.
Then, as shown in Fig. 3 b-3, form barrier layer 44, described barrier layer 44 covers diapire and the sidewall of described low K dielectric layer 41 surface and groove 42.At this, form described barrier layer 44 by the existing semiconductor technology such as physical gas-phase deposition, chemical vapor deposition method, the material on described barrier layer 44 can be one or more in Ta, TaN, Ti and TiN.
Then, as shown in Fig. 3 b-4, described barrier layer 44 forms metal copper layer 45, wherein, described metal copper layer 45 fills full described groove 42 and part overflows described groove 42.Concrete, first can form copper seed layer on described barrier layer 44, described copper seed layer is by the formation such as physical gas-phase deposition or chemical vapor deposition method; Then, copper electroplating layer in described copper seed layer, final formation metal copper layer 45.
Then, as shown in Fig. 3 b-5, chemical mechanical milling tech is performed to described barrier layer 44 and metal copper layer 45, remove the barrier layer 44 outside described groove 42 and metal copper layer 45.Just structure sheaf 40 is defined by above-mentioned technique, described structure sheaf 40 comprises: low K dielectric layer 41, be positioned at the groove 42 of described low K dielectric layer 41, be positioned at barrier layer 43 and the metal copper layer 44 of described groove 42, namely described barrier layer 43 and metal copper layer 44 are full of described groove 42.
Then, as shown in Figure 3 c, described structure sheaf 40 is etched, to form groove 46 on described structure sheaf 40.Preferably, described groove 46 is positioned on described low K dielectric layer 41, and described groove 46 presses close to described groove 42, and namely described groove 46 presses close to barrier layer 44, and that is, on the part low K dielectric layer 41 of damaged, etching forms described groove 46.At this, by low K dielectric layer 41 described in DHF (hydrogen fluoride of dilution) solution etches, form described groove 46.At this, only need can form described groove 46 by simple etching process, mainly make use of the characteristic that the corrosion rate of the part low K dielectric layer 41 of damaged is fast compared with other partial corrosion speed, thus just can form groove 46 by simple technique.In other embodiments of the invention, also can form described groove 46 in its elsewhere of structure sheaf 40, such as, on barrier layer 44, metal copper layer 45 or the part low K dielectric layer 41 not by aforementioned etching technics damage, the application is not construed as limiting this.
It should be noted that, as a preferred version of the application, the groove 46 of the application is formed by simple DHF solution corrosion technique, it makes use of the characteristic that inventor finds in semiconductor fabrication process, thus can Simplified flowsheet greatly, reduce production cost.
Then, as shown in Figure 3 d, described structure sheaf 40 forms dielectric capping layer 50, described dielectric capping layer 50 by described groove 46 and described structure sheaf 40 block with.Concrete, described dielectric capping layer 50 is formed by the existing semiconductor technology such as physical gas-phase deposition, chemical vapor deposition method, described dielectric capping layer 50 covers the surface of described structure sheaf 40 and fills up described groove 46, thus, by this kind card and mode and structure sheaf 40 compact siro spinning technology, namely improve the adhesive force between dielectric capping layer 50 and metal copper layer 45, avoid copper to diffuse in low K dielectric layer 41, improve the reliability of device.
Finally, define copper interconnection structure 3 by the formation method of above-mentioned copper interconnection structure, please continue to refer to Fig. 3 d, described copper interconnection structure 3 comprises:
Substrate 30;
Be positioned at the structure sheaf 40 on described substrate 30, described structure sheaf 40 comprises: low K dielectric layer 41, be positioned at the groove 42 (can corresponding reference diagram 3b-2) of described low K dielectric layer 41 and be positioned at barrier layer 44 and the metal copper layer 45 of described groove 42; Wherein, described structure sheaf 40 is formed with groove 46 (can corresponding reference diagram 3c); And
Be positioned at the dielectric capping layer 50 on described structure sheaf 40, described dielectric capping layer 50 by described groove 46 and described structure sheaf 40 block with.
Thus, by this kind of card and mode make described dielectric capping layer 50 and structure sheaf 40 compact siro spinning technology, namely improve the adhesive force between dielectric capping layer 50 and metal copper layer 45, avoid copper to diffuse in low K dielectric layer 41, improve the reliability of device.
Foregoing description is only the description to present pre-ferred embodiments, any restriction not to the scope of the invention, and any change that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, modification, all belong to the protection range of claims.
Claims (7)
1. a formation method for copper interconnection structure, is characterized in that, comprising:
Substrate is provided;
Form structure sheaf over the substrate, described structure sheaf comprises: low K dielectric layer, be positioned at the groove of described low K dielectric layer and be positioned at barrier layer and the metal copper layer of described groove;
Etch described structure sheaf, to form groove on described structure sheaf, etch described low K dielectric layer by the hydrogen fluoride solution of dilution, form described groove, described groove is positioned on described low K dielectric layer, and described groove presses close to described groove;
Described structure sheaf forms dielectric capping layer, described dielectric capping layer by described groove and described structure sheaf card with.
2. the formation method of copper interconnection structure as claimed in claim 1, it is characterized in that, the technique forming structure sheaf over the substrate comprises the steps:
Form low K dielectric layer over the substrate;
Etch described low K dielectric layer, to form groove in described low K dielectric layer;
Form barrier layer, described barrier layer covers diapire and the sidewall of described low K dielectric layer surface and groove;
Described barrier layer forms metal copper layer;
Chemical mechanical milling tech is performed to described barrier layer and metal copper layer, removes the barrier layer outside described groove and metal copper layer.
3. the formation method of the copper interconnection structure as described in any one in claim 1 to 2, is characterized in that, the degree of depth of described groove is 50 dust ~ 150 dusts.
4. the formation method of the copper interconnection structure as described in any one in claim 1 to 2, is characterized in that, the cross-sectional width of described groove is 50 dust ~ 150 dusts.
5. the formation method of the copper interconnection structure as described in any one in claim 1 to 2, is characterized in that, the material of described dielectric capping layer is one or more in SiC, SiN and SiCN.
6. the formation method of the copper interconnection structure as described in any one in claim 1 to 2, is characterized in that, the material on described barrier layer is one or more in Ta, TaN, Ti and TiN.
7. the formation method of the copper interconnection structure as described in any one in claim 1 to 6 the copper interconnection structure that formed, it is characterized in that, comprising:
Substrate;
Be positioned at the structure sheaf on described substrate, described structure sheaf comprises: low K dielectric layer, be positioned at the groove of described low K dielectric layer and be positioned at barrier layer and the metal copper layer of described groove; Wherein, described structure sheaf is formed with groove; And
Be positioned at the dielectric capping layer on described structure sheaf, described dielectric capping layer by described groove and described structure sheaf card with.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6156642A (en) * | 1999-03-23 | 2000-12-05 | United Microelectronics Corp. | Method of fabricating a dual damascene structure in an integrated circuit |
| CN102364673A (en) * | 2011-11-10 | 2012-02-29 | 上海华力微电子有限公司 | Method for forming copper interconnection structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1832126A (en) * | 2005-03-08 | 2006-09-13 | 联华电子股份有限公司 | Manufacturing method of in-connection and manufacturing method of composite dielectric barrier-layer |
| US7348672B2 (en) * | 2005-07-07 | 2008-03-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnects with improved reliability |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6156642A (en) * | 1999-03-23 | 2000-12-05 | United Microelectronics Corp. | Method of fabricating a dual damascene structure in an integrated circuit |
| CN102364673A (en) * | 2011-11-10 | 2012-02-29 | 上海华力微电子有限公司 | Method for forming copper interconnection structure |
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