DE102016118207A1 - SEMICONDUCTOR DEVICE AND METHOD FOR THE PRODUCTION THEREOF - Google Patents

Abstract

A semiconductor device includes a first gate structure, a second gate structure, a first source / drain structure, and a second source / drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source / drain structure includes a first source / drain conductive layer and a second cap insulating layer disposed over the first source / drain conductive layer. The second source / drain structure includes a second source / drain conductive layer and a second conductive contact layer disposed over the second source / drain conductive layer.

Description

RELATED APPLICATIONS

This application claims priority from US Provisional Application No. 62 / 273,378, filed Dec. 30, 2015, the entire contents of which are incorporated herein by reference.

TECHNICAL AREA

The disclosure relates to a method of manufacturing a semiconductor device, and more particularly to a structure and method of manufacturing a self-aligned contact or a sacrificial layer over source / drain regions.

GENERAL PRIOR ART

With the decrease in the dimensions of semiconductor devices, a sacrificial layer structure (SAC) is widely used to provide e.g. B. in a field effect transistor (FET) source / drain (S / D) to make contacts that are closer to gate structures. Typically, an SAC is made by patterning an interlayer dielectric (ILD) layer on a gate structure and between sidewall spacers. The SAC layer is formed by a dielectric filling and a planarization after etch back of the metal gate. The SAC layer on the gate, typically as a nitride, produces good etch selectivity on the S / D as compared to the dielectric of the ILD, which is typically an oxide. This selective etching process improves the S / D contact process window. With the increase in the device density (i.e., the decrease in the dimensions of the semiconductor device), the thickness of the sidewall spacer becomes thinner, which may cause a short circuit between the S / D contact and the gate electrodes. Accordingly, it has been necessary to provide SAC structures to achieve the process window of establishing electrical isolation between the S / D contacts and gate electrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detailed description when read with the accompanying drawings. It is emphasized that various features are not drawn to scale according to standard practice in the industry and are used for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of the meeting.

1A FIG. 12 is an exemplary plan view (seen from above) illustrating a stage of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. FIG. 1B shows an exemplary sectional view along the line X1-X1 in 14A , 1C is an enlarged view of the in 1B shown gate structure. 1D FIG. 12 is an exemplary perspective view illustrating a stage of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. FIG.

2 to 13 10 are exemplary sectional views illustrating various stages of the sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure.

14 to 23 10 are exemplary sectional views illustrating various stages of the sequential manufacturing process of a semiconductor device according to another embodiment of the present disclosure.

24 shows an exemplary sectional view illustrating one of the advantages of the present embodiments.

25 FIG. 12 shows an example layout structure according to an embodiment of the present disclosure. FIG.

DETAILED DESCRIPTION

It should be understood that the following disclosure provides many different embodiments or examples for practicing various features of the invention. Hereinafter, certain embodiments of or examples of components and arrangements will be described to simplify the present disclosure. Of course these are just examples and should not be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired characteristics of the device. Moreover, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which between the first and second features Feature additional features can be formed so that the first and the second feature may not be in direct contact. Various features may be arbitrarily drawn at different scales for simplicity and clarity.

Further, spatially referenced terms such as "below,""below,""below,""above,""above," and the like may be used herein for ease of description to refer to the relationship of an element or feature as illustrated in the figures ) describe another element (s) or feature (s). The spatially referenced expressions, in addition to the orientation shown in the figures, are intended to encompass different orientations of the device in use or in operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial descriptors used herein may also be interpreted accordingly. In addition, the term "consisting of" may mean either "comprising" or "consisting of".

1A and 1B show a stage of a sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. 1A shows a plan view (a view in plan) and 1B shows a sectional view taken along the line X1-X1 in 1A ,

1A and 1B show a structure of a semiconductor device after metal gate structures have been formed. In 1A and 1B are metal gate structures 40 over a channel layer, for example a portion of one above a substrate 10 formed fin construction 20 , educated. The metal gate structures 40 include a first to fourth metal gate structure 40A . 40B . 40C and 40D and extend in the Y direction and are arranged in the X direction. The thickness of the metal gate assemblies 40 in some embodiments ranges from about 20 nm to about 80 nm. Each of the gate structures 40 includes a gate dielectric layer 42 a metal gate electrode 44 and sidewall spacers 46 at main sidewalls of the metal gate electrode 44 are provided. The sidewall spacers 46 consist of at least one of SiN, SiON, SiCN or SiOCN. The film thickness of the sidewall spacers 46 at the bottom of the sidewall spacers, in some embodiments, ranges from about 3 nm to about 15 nm, and in other embodiments, from about 4 nm to about 8 nm. Further, in addition to the gate structures, source / drain regions 25 and are spaces between the gate structures with a first interlayer dielectric (ILD) layer 50 filled. The first ILD layer 50 comprises one or more layers of an insulating material such as SiO ₂ , SiON, SiOCN or SiCN. In one embodiment, SiO _{2 is} used. In this disclosure, a source and a drain are used interchangeably and refer "source / drain" to one of a source and a drain.

1C is an enlarged view of the gate structure. The metal gate construction 40 includes one or more layers 45 of a metal material such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi, and other conductive materials. A gate dielectric layer 42 between the channel layer and the metal gate electrode 44 comprises one or more layers of metal oxides such as a high-k metal oxide. Examples of metal oxides used for high-k dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd , Tb, Dy, Ho, Er, Tm, Yb, Lu and / or mixtures thereof. In some embodiments, there is between the channel layer and the gate dielectric layer 42 an interface dielectric layer 41 formed of, for example, silicon dioxide.

In some embodiments, there are between the gate dielectric layer 42 and the metal material 45 one or more work function regulating layers 43 inserted. The work function control layers 43 consist of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC or a multiple layer of two or more of these materials. For an n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function regulating layer, and for a p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co are used as the work function regulating layer.

In this embodiment, fin field effect transistors (FinFETs) made by a gate replacement process are used.

1D shows an exemplary perspective view of a FinFET structure.

First, a fin construction 310 over a substrate 300 produced. The fin structure includes a lower portion and an upper portion as a channel portion 315 , The substrate is, for example, a p-type silicon substrate having an impurity concentration in a range of about 1 × 10 ¹⁵ cm ^-3 to about 1 × 10 ¹⁸ cm ^-3 . In other embodiments, the substrate is an n-type silicon substrate having an impurity concentration in a range of about 1 × 10 ¹⁵ cm ^-3 to about 1 × 10 ¹⁸ cm ^-3 . Alternatively, the substrate may comprise another elemental semiconductor such as germanium; a compound semiconductor containing Group IV-IV compound semiconductors such as SiC and SiGe, Group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. At a Embodiment, the substrate is a silicon layer of a SOI (silicon on insulator) substrate.

After making the fin construction 310 will be over the construction 310 an insulation insulating layer 320 educated. The insulation insulating layer 320 comprises one or more layers of insulating materials such as silicon oxide, silicon oxynitride or silicon nitride formed by LPCVD (low pressure chemical vapor deposition), plasma CVD or flowable CVD. The insulation insulating layer may be formed by one or more layers of spin-on-glass (SOG), SiO, SiON, SiOCN, and / or fluorine-doped silicate glass (FSG).

After forming the insulation insulating layer 320 A planarization operation is performed over the fin structure to form part of the insulation insulating layer 320 to remove. The planarization activity may include a chemical mechanical polishing (CMP) and / or an etch back process. Then, the insulation insulating layer becomes 320 further (recessed), so that the upper area of the fin structure is exposed.

Over the exposed fin structure, a dummy gate structure is formed. The dummy gate structure includes a dummy gate electrode layer formed of polysilicon and a dummy gate dielectric layer. Sidewalls of the dummy gate electrode layer also have sidewall spacers 350 comprising one or more layers of insulating materials. After the formation of the dummy gate structure, the fin structure becomes 310 which is not covered by the dummy gate structure, under the upper surface of the insulation insulating layer 320 deepened. Then, a source / drain region is formed over the recessed fin structure using an epitaxial growth process 360 educated. The source / drain region may include a strain material to access the channel region 315 to exercise a strain.

Then, over the dummy electrode assembly and the source / drain region 360 an interlayer dielectric (ILD) layer 370 educated. After a planarization operation, the dummy gate assembly is removed to create a gate space. Then, in the gate room, a metal gate assembly 330 formed comprising a metal gate electrode and a gate dielectric layer such as a high-k dielectric layer. In 1D is the view of parts of the metal gate construction 330 , the side walls 330 and the ILD 370 cut to show the underlying structure.

The metal gate construction 330 and the side walls 330 , the source / the drain 360 and the ILD 370 from 1D essentially correspond to the metal gate structure, respectively 40 , the source / drain regions 25 and the first interlayer dielectric layer (ILD) 50 from 1A and 1B ,

2 to 13 show exemplary sectional views taken along the line X1-X1 in FIG 1A and illustrate various stages of the sequential manufacturing process of a semiconductor device according to an embodiment of the present disclosure. It is understood that before, during and after the processes by 2 to 13 may be provided, additional activities may be provided, and that some of the activities described below may be substituted or eliminated for additional embodiments of the method. The sequence of activities / processes can be interchangeable.

As in 2 the metal gate electrodes are shown 44 by a dry and / or a wet etching process under the upper surface of the sidewall spacers 46 deepened. The remaining height H1 of the recessed gate electrode 44 is in a range of about 15 nm to about 50 nm in some embodiments.

After the gate electrodes 44 are deepened, as in 2 shown a first cover layer 61 formed from a first insulating material. The first insulating material includes one or more of SiC, SiON, SiOCN, SiCN and SiN.

At the top layer 61 For example, a planarizing operation such as an etch back process or a chemical mechanical polishing (CMP) process is performed to allow the gate cap insulating layers 60 over the gate electrode 44 be formed as in 3 is shown.

As in 4 the first ILD layer is shown 50 removed by a dry and / or a wet etching, whereby openings 65 are formed and the source / drain regions 25 at the bottoms of the openings 65 be exposed.

Subsequently, a cover layer of a first conductive material 71 formed as in 5 is shown. The first conductive material 71 includes one or more of W, Co, Ni or Ti. At the interface between the first conductive material 71 and the source / drain structure 25 For example, a silicide layer such as WSi, CoSi ₂ or TiSi may be formed. In one embodiment, W is used.

At the top layer 71 For example, a planarization operation, such as an etch back process or a CMP process, is performed over the source / drain regions 25 the source / drain conductive layers 70 be formed as in 6 is shown.

Then be like in 7 show the source / drain conductive layers 70 by a dry and / or wet etch action under the top surface of the sidewall spacers 46 deepened. The remaining height H2 of the source / drain conductive layer 70 is in a range of about 15 nm to about 50 nm in some embodiments.

Subsequently, as in 8th shown a cover layer of a second insulating material 81 educated. The second insulating material 81 differs from the first insulating material 61 and comprises one or more of SiC, SiON, Al ₂ O ₃ , SiOCN, SiCN and SiN. The two materials for the first and second insulating materials are interchangeable to meet different process requirements.

At the top layer 81 For example, a planarization operation, such as an etch back process or a CMP process, is performed over the source / drain conductive layers 70 Source / drain Kappenisolierschichten 80 be formed as in 9 is shown. As in 9 As shown, a plurality of gate structures extending in the Y direction are arranged at equal intervals in the X direction. Each of the gate structures comprises a gate electrode 44 a gate cap insulating layer 60 that over the gate electrode 44 is arranged, and sidewall spacers 46 located on opposite side surfaces of the gate electrode 44 and the gate cap insulating layer 60 are arranged. Furthermore, a plurality of source / drain structures are arranged between two adjacent gate structures. Each of the source / drain structures comprises a source / drain conductive layer 70 and a source / drain cap insulating layer 80 passing over the source / drain conductive layer 70 is arranged.

The thickness H3 of the gate cap insulating layer 60 is in a range of about 10 nm to about 40 nm in some embodiments. The thickness H4 of the source / drain cap insulating layer 80 in some embodiments ranges from about 10 nm to about 40 nm.

Next, as in 10 shown at least one gate structure (eg, the gate structures 40C and 40D ) and at least one source / drain structure having the source / drain cap insulating layer through a first mask layer 72 while at least one gate structure (eg. 40A and 40B ) and at least one source / drain structure are exposed with the source / drain cap insulating layer. Then, the gate cap insulating layers become 60 selectively removes a gate opening 85 is formed.

Here, the gate cap insulating layer exists 60 , the source / drain cap insulating layer 80 and the sidewall spacers 45 made of different insulating materials. In particular, the source / drain cap insulating layer is 80 and the sidewall spacers 45 Materials having a high etch selectivity (about 4 or more) over the gate cap insulating layer 60 during etching of the gate cap insulating layer 60 , In some embodiments, the etch selectivity is about 6 to 20. Accordingly, the gate cap insulating layer 60 be selectively removed in a self-aligned manner. As in 10 an edge of the opening structure of the first mask layer can be shown 72 on at least one source / drain cap insulating layer 80 are located.

In some embodiments, the structure of 9 before the formation of the first mask layer 72 a second ILD layer 110 (please refer 24 ) composed of, for example, SiO ₂ (or one or more of SiON, SiOCN, SiCN or SiCO). In such a case, first the second ILD is made using the first mask layer 72 etched as an etch mask, and then become the gate cap insulating layers 60 etched. The etching condition for the etching of the second ILD may be different from the etching condition for the etching of the gate cap insulating layers.

In the same way as in 11 shown at least one gate structure (eg, the gate structures 40A and 40A ) and at least one source / drain structure having the source / drain cap insulating layer through a second mask layer 74 while at least one gate structure (eg. 40D ) and at least one source / drain structure are exposed with the source / drain cap insulating layer. Then, the source / drain cap insulating layers become 80 selectively removed, creating a source / drain opening 87 is formed. Here are the gate cap insulating layer 60 and the sidewall spacers 45 Materials having a high etch selectivity (about 4 or more) over the source / drain capping insulating layer 80 during the etching of the source / drain cap insulating layer 80 , In some embodiments, the etch selectivity is about 6 to 20. Accordingly, the source / drain cap insulating layer may be 80 be selectively removed in a self-aligned manner. As in 11 an edge of the opening structure of the second mask layer can be shown 74 on at least one gate cap insulating layer 60 are located.

The order of removal of the gate cap insulating layer 60 and removing the source / drain cap insulating layer 80 is exchangeable.

Subsequently, as in 12 shown a cover layer 101 formed of a second conductive material. The second conductive material comprises one or more of Cu, W, Co, Ni, Ti or an alloy thereof.

As in 13 is shown on the cover layer 101 a planarization operation such as an etch back process or a CMP process is performed so that over the gate electrode and the source / drain conductive layers 70 Gate contact layers 100 and source / drain contact layers 105 be formed.

It is understood that the device used in 13 is subjected to further CMOS processes to form various features such as interconnect metal layers, dielectric layers, passivation layers, and so on.

14 to 23 10 are exemplary sectional views illustrating various stages of the sequential manufacturing process of a semiconductor device according to another embodiment of the present disclosure. It is understood that before, during and after the processes by 14 to 23 may be provided, additional activities may be provided, and that some of the activities described below may be substituted or eliminated for additional embodiments of the method. The sequence of activities / processes can be interchangeable. As for the configurations, structures, materials, processes and / or activities, in this embodiment, substantially the same as the above embodiment can be applied, and their detailed explanation can be omitted.

After the formation of the construction of 3 becomes at least one of the source / drain regions with the first ILD 50 through a mask layer 53 covered, as in 13 is shown. The mask layer 53 includes a hardmask layer 52 and an organic resin layer 54 , The hard mask layer 52 comprises one or more layers of TiN, SiN, Ti, Si, TiO ₂ and SiO ₂ . In one embodiment, a stacked layer of SiO ₂ / Si / SiO _{2 is} used. On the silicon / oxide stacking layer of the hardmask layer 52 becomes a photoresist layer or a bottom anti-reflective coating layer 54 educated.

By using the mask layer 53 the first ILD layers are used as the etching mask 50 from the source / drain regions that are not from the mask layer 53 are covered, removed.

Then it will be similar to in 5 a cover layer of a first conductive material 71 formed as in 15 is shown. Before forming the first conductive material layer, at least the organic resin layer becomes 54 away. Subsequently, the cover layer is applied 71 a planarization operation such as an etch back process or a CMP process is performed to allow the source / drain conductive layers 70 over the source / drain regions 25 be formed as in 16 is shown. The planarization activity becomes the hard mask layer 52 away.

Next will be similar to in 7 the source / drain conductive layers 70 by a dry and / or wet etch action under the top surface of the sidewall spacers 46 deepened, as in 17 is shown.

Subsequently, similar to in 8th a cover layer of a second insulating material 81 formed as in 18 is shown. Similar to in 9 gets on the topcoat 81 a planarization operation such as an etch back process or a CMP process is performed to allow the source / drain cap insulating layers 80 over the source / drain conductive layers 70 be formed as in 19 is shown.

Next will be similar to in 10 at least one gate structure (eg the gate structures 40C and 40D ) and at least one source / drain structure having the source / drain cap insulating layer through a first mask layer 72 while at least one gate structure (eg. 40A and 40B ) and at least one source / drain structure are exposed with the source / drain cap insulating layer. Then, the gate cap insulating layers become 60 selectively removed, creating a gate opening 85 is formed as in 20 is shown. As in 20 an edge of the opening structure of the first mask layer can be shown 72 on the first ILD layer 50 located on at least one source / drain area 25 is arranged.

Here, the gate cap insulating layer exists 60 , the source / drain cap insulating layer 80 , the sidewall spacer 45 and the first ILD layer 50 made of different insulating materials. In particular, the source / drain cap insulating layer is 80 , the sidewall spacer 45 and the first ILD layer 50 Materials having a high etch selectivity (about 4 or more) over the gate cap insulating layer 60 during etching of the gate cap insulating layer 60 , In some embodiments, the etch selectivity is about 6 to 20. Accordingly, the gate cap insulating layer 60 be selectively removed in a self-aligned manner.

Similar to in 11 be at least one gate structure (eg., The gate structures 40A and 40B ) and at least one source / drain structure having the source / drain cap insulating layer through a second mask layer 74 while at least one gate structure (eg. 40D ) and at least one source / drain structure are exposed with the source / drain cap insulating layer. Then, the source / drain cap insulating layer becomes 80 selectively removed, creating a source / drain opening 87 is formed as in 21 is shown. As in 21 an edge of the opening structure of the second mask layer can be shown 74 on at least one gate cap insulating layer.

The order of removal of the gate cap insulating layer 60 and removing the source / drain cap insulating layer 80 is exchangeable.

Subsequently, similar to in 12 a cover layer 101 formed of a second conductive material, as in 22 is shown. At the top layer 101 For example, a planarization operation, such as an etch back process or a CMP process, is performed over the gate electrode 44 and the source / drain conductive layers 70 Gate contact layers 100 and source / drain contact layers 105 be formed as in 23 is shown.

It is understood that in 23 is subjected to further CMOS processes to form various features such as interconnect metal layers, dielectric layers, passivation layers, and so on.

The various embodiments or examples described herein offer several advantages over the existing art.

24 shows an exemplary sectional view illustrating one of the advantages of the present invention.

24 Fig. 12 illustrates the structure when a mask pattern having an opening (eg, a via structure) over the gate electrode 44 For example, due to a process variation, the amount D1 is shifted to the left. The mask structure becomes the second ILD layer 110 etched and then becomes the gate cap insulating layer 60 etched. Due to misalignment, etching of a portion of the sidewall spacers may occur 46 and / or a portion of the source / drain cap insulating layer 80 come. However, because the etch selectivity of the sidewall spacers 46 and the source / drain cap insulating layer 80 opposite the gate cap insulating layer 60 is sufficiently high, the extent of such etching can be minimized. Accordingly, the gate contact 100 can be formed in a self-aligned manner and becomes a short circuit to the source / drain conductive layer 70 avoided.

Similarly, as in 24 10 illustrates a mask structure having an opening (eg, a via structure) over the source / drain conductive layer 70 for example, be shifted to the right by the extent D2 due to a process fluctuation. The mask structure becomes the second ILD layer 110 etched, and then becomes the source / drain cap insulating layer 80 etched. Due to misalignment, etching of a portion of the sidewall spacers may occur 46 and / or a part of the gate cap insulating layer 60 come. However, because the etch selectivity of the sidewall spacers 46 and the gate cap insulating layer 60 opposite the source / drain cap insulating layer 80 is sufficiently high, the extent of such etching can be minimized. Accordingly, the source / drain contact 105 be formed in a self-aligning manner and becomes a short circuit to the gate electrode 44 avoided.

Due to the above advantages of the self-aligning contacts, it is also possible to reduce a gate structure density.

25 FIG. 12 shows an example layout structure according to an embodiment of the present disclosure. FIG. 25 shows an exemplary design structure around a cell boundary of two standard cells.

In 25 For example, four gate structures P40 extending in the Y direction are arranged at equal intervals in the X direction. Between two adjacent gate structures, source / drain structures P70 are arranged. Over the gate structures, gate contact structures P100A are arranged over a fin structure P20. In addition, a gate contact structure P100B is disposed over the gate structures over a region other than the fin structures P20. Over the source / drain structures P70, source / drain contacts P105 are arranged.

Because the gate contact 100 in the present embodiment, in a self-aligned manner substantially free of a short circuit to the source / drain conductive layer 70 may be formed, the gate contact structure P100A (the gate contact 100 ) over the fin structure P20 (the fin structure 20 ), in which the source / drain structures P70 (the source / drain conductive layer 70 ), as in the area A1 of FIG 25 is shown.

Similarly, in the range A2 of 25 the gate contact structure P100B may be arranged closer to the fin structure P20. The distance S1 between the gate contact structure P100B and the fin structure P20 is less than about 15 nm and, in some embodiments, is in a range of about 5 nm to about 12 nm.

Accordingly, it is possible to reduce a gate pattern density.

It will be understood that not all advantages have been necessarily discussed here, that no particular advantage is required for all embodiments or examples, and other embodiments or examples may provide other advantages.

According to one aspect of the present disclosure, in a method of manufacturing a semiconductor device, gate structures extending in a first direction and arranged in a second direction crossing the first direction are formed. Each of the gate structures includes a gate electrode, a gate cap insulating layer disposed over the gate electrode, and sidewall spacers disposed on opposite faces of the gate electrode and the gate cap insulating layer. Between two adjacent gate structures, source / drain structures are formed. Each of the source / drain structures includes a source / drain conductive layer and a source / drain cap insulating layer disposed on the source / drain conductive layer. The gate cap insulating layer is selectively removed from at least one of the gate structures while protecting at least one of the remaining gate structures, thereby exposing the gate electrode of the at least one of the gate structures. The source / drain cap insulating layer is selectively removed from at least one of the source / drain structures while protecting at least one of the remaining source / drain structures, thereby exposing the source / drain conductive layer of the at least one of the source / drain structures , Conductive contact layers are formed on the exposed gate electrode and the exposed source / drain conductive layer.

According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure extending in a first direction are formed over a substrate educated. The first gate structure includes a first gate electrode, a first gate dielectric layer, and first sidewall spacers disposed on opposite side surfaces of the first gate electrode. The second gate structure includes a second gate electrode, a second gate dielectric layer, and second sidewall spacers disposed on opposite side surfaces of the second gate electrode. The third gate structure includes a third gate electrode, a third gate dielectric layer, and third sidewall spacers disposed on opposite sides of the third gate electrode. The fourth gate structure includes a fourth gate electrode, a fourth gate dielectric layer, and fourth sidewall spacers disposed on opposite side surfaces of the fourth gate electrode. The first to fourth gate structures are arranged in a second direction crossing the first direction. A first source / drain region is formed between the first and second gate structures, a second source / drain region is formed between the second and third gate structures, and a second source / drain region is formed between the third and fourth gate structures third source / drain region formed. Over the first to third source / drain region, a first insulating layer is formed. The first to fourth gate electrodes are recessed below upper surfaces of the first to fourth sidewall spacers, thereby forming first through fourth gate openings, respectively. In each of the first to fourth gate openings, first to fourth gate cap insulating layers are formed. The first insulating layer is removed to expose the first and third source / drain regions. A first and a third source / drain conductive layer are respectively formed over the first and the third source / drain regions. The first and third source / drain conductive layers are recessed below upper surfaces of the first to fourth sidewall spacers, thereby forming first and third source / drain openings, respectively. In each of the first and third source / drain openings, first and third source / drain cap insulating layers are formed. The first and second gate cap insulating layers are removed while protecting the third and fourth gate cap insulating layers and the third source / drain cap insulating layer, thereby exposing the first and second gate electrodes. The third source / drain cap insulating layer is removed while protecting the first source / drain cap insulating layer, thereby exposing the third source / drain region. Conductive contact layers are formed on the exposed first and second gate electrodes and the exposed third source / drain region.

According to still another aspect of the present disclosure, a semiconductor device includes a first gate structure, a second gate structure, a first source / drain structure, and a second source / drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed over the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source / drain structure includes a first source / drain conductive layer and a second cap insulating layer disposed over the first source / drain conductive layer. The second source / drain structure includes a second source / drain conductive layer and a second conductive contact layer disposed over the second source / drain conductive layer.

The above outlines features of several embodiments or examples so that those skilled in the art can better understand the aspects of the present disclosure. It should be appreciated by those skilled in the art that they may readily use the present disclosure as a basis for designing or modifying other processes and constructions to accomplish the same purposes and / or to achieve the same advantages as the embodiments or examples presented herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

A method of manufacturing a semiconductor device, the method comprising: Forming gate structures extending in a first direction and arranged in a second direction crossing the first direction, each of the gate structures comprising a gate electrode, a gate cap insulating layer disposed over the gate electrode, and sidewall capping layers; Spacer disposed on opposite surfaces of the gate electrode and the gate cap insulating layer comprises; Forming source / drain structures between two adjacent gate structures, each of the source / drain structures comprising a source / drain conductive layer and a source / drain cap insulating layer disposed on the source / drain conductive layer; selectively removing the gate cap insulating layer from at least one of the gate structures while protecting at least one of the remaining gate structures, thereby exposing the gate electrode of the at least one of the gate structures; selectively removing the source / drain cap insulating layer of at least one of the source / drain structures while protecting at least one of the remaining source / drain structures, thereby exposing the source / drain conductive layer of the at least one of the source / drain structures; and Forming conductive contact layers on the exposed gate electrode and the exposed source / drain contact layer. The method of claim 1, wherein in selectively removing the gate cap insulating layer at least one source / drain cap insulating layer is not protected. The method of claim 1 or 2, wherein in the selective removal of the source / drain cap insulating layer at least one gate insulating layer is not protected. Method according to one of the preceding claims, wherein in the selective removal of the gate cap insulating layer, the at least one of the remaining gate structures is protected by a protective structure, and an edge of the protective structure is on at least one source / drain cap insulating layer. Method according to one of the preceding claims, wherein in the selective removal of the source / drain cap insulating layer, the at least one of the remaining source / drain structures is protected by a protective structure, and an edge of the protective structure is located on at least one gate cap insulating layer. The method of any one of the preceding claims, wherein an upper surface of the gate electrode is in a plane different from an upper surface of the source / drain conductive layer. The method of claim 6, wherein the top surface of the gate electrode is located in a lower plane than the top surface of the source / drain conductive layer. The method of any one of the preceding claims, wherein the gate cap insulating layer is made of a different material than the source / drain cap insulating layer. The method of claim 8, wherein the gate cap insulating layer and the source / drain cap insulating layer are made of at least one of SiC, SiOCN, SiON, SiCN and SiN. The method of any one of the preceding claims, wherein the sidewall spacers are made of a different material than the gate cap insulating layer and the source / drain cap insulating layer. The method of claim 10, wherein the sidewall spacers are made of at least one of SiC, SiON, Al ₂ O ₃ ; SiOCN, SiCN and SiN exist. A method of manufacturing a semiconductor device, the method comprising forming a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure extending in a first direction over a substrate, wherein the first gate structure comprises a first gate electrode, a first gate dielectric layer, and first Sidewall spacers disposed on opposite side surfaces of the first gate electrode, the second gate structure comprising a second gate electrode, a second gate dielectric layer, and second sidewall spacers disposed on opposite side surfaces of the second gate electrode, the third gate Comprises a third gate dielectric layer, and third sidewall spacers disposed on opposite sides of the third gate electrode, the fourth gate structure comprises a fourth gate electrode, a fourth gate dielectric layer, and fourth sidewall spacers disposed on opposite side surfaces of the fourth gate electrode are disposed, and the first to fourth gate structures are arranged in a second direction crossing the first direction; Forming a first source / drain region between the first and second gate structures, a second source / drain region between the second and third gate structures, and a third source / drain structure between the third and fourth gates -Construction; Forming a first insulating layer over the first to third source / drain regions; Recessing the first to fourth gate electrodes under upper surfaces of the first to fourth sidewall spacers, thereby forming first to fourth gate openings, respectively; respectively forming first to fourth gate cap insulating layers in the first to fourth gate openings; Removing the first insulating layer to expose the first and third source / drain regions; respectively forming first and third source / drain conductive layers over the first and third source / drain regions; Recessing the first and third source / drain conductive layers below upper surfaces of the first to fourth sidewall spacers, thereby forming first and third source / drain openings, respectively; respectively forming first and third source / drain cap insulating layers in the first and third source / drain openings; Removing the first and second gate cap insulating layers while protecting the third and fourth gate cap insulating layers and the third source / drain cap insulating layer, thereby exposing the first and second gate electrodes; Removing the third source / drain cap insulating layer while protecting the first source / drain cap insulating layer, thereby exposing the third source / drain region; and forming conductive contact layers on the exposed first and second gate electrodes and the exposed third source / drain region. The method of claim 12, wherein in removing the first insulating layer to expose the first and third source / drain regions, the second source / drain region is protected and the first insulating layer formed over the second source / drain region , not removed. The method of claim 12 or 13, wherein the first to fourth gate cap insulating layers are made of a different material than the first and third source / drain cap insulating layers, the first to fourth gate cap insulating layers, and the first and third source / drain cap insulating layers of at least one of SiC, SiON, SiOCN, SiCN and SiN, the first to fourth sidewall spacers are made of a material other than the first to fourth gate cap insulating layers, and the first and third source / drain cap insulating layers, and the first to fourth sidewall spacers of at least one of SiC, SiON, Al ₂ O ₃ , SiOCN, SiCN and SiN exist. A semiconductor device, comprising: a first gate structure including a first gate electrode and a first cap insulating layer disposed over the first gate electrode; a second gate structure comprising a second gate electrode and a first conductive contact layer disposed on the first gate electrode; a first source / drain structure comprising a first source / drain conductive layer and a second cap insulating layer disposed over the first source / drain conductive layer; and a second source / drain structure comprising a second source / drain conductive layer and a second conductive contact layer disposed over the second source / drain conductive layer. The semiconductor device according to claim 15, wherein an upper surface of the first gate electrode is in a plane different from an upper surface of the first source / drain conductive layer. The semiconductor device according to claim 15 or 16, wherein the first cap insulating layer is made of a different material than the second cap insulating layer. The semiconductor device according to claim 17, wherein the first cap insulating layer and the second cap insulating layer are made of at least one of SiC, SiON, SiOCN, SiCN and SiN. A semiconductor device according to any one of claims 15 to 18, wherein the first gate structure is arranged next to one of the first and the second source / drain structure, between the first gate structure and the one of the first and the second source / drain structure, a spacer layer is arranged, and the spacer layer is made of a different material than the first cap insulating layer and the second cap insulating layer. The semiconductor device according to claim 19, wherein the spacer layer is composed of at least one of SiC, SiON, Al ₂ O ₃ , SiOCN, SiCN and SiN.

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