JP2009164391A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of being manufactured by a simple manufacturing method, capable of preventing a contact plug from becoming a high resistance, and causing no diffusion of constituting materials of the contact plug into a source-drain region. <P>SOLUTION: The semiconductor device has a gate electrode 4, a first interlayer dielectric 7, a first contact plug 8, a second interlayer dielectric 9, and a second contact plug 10. The top face of the first interlayer dielectric 7 has the same elevation as that of the top face of the gate electrode 4. The first contact plug 8 is formed penetrating the first interlayer dielectric 7 in the thickness direction thereof, is electrically-connected with a source-drain region 5 at the bottom face thereof, and has a first electric resistivity. The second contact plug 10 is formed penetrating the second interlayer dielectric 9 in the thickness direction thereof, is electrically-connected with the top face of the first contact plug 8 at the bottom face thereof, and has a second electric resistivity lower than the first electric resistivity. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and in particular, a semiconductor device having a contact plug that electrically connects a source / drain region of a transistor and a wiring disposed in an upper layer, and The present invention can be applied to the manufacturing method of the semiconductor device.

  Conventionally, there is a semiconductor device having a contact plug that electrically connects a source / drain region of a transistor and a wiring (for example, Patent Document 1). The arrangement is arranged above the gate electrode constituting the transistor. Therefore, the contact plug is formed from the semiconductor substrate to a position higher than the gate electrode. The semiconductor device is formed by the following process.

  First, a transistor is formed in the upper surface of the semiconductor substrate. Next, an interlayer insulating film is formed on the semiconductor substrate so as to cover the gate electrode. That is, the upper surface of the interlayer insulating film is located higher than the upper surface of the gate electrode. Next, contact holes extending from the upper surface to the source / drain regions are formed in the interlayer insulating film. Thereafter, a contact plug is formed in the interlayer insulating film by filling the contact hole with a conductive material.

Japanese Patent Laid-Open No. 10-340955

  However, with the high integration of devices, the source / drain regions of transistors have been reduced, and the contact plug diameter has also been reduced. Thus, as the diameter of the contact plug becomes smaller, the resistance of the contact plug has become higher than can be ignored. As the contact plug increases in resistance, the transistor drive current may be reduced. However, the decrease in the drive current causes performance degradation. Therefore, the increase in resistance of the contact plug accompanying the high integration of the device is a big problem.

  In order to reduce the contact plug resistance, it is effective to embed a material having a low electrical resistivity in the contact hole. Therefore, it is conceivable to use copper as the material for the contact plug. However, the contact plug made of copper is directly formed on the source / drain regions formed in the semiconductor substrate. Therefore, copper is diffused into the source / drain regions by the subsequent heat treatment. Thus, when copper diffuses into the source / drain regions, there arises a problem that the junction is broken. Even if a barrier metal is formed, copper diffusion cannot be completely prevented by the barrier metal.

  As a method for reducing the resistance of the contact plug, a configuration in which the height of the contact plug is lowered is also conceivable. However, reducing the height of the contact plug also reduces the thickness of the interlayer insulating film on which the contact plug is formed. When the interlayer insulating film thickness is reduced, a problem arises in the inter-wiring capacitance between the upper and lower layers, and the configuration is not appropriate.

  Therefore, the present invention can suppress the increase in resistance of the contact plug even if the device is highly integrated, and the diffusion of the constituent material of the contact plug into the source / drain region does not occur. It is an object of the present invention to provide a semiconductor device that can be manufactured by a simple manufacturing process and a method for manufacturing the semiconductor device.

  In one embodiment of the present invention, a semiconductor device includes a gate electrode, a first interlayer insulating film, a second interlayer insulating film, a first contact plug, and a second contact plug. The upper surface position of the first interlayer insulating film and the upper surface position of the gate electrode are the same height. The first contact plug is formed in the first interlayer insulating film and has a first electrical resistivity. The second contact plug is formed in the second interlayer insulating film and has a second electrical resistivity lower than the first electrical resistivity.

  According to the above embodiment, a semiconductor that can be manufactured by a simple manufacturing process, can suppress the increase in resistance of the contact plug, and can prevent diffusion of the constituent material of the contact plug into the electrode region. Equipment can be provided.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the present embodiment.

  In the semiconductor device, a MISFET (Metal Insulator Semiconductor Field Effect Transistor: hereinafter simply referred to as a transistor) Tr1 is formed in the upper surface of a semiconductor substrate 1 made of silicon. The transistor Tr1 is formed in a region defined by the element isolation insulating film 2 formed in the surface of the semiconductor substrate 1. That is, the transistor Tr1 is electrically isolated from other adjacent semiconductor elements by the element isolation insulating film 2. Further, the transistor Tr1 includes a gate structure G1 and source / drain regions (which can be grasped as electrode regions) 5.

  The gate structure G1 has a laminated structure in which a gate insulating film 3 and a gate electrode (which can be grasped as a first gate electrode) 4 made of polysilicon are laminated in this order. The gate insulating film 3 is formed on the upper surface of the semiconductor substrate 1. The gate electrode 4 is formed on the semiconductor substrate 1 via the gate insulating film 3. The thickness of the gate electrode 4 is about 100 nm. Note that a sidewall film SW having a multilayer structure is formed on both side surfaces of the gate structure G1. Specifically, the sidewall film SW has a laminated structure of an L-shaped silicon oxide film and a silicon nitride film formed on the silicon oxide film.

  The source / drain regions 5 are formed in the surface of the semiconductor substrate 1 on both sides of the gate structure G1. The source / drain region 5 has a two-stage configuration including an impurity diffusion region 5a having a relatively shallow diffusion depth and an impurity diffusion region 5b having a relatively large diffusion depth. A metal silicide film 6 is formed on the upper surface of the source / drain region. As the metal silicide film 6, in addition to Ni (nickel) silicide, Co (cobalt), Pt (platinum), Ti (titanium), V (vanadium), Pd (palladium), Hf (hafnium), Yb (ytterbium) , Silicide containing metal such as Er (erbium), Mo (molybdenum), W (tungsten).

  A first interlayer insulating film 7 is formed on the semiconductor substrate 1. The upper surface of the first interlayer insulating film 7 is at the same position as the upper surface of the gate electrode 4 as shown in FIG. In other words, the thickness of the first interlayer insulating film 7 is the same as the height of the gate structure G1. In the first interlayer insulating film 7, first contact plugs 8A and 8B are formed. Both first contact plugs 8A and 8B are formed so as to penetrate the first interlayer insulating film 7 in the film thickness direction.

  Specifically, both first contact plugs 8A and 8B are formed to reach the source / drain region 5 (more specifically, the metal silicide film 6) from the upper surface of the first interlayer insulating film 7. That is, the lower surfaces of the first contact plugs 8A and 8B and the source / drain regions 5 are electrically connected. The first contact plug 8A is formed on the right side of the gate structure G1 with the first interlayer insulating film 7 interposed therebetween. On the other hand, the second contact plug 8B is formed on the left side of the drawing of the gate structure G1 with the first interlayer insulating film 7 interposed therebetween. As will be described later, the first contact plug 8A also functions as a wiring for electrically connecting members formed apart in a plan view, and the first contact plug 8A is seen in a plan view in the first interlayer insulating film 7. It extends in the direction.

  Here, in the present application, the “contact plug” is a member that electrically connects the upper layer member and the lower layer member. In addition, the “wiring” is a member that is formed in a horizontal direction apart from each other and that connects the members.

  The first contact plugs 8A and 8B are composed of a barrier metal film 8a formed on the outermost side and a tungsten (W) film 8b formed on the inner side. The first contact plugs 8A and 8B have a first electrical resistivity. Here, the barrier metal film 8a is thin. That is, most of the first contact plugs 8A and 8B are composed of the tungsten film 8b.

  A second interlayer insulating film 9 is formed on the first interlayer insulating film 7. A second contact plug 10 is formed in the second interlayer insulating film 9. The second contact plug 10 is formed so as to penetrate the second interlayer insulating film 9 in the film thickness direction. Specifically, the second contact plug 10 is formed from the upper surface of the second interlayer insulating film 9 to the upper surfaces of the first contact plugs 8A and 8B. That is, the lower surface of the second contact plug 10 and the upper surfaces of the first contact plugs 8A and 8B are electrically connected.

  The second contact plug 10 is composed of a barrier metal film 10a formed on the outermost side and a copper (Cu) film 10b formed on the inner side. The second contact plug 10 has a second electrical resistivity. Here, the second electrical resistivity is lower than the first electrical resistivity. The barrier metal film 10a is thin. That is, most of the second contact plug 10 is composed of the copper film 10b.

  As the barrier metal film 10a, a single layer of TaN (tantalum nitride) or a stack of Ta (tantalum) and TaN can be employed. In addition, Ru (ruthenium), W, Mn (manganese), or a nitride, oxide, silicide, or the like thereof can be used as the barrier metal film 10a.

  A third interlayer insulating film 11 is formed on the second interlayer insulating film 9. In the third interlayer insulating film 11, a copper wiring 12 is disposed. The lower surface of the copper wiring 12 is electrically connected to the upper surface of the second contact plug 10. As can be seen from the configuration, the copper wiring 12 and the source / drain region 5 are electrically connected via the first contact plugs 8A and 8B and the second contact plug 10. The copper wiring 12 is composed of a barrier metal film 12a formed on the outermost side and a copper (Cu) film 12b formed on the inner side.

  The third interlayer insulating film 11 on which the copper wiring 12 is disposed may be a silicon oxide film, but is preferably a low relative dielectric constant film. For example, as the third interlayer insulating film 11, a low relative dielectric constant film in which a SiOC film or the like and a SiCO, SiCN, SiN film or the like are combined can be employed.

  Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described in detail with reference to process cross-sectional views.

  As shown in FIG. 2, a semiconductor substrate 1 made of silicon is prepared. Then, an element isolation insulating film 2 is formed in the surface of the semiconductor substrate 1. In FIG. 2, a region partitioned by the element isolation insulating film 2 is a transistor formation region.

  Next, an insulating film (for example, a high dielectric constant film such as a silicon oxide film, a silicon oxynitride film, or hafnium silicate) is formed on the semiconductor substrate 1. Next, a polysilicon film is formed over the insulating film. Next, a silicon oxide film is formed on the polysilicon film. Thereafter, the insulating film, the polysilicon film, and the silicon oxide film are patterned into a predetermined shape. As a result, as shown in FIG. 3, a stacked body including the gate insulating film 3, the gate electrode 4, and the hard mask HM is formed on the semiconductor substrate 1 in the transistor formation region.

  Next, impurity ions having a predetermined conductivity type are implanted into the semiconductor substrate 1 using the gate structure G1 with the hard mask HM formed thereon as a mask (first ion implantation). The first ion implantation is performed at a desired energy and a desired implantation concentration condition. Thereby, as shown in FIG. 4, impurity diffusion regions 5a having a relatively shallow diffusion depth are formed in the surface of the semiconductor substrate 1 on both sides of the gate structure G1.

  Next, a silicon oxide film s1 is formed on the semiconductor substrate 1 so as to cover the stacked body including the gate insulating film 3, the gate electrode 4, and the hard mask HM. The film thickness of the silicon oxide film s1 is relatively thin. Next, a silicon nitride film s2 is formed on the silicon oxide film s1. The film thickness of the silicon nitride film s2 is larger than the film thickness of the silicon oxide film s1. Next, anisotropic etching is performed on the silicon oxide film s1 and the silicon nitride film s2. Thereby, as shown in FIG. 5, sidewall films SW having a two-layer structure are formed on both side surfaces of the stacked body including the gate electrode 4.

  Next, impurity ions having a predetermined conductivity type are implanted into the semiconductor substrate 1 using the gate structure G1 with the hard mask HM formed on the upper portion and the sidewall films SW formed on both side surfaces as a mask (second ion implantation). ). The second ion implantation is performed at a desired energy and a desired implantation concentration condition. As a result, as shown in FIG. 6, impurity diffusion regions 5b having a relatively large diffusion depth are formed in the surface of the semiconductor substrate 1 on both sides of the gate structure G1 in which the sidewall film SW is formed on the side surface. . The impurity diffusion region 5a and the impurity diffusion region 5b form a two-stage source / drain region 5.

  Through the steps up to FIG. 6, the transistor Tr <b> 1 having at least the gate structure G <b> 1 formed on the semiconductor substrate 1 and the source / drain formed in the surface of the semiconductor substrate 1 is formed.

  Next, in the structure shown in FIG. 6, a natural oxide film (not shown) formed on the exposed upper surface of the semiconductor substrate 1 is removed. Thereafter, a sputtering method is applied to the structure shown in FIG. Thereby, as shown in FIG. 7, a metal film 21 made of, for example, nickel is formed on the semiconductor substrate 1 so as to cover the stacked body including the gate electrode 4. The thickness of the metal film 21 is, for example, about 10 nm. Next, the metal film 21 is further sputtered. As a result, as shown in FIG. 7, an anti-oxidation TiN film 22 is formed on the metal film 21. The thickness of the TiN film 22 is, for example, about 10 nm.

  Next, a known salicide method is applied. Specifically, heat treatment at 250 ° C. to 400 ° C. is performed on the structure shown in FIG. By the heat treatment, the metal film 21 reacts with silicon on the surface of the semiconductor substrate 1. The state after the reaction is shown in FIG. As shown in FIG. 8, a metal silicide film 6 is formed in the surface of the source / drain region 5. Note that the metal film 21 and the TiN film 22 that have not been silicided are removed by a mixed solution of sulfuric acid and hydrogen peroxide solution or the like (FIG. 8).

  Next, a CVD (Chemical Vapor Deposition) method is performed on the structure shown in FIG. Thereby, a first interlayer insulating film 7 is formed on the semiconductor substrate 1 so as to cover the stacked body including the gate electrode 4. The first interlayer insulating film 7 is made of a silicon oxide film. Thereafter, a CMP (Chemical Mechanical Polishing) method is applied to the first interlayer insulating film 7 and the hard mask HM. As a result, as shown in FIG. 9, the first interlayer insulating film 7 is planarized, and the hard mask HM is removed. As shown in FIG. 9, the upper surface of the first interlayer insulating film 7 and the upper surface of the gate electrode 4 made of polysilicon are flush with each other. In other words, the upper surface of the gate structure G <b> 1 is exposed from the upper surface of the first interlayer insulating film 7. As shown in FIG. 9, the gate structure G <b> 1 is formed by the gate electrode 4 and the gate insulating film 3.

  Next, a sputtering method is performed on the structure shown in FIG. Thereby, as shown in FIG. 10, a metal film 23 such as nickel is formed on the first interlayer insulating film 7 and the gate electrode 4. Here, it should be noted that until the step shown in FIG. 10, the gate electrode 4 is made of polysilicon.

  Next, the salicide method is performed on the structure shown in FIG. Thereby, in the structure shown in FIG. 11, the gate electrode 4 is fully silicided. That is, in the structure shown in FIG. 11, the gate electrode 4 is made of metal silicide. Thereafter, the unreacted metal film 23 is removed. Thereby, the upper surface of the fully silicided gate electrode 4 is exposed again from the upper surface of the first interlayer insulating film 7. That is, the upper surface of the first interlayer insulating film 7 and the upper surface of the fully silicided gate electrode 4 are flush with each other.

  Next, a trench 7a and a contact hole 7b are formed in the first interlayer insulating film 7 by a combination of lithography and etching (FIG. 12). Here, both the trench 7a and the contact hole 7b penetrate from the upper surface of the first interlayer insulating film 7 to the upper surface of the semiconductor substrate 1 (more specifically, the source / drain region (electrode region) 5). Is formed.

  The trench 7a is formed on the right side of the drawing of the gate structure G1 with the first interlayer insulating film 7 interposed therebetween. As shown in FIG. 12, the element isolation insulating film 2 and the metal silicide film 6 are exposed from the bottom of the trench 7a. The trench 7 a is extended in the first interlayer insulating film 7. On the other hand, the contact hole 7b is formed on the left side of the gate structure G1 with the first interlayer insulating film 7 interposed therebetween. As shown in FIG. 12, the metal silicide film 6 is exposed from the bottom of the contact hole 7b. Further, the contact hole 7b is not extended in the first interlayer insulating film 7 like the trench 7a, but is formed in an island shape in plan view.

  Both the trench 7a and the contact hole 7b are formed so as to penetrate the first interlayer insulating film 7. Therefore, in this specification, both the trench 7a and the contact hole 7b are referred to as first contact holes 7a and 7b.

  Next, the natural oxide film present in the portions exposed from the bottom surfaces of the first contact holes 7a and 7b is removed. Thereafter, first contact plugs 8A and 8B are formed in the first contact holes 7a and 7b. Here, the first contact plugs 8A and 8B both have the first electrical resistivity.

  Specifically, sputtering or CVD is performed on the structure shown in FIG. Thereby, the barrier metal film 8a of the laminated film made of Ti and TiN is formed on both side surfaces and bottom surfaces of the first contact holes 7a and 7b, the upper surface of the first interlayer insulating film 7, and the upper surface of the gate electrode 4. Form a film. The thickness of the barrier metal film 8a is, for example, about 5 to 10 nm. Thereafter, a CVD method is performed on the barrier metal film 8a. Thereby, a tungsten film 8b is formed on the barrier metal 8a. Thereafter, a CMP method is performed on the barrier metal film 8a and the tungsten film 8b.

  Thereby, the barrier metal film 8a and the tungsten film 8b are left only in the first contact holes 7a and 7b. That is, as shown in FIG. 13, the gate electrode 4 and the first interlayer insulating film 7 are exposed again, and the first contact plugs 8A and 8B are formed in the first contact holes 7a and 7b. As shown in the configuration of FIG. 13, the first contact plugs 8A and 8B both have a laminated structure of a barrier metal 8a and a tungsten film 8b. As described above, most of the first contact plugs 8A and 8B are composed of the tungsten film 8b.

  FIG. 14 is a plan view of the semiconductor device shown in FIG. As shown in FIG. 14, on the right side of the drawing, a first contact plug 8A extending in the first interlayer insulating film 7 and functioning as a wiring is formed. As shown in FIG. 13, the first contact plug 8 </ b> A functioning as a wiring is disposed to reach the element isolation insulating film 2. By the first contact plug 8A functioning as the wiring, the members formed apart in plan view (in FIG. 1, the source / drain region 5 and the second contact plug 10) are electrically connected.

  On the other hand, a first contact plug 8B formed in an island shape in the first interlayer insulating film 7 exists on the left side of the drawing. Both the first contact plugs 8A and 8B function as contact plugs that electrically connect the source / drain regions 5 and the members existing on the upper surface of the first interlayer insulating film 7. Accordingly, in the present invention, the first contact plugs 8A and 8B are both referred to as contact plugs.

  Next, a CVD method is performed on the structure shown in FIG. Thereby, as shown in FIG. 15, the second interlayer insulating film 9 is formed on the first interlayer insulating film 7 and the first contact plugs 8A and 8B. As the second interlayer insulating film 9, for example, a silicon oxide film can be employed.

  Next, a second contact hole 9a is formed in the second interlayer insulating film 9 by a combination of lithography and etching (FIG. 16). Here, each second contact hole 9a extends from the upper surface of the second interlayer insulating film 9 to the upper surface of the first interlayer insulating film 7 (more specifically, the first contact plugs 8A and 8B). It is formed through.

  From the bottom of the second contact hole 9a formed on the right side of the drawing, the upper surface of the first contact plug 8A functioning as a contact plug and wiring is exposed. On the other hand, the upper surface of the first contact plug 8B functioning as a contact plug is exposed from the bottom of the second contact hole 9a formed on the left side of the drawing.

  Next, a second contact plug 10 is formed in the second contact hole 9a. Here, both the second contact plugs 10 have a second electrical resistivity. The second electrical resistivity is smaller (lower) than the first electrical resistivity of the first contact plugs 8A and 8B.

  Specifically, a CVD method or a sputtering method is performed on the structure shown in FIG. Thus, a barrier metal film 10a of a laminated film made of Ta and TaN is formed on both side surfaces and the bottom surface of the second contact hole 9a and the upper surface of the second interlayer insulating film 9. The thickness of the barrier metal film 10a is, for example, about 5 to 10 nm. Thereafter, a sputtering method is performed on the barrier metal film 10a. As a result, copper or ruthenium is formed on the barrier metal 10a as a seed layer. Thereafter, a copper film 10b is formed by performing a plating method. Thereafter, a CMP method is performed on the barrier metal film 10a and the copper film 10b.

  Thereby, the barrier metal film 10a and the copper film 10b are left only in the second contact hole 9a. That is, as shown in FIG. 17, the second interlayer insulating film 9 is exposed again, and the second contact plug 10 is formed in the second contact hole 9a. As shown in the configuration of FIG. 17, both the second contact plugs 10 have a laminated structure of a barrier metal 10a and a copper film 10b. As described above, most of the second contact plug 10 is made of the copper film 10b.

  As shown in FIG. 17, the second contact plug 10 on the right side of the drawing is electrically connected to the first contact plug 8A. On the other hand, the second contact plug 10 on the left side of the drawing is electrically connected to the first contact plug 8B. That is, both the second contact plugs 10 function as contact plugs that electrically connect the first contact plugs 8A and 8B and a member formed in an upper layer.

  Thereafter, a third interlayer insulating film 11 made of a silicon oxide film or the like is formed on the second interlayer insulating film 9 by CVD. Then, a copper wiring 12 is disposed on the third interlayer insulating film 11 by performing trench formation, sputtering, plating, or the like (see FIG. 1). Here, the copper wiring 12 has a laminated structure of a barrier metal film 12a and a copper film 12b. Further, the lower surface of the copper wiring 12 is connected to the upper surface of the second contact plug 12. Therefore, the source / drain region 5 and the copper wiring 12 are electrically connected via the first contact plugs 8A and 8B and the second contact plug 10.

  Thus, the semiconductor device having the structure shown in FIG. 1 is completed.

  In the above description, the full silicidation of the gate electrode 4 is mentioned. However, salicide formation of the gate electrode 4 (that is, a process of siliciding only the surface of the gate electrode 4) may be used. When the salicide is applied, the formation of the hard mask HM is omitted, and the silicidation described with reference to FIG. 7 may be performed with the upper surface of the gate electrode 4 exposed. In the case of the salicide formation, the full silicide process described with reference to FIG. 10 is naturally omitted.

  By the way, in the case of the configuration shown in FIG. 18, the problem mentioned in “Problems to be solved by the invention” occurs. That is, in the configuration in which the source / drain region 5 and the copper wiring 12 are connected by the one contact plug 51 formed in the interlayer insulating film 50, the contact plug has a higher resistance due to higher device integration. Problems arise. Further, if the main component of the one contact plug 51 is made of copper in order to suppress the increase in resistance, the diffusion of copper into the source / drain region 5 occurs as a problem.

  Therefore, in the semiconductor device according to the present embodiment, source / drain region 5 and a member (for example, copper wiring 12) disposed in an upper layer are connected via two contact plugs 8A, 8B, and 10. ing. In other words, the contact plug existing between the source / drain region 5 and the member disposed in the upper layer is divided into two by the first contact plugs 8A and 8B and the second contact plug 10. . The second electrical resistivity of the second contact plug 10 is lower than the first electrical resistivity of the first contact plugs 8A and 8B.

  Therefore, the constituent materials of the first contact plugs 8A, 8B can be selected from the viewpoint of preventing diffusion of the constituent materials of the contact plugs 8A, 8B, 10 into the source / drain regions 5. The constituent material of the second contact plug 10 can be selected from the viewpoint of reducing the resistance of the contact plug. Therefore, even if the device is highly integrated, the increase in resistance of the contact plug can be suppressed. Furthermore, the diffusion of the constituent material of the contact plugs 8A, 8B, 10 into the source / drain regions 5 can be prevented.

  In the semiconductor device according to the present embodiment, the upper surface of the gate electrode 4 and the upper surface of the first interlayer insulating film 7 are flush with each other. The first contact plugs 8A and 8B penetrate the first interlayer insulating film 7 in the vertical direction.

  9 to 11 are steps conventionally required in the full silicidation process. Therefore, for example, when the full silicide (FUSI) process of the gate electrode 4 is applied as in the present embodiment, the configuration shown in FIG. 1 can be manufactured without major process changes. That is, in the present embodiment, a step of forming the first interlayer insulating film 7 on the semiconductor substrate, the upper surface of which is the same height as the upper surface of the gate electrode 4 (which can also be grasped as the upper surface of the gate structure G1). A step of forming first contact holes 7a and 7b penetrating the first interlayer insulating film 7 is included. Therefore, when the gate electrode 4 is fully silicided, a semiconductor device having the structure shown in FIG. 1 can be manufactured by a simple process.

  The heights of the first contact plugs 8A and 8B having a relatively high first electrical resistivity are the same as the height of the gate electrode 4 as described above. That is, it can be seen that the heights of the first contact plugs 8A and 8B are relatively low. Therefore, the ratio of the resistance value of the first contact plugs 8A and 8B to the resistance value of the entire contact plug can be reduced. In other words, the resistance of the entire contact plug can be reduced.

  In the semiconductor device according to the present embodiment, the first contact plug 8A is extended in the first interlayer insulating film 7 and also functions as a wiring. Therefore, the degree of freedom in the pattern layout of the metal wiring disposed in the upper layer can be improved.

  In the above embodiment, the first contact plugs 8A and 8B are mainly composed of tungsten (tungsten film 8b). In addition, the first contact plugs 8A and 8B may contain any one of tantalum, titanium, and ruthenium as a main component. Alternatively, nitrides, oxides, silicides and the like listed above (for example, tantalum silicide, tantalum silicon nitride) can also be employed as the main components of the first contact plugs 8A and 8B.

  By using these listed conductive materials as the main components of the first contact plugs 8A and 8B, diffusion of the conductive material constituting the contact plugs 8A, 8B and 10 into the source / drain regions 5 can be prevented. .

  In the above embodiment, the second contact plug 10 is mainly composed of copper (copper film 10b). In addition, the second contact plug 10 may contain any one of aluminum, rhodium, ruthenium and silver as a main component.

  By using these listed conductive materials as the main component of the second contact plug 10, the resistance of the entire contact plug including the first contact plugs 8A and 8B and the second contact plug 10 can be reduced. be able to.

  In the above description, the barrier metal film 10a is formed on the bottom surface and both side surfaces of the second contact hole 9a (FIGS. 16 and 17). However, after that, the barrier metal film 10a existing on the bottom surface of the second contact hole 9a may be removed by, for example, sputter etching. Therefore, the barrier metal 10a remains only on both side surfaces of the second contact hole 9a by the removal process of the barrier metal film 10a.

  The barrier metal film 10a such as TaN has a resistance several times higher than copper. Therefore, as described above, the barrier metal film 10a on the bottom surface of the second contact hole 9a is removed. Thereby, in the structure of FIG. 1, the contact resistance between 1st contact plug 8A, 8B-2nd contact plug 10 can be reduced more. As described above, the first contact plugs 8A and 8B made of tungsten or the like exist below the second contact plug 10. Therefore, it is possible to prevent copper or the like that is a constituent material of the second contact plug 10 from diffusing into the semiconductor substrate 1. In addition, barrier metal films 10a exist on both side surfaces of the second contact hole 9a. Therefore, it is possible to prevent copper or the like which is a constituent material of the second contact plug 10 from diffusing into the second interlayer insulating film 9.

  Further, when the gate electrode 4 and the upper copper wiring 12 are connected, the configuration shown in FIG. 19 can be employed. That is, when forming the second contact plug 10 described above, the second contact plug 10 connected to the upper surface of the gate electrode 4 is also formed. The second contact plug 10 connected to the gate electrode 4 also has a laminated structure of a barrier metal film 10a and a copper film 10b. The copper wiring connected to the upper surface of the second contact plug 10 also has a laminated structure of the barrier metal film 12a and the copper film 12b.

  The second contact plug 10 has a second electrical resistivity with a relatively small value. Therefore, in the configuration of FIG. 19, the contact resistance between the gate electrode 4 and the second contact plug 10 can be further reduced. Accordingly, since the fully silicided gate electrode 4 has a lower resistance, local wiring (for example, a ground line that does not require generation of a potential difference) can be realized with fine wiring using the gate electrode 4.

  The gate electrode 4 has no junction in the source / drain region 5. Therefore, even if the second contact plug 10 mainly composed of copper or the like is brought into direct contact with the gate electrode 4, there is no need to worry about the problem of junction breakdown.

  The conventional contact hole connects the copper wiring 12 and the source / drain region 5 with a continuous hole. As an ideal contact hole, it is expected that the side wall has a vertical structure, that is, the top opening diameter of the contact hole and the bottom opening diameter in contact with the source / drain region 5 are the same. However, in an actual process, it is inevitable that a taper is formed, and the bottom opening diameter is smaller than the top opening diameter. For example, since there is a taper of about 2 °, the difference between the upper opening diameter and the bottom opening diameter increases as the contact hole depth increases, and the bottom opening diameter is reduced. Since the contact resistance with the source / drain region 5 becomes higher as the contact area is reduced, not only the contact plug resistance but also the contact with the source / drain region 5 as the contact hole depth increases. The resistance itself increases. In the present invention, the contact hole is divided into two parts to substantially reduce the depth of each individual contact hole, thereby reducing the size of the bottom opening diameter with respect to the top opening diameter even in a tapered contact hole shape. The contact resistance itself can be reduced as compared with a conventional contact hole.

<Embodiment 2>
In the first embodiment, the first contact plug 8A and the first contact plug 8B are electrically insulated by the gate electrode 4 on which the sidewall film SW is formed and the first interlayer insulating film 7. . In contrast, the present embodiment has a configuration shown in the cross-sectional view of FIG. That is, in the present embodiment, the first contact plugs 18 are electrically insulated from each other by the gate electrode 4 on which the sidewall film SW is formed (FIG. 20).

  In FIG. 20, as in the first embodiment, one contact plug 18 is electrically connected to either one of the source region 5 and the drain region 5 (which can be regarded as the first electrode region). Yes. The other contact plug 18 is electrically connected to the other electrode region of the source region 5 or the drain region 5 (which can be grasped as a second electrode region). In addition, it can be understood that one contact plug 18 and the other contact plug 18 are both the first contact plugs 18 described in the first embodiment. Also in this embodiment, the first contact plug 18 may function as a wiring in the first interlayer insulating film 7 as in the first embodiment.

  In the present application, for convenience, the first contact plug 18 and the source / drain region 5 formed on the right side of the gate structure G 1 in the drawing are referred to as one contact plug 18 and the first electrode region 6. On the other hand, the first contact plug 18 and the source / drain region 5 formed on the left side of the gate structure G 1 in the drawing are referred to as the other contact plug 18 and the second electrode region 6.

  Also in the present embodiment, sidewall films SW are formed on both side surfaces of the gate electrode 4. However, in the present embodiment, the sidewall film SW has a single layer structure made of only a silicon nitride film. In the present embodiment, the gate insulating film 3 is formed under the gate electrode 4 and under the sidewall film SW. Also in the present embodiment, the gate structure G1 is configured by a stacked body in which the gate insulating film 3 and the gate electrode 4 are stacked in this order.

  Similarly to the first embodiment, the source / drain regions 5 are respectively formed in the surface of the semiconductor substrate 1 on both sides of the gate electrode 4 having the sidewall films SW formed on both side surfaces.

  As described in the first embodiment, the first contact plug 18 is formed so as to penetrate from the upper surface to the lower surface of the first interlayer insulating film 7. In other words, the first contact plug 18 electrically connects the source / drain region 5 and the second contact plug 10 also in the present embodiment. However, in the present embodiment, the one contact plug 18 and the other contact plug 18 are formed in the first interlayer insulating film 7 in the following manner.

  That is, as shown in FIG. 20, one side surface (left side of the drawing) of one contact plug 18 is in direct contact with the sidewall film SW formed on one side surface (right side of the drawing) of the gate electrode 4. ing. The other side surface portion (the right side in the drawing) of the one contact plug 18 is in direct contact with the first interlayer insulating film 7. On the other hand, the side surface portion (right side of the drawing) of the other contact plug 18 is in direct contact with the sidewall film SW formed on the other side surface portion (left side of the drawing) of the gate electrode 4. The other side surface portion (left side in the drawing) of the other contact plug 18 is in direct contact with the first interlayer insulating film 7.

  Further, the one contact plug 18 and the other contact plug 18 are electrically insulated by the gate electrode 4 (gate structure G1) on which the sidewall film SW is formed.

  The semiconductor device according to the present embodiment is the same as the configuration described in the first embodiment except for the configuration described above. For example, also in the present embodiment, the first contact plug 18 has a laminated structure of a barrier metal film 18a and a tungsten film 18b. The second electrical resistivity of the second contact plug 10 is lower than the first electrical resistivity of the first contact plug 18. Here, description of other configurations (the same configurations as in the first embodiment) is omitted.

  Next, a method for manufacturing a semiconductor device according to the present embodiment will be described.

  First, the configuration shown in FIG. 21 is created by performing the steps described with reference to FIGS. In the present embodiment, the applied method is almost the same as in the first embodiment. However, it should be noted that the form of the gate insulating film 3 and the form of the sidewall film SW are different as described above. Specifically, unlike the configuration of FIG. 8, in this embodiment, as shown in FIG. 21, the sidewall film SW has a single layer structure made of a silicon nitride film on the side surface of the gate electrode 4. A gate insulating film 3 is formed under the gate electrode 4 and the sidewall film SW.

  For example, the gate electrode 4 is etched using the gate insulating film 3 as an etching stopper. Thereafter, a silicon nitride film is formed and etched back. Thereby, the sidewall film SW having the single layer structure described above can be formed. Further, after the sidewall film SW is formed, the gate insulating film 3 is removed using the sidewall film SW and the gate electrode 4 as a mask. Thereby, the gate insulating film 3 remains under the gate electrode 4 and the sidewall film SW.

  Next, the process described with reference to FIGS. 9 to 11 is performed on the structure of FIG. Thereby, the structure shown in FIG. 22 is formed. Also in this embodiment, the upper surface of the fully silicided gate electrode 4 (that is, the gate structure G1) and the upper surface of the first interlayer insulating film 7 are flush with each other.

  Next, a wide first contact hole 7d is formed in the first interlayer insulating film 7 by a combination of lithography and etching (FIG. 23). That is, not only the metal silicide film 6 formed in the first electrode region 5 but also the metal silicide film 6 formed in the second electrode region 5 from the bottom surface of the first contact hole 7d to be formed. Is also exposed. In other words, the first contact hole 7d is formed in the first interlayer insulating film 7 so that the gate electrode 4 (or the gate structure G1) exists inside the opening.

  The first interlayer insulating film 7 is a silicon oxide film, the sidewall film SW is a silicon nitride film, and the gate electrode 4 is made of metal silicide. Therefore, a resist having one opening exposing the upper surface of the gate electrode 4 is formed on the first interlayer insulating film 7. Thereafter, using the resist as a mask, a known dry etching process is performed to selectively etch the first interlayer insulating film 7 made of a silicon oxide film. Accordingly, as shown in FIG. 23, a wide first contact hole 7d in which the gate electrode 4 (or the gate structure G1) exists inside the opening is formed in the first interlayer insulating film 7.

  A plan view of the structure shown in FIG. 23 is shown in FIG. Also in FIG. 24, it can be seen that the gate electrode 4 having the side wall film SW formed on the side surface is present inside the first contact hole 7d. Also in FIG. 24, from the bottom surface of one first contact hole 7d, the metal silicide film 6 formed in the first electrode region 5 and the metal silicide film 6 formed in the second electrode region 5 It can be seen that each is exposed.

  Next, conductors 18a and 18b are formed on the first interlayer insulating film 7 so as to fill the first contact hole 7d and cover the gate electrode 4 existing in the opening (FIG. 25).

  Specifically, a CVD method or a sputtering method is applied to the structure shown in FIGS. Thus, as shown in FIG. 25, the barrier metal film 18a is formed on the upper surface of the gate electrode 4, on the sidewall film SW, on the bottom and side surfaces of the first contact hole 7d, and on the first interlayer insulating film 7. To do. The barrier metal film 18a is a laminated film made of Ti and TiN. Thereafter, a CVD method is performed on the upper surface of the barrier metal film 18a. Thus, as shown in FIG. 25, a tungsten film 18b is formed on the barrier metal film 18a so as to completely fill the first contact hole 7d.

  As can be seen from the configuration in FIG. 25, the conductors 18 a and 18 b are also formed on the gate electrode 4. Therefore, until the said process, the 1st electrode area | region 5 and the 2nd electrode area | region 5 are electrically connected by the conductors 18a and 18b formed in the 1st contact hole 7d.

  Next, a CMP method or an etch back method is performed on the barrier metal film 18a and the tungsten film 18b. As a result, as shown in FIG. 26, the barrier metal film 18a and the tungsten film 18b on the upper surface of the gate electrode 4 and the upper surface of the first interlayer insulating film 7 are removed, and the conductive films 18a, 18b are formed in the first contact hole 7d. 18b remains. Further, two first contact plugs 18 separated by the gate electrode 4 having the side wall film SW formed on the side surfaces thereof are removed in the first interlayer insulating film 7 by the removal process of the conductive films 18a and 18b. It is formed.

  As can be seen from FIG. 26, the barrier metal film 18 a and the tungsten film 18 b do not exist on the upper surface of the gate electrode 4. Therefore, one contact plug 18 electrically connected to the first electrode region 5 and the other contact plug 18 electrically connected to the second electrode region 5 are insulated. In other words, the first conductive plugs 18a and 18b are partially removed, so that the two first contact plugs 18 insulated by the gate electrode 4 on which the sidewall film SW is formed are formed on both side surfaces of the gate electrode 4. Are formed respectively.

  It is desirable that overpolishing or overetching be performed during the CMP process or etchback process for each conductive film 18a, 18b. Thereby, the upper surface of the first contact plug 18 can be reliably set lower than the upper surface position of the gate electrode 4. The first contact plugs 18 can be reliably electrically insulated by the gate electrode 4 having the sidewall film SW formed on the side surface.

  Thereafter, the second interlayer insulating film 9, the second contact plug 10, the third interlayer insulating film 11, the copper wiring 12, and the like are formed by the same method as described in the first embodiment. Thereby, the semiconductor device having the structure shown in FIG. 20 is completed.

  As described above, in the present embodiment, one side surface portion of one and the other contact plug 18 is in direct contact with the side wall film SW formed on the side surface portion of the gate electrode 4. One contact plug 18 and the other contact plug 18 are electrically insulated by the gate electrode 4 on which the sidewall film SW is formed.

  Therefore, the first contact plug 18 having a large contact area with the source / drain region 5 (specifically, the metal silicide film 6) can be formed while preventing the connection between the first contact plugs 18. . Therefore, the contact resistance between the source / drain region 5 and the first contact plug 18 can be further reduced.

  Further, one contact plug 18 and the other contact plug 18 are separated from each other by a necessary minimum distance (the gate length of the gate electrode 4) in the horizontal direction. Therefore, the semiconductor device can be miniaturized and the distance of the current flowing through the first electrode region 6 → the channel → the second electrode region 6 can be set to the minimum. Thus, the drive current can be improved by setting the distance of the current flowing through the channel or the like to the minimum.

  In the case of manufacturing the configuration shown in FIG. 20, in the present embodiment, a wide first contact hole 7 d is formed in the first interlayer insulating film 7 at a time. Note that the gate electrode 4 is present in the first contact hole 7d.

  Therefore, the conductors 18a and 18b are formed on the first interlayer insulating film 7 so as to fill the first contact hole 7d and cover the gate electrode 4, and as described above, the conductors (each film 18a , 18b) can be partially removed to easily form the first contact plug 18 having a large bottom surface insulated by the gate electrode 4 on which the sidewall film SW is formed.

  The opening area of first contact hole 7d is larger than the opening area of first contact hole 7b described in the first embodiment, for example. Therefore, high resolution is not required in the lithography process performed at the time of the first contact hole 7d. The method according to the present embodiment also has an advantage in that the high resolution is not required.

<Embodiment 3>
The semiconductor device according to the present embodiment is configured based on the configuration of the semiconductor device according to the first embodiment. A cross-sectional view of the semiconductor device according to this embodiment is shown in FIG. As shown in FIG. 27, the semiconductor device according to the present embodiment further includes a gate structure G2 and a local wiring 31 in addition to the configuration of FIG.

  Another transistor Tr2 is formed in the upper surface of the semiconductor substrate 1 adjacent to the transistor Tr1. The other transistor Tr2 has a gate structure G2. The gate structure G2 includes a gate insulating film 3 and a gate electrode (which can be grasped as a second gate electrode) 4. The gate electrode 4 is formed on the semiconductor substrate 1 via the gate insulating film 3. A sidewall film SW is also formed on the side surface of the gate structure G2.

  The local wiring 31 is disposed in the second interlayer insulating film 9. The local arrangement 31 electrically connects the upper surface of the first contact plug 8A extending in the first interlayer insulating film 7 and the gate electrode 4 constituting the gate structure G2.

  Other configurations are the same as those described in the first embodiment. Therefore, the description of the other configuration here is omitted.

  The semiconductor device according to the present embodiment is manufactured, for example, including the following steps.

  First, a structure having a predetermined cross-sectional configuration shown in FIG. 28 is formed by a method similar to the method described with reference to FIGS. Here, it should be noted that not only the transistor Tr1 but also the transistor Tr2 is formed in the upper surface of the semiconductor substrate 1 in the present embodiment.

  Therefore, the configuration of the gate structure G2 and the like included in the transistor Tr2 is naturally the same as the configuration of the gate structure G1 and the like included in the transistor Tr1. Therefore, the gate electrode 4 on the transistor Tr2 side is also fully silicided. A sidewall film SW is also formed on the side surface of the gate structure G2.

  As shown in FIG. 29 which is a plan view of FIG. 28, in the present embodiment, the pattern of the first contact plug 8A extended is the same as the pattern of the first contact plug 8A shown in FIG. Different.

  A sputtering method or a CVD method is applied to the structures shown in FIGS. Thereby, a conductive film is formed on the entire surface of the first interlayer insulating film 7. For example, tungsten, TiN, TaN, or the like can be used as the conductive film. Thereafter, a combination process of lithography and etching is performed on the conductive film. Thereby, the local wiring 31 that electrically connects the first contact plug 8A and the gate electrode 4 constituting the gate structure G2 is formed by patterning (FIG. 30).

  Thereafter, the second interlayer insulating film 9, the second contact plug 10, the third interlayer insulating film 11, the copper wiring 12, and the like are formed by the same method as described in the first embodiment. Thereby, the semiconductor device having the structure shown in FIG. 27 is completed.

  For example, as a method of electrically connecting the source / drain region 5 of the transistor Tr1 and the gate electrode 4 of the transistor Tr2, the following configuration is also conceivable (referred to as another configuration). In the other configuration, another contact plug connected to the gate electrode 4 is also formed in the second interlayer insulating film 9. In another configuration, other wiring for connecting the second contact plug 10 and the other contact plug is provided in the third interlayer insulating film 11. Then, the source / drain region 5 and the gate electrode 4 described above are connected via the first and second contact plugs 8A, 8 and other contact plugs and other wirings.

  In contrast, the present embodiment further includes a local wiring 31 that electrically connects the first contact plug 8A and the gate electrode 4 constituting the gate structure G2.

  Therefore, other contact plugs and other wirings formed in other configurations can be omitted. Therefore, a space for other circuit wirings can be secured in the omitted interlayer insulating film. Thereby, compared with the said other structure, the direction of this Embodiment can improve the freedom degree of design more.

  Note that this embodiment is beneficial when applied to a configuration such as an SRAM (Static Random Access Memory). This is because the SRAM has a configuration in which a plurality of transistors are formed adjacent to each other on the same semiconductor substrate 1 and a gate electrode constituting one transistor is connected to a source / drain region constituting the other transistor.

<Embodiment 4>
FIG. 31 is a cross-sectional view showing the configuration of the semiconductor device according to the present embodiment. The semiconductor device according to the present embodiment is different from the semiconductor device according to the first embodiment in the following points.

  That is, in the semiconductor device according to the present embodiment, the metal silicide film 6 formed in the source / drain region 5 is omitted (FIG. 31). That is, as shown in FIG. 31, the bottom surfaces of the first contact plugs 8 </ b> A and 8 </ b> B are directly connected to the top surface of the source / drain region 5. Also in this embodiment, the gate structure G1 is a stacked body in which the gate insulating film 3 and the gate electrode 4 are stacked in this order.

  Furthermore, in the semiconductor device according to the present embodiment, the dimensions of the first contact plugs 8A and 8B are specified as shown in FIG. FIG. 32 is a plan view of the upper surface of the first interlayer insulating film 7 in the configuration of FIG. Since the source / drain region 5 exists in the lower layer, its outline is shown by a dotted line.

  Here, as defined in the second embodiment, for convenience, the first contact plug 8A and the source / drain region 5 formed on the right side of the gate structure G1 in the drawing are replaced with one contact plug 8A and the first electrode. This is referred to as region 5. In contrast, the first contact plug 8B and the source / drain region 5 formed on the left side of the gate structure G1 in the drawing are referred to as the other contact plug 8B and the second electrode region 5.

  In the present embodiment, as in the second embodiment, one side surface (left side in the drawing) of one contact plug 8A is a side wall formed on one side surface (right side in the drawing) of the gate structure G1. It is in direct contact with the film SW. On the other hand, the side surface portion (right side of the drawing) of the other contact plug 8B is in direct contact with the sidewall film SW formed on the other side surface portion (left side of the drawing) of the gate structure G1.

  Further, as shown in FIG. 32, the length La of one contact plug 8A of the portion in contact with the sidewall film SW in plan view is the first electrode region 5 in the gate width direction of the gate electrode 4 in plan view. It is more than length Ls. On the other hand, as shown in FIG. 32, the length of the other contact plug 8B in the portion in contact with the sidewall film SW in the plan view is Lb in the gate width direction of the gate electrode 4 in the plan view. This is not less than the length Lt of the electrode region. In other words, the first contact plugs 8A and 8B completely cover the source / drain region 5 at least in the gate width direction near the end of the sidewall film SW.

  In the present embodiment, the barrier metal film 8a constituting the first contact plugs 8A and 8B has the following configuration. The barrier metal film 8a has a laminated structure of Ti and TiN films. The thickness of Ti is about 3 to 5 nm, and the thickness of TiN is about 5 to 10 nm. Note that a tungsten film 8b is formed on the barrier metal film 8a. Further, by forming Ti silicide in addition to Ti as the barrier metal 8a, consumption of the silicon substrate 1 due to silicidation can be further reduced.

  As described above, in the present embodiment, the first contact plugs 8A and 8B, in which tungsten is the main component, are formed directly in the source / drain region 5. That is, the metal silicide film is omitted between the source / drain region 5 and the first contact plugs 8A and 8B.

  Therefore, the contact resistance between the first contact plugs 8A and 8B made of a conductive material and the source / drain region 5 can be reduced. Further, since no metal silicide film is formed, it is possible to prevent consumption of silicon in the semiconductor substrate 1 due to silicidation. Therefore, it is possible to prevent the shallow junction of the source / drain region 5 from being broken during operation.

  Further, the current density of the drive current becomes dominant at the end portion of the sidewall film SW. Therefore, the electrical resistance of the drive current can be reduced by forming the first contact plugs 8A and 8B so as to be in contact with the sidewall film SW. Further, the current density of the drive current becomes dominant at the end portion of the sidewall film SW. Therefore, the dimensions of the first contact plugs 8A and 8B in the gate width direction are more important than the dimensions of the first contact plugs 8A and 8B in the gate length direction.

  The current between the source / drain regions 5 of the transistor concentrates on the sidewall film SW. Therefore, the resistance between the source / drain regions 5 can be set to the minimum by covering the sidewall film SW portion where the current is concentrated. Specifically, the length La of one of the contact plugs 8A in contact with the sidewall film SW is equal to or longer than the length Ls of the first electrode region 5 in the gate width direction. Further, the length Lb of the other contact plug 8B in contact with the sidewall film SW is set to be equal to or longer than the length Lt of the second electrode region in the gate width direction.

<Embodiment 5>
In the semiconductor device according to the present embodiment, an NMIS transistor (hereinafter simply referred to as NMIS) and a PMIS transistor (hereinafter simply referred to as PMIS) are formed in the upper surface of the same semiconductor substrate. That is, the semiconductor device has a CMIS structure. In the semiconductor device according to the present embodiment, the metal silicide film is omitted between the source / drain regions and the first contact plug. Furthermore, in the semiconductor device according to the present embodiment, the conductor on the bottom surface of the first contact plug on the NMIS side and the conductor on the bottom surface of the first contact plug on the PMIS side are different materials.

  Next, by explaining the method for manufacturing a semiconductor device according to the present embodiment, the configuration of the semiconductor device is also described.

  First, an element isolation insulating film 2 is formed in the surface of a semiconductor substrate 1 made of silicon. Adjacent semiconductor elements are electrically isolated by the element isolation insulating film 2. In the present embodiment, as shown in FIG. 33, the semiconductor substrate 1 has an NMIS formation region 100 and a PMIS formation region 200 partitioned by the element isolation insulating film 2. Also, different conductivity type well regions are formed in the semiconductor substrate 1 in the MIS formation regions 100 and 200 by different impurity implantation processes. In FIG. 33, the well regions are not shown.

  Next, a method similar to the method described with reference to FIGS. 3 to 6 is performed on each of the NMIS formation region 100 and the PMIS formation region 200. Thereby, as shown in FIG. 34, NMISTrn is formed in the upper surface of the semiconductor substrate 1 in the NMIS formation region 100. On the other hand, PMISTrp is formed in the upper surface of the semiconductor substrate 1 in the PMIS formation region 200.

  In the NMIS formation region 100, an NMISTrn having a source / drain region (which can be grasped as a first electrode region) 5n and a gate structure Gn is formed. Here, the gate structure Gn is a stacked structure in which a gate insulating film 3n and a gate electrode (which can be grasped as a first gate electrode) 4n are stacked in this order. A sidewall film SWn having a multilayer structure is formed on both side surfaces of the gate structure Gn. The gate structure Gn is formed on the upper surface of the semiconductor substrate 1. Source / drain regions 5n are formed in the surface of the semiconductor substrate 1 on both sides of the gate structure Gn. The source / drain region 5n has a two-stage structure including a shallow impurity diffusion region 5na and a deep impurity diffusion region 5nb.

  In the PMIS formation region 200, a PMISTrp having a source / drain region (which can be grasped as a second electrode region) 5p and a gate structure Gp is formed. Here, the gate structure Gp is a laminated structure in which a gate insulating film 3p and a gate electrode (which can be grasped as a second gate electrode) 4p are laminated in this order. Multi-layered sidewall films SWp are formed on both side surfaces of the gate structure Gp. The gate structure Gp is formed on the upper surface of the semiconductor substrate 1. Source / drain regions 5p are formed in the surface of the semiconductor substrate 1 on both sides of the gate structure Gp. The source / drain region 5p has a two-stage structure including a shallow impurity diffusion region 5pa and a deep impurity diffusion region 5pb.

  Here, when the impurity implantation process of FIGS. 4 and 6 is performed on the semiconductor substrate 1 in the NMIS formation region 100, n-type impurity ions are implanted in the process of FIGS. 4 and 6 are applied to the semiconductor substrate 1 in the PMIS formation region 200, p-type impurity ions are implanted in the process of FIGS.

  After forming each MISTrn, Trp, next, a method similar to the method described with reference to FIG. 9 is performed on each of the NMIS formation region 100 and the PMIS formation region 200.

  As a result, as shown in FIG. 35, the first interlayer insulating film 7 is formed on the upper surface of the semiconductor substrate 1 in both the MIS formation regions 100 and 200. Here, the upper surface of the first interlayer insulating film 7 is at the same height as the upper surface of the gate electrode 4n and the upper surface of the gate electrode 4p. That is, the upper surface of the first interlayer insulating film 7 is flush with the upper surfaces of the gate structures Gn and Gp, and the upper surfaces of the gate electrodes 4n and 4p are exposed from the upper surface of the first interlayer insulating film 7. ing. Note that the hard mask HM formed on the gate electrodes 4n and 4p is also removed by the process shown in FIG.

  Next, a method similar to the method described with reference to FIGS. 10 and 11 is applied to each of the gate electrodes 4n and 4p. Thus, the gate electrodes 4n and 4p are fully silicided. In FIG. 35, it is assumed that the gate electrodes 4n and 4p that are fully silicided are illustrated.

  Next, a combination process of lithography and etching is performed on the first interlayer insulating film 7. As a result, a first opening 7m, which is a first contact hole, is formed in the first interlayer insulating film 7 formed in the NMIS formation region 100 (FIG. 36). The first openings 7m are respectively formed on both side surfaces of the gate structure Gn. The first openings 7m are formed penetrating from the upper surface of the first interlayer insulating film 7 to the upper surface of the semiconductor substrate 1. In other words, the source / drain region 5n is exposed from the bottom surface of each first opening 7m.

  Next, the natural oxide film present in the portion exposed from the bottom surface of the first opening 7m is removed. Thereafter, a sputtering method or a CVD method is applied to the structure shown in FIG. Thus, as shown in FIG. 37, the first conductor is formed on both side surfaces and the bottom surface of the first opening 7m, the upper surface of the first interlayer insulating film 7, and the upper surfaces of the gate electrodes 4n and 4p. A barrier metal film 8sn is formed. In the present embodiment, unlike the first embodiment, the barrier metal film 8sn is formed directly in the source / drain region 5n. That is, the metal silicide film 6 is not formed on the source / drain region 5n.

  Here, a material that lowers the barrier height with respect to the n-type source / drain region 5n in direct contact with the first conductor is selected as the first conductor. For example, as the first conductor, Yb, Ta, Cr (chromium), Zr (zirconium), Eu (europium), Gd (gadonium), Dy (dysprosium), Er, Hf, Y, La, V (vanadium) ) And Ho (fornium) can be used at least. The first conductor may be a metal silicide of these conductors. The first conductor may be an alloy in which Ni, Ti, or Co is contained in the conductors listed above.

  The barrier metal film 8sn may have a laminated structure in which the first conductor and the TiN film as described above are laminated in this order. Even when the barrier metal film 8sn has the laminated structure, the first conductor is in direct contact with the n-type source / drain region 5n.

  Next, a CVD method is performed on the barrier metal film 8sn. Thereby, a tungsten film 8b is formed on the barrier metal 8s. Thereafter, a CMP method is performed on the barrier metal film 8sn and the tungsten film 8b.

  Thereby, the barrier metal film 8sn and the tungsten film 8b are left only in the first opening 7m. That is, as shown in FIG. 38, the gate electrodes 4n and 4p and the first interlayer insulating film 7 are exposed again, and an NMIS-side contact plug 8N is formed as a first contact plug in the first opening 7m. (Filled).

  As shown in the configuration of FIG. 38, the NMIS side contact plug 8N has a laminated structure of a barrier metal 8s and a tungsten film 8b. Here, as can be seen from the above, the bottom surface of the NMIS side contact plug 8N is composed of the first conductor. That is, when the first conductivity type and the source / drain region 5n are in direct contact, the lower surface of the NMIS side contact plug 8N and the source / drain region 5n are electrically connected.

  Further, the NMIS side contact plug 8N has a predetermined electrical resistivity.

  Next, a combined process of lithography and etching is performed again on the first interlayer insulating film 7. As a result, a second opening 7f which is a first contact hole is formed in the first interlayer insulating film 7 formed in the PMIS formation region 200 (FIG. 39). The second openings 7f are respectively formed on both side surfaces of the gate structure Gp. The second openings 7 f are formed penetrating from the upper surface of the first interlayer insulating film 7 to the upper surface of the semiconductor substrate 1. In other words, the source / drain region 5p is exposed from the bottom surface of each second opening 7f.

  Next, the natural oxide film present in the portion exposed from the bottom surface of the second opening 7f is removed. Thereafter, a sputtering method or a CVD method is applied to the structure shown in FIG. As a result, as shown in FIG. 40, both side surfaces and the bottom surface of the second opening 7f, the top surface of the first interlayer insulating film 7, and the top surfaces of the gate electrodes 4n and 4p are made of the second conductor. A barrier metal film 8t is formed. In the present embodiment, unlike the first embodiment, the barrier metal film 8t is formed directly in the source / drain region 5p. That is, no metal silicide film is formed on the source / drain region 5p.

  Here, a material that lowers the barrier height with respect to the p-type source / drain region 5p in direct contact with the second conductor is selected as the second conductor. For example, as the second conductor, at least one of Pt, Ru, Pd, Ir (iridium), Ni, Mn, and Rh (rhodium) can be used. The second conductor may be a metal silicide of these conductors. The second conductor may be an alloy in which the conductors listed above contain Ni, Ti, or Co.

  Further, the barrier metal film 8t may have a stacked structure in which the second conductor and the TiN film are stacked in this order. Even when the barrier metal film 8t has the laminated structure, the second conductor is in direct contact with the p-type source / drain region 5p.

  Next, a CVD method is performed on the barrier metal film 8t. Thereby, a tungsten film 8b is formed on the barrier metal 8t. Thereafter, a CMP method is performed on the barrier metal film 8t and the tungsten film 8b.

  Thereby, the barrier metal film 8t and the tungsten film 8b are left only in the second opening 7f. That is, as shown in FIG. 41, the gate electrodes 4n and 4p and the first interlayer insulating film 7 are exposed again, and the PMIS side contact plug 8P is formed as the first contact plug in the second opening 7f. (Filled).

  As shown in the configuration of FIG. 41, the PMIS side contact plug 8P has a laminated structure of a barrier metal 8t and a tungsten film 8b. Here, as can be seen from the above, the bottom surface of the PMIS side contact plug 8P is composed of the second conductor. That is, when the second conductivity type and the source / drain region 5p are in direct contact with each other, the lower surface of the PMIS side contact plug 8P and the source / drain region 5p are electrically connected.

  The PMIS side contact plug 8P has a predetermined electrical resistivity.

  In each of the MIS formation regions 100 and 200, a material that reduces the barrier height with respect to the source / drain regions 5n and 5p is selected. Therefore, as described above, the first conductor formed at the bottom of the NMIS side contact plug 8N is different from the second conductor formed at the bottom of the PMIS side contact plug 8P.

  However, the tungsten film 8b is a main component of both the NMIS side contact plug 8N and the PMIS side contact plug 8P. Therefore, the electrical resistivity of the NMIS side contact plug 8N is substantially the same as that of the PMIS side contact plug 8P. Strictly speaking, due to the difference between the barrier metal films 8sn and 8t, the electrical resistivity of the contact plugs 8N and 8P is slightly different.

  Next, the CVD method is applied to the structure shown in FIG. Thus, the second interlayer insulating film 9 is formed on the first interlayer insulating film 7, the NMIS side contact plug 8N, and the PMIS side contact plug 8P (FIG. 42). As the second interlayer insulating film 9, for example, a silicon oxide film can be employed.

  Next, a second contact plug 10 is formed in the second interlayer insulating film 9 by a method similar to the method described with reference to FIGS. 16 and 17 (FIG. 42).

  The second contact plug 10 has a predetermined electrical resistivity. Here, the electrical resistivity of the second contact plug 10 is smaller (lower) than the electrical resistivity of the first contact plugs 8P and 8N. The second contact plug 10 is formed so as to penetrate the second interlayer insulating film 9 in the vertical direction (film thickness direction). Furthermore, as shown in FIG. 42, the lower surface of each second contact plug 10 is electrically connected to the upper surface of the NMIS side contact plug 8N or the upper surface of the PMIS side contact plug 8P. That is, the second contact plug 10 functions as a contact plug that electrically connects the first contact plugs 8N and 8P and a member (a lower surface of a copper wiring 12 described later) formed in an upper layer.

  The second contact plug 10 has a laminated structure of a barrier metal 10a and a copper film 10b.

  Next, a third interlayer insulating film 11 made of a silicon oxide film or the like is formed on the second interlayer insulating film 9. Thereafter, the copper wiring 12 is disposed on the third interlayer insulating film 11 (FIG. 42). The formation method and configuration of the third interlayer insulating film 11 and the copper wiring 12 are the same as those described in the first embodiment.

  Thus, the semiconductor device having the structure shown in FIG. 42 is completed.

  By adopting the above manufacturing method, the first conductor formed at the bottom of the NMIS-side contact plug 8N is different from the second conductor formed at the bottom of the PMIS-side contact plug 8P. You can easily create a configuration that can.

  Then, by making the first conductor different from the second conductor, on the NMIS formation region 100 side, as the first conductor, an n-type source that is in direct contact with the first conductor A material that lowers the barrier height with respect to the drain region 5n can be selected. On the other hand, on the PMIS formation region 200 side, as the second conductor, a material with a low barrier height with respect to the p-type source / drain region 5p in direct contact with the second conductor can be selected.

  Therefore, the contact resistance between the first contact plugs 8N and 8P and the source / drain regions 5n and 5p can be lowered on both the NMIS side and the PMIS side. Therefore, in the CMIS structure, the drive current can be improved on both transistor sides, and a high-performance CMIS transistor can be provided.

  In the above description, the PMIS side contact plug 8P is created after the NMIS side contact plug 8N is created. However, the PMIS side contact plug 8P may be created first, and then the NMIS side contact plug 8N may be created.

<Embodiment 6>
The present embodiment provides a semiconductor device that can prevent the connection between the second contact plug 10 and the gate electrode 4 even if, for example, the second contact plug 10 is formed out of alignment. Also in this embodiment, the gate structure G1 is a stacked body in which the gate insulating film 3 and the gate electrode 4 are stacked in this order.

  Hereinafter, by explaining the manufacturing method of the semiconductor device according to the present embodiment, the configuration of the semiconductor device will also be described.

  First, the configuration shown in FIG. 43 is created by performing the steps described with reference to FIGS. In the present embodiment, the applied method is almost the same as in the first embodiment.

  Next, an insulating film 41 is formed on the first interlayer insulating film 7, the first contact plug 8, and the gate electrode 4. Here, the insulating film 41 is an insulating film having an etching selectivity with a second interlayer insulating film 9 described later. In the present embodiment, the insulating film 41 is a silicon nitride film. As in the first embodiment, in this embodiment, the first interlayer insulating film 7 is a silicon oxide film. Thereafter, the insulating film 41 is subjected to a combination process of lithography and etching. Thereby, the insulating film 41 is patterned as shown in FIG. A plan view of the configuration of FIG. 44 viewed from above is shown in FIG.

  Specifically, the insulating film 41 is patterned on the gate electrode 4 so as to cover the gate electrode 4 and to have an opening 41a having a size such that the upper surface of the first contact plug 8 is completely exposed. The size of the opening of the opening 41 a is approximately the same as or larger than the upper surface of the first contact plug 8. As shown in FIG. 45, the insulating film 41 covers at least the upper surface portion of the gate electrode 4 adjacent to the first contact plug 8.

  Next, a CVD method is applied to the structures shown in FIGS. Thereby, as shown in FIG. 46, the second interlayer insulating film 9 is formed on the first interlayer insulating film 7 so as to cover the insulating film 41 and fill the opening 41a. In the present embodiment, the second interlayer insulating film 9 is a silicon oxide film.

  Next, a second contact hole is formed in the second interlayer insulating film 9 by a combination of lithography and etching. Here, the second contact hole is formed penetrating from the upper surface of the second interlayer insulating film 9 to the upper surface of the first interlayer insulating film 7 (more specifically, the first contact plug 8). Has been.

  Here, when forming the second contact hole, the etching process of the second interlayer insulating film 9 is performed under the condition that the insulating film 41 functions as an etching stopper. The insulating film 41 is a silicon nitride film and has an etching selectivity with respect to the second interlayer insulating film 9 which is a silicon oxide film. Therefore, the condition is satisfied by selecting a predetermined etching gas or the like. In the present embodiment, the diameter of the second contact hole in the drawing horizontal direction is larger than the diameter of the opening 41a in the drawing horizontal direction.

  Next, a barrier metal film 10a and a copper film 10b are stacked in this order on the second interlayer insulating film 9 so as to fill the second contact hole by the same method as in the first embodiment. Here, as shown in FIG. 47, the thickness of the copper film 10b is much larger than the thickness of the barrier metal film 10a.

  Next, a CMP method is performed on the barrier metal film 10a and the copper film 10b. As a result, the second interlayer insulating film 9 is exposed again, and the second contact plug 10 is formed in the second contact hole (FIG. 48). As shown in the configuration of FIG. 48, the second contact plug 10 has a laminated structure of a barrier metal 10a and a copper film 10b.

  As shown in FIG. 48, the second contact plug 10 is formed so as to penetrate the second interlayer insulating film 9 in the film thickness direction. Therefore, the lower surface of the second contact plug 10 is electrically connected to the upper surface of the first contact plug 8. The diameter in the drawing horizontal direction of the second contact plug 10 is larger than the diameter in the drawing horizontal direction of the opening 41a. Therefore, a part of the lower surface of the second contact plug 10 is also in contact with the upper surface of the insulating film 41 (see FIG. 48).

  Here, the second contact plug 10 has a second electrical resistivity lower than the first electrical resistivity of the first contact plug 8. As described above, most of the second contact plug 10 is made of the copper film 10b.

  Thereafter, as in the first embodiment, a third interlayer insulating film 11 is formed on the second interlayer insulating film 9, and a copper wiring 12 is disposed on the third interlayer insulating film 11 (FIG. 49). ). Here, the lower surface of the copper wiring 12 is connected to the upper surface of the second contact plug 12.

  As described above, in the present embodiment, the insulating film 41 covering at least the gate electrode 4 is formed, and the insulating film 41 is caused to function as an etching stopper, and the etching process of the second interlayer insulating film 9 is performed. Yes. That is, the second contact hole is formed in the second interlayer insulating film 9 by using the insulating film 41 as an etching stopper.

  Therefore, the second contact hole having a large cross-sectional area can be formed in the second interlayer insulating film 9. That is, the presence of the insulating film 41 can prevent the second contact hole from reaching the gate electrode 4. Therefore, the second contact hole having a large cross-sectional area can be formed in the second interlayer insulating film 10 without worrying about the formation of the second contact hole.

  Therefore, by forming the second contact plug 10 in the second contact hole, it is possible to form the second contact plug 10 that contacts the entire upper surface of the first contact plug 8. That is, the contact resistance between the first contact plug 8 and the second contact plug 10 can be further reduced.

  Even if the second contact hole is displaced and formed even above the gate electrode 4, the second contact plug 10 and the gate electrode 4 are insulated by the presence of the insulating film 41. That is, an undesirable short circuit between the second contact plug 10 and the gate electrode 4 can be prevented.

  Although not shown, it is assumed that wirings and the like are also provided below the insulating film 41 in FIG. Also in the case of the configuration, since the wiring and the like are covered with the insulating film 41, the second contact hole having a large cross-sectional area can be formed without worrying about the displacement of the second contact hole. In other words, even if the above-described misalignment occurs and the second contact hole is formed above the wiring or the like, an undesired short circuit between the second contact plug 10 and the wiring or the like is caused by the presence of the insulating film 41. Can be prevented.

<Embodiment 7>
In each of the above-described embodiments and later-described embodiments (particularly, without limiting the configuration of the gate electrode), the case where the gate electrode is a full silicide gate electrode is mentioned. In this embodiment, a case where a part of the gate electrode is made of metal will be described.

  FIG. 50 is a cross-sectional view showing the configuration of the semiconductor device according to the present embodiment.

  As shown in FIG. 50, a gate electrode (which can be grasped as a first gate electrode) is formed on the gate insulating film 3. In the present embodiment, the gate electrode has a stacked structure in which the metal conductive layer 4M and the insulating film 41M are stacked in this order. That is, in the present embodiment, the gate structure is a stacked body in which the gate insulating film 3, the metal conductive layer 4M, and the insulating film 41M are stacked in this order.

  Here, for example, a laminated film of TiN and W can be employed as the metal conductive layer 4M. The insulating film 41M is a silicon nitride film and is an insulating film having an etching selectivity with the second interlayer insulating film 9.

  That is, the second contact hole is formed in the second interlayer insulation 9 by the etching process. The insulating film 41M functions as an etching stopper when the second contact hole is formed. The insulating film 41M also functions as a mask that protects the metal conductive layer 4M from contamination during the manufacturing process.

  The configuration of FIG. 50 other than the configuration of the gate electrode is the same as the configuration shown in FIG. Therefore, detailed description of the other configuration of FIG. 50 here is omitted.

  The semiconductor device according to the present embodiment has the following effects in addition to the effects described in the first embodiment.

  That is, the insulating film 41M functioning as an etching stopper when the second contact hole is formed is formed on the metal conductive layer 4M. That is, the bottom surface of the second contact hole is formed on the top surface of the insulating film 41M. Therefore, even if lithography misalignment occurs when forming the second contact hole, it is possible to prevent the second contact plug 9 from being connected to the metal conductive layer 4M in the end. Therefore, a second contact hole having a large cross-sectional area can be formed in the second interlayer insulating film 10. Therefore, the second contact plug 10 that contacts the entire upper surface of the first contact plug 8 can be formed. That is, the contact resistance between the first contact plug 8 and the second contact plug 10 can be further reduced.

  Note that after the formation of the first interlayer insulating film 7, a CMP process is performed to planarize the upper surface. At this time, the CMP process can be easily stopped by detecting the upper surface of the insulating film 41M. That is, the CMP process of the first interlayer insulating film 7 is controlled using the insulating film 41M as a stopper. Thus, a configuration in which the upper surface of the gate electrode (that is, the upper surface of the gate structure, more specifically, the insulating film 41M) and the upper surface of the first interlayer insulating film 7 are flush with each other is easily created. be able to.

  When a via connected to the metal conductive layer 4M is formed in order to connect the metal conductive layer 4M and the upper layer wiring, an opening is formed in the insulating film 41M for the formation and connection of the via. Part is formed.

<Eighth embodiment>
FIG. 51 is a cross-sectional view showing the configuration of the semiconductor device according to this embodiment. The configuration of FIG. 51 is different from the configuration of FIG. 1 in the following points.

  That is, in the first embodiment, the gate electrode is a full silicide gate electrode. In the present embodiment, the gate electrode has a laminated structure of the polysilicon film 4po and the metal silicide film 6. As in the first embodiment, the gate electrode of the stacked structure is formed on the gate insulating film 3. Here, in the present embodiment, the gate structure is a stacked body in which the gate insulating film 3, the polysilicon film 4po, and the metal silicide film 6 are stacked in this order.

  In the present embodiment, the insulating film 61 is formed on the semiconductor substrate 1 so as to cover the gate electrode on which the sidewall film SW is formed. More specifically, the insulating film 61 is also formed on the source / drain region (electrode region) 5 formed in the surface of the semiconductor substrate 1. The insulating film 61 is a stress insulating film capable of causing a predetermined strain in the channel region of the transistor Tr formed in the upper surface of the semiconductor substrate 1.

  The insulating film 61 is a silicon nitride film and is an insulating film having an etching selectivity with the second interlayer insulating film 9. That is, a second contact hole is formed in the second interlayer insulating film 9 by the etching process. The insulating film 61 functions as an etching stopper when the second contact hole is formed.

  Other configurations in FIG. 51 are the same as those in FIG. Therefore, the description of the other configuration in FIG. 51 is omitted here.

  Next, a method for manufacturing a semiconductor device according to the present embodiment will be described.

  First, steps similar to those described with reference to FIGS. Here, in the present embodiment, unlike the first embodiment, no hard mask is formed on the polysilicon film 4po. That is, in the present embodiment, only the polysilicon film 4po is formed on the semiconductor substrate 1 with the gate insulating film 3 interposed therebetween as shown in FIG. Also in the present embodiment, multi-stage source / drain regions 5 are formed in the surface of the semiconductor substrate 1 on both sides of the polysilicon film 4po. Further, a sidewall film SW having a multilayer structure is formed on both side surfaces of the polysilicon film 4po.

  Next, in the structure shown in FIG. 52, a natural oxide film (not shown) formed on the exposed upper surface of the semiconductor substrate 1 is removed. Thereafter, a sputtering method is applied to the structure shown in FIG. Thereby, as shown in FIG. 53, a metal film 21 made of nickel or the like is formed on the semiconductor substrate 1 so as to cover the polysilicon film 4po. The thickness of the metal film 21 is, for example, about 10 nm. As the metal film 21, in addition to nickel, Co, Ti, Pt, V, Pd, Hf, Yb, Er, or an alloy containing two or more metals listed above can be used.

  Next, the metal film 21 is further sputtered. As a result, as shown in FIG. 53, an anti-oxidation TiN film 22 is formed on the metal film 21. The thickness of the TiN film 22 is, for example, about 10 nm.

  Next, a known salicide method is applied. Specifically, heat treatment at 250 ° C. to 400 ° C. is performed on the structure shown in FIG. By the heat treatment, the metal film 21 reacts with silicon on the surface of the semiconductor substrate 1, and the metal film 21 reacts with silicon in the polysilicon film 4po. FIG. 54 shows the state after the reaction. As shown in FIG. 54, metal silicide films 6 are formed in the surface of source / drain region 5 and in the surface of polysilicon film 4po, respectively. Note that the metal film 21 and the TiN film 22 that have not been silicided are removed by a mixed solution of sulfuric acid and hydrogen peroxide solution (FIG. 54).

  Next, a CVD method is performed on the structure shown in FIG. Thereby, as shown in FIG. 55, an insulating film 61 made of a silicon nitride film is formed on the semiconductor substrate 1 so as to cover the gate structure. More specifically, the insulating film 61 is also formed on the source / drain region 5.

  Here, the insulating film 61 has a film thickness of, for example, about 15 to 30 nm. In addition, it functions as a stress insulating film that generates strain in the channel region formed below the gate structure. Further, as described above, the insulating film 61 is an insulating film having an etching selectivity with respect to the second interlayer insulating film 9. That is, when the second contact hole is formed in the second interlayer insulating film 9 by etching, the insulating film 61 functions as an etching stopper.

  Next, a CVD method is performed on the structure shown in FIG. Thereby, the first interlayer insulating film 7 is formed on the insulating film 61. The first interlayer insulating film 7 is made of a silicon oxide film. Thereafter, a CMP method is performed on the first interlayer insulating film 7. Thereby, as shown in FIG. 56, the first interlayer insulating film 7 is planarized. As shown in FIG. 56, a part of the insulating film 61 is exposed from the upper surface of the first interlayer insulating film 7 by the CMP process. More specifically, the insulating film 61 formed on the upper portion of the gate structure is exposed from the upper surface of the first interlayer insulating film 7 by the CMP process.

  Next, trenches and contact holes are formed in the first interlayer insulating film 7 and the insulating film 61 by a combination of lithography and etching. Here, both the trench and the contact hole are formed penetrating from the upper surface of the first interlayer insulating film 7 to the upper surface of the semiconductor substrate 1 (more specifically, the source / drain region (electrode region) 5). The

  Both the trench and the contact hole are formed through the first interlayer insulating film 7 and the insulating film 61. Therefore, in this specification, both the trench and the contact hole are referred to as a first contact hole.

  Next, the natural oxide film present in the portion exposed from the bottom surface of the first contact hole is removed. Thereafter, as shown in FIG. 57, a first contact plug 8 is formed in the first contact hole. Here, both the first contact plugs 8 have a first electrical resistivity. The method for forming the first contact plug 8 is the same as the method for forming the first contact plugs 8A and 8B described in the first embodiment. Therefore, the detailed description of the method for forming the first contact plug 8 is omitted here.

  As described in the first embodiment, both the first contact plugs 8 have a laminated structure of barrier metal 8a and tungsten film 8b. As described above, most of the first contact plug 8 is composed of the tungsten film 8b.

  As shown in FIG. 57, a part of the insulating film 61 (the insulating film 61 on the gate electrode 61) is formed from the upper surface of the first interlayer insulating film 7 by the CMP process performed when the first contact plug 8 is formed. And the upper surface of the first contact plug 8 is exposed. That is, the upper surface of the first interlayer insulating film 8 and the upper surface of the insulating film 61 on the gate electrode are at the same height position. The first contact plug 8 is formed through the first interlayer insulating film 7 and the insulating film 61. The first contact plug 8 functions as a contact plug that electrically connects the source / drain region 5 and a member existing on the upper surface of the first interlayer insulating film 7.

  Thereafter, the second interlayer insulating film 9, the second contact plug 10, the third interlayer insulating film 11 and the copper wiring 12 are formed, and the semiconductor device having the structure shown in FIG. 51 is completed.

  Here, the insulating film 61 is an insulating film having an etching selectivity with respect to the second interlayer insulating film 9. Accordingly, when the second contact hole is formed in the second interlayer insulation 9 by the etching process, the insulating film 61 functions as an etching stopper. For example, the insulating film 61 is a silicon nitride film and has an etching selectivity with respect to the second interlayer insulating film 9 which is a silicon oxide film. Therefore, the insulating film 61 can function as an etching stopper by selecting a predetermined etching gas or the like.

  The second contact plug 10 has a second electrical resistivity smaller than the first electrical resistivity. Further, as described in the first embodiment, most of the second contact plug 10 is made of a copper film.

  As described above, in the present embodiment, the insulating film 61 is also formed on the source / drain region 5 so as to cover the gate structure. Here, the insulating film 61 has an etching selection ratio with the second interlayer insulating film 9. The insulating film 61 functions as a stress insulating film capable of causing a predetermined strain in the channel region of the transistor Tr.

  Therefore, in addition to the effects described in Embodiment 7, driving of the transistor Tr can be improved due to distortion generated in the channel region. That is, only by providing one insulating film 61 according to the present embodiment, the second contact plug 9 having a large diameter can be formed without worrying about misalignment of lithography, and further, the driving capability of the transistor Tr is improved. be able to.

  Note that after the formation of the first interlayer insulating film 7, a CMP process is performed to planarize the upper surface. At this time, the CMP process can be easily stopped by detecting the upper surface of the insulating film 61 on the gate electrode. That is, the CMP process of the first interlayer insulating film 7 is controlled using the insulating film 61 as a stopper. Thereby, a configuration in which the upper surface of the gate insulating film 61 on the gate electrode and the upper surface of the first interlayer insulating film 7 are flush with each other can be easily created.

  Further, in the case where a via connected to the gate electrode is formed in order to connect the gate electrode and the upper layer wiring, an opening is formed in the insulating film 61 for the formation and connection of the via. The

<Embodiment 9>
In the above embodiments, the second interlayer insulating film 9 is a silicon oxide film. By the way, a second contact plug 10 having a second electrical resistivity which is a low electrical resistivity is formed in the second interlayer insulating film 9.

  Therefore, in the present embodiment, a low relative dielectric constant film (low-k film) is applied as the second interlayer insulating film 9. More specifically, the second interlayer insulating film 9 according to the present embodiment has a specific dielectric constant lower than the specific dielectric constant of FSG (Fluorine doped Silicon Glass: relative dielectric constant k = 3.4 to 3.6). Has a dielectric constant.

  As the second interlayer insulating film 9, for example, a film including any one of a SiOC film (silicon oxide film added with carbon), a SiCO film (SiC film added with oxygen), an organic polymer film, and porous silica is adopted. it can. The organic polymer film is a polyallyl ether film, a polyimide film, a parylene film, a Teflon (registered trademark) film, or the like. The porous silica film is, for example, a porous MSQ film (Methylsilsesquioxane).

  The relative dielectric constant of the SiOC film is about 2.7 to 2.9. The relative dielectric constant of the SiCO film is about 3. The relative dielectric constant of the organic polymer film is about 2.5 to 3. The relative dielectric constant of the MSQ film is about 2.0 to 2.5.

  Note that the low relative dielectric constant film may be applied as the first interlayer insulating film 7 on which the first contact plug 8 having the first electric resistivity higher than the second electric resistivity is formed. . However, a gate electrode is formed on the first interlayer insulating film 7. Therefore, as the first interlayer insulating film 7, it is desirable to apply a SiO 2 film, an FSG film, a TEOS film, and a USG film (the relative dielectric constant of these films is about 4).

  As described above, in the present embodiment, the second interlayer insulating film 9 is a low relative dielectric constant film. Therefore, the capacity between the second contact plugs 10 can be reduced. Thereby, the delay of the electric signal in the second contact plug 10 can be suppressed. Further, since the second interlayer insulating film 9 is a low relative dielectric constant film, the thickness of the second interlayer insulating film 9 can be set thin. That is, the height of the second contact plug 10 formed in the second interlayer insulating film 9 can be set low. Therefore, the electrical resistance of the second contact plug 10 can be further reduced. Also from this viewpoint, the electric signal delay in the second contact plug 10 is suppressed.

  In each embodiment of the present application, the second contact plug 10 may function as a wiring that electrically connects members formed apart in plan view. That is, as shown in FIG. 58, a portion 10 </ b> L of the second contact plug 10 extends in the planar view direction in the second interlayer insulating film 9. The first contact plug 8 and the copper wiring 12 that are formed apart in plan view are electrically connected by the second contact plug 10 having the portion 10L.

  However, the configuration in which the second contact plug 10 functions as a wiring is more effective when the second interlayer insulating film 9 is a low relative dielectric constant film as in the present embodiment. This is because in the present embodiment, the electric signal delay in the second contact plug 10 can be suppressed. In addition, by making the second contact plug 10 function as a wiring, the degree of freedom in device design can be improved.

  A second contact plug 10 having a copper film as a main element is formed in the second interlayer insulating film 9. Therefore, a configuration that can further suppress the diffusion of copper into the second interlayer insulating film 9 is desirable. For example, it is more desirable from the viewpoint of preventing copper diffusion that the second interlayer insulating film 9 is a laminated film of a SiCN film having a copper expansion suppressing effect and the low relative dielectric constant film.

<Embodiment 10>
FIG. 59 is a cross-sectional view showing the configuration of the semiconductor device according to this embodiment. As shown in FIG. 59, in the present embodiment, the upper surface of the first contact plug 8 has a recessed portion (seam portion) 8s. Then, the second contact plug 10 is formed so as to fill the recessed portion 8s. Other configurations are the same as those in the above-described embodiment (more specifically, the configuration in FIG. 20). Therefore, the description of the other configuration here is omitted.

  For example, when another configuration including FIG. 20, that is, when the upper surface of the first contact plug 8 is flattened, the following forming method is employed. That is, the tungsten film 8b having a thickness is formed so that the first contact hole shape is completely embedded. That is, the thick tungsten film 8b is formed on the upper surface of the tungsten film 8b to such an extent that the depression due to the shape of the first contact hole is eliminated. Thereafter, the tungsten film 8b and the like are polished by a CMP process and planarized.

  On the other hand, in the present embodiment, for example, the following method is adopted.

  When the tungsten film 8b (which can be grasped as a conductive material) 8b is embedded in the first contact hole, the film thickness of the tungsten film 8b is set to, for example, the film thickness necessary for embedding the first contact hole (ie, from half of the hole The film thickness is set to about 20% of the half). That is, the first contact hole is filled with the thin tungsten film 8b by the above-described method. Thereby, as shown in FIG. 60, a recessed portion (seam portion) r1 is formed on the upper surface of the tungsten film 8b. In FIG. 60, the barrier metal film 8a, the metal silicide film 6, the source / drain region 5 and the like are not shown for simplification.

  Next, a CMP process with an adjusted polishing amount is performed on the tungsten film 8b. Alternatively, dry etching treatment is performed on the tungsten film 8b. Thereby, the first contact plug 8 having a recessed portion (seam portion) 8s on the upper surface is formed (FIG. 59).

  Thereafter, the barrier metal film 10a and the copper film 10b are formed so as to fill the recessed portion 8s. Thereby, as shown in FIG. 59, the lower surface of the second contact plug 10 can be connected to the recessed portion 8s.

  As described above, in the present embodiment, the upper surface of the first contact plug 8 has the recessed portion 8s. Then, the second contact plug 10 is formed so as to fill the recessed portion 8s.

  Therefore, the contact area between the first contact plug 8 and the second contact plug 10 increases. Therefore, the interface resistance between the contact plugs 8 and 10 can be reduced.

<Embodiment 11>
A configuration cross-sectional view of the semiconductor device according to the present embodiment is shown in FIG. Here, the left-right direction in FIG. 61 is the gate length direction, and the front-back direction in FIG. 61 is the gate width direction.

  As shown in FIG. 61, in the present embodiment, a first gate electrode 4l and a second gate electrode 4r are formed on the upper surface of the semiconductor substrate 1. Here, the first gate electrode 4l is formed on the semiconductor substrate 1 via the first gate insulating film 3l. The second gate electrode 4r is formed on the semiconductor substrate 1 via the second gate insulating film 3r. The first gate electrode 4l and the first gate insulating film 3l constitute a gate structure Gl. The second gate electrode 4r and the second gate insulating film 3r constitute a gate structure Gr. Note that sidewall films SW are formed on both side surfaces of the gate structures Gl and Gr.

  The first gate electrode 4l is a component of one transistor, and the second gate electrode 4r is a component of the other transistor.

  In the present embodiment, the first contact plug 8CL also functions as a wiring. That is, the first contact plug 8CL connects the source / drain region (not shown in FIG. 61) and the second contact plug 10. Further, the first contact plug 8CL functions as a wiring having at least a portion extending in the gate width direction in the first interlayer insulating film 7. That is, a part of the first contact plug 8CL extends in a direction perpendicular to the arrangement direction of the gate electrodes 4l and 4r in a sectional view.

  The first contact plug 8CL is formed between the first gate electrode 4l and the second gate electrode 4r. More specifically, one side surface of the first contact plug 8CL is in direct contact with the sidewall film SW formed on the side surface of the first gate electrode 4l. The other side surface of the first contact plug 8CL is in direct contact with the sidewall film SW formed on the side surface of the second gate electrode 4r.

  As in the first embodiment, also in the present embodiment, the first contact plug 8CL is composed of a barrier metal film 8a and a tungsten film 8b. The first contact plug 8CL has a first electrical resistivity higher than the second electrical resistivity of the second contact plug 10 as in the first embodiment.

  In FIG. 61, the source / drain region 5 and the element isolation insulating film 2 are omitted for simplification of the drawing. The configuration other than the first contact plug 8CL (for example, each of the interlayer insulating films 7, 9, 11, the second contact plug 10, the copper wiring 12, etc.) is the same as the configuration described in the first embodiment. . Therefore, description of these configurations is omitted here.

  For example, when the distance between the gate electrodes 4l and 4r becomes very narrow, the metal silicide film 6 formed in the surface of the semiconductor substrate 1 between the gate electrodes 4l and 4r becomes thin. Then, there is a high possibility that disconnection of the metal silicide film 6 occurs due to high resistance or aggregation of the metal silicide film 6.

  On the other hand, in the present embodiment, the first contact plug 8CL is formed between the first gate electrode 4l and the second gate electrode 4r. Further, the first contact plug 8CL also functions as a wiring extending in a direction perpendicular to the arrangement direction of the gate electrodes 4l and 4r in the cross-sectional view.

  Accordingly, it is possible to obtain a narrow inter-gate wiring that has a low resistance value and is stable and does not cause disconnection.

<Embodiment 12>
FIG. 62 shows a structural cross-sectional view of the semiconductor device according to the present embodiment.

  As shown in FIG. 62, in the present embodiment, a first gate electrode 4o and a second gate electrode 4f are formed on the upper surface of the semiconductor substrate 1. Here, the first gate electrode 4o is formed on the semiconductor substrate 1 via the first gate insulating film 3o. The second gate electrode 4f is formed on the semiconductor substrate 1 (the element isolation insulating film 2 in the sectional state of FIG. 62) via the second gate insulating film 3f. The first gate electrode 4o and the first gate insulating film 3o constitute a gate structure Go. The second gate electrode 4f and the second gate insulating film 3f form a gate structure Gf. Note that sidewall films SW are formed on both side surfaces of the gate structures Go and Gf.

  That is, as shown in FIG. 62, two transistors are formed on the semiconductor substrate 1. The first gate electrode 4o is a component of one transistor, while the second gate electrode 4f is a component of the other transistor. 62, the gate electrode 4o in the gate length direction is illustrated, and the gate electrode 4f in the gate width direction is illustrated.

  As in the first embodiment, the first contact plug 8S electrically connects the source / drain region 5 (more specifically, the metal silicide film 6) and the second contact plug 10S. . Specifically, the bottom surface of the first contact plug 8S is electrically connected to the metal silicide film 6 formed in the source / drain region 5. On the other hand, the upper surface of the first contact plug 8S is electrically connected to the bottom surface of the second contact plug 10S.

  In the present embodiment, the first contact plug 8S is formed between the first gate electrode 4o and the second gate electrode 4f. More specifically, one side surface of the first contact plug 8S is in direct contact with the sidewall film SW formed on the side surface of the first gate electrode 4o. The other side surface of the first contact plug 8S is in direct contact with the sidewall film SW formed on the side surface of the second gate electrode 4f.

  As in the first embodiment, also in this embodiment, the first contact plug 8S is composed of a barrier metal film 8a and a tungsten film 8b. The first contact plug 8S has a first electrical resistivity higher than the second electrical resistivity of the second contact plug 10 as in the first embodiment.

  The second contact plug 10S is electrically connected to the first contact plug 8S, the second gate electrode 4f, and the copper wiring 12. Specifically, the bottom surface of the second contact plug 10S is electrically connected to the top surface of the first contact plug 8S and the top surface of the second gate electrode 4f. Further, the upper surface of the second contact plug 10 </ b> S is electrically connected to the bottom surface of the copper wiring 12.

  As in the first embodiment, also in the present embodiment, the second contact plug 10S is composed of a barrier metal film 10a and a copper film 10b. Similarly to the first embodiment, the second contact plug 10S has a second electrical resistivity that is lower than the first electrical resistivity of the first contact plug 8S.

  In the present embodiment, the shared contact that electrically connects the source / drain region 5 of one transistor and the gate electrode 4f of the other transistor with the first contact plug 8S and the second contact plug 10S. Is configured.

  62 other than the above (for example, the source / drain region 5, the interlayer insulating films 7, 9, 11 and the copper wiring 12, etc.) are the same as those described in the first embodiment. Therefore, description of these configurations is omitted here.

  For example, in the configuration in which the contact plugs are not divided and formed as in the first contact plug 8S and the second contact plug 10S, the following problem may occur.

  As shown in FIG. 63, it is assumed that misalignment occurs when the contact plug 72 is formed in the interlayer insulating film 70. As a result, it is assumed that the contact plug 72 is formed so as to be shifted to the second gate electrode 4f side from the position at the design stage. In this case, only the sidewall film SW formed on the upper surface of the second gate electrode 4f and the side surface of the second gate electrode 4f is connected to the bottom surface of the contact plug 72. That is, in this case, the bottom surface of the contact plug 72 is not electrically connected to the source / drain region 5.

  On the other hand, in the present embodiment, the contact plug is divided and formed. The first contact plug 8S is formed between the first gate electrode 4o and the second gate electrode 4f. The bottom surface of the second contact plug 10S is electrically connected to the top surface of the first contact plug 8S and the top surface of the second gate electrode 4f.

  Accordingly, even if the second contact plug 10S is formed slightly shifted from the design stage position to the second gate electrode 4f side, the bottom surface of the second contact plug 10S is moved away from the second gate electrode 4f. And the upper surface of the first contact plug 8S. That is, even if an alignment shift occurs when the second contact plug 10S is formed, it is possible to suppress a situation in which the bottom surface of the second contact plug 10S is not connected to the top surface of the first contact plug 8S.

  As can be seen from FIG. 64, when the second contact plug 10S is formed, an alignment shift corresponding to the thickness of the sidewall film SW (about 30 nm) is allowed. FIG. 64 shows a state where misalignment has occurred. In FIG. 64, the end portion 10Se of the second contact plug 10S is located on the sidewall film SW formed on the side surface of the gate electrode 4f in plan view. Even in such a case, it can be understood that the bottom of the second contact plug 10S is in contact with the upper surface of the first contact plug 8S.

  In some cases, the gate structure Gf is not disposed on the extension line of the gate electrode 4o in the gate length direction. In such a case, the first contact plug 8S may be extended in the first interlayer insulating film 7 to function as a wiring.

  The inventions described in the above embodiments can be applied to all semiconductor devices having contact plugs. In particular, the invention described in each of the above-described embodiments is effective in a highly integrated SOC (System On a Chip), SRAM (Static Random Access Memory), and the like of 45 nm or more.

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a plan view for illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view for illustrating the effect of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view showing another configuration of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a plan view for illustrating the method for manufacturing a semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment. FIG. 11 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the third embodiment. FIG. 10 is a plan view for illustrating the method for manufacturing a semiconductor device according to the third embodiment. FIG. 11 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the third embodiment. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a fourth embodiment. FIG. 6 is a plan view showing a configuration of a semiconductor device according to a fourth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 16 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the sixth embodiment. FIG. 16 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the sixth embodiment. FIG. 10 is a plan view for illustrating the method for manufacturing a semiconductor device according to the sixth embodiment. FIG. 16 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the sixth embodiment. FIG. 16 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the sixth embodiment. FIG. 16 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the sixth embodiment. FIG. 16 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the sixth embodiment. FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a seventh embodiment. FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to an eighth embodiment. FIG. 24 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the eighth embodiment. FIG. 24 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the eighth embodiment. FIG. 24 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the eighth embodiment. FIG. 24 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the eighth embodiment. FIG. 24 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the eighth embodiment. FIG. 24 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the eighth embodiment. FIG. 10 is a cross-sectional view illustrating a configuration of a semiconductor device according to a ninth embodiment. FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a tenth embodiment. FIG. 24 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the tenth embodiment. FIG. 22 is a cross-sectional view showing a configuration of a semiconductor device according to an eleventh embodiment. FIG. 22 is a cross-sectional view showing a configuration of a semiconductor device according to a twelfth embodiment. FIG. 29 is a cross sectional view for illustrating an effect of the semiconductor device according to the twelfth embodiment. FIG. 29 is a cross sectional view for illustrating an effect of the semiconductor device according to the twelfth embodiment.

Explanation of symbols

  1 Semiconductor substrate, 2 element isolation insulating film, 3, 3n, 3p, 3l, 3r, 3f, 3o gate insulating film, 4, 4n, 4p, 4l, 4r, 4f, 4o gate electrode, 5, 5n, 5p Drain region (electrode region), 4M metal conductive layer, 4po polysilicon film, 6 metal silicide film, 7 first interlayer insulating film, 7a, 7d first contact hole, 7m first opening, 7f second Opening, 8, 8A, 8B, 8N, 8P, 8CL, 8S, 18 First contact plug, 8a, 10a, 12a, 8sn, 8t Barrier metal film, 8b Tungsten film, 8s Recessed part, 9 Second Interlayer insulating film, 9a Second contact hole, 10, 10S Second contact plug, 10b, 12b Copper film, 10L Part of second contact plug 10, 11 Third interlayer insulating film, 12 copper wiring, 31 local wiring, 41, 41M, 61 insulating film, 41a opening, 100 NMIS forming area, 200 PMIS forming area, G1, G2, Gn, Gp, Gl, Gr, Gf , Go gate structure, the length of one contact plug in contact with the La sidewall film, the length of the other contact plug in contact with the Lb sidewall film, the length of the first electrode region in the Ls gate width direction , Lt Length of the second electrode region in the gate width direction, SW, SWa, SWp side wall film, Tr1, Tr2, Trn, Trp transistor.

Claims (25)

A semiconductor substrate;
A transistor having a first gate electrode formed on the semiconductor substrate and an electrode region formed in a surface of the semiconductor substrate;
A first interlayer insulating film having an upper surface at the same height as the upper surface of the first gate electrode;
A second interlayer insulating film formed on the first interlayer insulating film;
A first contact plug formed penetrating in the film thickness direction of the first interlayer insulating film, electrically connected to the electrode region on the lower surface, and having a first electrical resistivity;
The second interlayer insulating film is formed so as to penetrate in the film thickness direction, and is electrically connected to the upper surface of the first contact plug on the lower surface, and has a second electrical resistivity lower than the first electrical resistivity. Having a second contact plug,
A semiconductor device. The first contact plug also functions as a wiring in the first interlayer insulating film.
The semiconductor device according to claim 1. The second contact plug also functions as a wiring in the second interlayer insulating film.
The semiconductor device according to claim 1. A second gate electrode formed on the semiconductor substrate;
A local wiring that is formed in the second interlayer insulating film and electrically connects the first contact plug and the second gate electrode;
The semiconductor device according to claim 2. The electrode region is
A first electrode region and a second electrode region;
The first contact plug is
One contact plug electrically connected to the first electrode region, and the other contact plug electrically connected to the second electrode region;
Sidewall films formed on both side surfaces of the first gate electrode,
In addition,
The first electrode region and the second electrode region are:
In the surface of the semiconductor substrate on one side of the first gate electrode and the other side of the first gate electrode, respectively,
One side surface portion of the one contact plug is
In direct contact with the sidewall film formed on one side of the first gate electrode;
One side surface portion of the other contact plug is
In direct contact with the sidewall film formed on the other side surface of the first gate electrode;
The one contact plug and the other contact plug are:
Electrically insulated by the first gate electrode on which the sidewall film is formed,
The semiconductor device according to claim 1. The length of the one contact plug in a portion in contact with the sidewall film in plan view is
In plan view, the length of the first electrode region in the gate width direction of the first gate electrode, or more,
The length of the other contact plug in the portion in contact with the sidewall film in plan view is
In plan view, the length of the second electrode region in the gate width direction of the first gate electrode, or more.
The semiconductor device according to claim 5. The transistor is
NMIS transistor,
At the bottom of the first contact plug,
Yb, Ta, Cr, Zr, Eu, Gd, Dy, Er, Hf, Y, La, V, and Ho are included at least.
The semiconductor device according to claim 1. The transistor is
A PMIS transistor,
At the bottom of the first contact plug,
At least a conductor of Pt, Ru, Pd, Ir, Ni, Mu, and Rh is included.
The semiconductor device according to claim 1. An insulating film formed on the first gate electrode and having an etching selectivity with respect to the second interlayer insulating film;
The semiconductor device according to claim 1. A semiconductor substrate;
A transistor having a gate electrode formed on the semiconductor substrate and an electrode region formed in the surface of the semiconductor substrate;
An insulating film formed on the electrode region so as to cover the gate electrode;
A first interlayer insulating film whose upper surface is at the same height as the upper surface of the insulating film on the gate electrode;
A second interlayer insulating film formed on the first interlayer insulating film;
A first contact plug formed penetrating in the film thickness direction of the first interlayer insulating film, electrically connected to the electrode region on the lower surface, and having a first electrical resistivity;
The second interlayer insulating film is formed so as to penetrate in the film thickness direction, and is electrically connected to the upper surface of the first contact plug on the lower surface, and has a second electrical resistivity lower than the first electrical resistivity. A second contact plug having,
The insulating film is
It has an etching selection ratio with the second interlayer insulating film, and can generate a predetermined strain in the channel region of the transistor.
A semiconductor device. The first gate electrode is
A full silicide gate electrode,
The semiconductor device according to claim 1. The first gate electrode is
A metal conductive layer;
An insulating film formed on the metal conductive layer and having an etching selectivity with the second interlayer insulating film;
The semiconductor device according to claim 1. The first contact plug is
Contains tungsten, tantalum, titanium, ruthenium and any of these nitrides, oxides, and silicides as the main component,
The second contact plug is
Contains copper, aluminum, rhodium, ruthenium, or silver as the main component.
The semiconductor device according to claim 1. The second interlayer insulating film is
Having a dielectric constant lower than that of FSG,
The semiconductor device according to claim 1. The second interlayer insulating film is
Including any of SiOC, SiCO, organic polymer and porous silica,
The semiconductor device according to claim 14. The upper surface of the first contact plug is
Has a recessed part,
The second contact plug is formed such that the recessed portion is filled;
The semiconductor device according to claim 1. A second gate electrode formed on the semiconductor substrate;
In addition,
The first contact plug is
It is formed between the first gate electrode and the second gate electrode, and also functions as the wiring extending in the first interlayer insulating film,
The semiconductor device according to claim 2. A second gate electrode formed on the semiconductor substrate;
In addition,
The first contact plug is
Formed between the first gate electrode and the second gate electrode;
The bottom surface of the second contact plug is
Electrically connected to the upper surface of the first contact plug and the upper surface of the second gate electrode;
The semiconductor device according to claim 1. A semiconductor substrate;
An NMIS transistor having a first gate electrode formed on the semiconductor substrate and a first electrode region formed in the surface of the semiconductor substrate;
A PMIS transistor having a second gate electrode formed on the semiconductor substrate and a second electrode region formed in the surface of the semiconductor substrate;
A first interlayer insulating film whose upper surface is at the same height as the upper surface of the first gate electrode and the upper surface of the second gate electrode;
A second interlayer insulating film formed on the first interlayer insulating film;
A first contact plug formed penetrating in the film thickness direction of the first interlayer insulating film;
Electrical resistance lower than the electrical resistivity of the first contact plug formed through the second interlayer insulating film in the film thickness direction, electrically connected to the upper surface of the first contact plug on the lower surface A second contact plug having a rate,
The first contact plug is
An NMIS-side contact plug electrically connected to the first electrode region on the lower surface;
A PMIS side contact plug electrically connected to the second electrode region on the lower surface;
The conductor formed on the bottom of the NMIS side contact plug is:
Different from the conductor formed at the bottom of the PMIS side contact plug,
A semiconductor device. (A) forming a transistor having a gate electrode formed on a semiconductor substrate and an electrode region formed in the surface of the semiconductor substrate;
(B) forming a first interlayer insulating film on the semiconductor substrate, the upper surface of which is the same height as the upper surface of the gate electrode;
(C) forming a first contact hole reaching the electrode region from the upper surface of the first interlayer insulating film;
(D) forming a first contact plug having a first electrical resistivity in the first contact hole;
(E) forming a second interlayer insulating film on the first interlayer insulating film;
(F) forming a second contact hole reaching the upper surface of the first contact plug from the upper surface of the second interlayer insulating film;
(G) forming a second contact plug having a second electrical resistivity lower than the first electrical resistivity in the second contact hole,
A method for manufacturing a semiconductor device. The step (C)
Forming the first contact hole, wherein the gate electrode is present in the opening;
(H) forming a sidewall film on both side surfaces of the gate electrode;
In addition,
The step (D)
(D-1) forming a conductor on the first interlayer insulating film so as to fill the first contact hole and cover the gate electrode;
(D-2) By removing the upper surface of the conductor, the two first contact plugs insulated by the gate electrode on which the sidewall film is formed are respectively formed on both side surfaces of the gate electrode. Forming the step,
Have
21. A method of manufacturing a semiconductor device according to claim 20, wherein: (I) A step of forming an insulating film so as to cover the upper surface of the gate electrode after the step (D),
In addition,
The step (E)
Forming the second interlayer insulating film on the first interlayer insulating film so as to cover the insulating film;
The step (F)
The step of forming the second contact hole by etching the second interlayer insulating film under the condition that the insulating film functions as an etching stopper.
21. A method of manufacturing a semiconductor device according to claim 20, wherein: (A) forming a transistor having a gate electrode formed on a semiconductor substrate and an electrode region formed in the surface of the semiconductor substrate;
(B) forming an insulating film on the electrode region so as to cover the upper surface of the gate electrode;
(C) forming a first interlayer insulating film on the semiconductor substrate, the upper surface of which is at the same height as the upper surface of the insulating film on the gate electrode;
(D) forming a first contact hole reaching the electrode region from the upper surface of the first interlayer insulating film;
(E) forming a first contact plug having a first electrical resistivity in the first contact hole;
(F) forming a second interlayer insulating film on the first interlayer insulating film and on the insulating film;
(G) etching the second interlayer insulating film under a condition that the insulating film functions as an etching stopper, thereby reaching the upper surface of the first contact plug from the upper surface of the second interlayer insulating film; Forming a second contact hole;
(H) forming a second contact plug having a second electrical resistivity lower than the first electrical resistivity in the second contact hole, and
The insulating film is
A stress insulating film capable of causing a predetermined strain in a channel region of the transistor;
A method for manufacturing a semiconductor device. The step (D)
(D-11) forming a conductive material in the first contact hole such that a depression due to the shape of the first contact hole is formed on the upper surface;
(D-12) A step of forming the first contact plug having a recessed portion on the upper surface in the first contact hole by performing a polishing process or a dry etching process on the conductive material. With
21. A method of manufacturing a semiconductor device according to claim 20, wherein: (A) forming an NMIS transistor having a first gate electrode formed on the semiconductor substrate and a first electrode region formed in the surface of the semiconductor substrate;
(B) forming a PMIS transistor having a second gate electrode formed on the semiconductor substrate and a second electrode region formed in the surface of the semiconductor substrate;
(C) forming a first interlayer insulating film on the semiconductor substrate, the upper surface of which is at the same height as the upper surface of the first gate electrode and the upper surface of the second gate electrode;
(D) forming a first opening exposing the first electrode region in the first interlayer insulating film;
(E) forming an NMIS side contact plug having a bottom surface made of a first conductor so as to fill the first opening as a first contact plug;
(F) forming a second opening exposing the second electrode region in the first interlayer insulating film;
(G) A PMIS-side contact plug having a bottom surface made of a second conductor different from the first conductor so as to fill the second opening is formed as the first contact plug. Process,
(H) after the steps (E) and (G), forming a second interlayer insulating film on the first interlayer insulating film;
(I) A second contact plug having a lower surface electrically connected to an upper surface of the first contact plug and having a lower electrical resistivity than the first contact plug has the second interlayer And a process of forming through the film thickness direction of the insulating film,
A method for manufacturing a semiconductor device.

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