TWI779462B - Method of manufacturing semiconductor structure - Google Patents

Abstract

A method of manufacturing a semiconductor structure including following operations is provided. A substrate extending along a first direction is provided. A trench crossing the substrate is then formed to define a first active region and a second active region. A lower isolation structure is formed in the trench, in which the lower isolation structure exposes a portion of a sidewall of the substrate. The exposed sidewall of the substrate is oxidized to form an upper isolation structure on the lower isolation structure, in which the upper isolation structure extends into the substrate. A conductive structure embedded in the upper isolation structure is formed. A first transistor and a second transistor are respectively formed in the first active region and the second active region.

Description

Method of fabricating a semiconductor structure

The present invention relates to a method of manufacturing a semiconductor structure. More specifically, the present invention relates to a method of fabricating a semiconductor structure having an antifuse structure.

Fuse elements are often used in semiconductor devices, such as semiconductor memory or logic devices. Antifuses have the opposite electrical characteristics of fuses, and a defective unit can be repaired by replacing it with a redundant unit.

Usually, an antifuse needs to be controlled by a control gate adjacent to it. Therefore, a memory cell (unit cell) is defined as 1T1C, which means a transistor (gate) and a capacitor (antifuse). However, when the number of antifuse increases, the traditional 1T1C structure will occupy a large area. In order to achieve high density memory cells or redundancy, memory cells should be as small as possible.

According to various embodiments of the present invention, a method of fabricating a semiconductor structure is provided. The method includes providing a substrate extending along a first direction. A trench is formed across the substrate to define a first active area and a second active area. Exposed sidewalls of the substrate are oxidized to form top isolation structures on the bottom isolation structures, wherein the top isolation structures extend into the substrate. A conductive structure embedded in the top isolation structure is formed. A first transistor and a second transistor are respectively formed in the first active region and the second active region.

According to some embodiments of the present invention, the source/drain regions of the first transistor and the second transistor respectively have lower surfaces located below the lower surfaces of the conductive structure.

According to some embodiments of the present invention, the top isolation structure and the bottom isolation structure jointly isolate the conductive structure from the source/drain regions of the first transistor and the second transistor.

According to some embodiments of the present invention, the width of the trench is greater than the width of the conductive structure.

According to some embodiments of the present invention, forming the first transistor and the second transistor includes forming a gate structure on the substrate of the first active region and the second active region; and forming a source/drain region on the substrate of the first active region. region and the substrate of the second active region, wherein the source/drain regions are located on opposite sides of the top isolation structure.

According to some embodiments of the present invention, the method further includes forming a plurality of contact plugs respectively connected to the source/drain regions, the gate structure and the conductive structure of the first transistor and the second transistor.

According to various embodiments of the present invention, a method of fabricating a semiconductor structure is provided. The method includes providing a substrate, the substrate includes a plurality of active regions extending along a first direction, wherein the active regions are separated from each other by shallow trench isolation structures. A trench is formed to span the active region and the shallow trench isolation structure. An antifuse structure is formed in the trench, wherein the antifuse structure includes an isolation structure covering the trench and a conductive structure embedded in the isolation structure. A transistor is formed in each active region, wherein the transistor is separated from the conductive structure by an isolation structure.

According to some embodiments of the present invention, forming the antifuse structure includes forming a bottom portion of the isolation structure in the trench, wherein the height of the bottom portion of the isolation structure is smaller than the depth of the trench; forming a top portion of the isolation structure, wherein the top portion extending laterally into the substrate; and forming a conductive structure on the isolation structure.

According to some embodiments of the present invention, forming a transistor includes forming a gate structure on the substrate of each active region; and forming a source/drain region in the substrate of the active region, wherein the source/drain region and the gate The structures are adjacent and have a lower surface located below the lower surface of the conductive structure.

According to some embodiments of the present invention, the method includes forming a plurality of contact plugs respectively connected to the source/drain regions, the gate structure, and the conductive structure.

The following disclosure provides many different embodiments, or examples, in order to achieve the different features of each embodiment. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these examples are only examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the ensuing description may include embodiments in which the first and second features are formed in direct contact, and may also include that additional features may be formed in the Between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat element symbols and/or letters in each example. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

Relative spatial terms such as "below", "below", "above", "above" and the like are used herein to facilitate the description of the relative relationship between one element or feature and another element or feature, such as shown in the figure. The real meaning of these spatially relative terms includes other orientations. For example, when the drawing is turned upside down by 180 degrees, the relationship between one element and another element may change from "below" and "below" to "above" and "above". In addition, the spatially relative descriptions used in this article should also be interpreted in the same way.

FIG. 1 is a flowchart of a method 10 for fabricating a semiconductor structure according to some embodiments of the present invention. Method 10 includes operation 12 , operation 14 , operation 16 , operation 18 , operation 20 and operation 22 . It should be noted that the method shown in Figure 1 is only an example and is not intended to limit the invention. Accordingly, additional operations may be performed before, during and/or after the method shown in FIG. 1 , and only some other operations are briefly described herein. FIGS. 2 to 4 and FIGS. 5A to 11 are top views and cross-sectional views of each step in the manufacturing process of the semiconductor structure according to the method 10 shown in FIG. 1 .

Please refer to Figure 1 and Figure 2. In operation 12 of FIG. 1 , a substrate 100 extending along a first direction D1 is provided. The substrate 100 may include a plurality of active regions 102 , 104 and 106 extending along a first direction D1 . Adjacent active regions are separated by shallow trench isolation structures 110 . For example, as shown in FIG. 2 , STI structure 110 is located between and separates active region 102 and active region 104 . In some embodiments, the substrate 100 may be a single crystal or polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium or the like, a silicon-on-insulator (SOI) substrate, or the like. In some embodiments, the shallow trench isolation structure 110 includes tetraethoxysilane (TEOS), silicon oxide, silicon nitride, silicon oxynitride, or fluoride-doped silicate (FSG).

Referring to FIG. 3 , a mask layer 120 is formed on the substrate 100 to cover the active regions 102 , 104 , 106 and the shallow trench isolation structure 110 . In some embodiments, the mask layer 120 is made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other suitable materials or combinations thereof. The mask layer 120 may be formed on the substrate 100 by a suitable deposition method including a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, or a combination thereof. In some embodiments, the mask layer 120 is patterned and has an opening OP1 to expose the underlying structure. The mask layer 120 can be patterned by a suitable method, such as photolithography patterning and etching. Accordingly, an opening OP1 is formed in the mask layer 120 to expose a portion of the active regions 102 , 104 and 106 and the shallow trench isolation structure 110 .

Please refer to Figure 1 and Figure 4. In operation 14 of FIG. 1 , a trench T1 is formed across the substrate 100 . In some embodiments, the portions of the active regions 102 , 104 , 106 and the STI structure 110 exposed by the opening OP1 (as shown in FIG. 3 ) are etched to form a trench T1 in the substrate 100 . The trench T1 extends along the second direction D2 across the active regions 102 , 104 and 106 and the STI structure 110 such that the active regions 102 , 104 and 106 are divided into a plurality of sections. For example, the trench T1 spans the active region 102 to define a first active region 102a and a second active region 102b.

Fig. 5A and Fig. 5B are cross-sectional views taken along line segments A-A' and B-B' of Fig. 4, respectively. As shown in FIG. 5A , the trench T1 exposes the sidewall 108 of the substrate 100 . A portion of the substrate 100 and the STI structure 110 may be etched by a suitable etching process to form the trench T1. In some embodiments, the depth H1 of the trench T1 in the active region 102 (as shown in FIG. 5A ) is deeper than the depth H1 ′ in the shallow trench isolation structure 110 (as shown in FIG. 5B ). In the following operations, a cross-sectional view of the active region 102 and the adjacent shallow trench isolation structure 110 is taken as an example.

Next, in operation 16 of FIG. 1 , a bottom isolation structure 202 is formed in the trench T1 . 6A to 7B are detailed steps for performing operation 16 according to an embodiment of the present invention. Figure 6A, Figure 7A and Figure 6B, Figure 7B are cross-sections taken along the line segments A-A' and B-B' of Figure 4, respectively.

Referring to FIG. 6A and FIG. 6B , the trench T1 is filled with an insulating material to form an isolation layer 200 ′. In some embodiments, the isolation layer 200' includes silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), or fluoride-doped silicate (FSG). In some examples, the material of the isolation layer 200' is the same as that of the shallow trench isolation structure 110. The isolation layer 200' can be formed by a suitable deposition method, including CVD process, ALD process, PVD process or a combination thereof. In some embodiments, an isolation material may be formed in the trench T1 and cover the top surface of the mask layer 120 , and then a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to form the isolation layer 200 ′.

After that, referring to FIG. 7A and FIG. 7B , the isolation layer 200' is recessed to form the bottom isolation structure 202. Referring to FIG. The recess isolation layer 200' exposes a portion of the sidewall 108 of the substrate 100 to be oxidized in a subsequent step. In some embodiments, the bottom isolation structure 202 is formed by using a suitable anisotropic etching process (eg, a dry etching process). In some embodiments, the height H2 of the bottom isolation structure 202 is smaller than the depth H1 of the trench T1 in the substrate 100 .

Please refer to Figure 1 and Figures 8A-8B. In operation 18 of FIG. 1 , exposed sidewalls 108 of substrate 100 are oxidized to form top isolation structures 204 on bottom isolation structures 202 , wherein top isolation structures 204 extend into substrate 100 . In some embodiments, the top isolation structure 204 is formed by performing a thermal oxidation process to oxidize the exposed sidewall 108 of the substrate 100 (as shown in FIG. 7A ). As shown in FIG. 8A , the top isolation structure 204 extends laterally into the substrate 100 . Specifically, the top isolation structure 204 is formed on the bottom isolation structure 202 and has an opening exposing a portion of the top surface of the bottom isolation structure 202 . In this way, the top isolation structure 204 and the bottom isolation structure 202 together form the isolation structure 200 to cover the sidewall and the bottom of the trench T1.

Please refer to Figure 1 and Figures 9A-9B. In operation 20 of FIG. 1 , a conductive structure 210 embedded in the isolation structure 200 is formed. In some embodiments, the conductive structure 210 is formed by a suitable deposition method, including chemical vapor deposition (chemical vapor deposition, CVD) process, atomic layer deposition (atomic layer deposition, ALD) process, physical vapor deposition (physical vapor deposition) , PVD) process or a combination thereof. The conductive structure 210 is disposed on the exposed top surface of the bottom isolation structure 202 shown in FIG. 8A. Specifically, the bottom portion of the sidewall of the conductive structure 210 is covered by the top isolation structure 204 . That is, the top isolation structure 204 separates the conductive structure 210 from the substrate 100 . As shown in FIG. 9A , the width W2 of the conductive structure 210 is smaller than the width W1 of the trench T1 . In some embodiments, the conductive structure 210 includes a conductive material (eg, polysilicon, metal, metal alloy), other suitable materials, and/or combinations thereof.

Please refer to FIG. 10A and FIG. 10B , after the conductive structure 210 is formed, the mask layer 120 is removed (as shown in FIG. 9A and FIG. 9B ). Specifically, the mask layer 120 is removed through an etching process such as a dry etching process or a wet etching process to expose the top surface of the substrate 100 . .

Please refer to Figure 1 and Figure 11. In operation 22 of FIG. 1 , a first transistor 302a and a second transistor 302 are formed in the first active region 102a and the second active region 102b, respectively. As shown in FIG. 11 , the first transistor 302 a includes a gate structure 310 and a source/drain region 312 , and the second transistor 302 b includes a gate structure 320 and a source/drain region 322 . In some embodiments, the first transistor 302 a and the second transistor 302 b are formed in a p-well region (not shown) of the substrate 100 . The source/drain regions 312 and 322 are located on opposite sides of the isolation structure 200 and adjacent to the gate structures 310 and 320 respectively. The source/drain regions 312 and 322 respectively have lower surfaces 312s and 322s located below the lower surface 210s of the conductive structure 210 to completely isolate the conductive structure from the p-type well region of the substrate 100 to prevent leakage issue.

The formation of the first transistor 302a may include forming a gate structure 310 on the substrate 100 of the first active region 102a, and forming a source/drain region 312 in the substrate 100 of the first active region 102a. For example, the formation of the gate structure 310 may include a suitable deposition method, such as a CVD process, a PVD process, or the like. In some embodiments, the gate structure 310 includes polysilicon, metals such as aluminum (Al), copper (Cu), or tungsten (W), other conductive materials, or combinations thereof. In addition, the source/drain region 312 can be formed by performing an ion implantation process, and the doping depth must be deeper than the lower surface 210 s of the conductive structure 210 . In some embodiments, the source/drain region 312 is doped with an N-type dopant, such as phosphorous or arsenic. The materials and formation of the gate structure 320 and the source/drain region 322 of the second transistor 302b may be the same as those of the first transistor 302a, and will not be repeated here. It should be noted that other transistors (not shown) may also be formed in other active regions (eg, active regions 104 , 106 ) through the above process.

In some embodiments, after forming the first transistor 302a and the second transistor 302b, the method further includes forming a plurality of contact plugs respectively connected to the source/drain regions of the first and second transistors 302a, 302b 312 , 322 are connected to the gate structures 310 , 320 and the conductive structure 210 . For example, the contact plugs 400 are grounded and respectively connected to the source/drain regions 312 and 322 away from the isolation structure 200 .

Please continue to refer to FIG. 11 , the isolation structure 200 separates the conductive structure 210 from the source/drain regions 312 and 322 of the first transistor 302 a and the second transistor 302 b. A pair of antifuse structures AF1 and AF2 are formed between transistors 302a and 302b. The conductive structure 210 acts as a top plate for the antifuse structures AF1 and AF2 . The source/drain regions 312 and 322 serve as bottom plates of the antifuse structures AF1 and AF2 . Isolation structure 200 , more specifically top isolation structure 204 , acts as a dielectric layer between the top and bottom plates of antifuse structures AF1 and AF2 . Specifically, the antifuse structure AF1 includes a conductive structure 210, an isolation structure 200, and a source/drain region 312 shared with the transistor 302a. Similarly, the antifuse structure AF2 includes a conductive structure 210, an isolation structure 200, and a source/drain region 322 shared with the transistor 302b. A voltage may be applied across antifuses AF1 and AF2 (ie, source/drain regions 312, 322 and conductive structure 210) to induce breakdown of the dielectric layer, which results in a rupture of the dielectric layer ( rupture).

As described above, according to an embodiment of the present invention, a method of manufacturing a semiconductor structure is provided. In the fabrication of the semiconductor structures of the present disclosure, isolation structures separate the substrate into multiple active regions. Conductive structures are then embedded from the top surface of the isolation structure, and transistors are formed in the active regions on opposite sides of the isolation structure. Therefore, a pair of antifuse structures are formed between two adjacent transistors and can be blown out at the same time. In other words, the method of the present disclosure can reduce the size of semiconductor structures having antifuse structures and transistors, thereby achieving high device density.

Although the present invention has been disclosed above in terms of implementation, it is not intended to limit the present invention. Anyone skilled in this art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be defined by the appended patent application scope.

10: method 12, 14, 16, 18, 20, 22: Operation 100: Semiconductors 102, 104, 106: active area 102a: The first active area 102b: the second active area 108: side wall 110:Shallow trench isolation structure 120: mask layer 200: isolation structure 200': isolation layer 202: Bottom isolation structure 204: top isolation structure 210: Conductive structure 210S, 312S, 322S: Lower surface 302a: first transistor 302b: second transistor 310, 320:Gate structure 312, 322: source/drain regions 400: contact plug A-A', B-B': line segment AF1, AF2: Antifuse structure D1: the first direction D2: Second direction H1, H1': Depth H2: height OP1: opening T1: Groove W1, W2: width

Aspects of the present disclosure can be best understood from the following detailed description when read with the accompanying drawings. It is worth noting that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a flowchart illustrating a method of fabricating a semiconductor structure according to some embodiments of the present invention. 2 to 4 are top views of various steps in the process of manufacturing a semiconductor structure according to some embodiments of the present invention. Figures 5A, 6A, 7A, 8A, 9A, and 10A are cross-sectional views taken along the line A-A' of Figure 4 for various steps in the process of manufacturing a semiconductor structure according to certain embodiments of the present invention. Figures 5B, 6B, 7B, 8B, 9B, and 10B are cross-sectional views taken along the line B-B' of Figure 4 for various steps in the process of manufacturing a semiconductor structure according to certain embodiments of the present invention. Figure 11 is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

10: method

12,14,16,18,20,22: Operation

Claims (9)

A method of manufacturing a semiconductor structure, comprising: providing a substrate extending along a first direction; forming a trench across the substrate to define a first active region and a second active region, wherein the trench has a width ; forming a bottom isolation structure in the trench, wherein the bottom isolation structure exposes a portion of a sidewall of the substrate; oxidizing the exposed sidewall of the substrate to form a top isolation structure on the bottom isolation structure, wherein the top isolation structure extending into the substrate; forming a conductive structure embedded in the top isolation structure, wherein the conductive structure has a width smaller than the width of the trench; and forming a conductive structure in the first active area and the second active area, respectively. The first transistor and a second transistor. The method according to claim 1, wherein a source/drain region of the first transistor and the second transistor respectively have lower surfaces located below the lower surface of the conductive structure. The method of claim 2, wherein the top isolation structure and the bottom isolation structure jointly isolate the conductive structure from the source/drain regions of the first transistor and the second transistor. The method according to claim 1, wherein forming the first transistor and the second transistor comprises: forming a gate structure on the substrate of the first active region and the second active region; and forming a source/drain region in the substrate of the first active region and the second active region, wherein the Source/drain regions are located on opposite sides of the top isolation structure. The method as claimed in claim 4, further comprising forming a plurality of contact plugs respectively connected to the source/drain regions of the first transistor and the second transistor, the gate structure and the conductive structure. A method of manufacturing a semiconductor structure, comprising: providing a substrate, the substrate includes a plurality of active regions extending along a first direction, wherein the active regions are separated from each other by a shallow trench isolation structure; forming a trench across the Active regions and the shallow trench isolation structure, wherein the trench has a width; forming an antifuse structure in the trench, wherein the antifuse structure includes an isolation structure covering the trench and embedding the isolation A conductive structure in the structure, wherein the conductive structure has a width smaller than the width of the trench; and a transistor is formed in each of the active regions, wherein the transistor is separated from the conductive structure by the isolation structure. The method according to claim 6, wherein forming the antifuse structure includes: forming a bottom portion of the isolation structure in the trench, wherein the bottom portion of the isolation structure has a height less than a depth of the trench; forming a top portion of the isolation structure, wherein the top portion extends laterally to in the substrate; and forming the conductive structure on the isolation structure. The method as described in claim 6, wherein forming the transistor comprises: forming a gate structure on the substrate of each active region; and forming a source/drain region in the substrate of each active region, Wherein the source/drain region is adjacent to the gate structure and has a lower surface located below the lower surface of the conductive structure. The method as claimed in claim 8, further comprising forming a plurality of contact plugs respectively connected to the source/drain region, the gate structure, and the conductive structure.

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