KR100688543B1 - Recess gate-type semiconductor device and method of fabricating the same - Google Patents

Abstract

A recess gate type semiconductor device and a method of manufacturing the same are provided. The semiconductor device according to the present invention has a recess formed in the active region by filling a recess trench formed in the first direction to be spaced apart from the sidewalls of the device isolation region and in contact with the sidewalls of the device isolation region in the second direction. And a source and a drain formed to be spaced apart from the active region with the gate electrode interposed therebetween. The width of the active region recess trench in the second direction is greater than the width of the source and drain in the second direction. Accordingly, the semiconductor device according to the present invention has excellent junction leakage current and refresh characteristics.

Description

Recess gate-type semiconductor device and method of fabricating the same

1A is a plan view showing a conventional recess gate type semiconductor device;

FIG. 1B is a cross-sectional view taken at II ′ of the semiconductor device of FIG. 1A; FIG.

2A is a plan view showing a recessed gate type semiconductor device according to the first embodiment of the present invention;

2B and 2C are cross sectional views taken along lines II ′ and II-II ′ of the semiconductor device of FIG. 2A, respectively;

3A to 7A are plan views showing a method of manufacturing a recessed gate type semiconductor device according to the first embodiment of the present invention;

3B to 7B are cross-sectional views taken on line II ′ of the semiconductor device of FIGS. 3A to 7A, respectively;

8A is a plan view showing a recessed gate type semiconductor device according to a second embodiment of the present invention;

8B and 8C are cross sectional views taken along lines II ′ and II-II ′ of the semiconductor device of FIG. 8A, respectively;

9A to 11A are plan views showing a method of manufacturing a recessed gate type semiconductor device according to a second embodiment of the present invention; And

9B to 11B are cross-sectional views taken on line II ′ of the semiconductor device of FIGS. 9A to 11A, respectively.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a recess gate-type semiconductor device and a method for manufacturing the same.

As the degree of integration of semiconductor devices increases, the design rules for the components of the semiconductor devices decrease. In particular, in semiconductor devices that require a large number of transistors, the gate length, which is a standard for design rules, has been reduced. As a result, the channel length of the transistor is also reduced. Reducing the channel length of the transistor increases the short channel effect. As a result, the off current of the transistor is increased, thereby lowering the refresh characteristics of the semiconductor device, for example, the memory device.

Recently, a method for increasing the channel length for the same gate electrode width has been studied in order to prevent the deterioration of the refresh characteristics due to such a short channel effect in a high density device. For example, a method of forming a recess trench or a trench gate by forming a recess trench into a semiconductor substrate has been studied. Hereinafter, a conventional recess gate semiconductor device will be described with reference to the accompanying drawings.

1A and 1B, a conventional recess gate type semiconductor device includes an active region 110 defined by an isolation region 105 of a semiconductor substrate 100 and a source and a drain spaced apart from each other within the active region 110. A gate electrode 130 formed between the source 150 and the source and drain 150 and insulated from the active region 110 by the gate insulating layer 125.

The gate electrode 130 includes a recess 130a formed by being recessed into the active region 110 and a protrusion 130b protruding onto the active region 110. The active region 110 extends in the X ₁ direction, and the gate electrode protrusion 130b extends in the X ₂ direction. A gate spacer 145 may be further formed on the sidewall of the gate electrode 130.

The channel region is formed in the active region 110 to surround the bottom of the gate recess 130a. As a result, the length of the channel may be longer than the length L ₁₂ of the gate electrode protrusion 130b in the X ₁ direction. Therefore, the recess gate type semiconductor device may have a longer channel length than the planar type semiconductor device. Accordingly, the recess gate type semiconductor device can suppress the short channel effect.

However, the edge portion of the active region 110 at the boundary portion B that is in contact with the device isolation region 105 protrudes sharply toward the gate electrode 130 (active core sharpening). This phenomenon is known to occur because the edge portion of the active region 110 is not etched because the recess trench etch rate for forming the gate recess 130a is slow at the boundary portion B1.

Accordingly, most of the gate electrodes 130 have an internal gate structure in which the width L ₁₂ of the protrusion 130b is smaller than the width L ₁₃ of the recess 130a, but is in contact with the device isolation region 105. At the edge, the gate electrode 130 has an outer gate structure in which the width L ₁₂ of the protrusion 130b is larger than the width L ₁₁ of the recess 130a. As a result, the source and drain 150, B below the edge of gate protrusion 130b are formed shallow at low concentration. This is because impurity implantation for forming the source and drain 150 is screened by the edge of the gate protrusion 130b and the gate spacer 145.

When a gate voltage is applied to the gate electrode 130 of the semiconductor device, an electric field is concentrated on the source / drain B under the edge of the gate electrode protrusion 130b. As a result, the leakage current at the junction of the source and drain 150 is increased, and the refresh characteristics of the semiconductor device such as the memory device are reduced.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a recess gate type semiconductor device having improved junction characteristics by reducing junction leakage current.

Another object of the present invention is to provide a method of manufacturing a recessed gate type semiconductor device in which the junction leakage current is reduced to improve refresh characteristics.

According to an aspect of the present invention for achieving the above technical problem, it is defined by a device isolation region formed in a semiconductor substrate, spaced apart from sidewalls of the device isolation region in a first direction and the device isolation in a second direction An active region comprising a recess trench formed in contact with sidewalls of the region; A gate insulating film on at least a portion of the active region including the recess trench; A gate electrode formed on the gate insulating layer, the gate electrode having a recess portion filling the recess trench; And a source and a drain formed in the active region with the gate electrode interposed therebetween. The width of the active region recess trench in the second direction is greater than the width of the source and drain in the second direction.

According to an aspect of the present invention for achieving the above technical problem, the gate electrode may include a protrusion on the active region connected to the recess. Further, the width in the first direction of the gate electrode protrusion may be smaller than the width in the first direction of the gate electrode recess.

According to another aspect of an aspect of the present invention for achieving the above technical problem, the active region recess trench is a first hole tap extending the width of the ends in contact with the device isolation region in the second direction than the source and drain (first hole tabs) may be provided.

According to another aspect of the present invention for achieving the above technical problem, the active region recess trench is a width in the first direction in the vicinity of the edge of the end contacting the source and drain of the active region recess trench It may include extending second hole taps. In addition, one end of each of the active region recess trench second hole tabs may be in contact with the device isolation region.

According to another aspect of the present invention for achieving the above technical problem, it is defined by a device isolation region formed in a semiconductor substrate, spaced apart from sidewalls of the device isolation region in a first direction and the device isolation in a second direction An active region comprising a recess trench formed in contact with sidewalls of the region; A gate insulating film on at least a portion of the active region including the recess trench; A gate electrode formed on the gate insulating layer, the gate electrode having a recess portion filling the recess trench; And a source and a drain formed in the active region with the gate electrode interposed therebetween. The active region recess trench has first hole tabs extending the width of the ends in contact with the device isolation region in the second direction than the source and the drain, and the edges near the edges of the ends in contact with the source and drain. Each of the second hole tabs extends in a width in the first direction.

According to an aspect of the present invention for achieving the above another technical problem, there is provided a method of manufacturing a recessed gate type semiconductor device comprising the following steps. First, a device isolation region is formed in the semiconductor substrate that extends in the first direction and defines an active region having a pair of tabs so that a portion of the opposite ends extends in the second direction. Subsequently, a photoresist pattern exposing an active region between the active region tabs and the active region tabs is formed. Subsequently, the exposed active region is etched using the photoresist pattern as an etch protective layer to form a recess trench. Subsequently, a gate insulating layer is formed on the active region including the recess trench. Subsequently, a gate electrode filling the recess trench is formed on the gate insulating film.

According to an aspect of the present invention for achieving the another technical problem, the photoresist pattern is formed including hole tabs to extend the edge portion of the active region between the active region tabs to extend in the first direction can do. Further, each of the photoresist pattern hole tabs may be formed such that one end thereof contacts the device isolation region.

According to another aspect of an aspect of the present invention for achieving the above another technical problem, the manufacturing method further comprises the step of forming a source and a drain in the active region on both sides of the gate electrode after forming the gate electrode; Can be.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. In the drawings, the components are exaggerated in size for convenience of description.

First embodiment

2A is a plan view illustrating a recess gate type semiconductor device according to a first exemplary embodiment of the present invention, and FIGS. 2B and 2C are cross-sectional views taken along lines II ′ and II-II ′ of FIG. 2A, respectively.

2A to 2C, the semiconductor device according to the first exemplary embodiment includes a recess 230a formed by filling an active region 210 arranged in an array and a recess trench 220 in the active region 210. And a gate electrode 230 having a protrusion 230b formed on the active region 210. The source and drain 250 may be formed in the active region 210 spaced apart from each other with the gate electrode 230 interposed therebetween. The source and drain 250 may be formed in groups of two or more, and are shown as one reference number without being separated from each other. For example, if one of the sources and the drain 250 is limited to the source, adjacent ones may be drains and vice versa.

The active region 210 is defined by the isolation region 205 formed in the semiconductor substrate 200. The device isolation region 205 may be formed of an insulating layer, for example, a shallow trench isolation (STI) formed of a silicon oxide layer. The active region 210 has a predetermined width and extends in the X ₁ direction. The active region 210 includes a recess trench 220 spaced apart from sidewalls of the device isolation region 205 from the X ₁ direction and in contact with the device isolation region 205 in the X ₂ direction.

The channel region 260 is formed along the active region 210 below the gate electrode recess 230a and is connected to the source and drain 250 as shown in FIG. 2B. Accordingly, the length of the channel region 260 is greater than the length D ₁₂ of the gate electrode protrusion 230b in the X ₁ direction, that is, the channel length of the planar gate electrode structure. As a result, the short channel effect is suppressed.

The recess trench 220 may include first hole tabs 220 ′ at both ends of the recess trench 220 to widen the width of the source and drain 250 in the X ₂ direction. The length of the recess trench first hole taps 220 ′ in the X ₁ direction may be the same as the length of the remaining recess trench 220 in the X ₁ direction. However, the edge portion of the recess trench first hole tabs 220 'may be formed in a round curve. In this case, the length of the recess trench first hole taps 220 ′ in the X ₁ direction may be equal to or smaller than the length of the remaining recess trench 220. However, since the recess trench first hole tabs 220 'are provided at the edge of the recess trench 220, the length of the recess trench 220 formed between the source and drain 250 in the X ₁ direction. Can be kept constant.

The gate electrode protrusion 230b is connected to the gate electrode recess 230a and may be formed in a line type extending in the X ₂ direction. The acute angle formed by the X ₁ direction and the X ₂ direction may be 30 ^° to 90 ^° , preferably in the range of 40 ^° to 80 ^° .

The gate electrode recess 330a is formed by filling the recess trench 220. Accordingly, the gate electrode recess 330a includes a first tab 230a 'formed by filling the recess trench first hole tab 220'. Accordingly, as shown in FIG. 2C, the length D _{23 in} the X ₂ direction of the gate electrode recess 330a is greater than the length D _{21 in} the X ₂ direction of the source and drain 250. It becomes larger by twice the length D _{22 in} the X ₂ direction of the tab 230a ′.

The length D _{11 in} the X ₁ direction of the portion of the gate electrode recess 330a between the source and the drain 250 may be kept constant. This is because, as described above, the portion of the recess trench 220 between the source and drain 250 is formed to have a constant width in the X ₁ direction. Therefore, the length of the portion of the gate electrode recess 330a between the source and drain 250 in the X ₁ direction is larger than the gate electrode protrusion 230b. Accordingly, the portion of the gate electrode 230 between the source and drain 250 is formed to have an internal gate structure. As a result, there is no region where the electric field is concentrated, so that the junction leakage current is not high, and as a result, the refresh characteristic is improved.

However, the edge portion of the gate electrode recess portion first tab 230a ′ formed by filling the recess trench first hole tabs 220 ′ may be curved. In this case, the length in the X ₁ direction in the edge portion of the gate electrode recessed portion first tab (230a ') may be less equal to the length in the X ₁ direction of the gate electrode projection (230b) or less. However, since the edge portion of the gate electrode recessed first tab 230a ′ is not directly adjacent to the source and drain 250, it does not significantly affect the junction leakage current and the refresh characteristic.

The gate insulating layer 225 insulates the gate electrode 230 from the active region 210. The gate insulating layer 225 is provided between the gate electrode 230 and the active region 210, but may remain between the source and drain 250.

According to the semiconductor device of the recessed gate structure according to the present invention, a portion of the gate electrode 230 between the source and the drain 250 is formed as an internal gate structure. Therefore, the junction leakage current and refresh characteristics are excellent.

3A to 7A are plan views illustrating a method of manufacturing a recessed gate type semiconductor device according to a first embodiment of the present invention, and FIGS. 3B to 7B are respectively taken along line II ′ of the semiconductor device of FIGS. 3A to 7A. These are cross sections taken. A method of manufacturing the semiconductor device according to the first embodiment of the present invention may refer to the semiconductor device and the description thereof according to the first embodiment of the present invention. Like reference numerals denote like elements.

3A and 3B, an isolation region 205 is formed in the semiconductor substrate 200 to define the active region 210. The active region 210 has a pair of tabs 210 ′ extending in the X ₁ direction and a portion of the opposite ends extending in the X ₂ direction. That is, based on the length in the X ₂ direction, the length D ₂₃ of the portion of the active region 210 where the active region tabs 210 'are provided is the active region without the active region tab 210'. The length D _{21 of the} portion 210 may be greater than twice the length D ₂₂ of the active region tab 210 ′. The active region tabs 210 ′ serve to extend the length of the recess trench 220 and the gate electrode 230 in the X ₂ direction.

4A and 4B, a photoresist pattern 215 exposing the active region 210 between the active region tabs 210 ′ and the active region tabs 210 ′ is formed. The photoresist pattern 215 may be formed by forming a photoresist layer (not shown) on the entire surface of the active region 210 and then patterning the photoresist layer by performing exposure and development operations. The photoresist pattern 215 may be formed in a line type extending in the second direction.

Referring to FIGS. 5A and 5B, the recessed trench 220 is formed by etching the exposed active region 210 using the photoresist pattern 215 as an etch protective layer, and the photoresist pattern 215 is removed. The etching step may be performed with a selectivity such that the device isolation region 205 exposed by the photoresist pattern 215 is not etched, and only the exposed active region 210 can be etched. The etch selectivity may be controlled by using an etching gas.

The recess trench 220 includes a hole tab 220 ′ formed by etching a portion of the active region tab 210 ′. Accordingly, the length of the recess trench 220 in the X ₂ direction is larger than the length of the peripheral active region 210 in the X ₂ direction.

6A and 6B, a gate insulating layer 225 is formed on the active region 210 including the recess trench 220. next. The gate electrode layer 228 is formed to fill the recess wrench 220 on the gate insulating layer 225. The gate insulating film 225 may be formed of a thermal oxide film using a thermal oxidation method, or may be formed by depositing an oxide film using a chemical vapor deposition (CVD) method. In the case where the gate insulating film 225 is formed by the CVD method, the gate insulating film 225 may be formed on the device isolation region 205 as shown in FIG. 6B.

The gate electrode layer 228 may be formed of polysilicon, aluminum (Al), tungsten (W), titanium nitride (TiN), tantalum (Ta), platinum (Pt), or a composite film thereof. The gate electrode layer 228 may further include a metal silicide layer (not shown) on the polysilicon to lower the resistance. For example, metal silicides such as tungsten, cobalt, titanium or nickel may be used as the metal silicide.

Subsequently, the gate electrode layer 228 may be planarized selectively. The planarization step may be performed using an etch-back or chemical mechanical polishing (CMP) method.

7A and 7B, the gate electrode layer 228 is patterned to form the gate electrode 230. Subsequently, the gate spacer 245 may be formed on the sidewall of the gate electrode 230. In the patterning of the gate electrode 230, a second photoresist pattern (not shown) is formed on the entire surface of the gate electrode layer 228, and the gate electrode layer 228 is etched using the second photoresist pattern as an etch protective layer. Can be done. The etching for forming the gate electrode 230 may be excessively performed to partially expose the active region 210 inside the recess trench 220. Preferably, the etching may be performed such that the sidewall of the gate electrode 230 is exposed to a depth of about 100 to 200 Å from the surface of the active region 210.

The gate electrode 230 includes a recess 230a formed by filling the recess trench 220 and a protrusion 230b formed on the active region 210. The length of the gate electrode protrusion 230b in the X ₁ direction is preferably smaller than the length of the gate electrode recess 230a in the X ₁ direction. In addition, the gate electrode protrusion 230b may be formed in a line type extending in the X ₂ direction. Accordingly, the gate electrode protrusion 230b may be shared by the active regions 210 arranged in the array. In addition, the gate electrode recess 230a may include tabs 230a 'formed by filling the recess trench hole tabs 220'.

Subsequently, a source and a drain (see 250 in FIG. 2) are formed in both active regions 210 with the gate electrode 230 interposed therebetween according to a method known to those skilled in the art. . Subsequently, a metal wiring can be formed by a conventional method to manufacture a semiconductor device. In particular, when the semiconductor device is a DRAM device, the method may further include forming a capacitor in a conventional manner before forming the metal line.

According to the method of manufacturing the semiconductor device, the length of the active region 210 in the X ₂ direction can be extended by forming the active region tab 210 ′. Accordingly, the length of the recess trench 220 and the gate electrode recess 230a in the X ₂ direction is extended. As a result, the gate electrode 230 between the source and the drain may be formed as an internal gate structure. Therefore, the semiconductor device manufactured according to the above manufacturing method has excellent junction leakage current and refresh characteristics.

Second embodiment

8A is a plan view illustrating a recessed gate type semiconductor device according to a second exemplary embodiment of the present invention, and FIGS. 8B and 8C are cross-sectional views taken along lines II ′ and II-II ′ of FIG. 8A, respectively. The semiconductor device according to the second embodiment is a modified structure of the semiconductor device according to the first embodiment. Therefore, the configuration of the semiconductor device according to the second embodiment may refer to the description and the drawings of the semiconductor device according to the first embodiment. Reference numerals of the same or similar structure differ only by 100 digits.

8A to 8C, the semiconductor device according to the second exemplary embodiment of the present invention includes a recess formed by filling an active region 410 arranged in an array and a recess trench 420 in the active region 410. And a gate electrode 430 having a portion 430a and a protrusion 430b formed on the active region 410. The source and drain 450 may be formed in the active region 410 spaced apart from each other with the gate electrode 430 interposed therebetween. The gate insulating layer 425 insulates the gate electrode 430 from the active region 410.

The active region 410 is defined by the isolation region 405 formed in the semiconductor substrate 400. In the active region 410, a recess trench 420 is spaced apart from the sidewalls of the device isolation region 405 from the X ₁ direction and in contact with the device isolation region 405 in the X ₂ direction. . The channel region 460 is formed along the active region 410 under the gate electrode recess 430a and may be connected to the source and drain 450.

The recess trench 420 includes first hole tabs 420 ′ at both ends to widen the X ₂ direction width than the source and drain 450. The length of the recess trench first hole taps 420 ′ in the X ₁ direction may be the same as the length of the remaining recess trench 420 in the X ₁ direction. The recess trench 420 also includes second hole tabs 420 "extending in the width of the X ₁ direction near the edges of the ends in contact with the source and drain 450. The recess trench second hole taps ( One end of the 420 ″ may be in contact with the isolation region 405.

The gate electrode protrusion 430b is connected to the gate electrode recess 430a and may be formed in a line type extending in the X ₂ direction. The gate electrode recess 430a is formed by filling the recess trench 420. Accordingly, the gate electrode recess 430a is formed by filling the first trench 430a 'formed by filling the recess trench first hole tab 420' and the recess trench second hole tab 420 ″. Two tabs 430a ". Accordingly, as shown in Fig. 8c, as viewed relative to the length in the X ₂ direction, the length of a gate electrode recess portion (430a) (H ₂₃₎ is a length of the source and drain (450) (H ₂₁₎ It is larger than twice the length H ₂₂ of the first tab 430a '.

As shown in FIG. 8B, the length H _{14 of the} portion of the gate electrode recessed portion 430a including the gate electrode recessed portion second tab 430a ″ when viewed based on the length in the X ₁ direction. May be greater than twice the length H ₁₃ of the gate electrode recess portion second tab 430a ″ than the length H ₁₁ of the portion of the gate electrode recess portion 430a of the other portion. The length H ₁₁ of the portion of the gate electrode recessed portion 430a not including the gate electrode recessed portion second tab 430a ″ may be greater than the length H ₁₂ of the gate electrode protrusion 430b. The gate electrode 430 between the source and the drain 250 may be formed to have an inner gate structure as compared with the first embodiment, whereby the junction leakage current and the refresh characteristic may be further improved.

9A to 11A are plan views illustrating a method of manufacturing a recessed gate type semiconductor device according to a second exemplary embodiment of the present invention, and FIGS. 9B to 11B are respectively taken along line II ′ of the semiconductor device of FIGS. 9A to 11A. These are cross sections taken. The method of manufacturing the semiconductor device according to the second embodiment of the present invention may refer to the method of manufacturing the semiconductor device according to the first embodiment. Like reference numerals denote like elements.

9A and 9B, according to the method described with reference to FIGS. 3A and 3B, an isolation region 405 is formed in a semiconductor substrate 400 to define an active region 410. The active region 410 has a pair of tabs 410 'such that it extends in the X ₁ direction and a portion of the opposite ends extends in the X ₂ direction.

Subsequently, the active region 410 between the active region tabs 410 'and the active region tabs 410' is exposed, and an edge portion of the active region 410 between the active region tabs 410 'is exposed. _A photoresist pattern 415 including a hole tab 415 ′ extending in _one direction is formed. The photoresist pattern hole tab 415 ′ may expose not only the edge portion of the active region 410 between the active region tabs 410 ′ but also the device isolation region 405 adjacent thereto.

Referring to FIGS. 10A and 10B, the recessed trench 420 is formed by etching the exposed active region 410 using the photoresist pattern 415 as an etch protective layer, and the photoresist pattern 415 is removed. The recess trench 420 is formed by etching the active region 410 exposed by the first hole tab 420 'and the photoresist pattern hole tab 415' formed by etching the active region tab 410 '. And a second hole tab 420 ". Therefore, the length of the recess trench 420 in the X ₂ direction is larger than the length of the peripheral active region 410 in the X ₂ direction. The portion of the recess trench 420 including the two hole tab 420 "extends in the X ₁ direction.

11A and 11B, a gate insulating layer 425 is formed on the active region 410 including the recess trench 420. next. A gate electrode layer (not shown) is formed on the gate insulating layer 425. Subsequently, the gate electrode layer is patterned to form the gate electrode 430. Subsequently, a gate spacer 445 may be formed on the sidewall of the gate electrode 430.

The gate electrode 430 includes a recess 430a formed by filling the recess trench 420 and a protrusion 430b formed on the active region 410. The length of the gate electrode protrusion 430b in the X ₁ direction is preferably smaller than the length of the gate electrode recess 430a in the X ₁ direction. The gate electrode protrusion 430b may be formed in a line type extending in the X ₂ direction. The gate electrode recess 430a may include a first tab 430a 'formed by filling the recess trench first hole tab 420' and a second trench formed by filling the recess trench second hole tab 420 ″. Tab 430a ".

Subsequently, according to a method known to those skilled in the art, a source and a drain (see 450 in FIG. 8) are formed in both active regions 410 with the gate electrode 430 interposed therebetween. . Subsequently, a metal wiring can be formed by a conventional method to manufacture a semiconductor device.

According to the method of manufacturing the semiconductor device, the length of the active region 210 in the X ₂ direction can be extended by forming the active region tab 210 ′. Accordingly, the length of the recess trench 420 and the gate electrode recess 430a in the X ₂ direction is extended. In addition, the photoresist pattern hole tab 415 ′ is formed to extend around the edges of the recess trench 420 and the gate electrode recess 430a in the X ₁ direction. As a result, the gate electrode 430 between the source and the drain can be formed in an internal gate structure. Therefore, the semiconductor device manufactured according to the above manufacturing method has excellent junction leakage current and refresh characteristics.

The foregoing description of specific embodiments of the invention has been presented for purposes of illustration and description. The present invention is not limited to the above embodiments, and it is apparent that many modifications and changes can be made in the technical spirit of the present invention by those having ordinary skill in the art in combination. .

According to the semiconductor device and the method of manufacturing the same according to an aspect of the present disclosure, the active region tab 210 ′ may be formed to extend the length of the active region 210 in the X ₂ direction. Accordingly, the length of the recess trench 220 and the gate electrode recess 230a in the X ₂ direction is extended. As a result, the gate electrode 230 between the source and the drain can be formed in an internal gate structure. Accordingly, the semiconductor device according to one aspect of the present invention has excellent junction leakage current and refresh characteristics.

According to the semiconductor device and the manufacturing method thereof according to another aspect of the present invention, by forming the active region tab 410 ′, the length of the active region 410 in the X ₂ direction can be extended. Accordingly, the length of the recess trench 420 and the gate electrode recess 430a in the X ₂ direction is extended. In addition, the photoresist pattern hole tab 415 ′ is formed to extend around the edges of the recess trench 420 and the gate electrode recess 430a in the X ₁ direction. As a result, the gate electrode 430 between the source and the drain can be formed in an internal gate structure. Therefore, the semiconductor device according to the present invention has excellent junction leakage current and refresh characteristics.

Claims (22)

An active region defined by a device isolation region formed in a semiconductor substrate, the active region including a recess trench spaced apart from sidewalls of the device isolation region in a first direction and contacting sidewalls of the device isolation region in a second direction ; A gate insulating film on at least a portion of the active region including the recess trench; A gate electrode formed on the gate insulating layer, the gate electrode having a recess portion filling a recess trench in the active region; And A source and a drain formed in the active region with the gate electrode interposed therebetween, And the width of the recess trench in the active region in the second direction is greater than the width of the source and drain in the second direction. The recess gate type semiconductor device of claim 1, wherein the gate electrode further comprises a protrusion on the active region connected to the recess. The recess gate type semiconductor device of claim 2, wherein the protrusion of the gate electrode extends in the second direction. The recess gate type semiconductor device according to claim 2, wherein the width of the protrusion of the gate electrode in the first direction is smaller than the width of the recess of the gate electrode in the first direction. 2. The recess of claim 1, wherein the recess trench of the active region includes first hole tabs at end portions of the active region that contact the device isolation region to extend a width in the second direction than the source and drain. Set-gate type semiconductor device. 6. The recess of claim 5, wherein the length of the first direction of the first hole tabs of the recess trench is equal to the length of the first direction of the recess trench portion around the first hole tabs. Gate type semiconductor device. The recess trench of claim 1, wherein the recess trench of the active region includes second hole tabs extending in a width in the first direction near edges of the ends in contact with the source and drain. Set-gate type semiconductor device. 8. The recess gate type semiconductor device of claim 7, wherein each of the second hole tabs of the recess trench is in contact with the device isolation region. An active region defined by a device isolation region formed in a semiconductor substrate, the active region including a recess trench spaced apart from sidewalls of the device isolation region in a first direction and contacting sidewalls of the device isolation region in a second direction ; A gate insulating film on at least a portion of the active region including the recess trench; A gate electrode formed on the gate insulating layer, the gate electrode having a recess portion filling the recess trench; And A source and a drain formed in the active region with the gate electrode interposed therebetween,  The recess trench of the active region includes first hole tabs at end portions in contact with the device isolation region so as to extend a width in the second direction than the source and drain portions, and is adjacent to edges of the end portions in contact with the source and drain portions. And a plurality of second hole tabs extending in a width in the first direction. 10. The recess of claim 9, wherein the length of the first direction of the first hole tabs of the recess trench is equal to the length of the first direction of the recess trench portion around the first hole tabs. Gate type semiconductor device. 10. The recess gate type semiconductor device of claim 9, wherein one end of each of the second hole tabs of the recess trench is in contact with the device isolation region. 10. The recess gate type semiconductor device of claim 9, wherein the gate electrode further comprises a protrusion on the active region connected to the recess portion. 13. The recess gate type semiconductor device according to claim 12, wherein the width of the protrusion of the gate electrode in the first direction is smaller than the width of the recess of the gate electrode in the first direction. Forming an isolation region in the semiconductor substrate, the device isolation region being formed extending in the first direction and defining an active region having a pair of tabs so that a portion of the opposite ends extends in the second direction; Forming a photoresist pattern exposing the pair of tabs and the active region therebetween; Forming a recess trench by etching the exposed active region using the photoresist pattern as an etch protective layer; Forming a gate insulating layer on the active region including the recess trench; And forming a gate electrode filling the recess trench on the gate insulating layer. The method of claim 14, wherein the photoresist pattern is formed to extend in the second direction to expose a portion of the device isolation region. 15. The method of claim 14, wherein forming the recess trench selectively etches the active region with respect to the device isolation region. The recessed gate type semiconductor device of claim 14, wherein the gate electrode includes a recess portion filling the recess trench and a protrusion connected to the recess portion and protruding onto the active region. Manufacturing method. 18. The method of claim 17, wherein the protrusion of the gate electrode is formed in a line type extending in the second direction. The method of claim 17, wherein the length of the protrusion of the gate electrode in the first direction is smaller than the length of the recess of the gate electrode in the first direction. Way. The recessed gate type semiconductor device of claim 14, wherein the photoresist pattern includes hole tabs that extend the edge portion of the active region between the pair of tabs to extend in the first direction. Manufacturing method. 21. The method of claim 20, wherein each of the hole tabs of the photoresist pattern is formed such that one end thereof contacts the device isolation region. 15. The method of claim 14, further comprising forming a source and a drain in the active region on both sides of the gate electrode after the forming of the gate electrode.

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