CN108735710B - Anti-fuse structure circuit and forming method thereof - Google Patents
Anti-fuse structure circuit and forming method thereof Download PDFInfo
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- CN108735710B CN108735710B CN201710243649.XA CN201710243649A CN108735710B CN 108735710 B CN108735710 B CN 108735710B CN 201710243649 A CN201710243649 A CN 201710243649A CN 108735710 B CN108735710 B CN 108735710B
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
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Abstract
An anti-fuse structure circuit and a forming method thereof are provided, the structure comprises: a substrate including a control region; a control gate structure group located on the substrate control region, the control gate structure group including a first gate structure; an antifuse, comprising: the interlayer dielectric layer is positioned on the substrate and covers the first grid structure, the interlayer dielectric layer comprises a first dielectric layer, and the top surface of the first dielectric layer is flush with the top surface of the first grid structure; the first conductive plug penetrates through the interlayer dielectric layer on the first grid structure and covers the top surface of the first grid structure and part of the first dielectric layer on two sides of the first grid structure; and the second conductive plug penetrates through the interlayer dielectric layers on two sides of the first grid structure, a first distance is formed between the second conductive plug and the first conductive plug, a second distance is formed between the second conductive plug and the first grid structure, and the first distance is smaller than the second distance. The performance of the anti-fuse structure circuit is improved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to an anti-fuse structure circuit and a forming method thereof.
Background
In the semiconductor industry, fuse elements are widely used in integrated circuits due to their multiple uses. For example, a plurality of circuit blocks having the same function are designed in an integrated circuit as backups, and when one of the circuit blocks is found to be defective, the circuit block and other functional circuits in the integrated circuit are blown by fuse elements, while the defective circuit block is replaced with another circuit block having the same function.
With the continuous development of semiconductor technology, Anti-fuse (Anti-fuse) technology has attracted much attention from the inventors and manufacturers. An antifuse structure is a structure that can change conductive states. The antifuse structure is non-conductive when unactivated and conductive when activated. Thus, the antifuse structure is capable of selectively electrically connecting two devices or chips that are otherwise electrically isolated.
However, the performance of the existing antifuse structures is poor.
Disclosure of Invention
The invention provides an anti-fuse structure circuit and a forming method thereof, which are used for improving the performance of the anti-fuse structure circuit.
To solve the above problems, the present invention provides an anti-fuse structure circuit, comprising: a substrate including a control region; a control gate structure group located on the substrate control region, the control gate structure group including a first gate structure; an antifuse, comprising: the interlayer dielectric layer is positioned on the substrate and covers the first grid structure, the interlayer dielectric layer comprises a first dielectric layer, and the top surface of the first dielectric layer is flush with the top surface of the first grid structure; the first conductive plug penetrates through the interlayer dielectric layer on the first grid structure and covers the top surface of the first grid structure and part of the first dielectric layer on two sides of the first grid structure; and the second conductive plug penetrates through the interlayer dielectric layers on two sides of the first grid structure, a first distance is formed between the second conductive plug and the first conductive plug, a second distance is formed between the second conductive plug and the first grid structure, and the first distance is smaller than the second distance.
Optionally, the first distance is 20% to 80% of the second distance.
Optionally, the first conductive plug and the second conductive plug are made of metal; the interlayer dielectric layer is made of silicon oxide or low-K dielectric material.
Optionally, the number of the first gate structures is one or more.
Optionally, when the number of the first gate structures is one, two first conductive plugs are arranged on the first gate structures, and the first conductive plugs are respectively located at two ends of the first gate structures along the extending direction of the first gate structures; when the number of the first gate structures is multiple, each first gate structure is provided with two first conductive plugs, and the first conductive plugs are respectively positioned at two ends of the first gate structure in the extending direction of the first gate structure.
Optionally, when the number of the first gate structures is one, the first gate structure has a first conductive plug thereon, and the first conductive plug is located at one end of the first gate structure in the extending direction of the first gate structure; when the number of the first gate structures is multiple, each first gate structure is provided with a first conductive plug, and the first conductive plug is positioned at one end of the first gate structure in the extending direction of the first gate structure.
Optionally, the extending direction of the first gate structure is parallel to the extending direction of the second conductive plug, and the dimension of the first gate structure in the extending direction is greater than the dimension of the second conductive plug in the extending direction; the first grid structure comprises a connecting area which is suitable for being connected with the first conductive plug, and an interlayer dielectric layer on the connecting area and an interlayer dielectric layer between the second conductive plugs on two sides of the first grid structure are not provided with an overlapping area.
Optionally, the first conductive plugs are located between the second conductive plugs.
Optionally, the method further includes: and the first source-drain doped regions are respectively positioned in the substrates at two sides of the first grid structure and are electrically connected with the second conductive plug.
Optionally, the interlayer dielectric layer further includes a second dielectric layer, and the second dielectric layer is located on the first dielectric layer and the first gate structure; the first conductive plug only penetrates through the second dielectric layer; the second conductive plug penetrates through the first dielectric layer and the second dielectric layer.
Optionally, the control gate structure group further includes a second gate structure; the interlayer dielectric layer also covers the second grid structure; the antifuse structure circuit further includes: the second source-drain doped regions are respectively positioned in the substrates at two sides of the second grid structure; a third conductive plug penetrating through the interlayer dielectric layer on the second grid structure; and the fourth conductive plug penetrates through the interlayer dielectric layers on the two sides of the second grid structure, is electrically connected with the second source-drain doped region, has a third distance from the fourth conductive plug to the third conductive plug, and has a fourth distance from the fourth conductive plug to the second grid structure.
Optionally, the second distance is smaller than or equal to a fourth distance, and the first distance is smaller than a third distance.
Optionally, the number of the control areas is multiple; the substrate further comprises isolation regions located between adjacent control regions; the antifuse structure circuit further includes: an isolation gate structure on the substrate isolation region, the isolation gate structure adapted to not have a voltage applied thereto; and the third source-drain doped regions are respectively positioned in the substrates at two sides of the isolation gate structure.
The invention also provides a method for forming the anti-fuse structure circuit, which comprises the following steps: providing a substrate, wherein the substrate comprises a control area; forming a control grid structure group and an antifuse on a substrate control area, wherein the control grid structure group comprises a first grid structure; the method for forming the antifuse comprises the following steps: forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the first grid structure and comprises a first dielectric layer, and the top surface of the first dielectric layer is flush with the top surface of the first grid structure; forming a first conductive plug penetrating through the interlayer dielectric layer on the first grid structure, wherein the first conductive plug covers the top surface of the first grid structure and part of the first dielectric layer on two sides of the first grid structure; and forming a second conductive plug penetrating through the interlayer dielectric layers on two sides of the first grid structure, wherein the second conductive plug has a first distance from the first conductive plug, the second conductive plug has a second distance from the first grid structure, and the first distance is smaller than the second distance.
Optionally, the first distance is 20% to 80% of the second distance.
Optionally, the number of the first gate structures is one or more; when the number of the first gate structures is one, the first gate structure is provided with two first conductive plugs which are respectively positioned at two ends of the first gate structure along the extension direction of the first gate structure, or the first gate structure is provided with one first conductive plug which is positioned at one end of the first gate structure along the extension direction of the first gate structure; when the number of the first gate structures is multiple, each first gate structure is provided with two first conductive plugs, the first conductive plugs are respectively located at two ends of the first gate structure along the extending direction of the first gate structure, or each first gate structure is provided with one first conductive plug, and the first conductive plugs are located at one end of the first gate structure along the extending direction of the first gate structure.
Optionally, the extending direction of the first gate structure is parallel to the extending direction of the second conductive plug, and the dimension of the first gate structure in the extending direction is greater than the dimension of the second conductive plug in the extending direction; the first grid structure comprises a connecting area which is suitable for being connected with the first conductive plug, and an interlayer dielectric layer on the connecting area and an interlayer dielectric layer between the second conductive plugs on two sides of the first grid structure are not provided with an overlapping area.
Optionally, the first conductive plugs are located between the second conductive plugs.
Optionally, the control gate structure group further includes a second gate structure; the interlayer dielectric layer also covers the second grid structure; the method for forming the anti-fuse structure circuit further comprises the following steps: forming a second source-drain doped region in the process of forming the control grid structure group and the anti-fuse, wherein the second source-drain doped region is respectively positioned in the substrates at two sides of the second grid structure; forming a third conductive plug penetrating through the interlayer dielectric layer on the second grid structure; forming a fourth conductive plug penetrating through the interlayer dielectric layers on the two sides of the second grid structure, wherein the fourth conductive plug is electrically connected with the second source drain doped region, a third distance is formed between the fourth conductive plug and the third conductive plug, and a fourth distance is formed between the fourth conductive plug and the second grid structure; the second distance is less than or equal to a fourth distance, and the first distance is less than a third distance.
Optionally, the number of the control areas is multiple; the substrate further comprises isolation regions located between adjacent control regions; the method for forming the anti-fuse structure circuit further comprises the following steps: and forming an isolation grid structure and a third source drain doped region, wherein the isolation grid structure is positioned on the substrate isolation region, the isolation grid structure is suitable for not applying voltage, and the third source drain doped region is respectively positioned in the substrate at two sides of the isolation grid structure.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the anti-fuse structure circuit provided by the technical scheme of the invention, the anti-fuse is formed by utilizing the first conductive plug, the second conductive plug and the interlayer dielectric layer between the second conductive plug and the first conductive plug, and a substrate outside a control area is not required to be occupied, so that the integration level of the anti-fuse structure circuit is improved. Since the first distance is smaller than the second distance, when a voltage is applied across the first conductive plug and the second conductive plug, the electric field strength between the second conductive plug and the first conductive plug is greater than the electric field strength between the second conductive plug and the first gate structure. And then the interlayer dielectric layer between the second conductive plug and the first conductive plug is easy to break through, so that the second conductive plug and the first conductive plug are conducted, namely the antifuse is changed into a conducting state from an isolation state. The anti-fuse is formed by utilizing the first conductive plug, the second conductive plug and the interlayer dielectric layer between the second conductive plug and the first conductive plug, so that the anti-fuse is not influenced by the width of the control grid structure group. And further, the length of a channel corresponding to the control grid structure group is prevented from being increased, and the resistance of the channel corresponding to the control grid structure group is prevented from being increased. Therefore, the control transistor correspondingly formed by the control gate structure provides larger breakdown current for the anti-fuse, and the anti-fuse is fully broken down, so that the performance of the anti-fuse structure circuit is improved.
In the method for forming the anti-fuse structure circuit provided by the technical scheme of the invention, the anti-fuse is formed by utilizing the first conductive plug, the second conductive plug and the interlayer dielectric layer between the second conductive plug and the first conductive plug, and a substrate outside a control area is not required to be occupied, so that the integration level of the anti-fuse structure circuit is improved. And secondly, the anti-fuse wire is not influenced by the width of the control grid structure group, so that the length of a channel corresponding to the control grid structure group is prevented from being increased, and the resistance of the channel corresponding to the control grid structure group is prevented from being increased. Therefore, the control transistor correspondingly formed by the control gate structure provides larger breakdown current for the anti-fuse, and the anti-fuse is fully broken down, so that the performance of the anti-fuse structure circuit is improved.
Drawings
FIG. 1 is a schematic diagram of an anti-fuse circuit;
fig. 2 to 5 are schematic structural diagrams illustrating a process of forming an antifuse structure circuit according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the existing anti-fuse structure circuit is poor.
Referring to fig. 1, the antifuse structure circuit includes: a substrate 100; a control gate structure group and a dielectric layer 110 covering the control gate structure group, the control gate structure group including a first gate structure 121 and a second gate structure 122; first source-drain doped regions 131 respectively located in the substrate 100 at two sides of the first gate structure 121; the second source-drain doped regions 132 are respectively located in the substrate 100 on two sides of the second gate structure 122, and the first gate structure 121 and the second gate structure 122 share a source drain; a first conductive plug 141 on the first source-drain doped region 131 and electrically connected to the first source-drain doped region 131; a second conductive plug 142 located on the second source-drain doped region 132 and electrically connected to the second source-drain doped region 132; the first conductive plug 141, the first gate structure 121, and the dielectric layer 110 between the first conductive plug 141 and the first gate structure 121 constitute an antifuse.
For convenience of description, the first source-drain doped region 131 or the second source-drain doped region 132 between the first gate structure 121 and the second gate structure 122 is referred to as a source-drain doped region, and the first conductive plug 141 or the second conductive plug 142 between the first gate structure 121 and the second gate structure 122 is referred to as a conductive plug.
The antifuse is formed by using the first conductive plug 141, the first gate structure 121, and the dielectric layer 110 between the first conductive plug 141 and the first gate structure 121, and the antifuse is formed without occupying an additional region of the substrate 100, so that the integration of the antifuse structure circuit is improved.
And the control transistor correspondingly formed by the control gate structure group is used for providing breakdown voltage for the antifuse to enable the antifuse to be conducted. Specifically, the conductive plug is electrically connected to the source-drain doped region, a voltage applied to the source-drain doped region end is applied to the conductive plug to provide a voltage to one end of the antifuse, and a voltage applied to the first gate structure 121 is applied to provide a voltage to the other end of the antifuse. When the antifuse is broken down, a channel current corresponding to the first gate structure 121 and a channel current corresponding to the second gate structure 122 provide a breakdown current for the antifuse.
However, the performance of the anti-fuse structure circuit is poor, and the research finds that the reason is that:
in order to make the antifuse conductive, the electric field strength between the first conductive plug 141 and the first gate structure 121 needs to be large. To achieve the above purpose, the width of the first gate structure 121 is generally increased, and the distance from the first conductive plug 141 to the first gate structure 121 is further decreased. The first gate structure 121 and the second gate structure 122 of the control gate structure are usually formed in one process, and the width of the first gate structure 121 is the same as that of the second gate structure 122. The width of the second gate structure 122 increases as the width of the first gate structure 121 increases. When the widths of the first and second gate structures 121 and 122 are increased, the channel lengths of the first and second gate structures 121 and 122 are increased accordingly, the channel resistances in the first and second gate structures 121 and 122 are increased, and accordingly, the channel currents in the first and second gate structures 121 and 122 are decreased. Therefore, when the antifuse is broken down, the breakdown current provided to the antifuse by the control gate structure group is small, the voltage drop across the antifuse is small, and the breakdown of the antifuse is insufficient.
On the basis, the invention provides a method for forming an anti-fuse structure circuit, which comprises the following steps: a substrate including a control region; a control gate structure group located on the substrate control region, the control gate structure group including a first gate structure; an antifuse, comprising: the interlayer dielectric layer is positioned on the substrate and covers the first grid structure, the interlayer dielectric layer comprises a first dielectric layer, and the top surface of the first dielectric layer is flush with the top surface of the first grid structure; the first conductive plug penetrates through the interlayer dielectric layer on the first grid structure and covers the top surface of the first grid structure and part of the first dielectric layer on two sides of the first grid structure; and the second conductive plug penetrates through the interlayer dielectric layers on two sides of the first grid structure, a first distance is formed between the second conductive plug and the first conductive plug, a second distance is formed between the second conductive plug and the first grid structure, and the first distance is smaller than the second distance.
In the method, the antifuse is formed by utilizing the first conductive plug, the second conductive plug and the interlayer dielectric layer between the second conductive plug and the first conductive plug, and a substrate outside a control area is not required to be occupied, so that the integration level of the antifuse structure circuit is improved. And secondly, the anti-fuse wire is not influenced by the width of the control grid structure group, so that the length of a channel corresponding to the control grid structure group is prevented from being increased, and the resistance of the channel corresponding to the control grid structure group is prevented from being increased. Therefore, the control transistor correspondingly formed by the control gate structure provides larger breakdown current for the anti-fuse, and the anti-fuse is fully broken down, so that the performance of the anti-fuse structure circuit is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 5 are schematic structural diagrams illustrating a process of forming an antifuse structure circuit according to an embodiment of the present invention.
Referring to fig. 2, a substrate 200 is provided, the substrate package 200 including a control region a.
The base 200 is a bulk silicon substrate, a bulk germanium substrate, a glass substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate. In this embodiment, the base 200 is a bulk silicon substrate.
The control area a is used for forming a control circuit, and the control circuit comprises a plurality of control transistors.
The number of the control areas A is one or more. In this embodiment, the number of the control areas a is plural, and the example is given by setting the number of the control areas a to two.
In this embodiment, the substrate 200 further includes an isolation region B, and the isolation region B is located between adjacent control regions a.
The isolation region B is used for isolating the adjacent control region A.
Next, a control gate structure group including a first gate structure and an antifuse are formed on the control region a of the substrate 200.
The method for forming the antifuse comprises the following steps: forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the first grid structure and comprises a first dielectric layer, and the top surface of the first dielectric layer is flush with the top surface of the first grid structure; forming a first conductive plug penetrating through the interlayer dielectric layer on the first grid structure, wherein the first conductive plug covers the top surface of the first grid structure and part of the first dielectric layer on two sides of the first grid structure; and forming a second conductive plug penetrating through the interlayer dielectric layers on two sides of the first grid structure, wherein the second conductive plug has a first distance from the first conductive plug, the second conductive plug has a second distance from the first grid structure, and the first distance is smaller than the second distance.
The method of forming the set of anti-fuse and control gate structures is described in detail below with reference to fig. 3-5.
With reference to fig. 3 and 4, fig. 3 is a schematic diagram based on fig. 2, fig. 4 is a schematic diagram along a cutting line M-M1 in fig. 3, and fig. 3 is a top view of an interlayer dielectric layer in fig. 4, a control gate structure group and an interlayer dielectric layer 220 are formed on a control region a of a substrate 200, the control gate structure group includes a first gate structure 210, the interlayer dielectric layer 220 covers the first gate structure 210, the interlayer dielectric layer 220 includes a first dielectric layer 221, and a top surface of the first dielectric layer 221 is flush with a top surface of the first gate structure 210.
The first gate structure 210 includes a first gate dielectric layer (not shown) on the control region a of the substrate 200 and a first gate electrode layer (not shown) on the first gate dielectric layer.
The set of control gate structures further comprises a second gate structure 211.
The second gate structure 211 includes a second gate dielectric layer (not shown) on the control region a of the substrate 200 and a second gate electrode layer (not shown) on the second gate dielectric layer.
The first gate dielectric layer and the second gate dielectric layer are made of high-K (K is more than or equal to 3.9) dielectric materials. The first gate electrode layer and the second gate electrode layer are made of metal.
The interlayer dielectric layer 220 also covers the second gate structure 211.
The interlayer dielectric layer 220 is made of silicon oxide or low-K (K is less than 3.9) dielectric material.
And the control transistor correspondingly formed by the control gate structure group is used for providing breakdown voltage for the antifuse to enable the antifuse to be conducted.
The interlayer dielectric layer 220 includes a first dielectric layer 221 and a second dielectric layer 222.
The first dielectric layer 221 covers the sidewall of the first gate structure 210, and the top surface of the first dielectric layer 221 is flush with the top surface of the first gate structure 210.
The first dielectric layer 221 further covers the sidewall of the second gate structure 211, and the top surface of the first dielectric layer 221 is flush with the top surface of the second gate structure 211.
The second dielectric layer 222 is located on the first dielectric layer 221 and the first gate structure 210.
The second dielectric layer 222 is also located on the second gate structure 211.
Specifically, a dummy gate structure (not shown) is formed on the control region a of the substrate 200, and the dummy gate structure includes a first dummy gate structure and a second dummy gate structure; forming a first dielectric layer 221 covering the dummy gate structure on the substrate 200; removing the first dummy gate structure, and forming a first opening in the first dielectric layer 221; removing the second dummy gate structure, and forming a second opening in the first dielectric layer 221; forming a first gate structure 210 in the first opening; forming a second gate structure 211 in the second opening; a second dielectric layer 222 is formed on the first gate structure 210, the second gate structure 211 and the first dielectric layer 221, and the second dielectric layer 222 and the first dielectric layer 221 form the interlayer dielectric layer 220.
The first dummy gate structure includes a first dummy gate dielectric layer on the control region a of the substrate 200 and a first dummy gate electrode layer on the first dummy gate dielectric layer.
The second dummy gate structure includes a second dummy gate dielectric layer on the control region a of the substrate 200 and a second dummy gate electrode layer on the second dummy gate dielectric layer.
The second dummy gate electrode layer and the first dummy gate electrode layer are made of polysilicon.
In this embodiment, the first dummy gate structure is removed to form the first opening, and the second dummy gate structure is removed to form the second opening. Correspondingly, the second dummy gate dielectric layer and the first dummy gate dielectric layer are made of silicon oxide.
In other embodiments, the first dummy gate electrode layer is removed to form a first opening, the second dummy gate electrode layer is removed to form a second opening, and after the first opening and the second opening are formed, the first dummy gate dielectric layer forms the first gate dielectric layer and the second dummy gate dielectric layer forms the second gate dielectric layer. Accordingly, it is only necessary to form the first gate electrode layer in the first opening and the second gate electrode layer in the second opening. In this case, the material of the second dummy gate dielectric layer and the first dummy gate dielectric layer is a high-K dielectric material.
In this embodiment, in the process of forming the control gate structure group and the antifuse, specifically, in the process of forming the control gate structure group and the interlayer dielectric layer 220, the first source-drain doped region 231 and the second source-drain doped region 232 are formed.
Specifically, before forming the first dielectric layer 221, a first source-drain doped region 231 is formed in the substrate 200 at two sides of the first dummy gate structure, and a second source-drain doped region 232 is formed in the substrate 200 at two sides of the second dummy gate structure; after the first gate structure 210 and the second gate structure 211 are formed, the first source-drain doped regions 231 are respectively located in the substrates 200 at two sides of the first gate structure 210, and the second source-drain doped regions 232 are respectively located in the substrates 200 at two sides of the second gate structure 211.
In this embodiment, the first gate structure 210 and the second gate structure 211 share a source/drain region.
In other embodiments, the first gate structure and the second gate structure do not share source and drain regions.
In this embodiment, an isolation gate structure 212 and a third source/drain doped region 233 are further formed, wherein the isolation gate structure 212 is located on the isolation region B of the substrate 200, and the third source/drain doped regions 233 are respectively located in the substrate 200 at two sides of the isolation gate structure 212.
The interlayer dielectric layer 220 also covers the isolation gate structure 212.
In this embodiment, the isolation gate structure 212 and the control gate structure group share a source/drain region.
In other embodiments, the set of isolated gate structures and control gate structures do not share source and drain regions.
The isolation gate structure 212 includes an isolation gate dielectric layer on the isolation region B of the substrate 200 and an isolation gate electrode layer on the isolation gate dielectric layer.
The isolation gate dielectric layer is made of silicon oxide or a high-K dielectric material. The isolation gate electrode layer is made of polysilicon or metal.
In this embodiment, an isolation transistor is formed on the isolation region B, and the isolation transistor includes an isolation gate structure 212 and a third source/drain doped region 233.
The isolation transistor is not electrically connected to other devices, and in particular, the isolation gate structure 212 is adapted to have no voltage applied thereto.
The isolation transistor functions include: electrically isolating the control transistors located on adjacent control regions a.
The number of the isolation transistors is 1-10.
In this embodiment, the isolation transistor is used to electrically isolate the control transistors in the adjacent control regions a without forming an isolation structure in the isolation region B of the substrate 200. The integration level of the fuse structure is improved because the area occupied by the isolation transistor is smaller.
Referring to fig. 5 in combination, fig. 5 is a schematic view based on fig. 3, and a first conductive plug 241 penetrating through the interlayer dielectric layer 220 on the first gate structure 210 is formed, where the first conductive plug 241 covers the top surface of the first gate structure 210 and a portion of the first dielectric layer 221 on both sides of the first gate structure 210; and forming a second conductive plug 242 penetrating through the interlayer dielectric layers 220 on two sides of the first gate structure 210, wherein a first distance is formed between the second conductive plug 242 and the first conductive plug 241, a second distance is formed between the second conductive plug 242 and the first gate structure 210, and the first distance is smaller than the second distance.
The first conductive plug 241 is electrically connected to the first gate structure 210. The second conductive plugs 242 are electrically connected to the first source-drain doped regions 231.
The material of the first conductive plug 241 and the second conductive plug 242 is metal, such as copper or tungsten.
The first conductive plug 241 only penetrates through the second dielectric layer 222 on the first gate structure 210. The second conductive plug 242 penetrates the first dielectric layer 221 and the second dielectric layer 222.
The antifuse includes: a first conductive plug 241, a second conductive plug 242, and an interlevel dielectric layer 220 between the first conductive plug 241 and the second conductive plug 242.
The antifuse is formed using the first conductive plug 241, the second conductive plug 242, and the interlayer dielectric layer 220 between the first conductive plug 241 and the second conductive plug 242 without occupying the substrate 200 outside the control region a. Therefore, the integration degree of the anti-fuse structure circuit is improved.
The first distance refers to a minimum distance from an edge of the second conductive plug 242 to an edge of the first conductive plug 241. The second distance refers to a minimum distance from an edge of the second conductive plug 242 to an edge of the first gate structure 210.
In one embodiment, the first distance is 20% to 80% of the second distance. The meaning of selecting this range includes: if the proportion of the first distance occupying the second distance is less than 20%, the second conductive plug 242 and the first conductive plug 241 are easily electrically connected due to the influence of the process precision; if the first distance occupies more than 80% of the second distance, a larger breakdown voltage needs to be provided to the antifuse.
The number of the first gate structures 210 is one or more.
When the number of the first gate structures 210 is one, the first gate structure 210 has two first conductive plugs 241, and the first conductive plugs 241 are respectively located at two ends of the first gate structure 210 along the extending direction of the first gate structure 210, or the first gate structure 210 has one first conductive plug 241, and the first conductive plug 241 is located at one end of the first gate structure 210 along the extending direction of the first gate structure 210.
When the number of the first gate structures 210 is multiple, each first gate structure 210 has two first conductive plugs 241, and the first conductive plugs 241 are respectively located at two ends of the first gate structure 210 along the extending direction of the first gate structure 210, or each first gate structure 210 has one first conductive plug 241, and the first conductive plug 241 is located at one end of the first gate structure 210 along the extending direction of the first gate structure 210.
In this embodiment, the first conductive plugs 241 are respectively located at two ends of the first gate structure 210, and the first conductive plugs 241 at two ends of the first gate structure 210 respectively form an antifuse with the second conductive plug 242, and the interlayer dielectric layer 220 between the first conductive plug 241 and the second conductive plug 242. Thereby increasing the probability of antifuse breakdown.
In this embodiment, the extending direction of the first gate structure 210 is parallel to the extending direction of the second conductive plug 242, and the dimension of the first gate structure 210 in the extending direction is greater than the dimension of the second conductive plug 242 in the extending direction. The first gate structure 210 includes a connection region adapted to be connected to the first conductive plug 241, and the interlayer dielectric layer 220 on the connection region has no overlapping region with the interlayer dielectric layer 220 between the second conductive plugs 242 on both sides of the first gate structure 210.
In other embodiments, the first electrically conductive plugs are located between the second electrically conductive plugs.
In this embodiment, the method further includes: forming a third conductive plug 243 penetrating through the interlayer dielectric layer 220 on the second gate structure 211; and forming a fourth conductive plug 244 penetrating through the interlayer dielectric layers 220 on two sides of the second gate structure 211, wherein the fourth conductive plug 244 is electrically connected with the second source-drain doped region 232, a third distance is formed between the fourth conductive plug 244 and the third conductive plug 243, and a fourth distance is formed between the fourth conductive plug 244 and the second gate structure 211.
The material of the third and fourth conductive plugs 243 and 244 refers to the material of the first and second conductive plugs 241 and 242.
In this embodiment, the second distance is smaller than the fourth distance, and the first distance is smaller than the third distance. In other embodiments, the second distance is equal to the fourth distance, and the first distance is less than the third distance.
In this embodiment, the number of the second gate structures 211 is multiple, and each second gate structure 211 has a third conductive plug 243 thereon.
In this embodiment, the third conductive plugs 243 are respectively located at one end of the second gate structure 211 along the extending direction of the second gate structure 211.
The steps of forming the first conductive plugs 241, the second conductive plugs 242, the third conductive plugs 243, and the fourth conductive plugs 244 include: forming a first through hole, a second through hole, a third through hole and a fourth through hole in the interlayer dielectric layer 220, wherein the first through hole exposes the top surface of the first gate structure 210, the second through hole exposes the surfaces of the first source-drain doped regions 231 on the two sides of the first gate structure 210, the third through hole exposes the top surface of the second gate structure 211, and the fourth through hole exposes the surfaces of the second source-drain doped regions 232 on the two sides of the second gate structure 211; forming a first conductive plug 241 in the first via hole; forming a second conductive plug 242 in the second via hole; forming a third conductive plug 243 in the third via hole; a fourth conductive plug 244 is formed in the fourth via.
In this embodiment, the first conductive plug 241, the second conductive plug 242, the third conductive plug 243, and the fourth conductive plug 244 are formed at the same time.
In other embodiments, the first conductive plug, the second conductive plug, the third conductive plug, and the fourth conductive plug are separately formed.
In this embodiment, there is no overlapping area between the interlayer dielectric layer 220 on the connection region and the interlayer dielectric layer 220 between the second conductive plugs 242 on two sides of the first gate structure 210. Accordingly, the formation of the first through hole and the second through hole is facilitated.
The control transistor includes: a first control transistor and a second control transistor.
The first control transistor includes: the first gate structure 210, the first source-drain doped region 231, the first conductive plug 241 and the second conductive plug 242.
The second control transistor includes: a second gate structure 211, a second source-drain doped region 232, a third conductive plug 243 and a fourth conductive plug 244.
The control transistor is adapted to provide a breakdown voltage to the antifuse to render the antifuse conductive.
Since the first distance is smaller than the second distance, when a voltage is applied to the first and second conductive plugs 241 and 242, the electric field intensity between the second conductive plug 242 and the first conductive plug 241 is greater than the electric field intensity between the second conductive plug 242 and the first gate structure 210. And then the interlayer dielectric layer 220 between the second conductive plug 242 and the first conductive plug 241 is easily broken down, so that the second conductive plug 242 and the first conductive plug 241 are conducted, that is, the antifuse is changed from an isolated state to a conducting state.
For convenience of description, the first source-drain doped region 231 or the second source-drain doped region 232 between the first gate structure 210 and the second gate structure 211 is referred to as a source-drain doped region, and the first conductive plug 241 or the second conductive plug 242 between the first gate structure 210 and the second gate structure 211 is referred to as a conductive plug.
And the control transistor correspondingly formed by the control gate structure group is used for providing breakdown voltage for the antifuse to enable the antifuse to be conducted. Specifically, the conductive plug is electrically connected to the source-drain doped region, a voltage at the source-drain doped region end is applied to the conductive plug to provide a voltage to one end of the antifuse, and a voltage applied to the first conductive plug 241 provides a voltage to the other end of the antifuse. When the antifuse is broken down, a channel current corresponding to the first gate structure 210 and a channel current corresponding to the second gate structure 211 provide a breakdown current for the antifuse.
In this embodiment, the antifuse is formed by using the first conductive plug 241, the second conductive plug 242, and the interlayer dielectric layer 220 between the second conductive plug 242 and the first conductive plug 241, so that the antifuse is not affected by the width of the control gate structure set. And further, the length of a channel corresponding to the control grid structure group is prevented from being increased, and the resistance of the channel corresponding to the control grid structure group is prevented from being increased. Therefore, the breakdown current provided by the control transistor correspondingly formed by the control gate structure to the antifuse is large, and the breakdown of the antifuse is sufficient. Thereby improving the performance of the anti-fuse structure circuit.
Accordingly, the present invention further provides an antifuse structure circuit formed by the above method, with reference to fig. 5, including: a substrate 200 (refer to fig. 3), the substrate 200 including a control region a; a control gate structure group on the control region a of the substrate 200, the control gate structure group including a first gate structure 210; an antifuse, comprising: an interlayer dielectric layer 220 located on the substrate 200 and covering the first gate structure 210, wherein the interlayer dielectric layer 220 includes a first dielectric layer 221, and a top surface of the first dielectric layer 221 is flush with a top surface of the first gate structure 210; a first conductive plug 241 penetrating through the interlayer dielectric layer 220 on the first gate structure 210, wherein the first conductive plug 241 covers the top surface of the first gate structure 210 and a part of the first dielectric layer 221 at two sides of the first gate structure 210; and the second conductive plug 242 penetrates through the interlayer dielectric layers 220 on two sides of the first gate structure 210, a first distance is formed between the second conductive plug 242 and the first conductive plug 241, a second distance is formed between the second conductive plug 242 and the first gate structure 210, and the first distance is smaller than the second distance.
The number of the control areas is one or more. In this embodiment, the number of the control areas is plural.
In this embodiment, the substrate 200 further includes an isolation region B, and the isolation region B is located between adjacent control regions a.
The structure and material of the first gate structure 210 and the second gate structure 211 refer to the foregoing embodiments and are not described in detail.
The first distance is 20% -80% of the second distance.
The first conductive plug 241 and the second conductive plug 242 are made of metal; the interlayer dielectric layer 220 is made of silicon oxide or a low-K dielectric material.
The number of the first gate structures 210 is one or more.
When the number of the first gate structures 210 is one, the first gate structure 210 has two first conductive plugs 241, and the first conductive plugs 241 are respectively located at two ends of the first gate structure 210 along the extending direction of the first gate structure 210, or the first gate structure 210 has one first conductive plug 241, and the first conductive plug 241 is located at one end of the first gate structure 210 along the extending direction of the first gate structure 210.
When the number of the first gate structures 210 is multiple, each first gate structure 210 has two first conductive plugs 241, and the first conductive plugs 241 are respectively located at two ends of the first gate structure 210 along the extending direction of the first gate structure 210, or each first gate structure 210 has one first conductive plug 241, and the first conductive plug 241 is located at one end of the first gate structure 210 along the extending direction of the first gate structure 210.
In this embodiment, the extending direction of the first gate structure 210 is parallel to the extending direction of the second conductive plug 242, and the dimension of the first gate structure 210 in the extending direction is greater than the dimension of the second conductive plug 242 in the extending direction. The first gate structure 210 includes a connection region adapted to be connected to the first conductive plug 241, and the interlayer dielectric layer 220 on the connection region has no overlapping region with the interlayer dielectric layer 220 between the second conductive plugs 242 on both sides of the first gate structure 210.
In other embodiments, the first electrically conductive plugs are located between the second electrically conductive plugs.
The first conductive plug 241 is electrically connected to the first gate structure 210.
The antifuse structure circuit further includes: the first source-drain doped regions 231 are respectively located in the substrate 200 at two sides of the first gate structure 210, and the first source-drain doped regions 231 are electrically connected with the second conductive plugs 242.
The first dielectric layer 221 further covers the sidewall of the second gate structure 211, and the top surface of the first dielectric layer 221 is flush with the top surface of the second gate structure 211.
The interlayer dielectric layer further includes a second dielectric layer 222, and the second dielectric layer 222 is located on the first dielectric layer 221 and the first gate structure 210. The second dielectric layer 222 is also located on the second gate structure 211.
The first conductive plug 241 only penetrates through the second dielectric layer 222 on the first gate structure 210. The second conductive plug 242 penetrates the first dielectric layer 221 and the second dielectric layer 222.
The control gate structure group further includes a second gate structure 211, and the interlayer dielectric layer 220 further covers the second gate structure 211.
The antifuse structure circuit further includes: second source-drain doped regions 232 respectively located in the substrate 200 at two sides of the second gate structure 211; a third conductive plug 243 penetrating through the interlayer dielectric layer 220 on the second gate structure 211; and a fourth conductive plug 244 penetrating through the interlayer dielectric layers 220 on both sides of the second gate structure 211, wherein the fourth conductive plug 244 is electrically connected to the second source-drain doped region 232, a third distance is provided between the fourth conductive plug 244 and the third conductive plug 243, and a fourth distance is provided between the fourth conductive plug 244 and the second gate structure 211.
The materials of the third and fourth conductive plugs 243 and 244 refer to the materials of the first and second conductive plugs 241 and 242.
In this embodiment, the number of the second gate structures 211 is multiple, and each second gate structure 211 has a third conductive plug 243 thereon.
In this embodiment, the third conductive plugs 243 are respectively located at one end of the second gate structure 211 along the extending direction of the second gate structure 211.
The second distance is less than or equal to a fourth distance, and the first distance is less than a third distance.
The antifuse structure circuit further includes: an isolation gate structure 212 located on the substrate 200 at the isolation region B, wherein the isolation gate structure 212 is suitable for no voltage application; and third source/drain doped regions 233 respectively located in the substrate 200 at two sides of the isolation gate structure 212.
The interlayer dielectric layer 220 also covers the isolation gate structure 212.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. An antifuse structure circuit, comprising:
a substrate including a control region;
a control gate structure group located on the substrate control region, the control gate structure group including a first gate structure;
an antifuse, comprising:
the interlayer dielectric layer is positioned on the substrate and covers the first grid structure, the interlayer dielectric layer comprises a first dielectric layer, and the top surface of the first dielectric layer is flush with the top surface of the first grid structure;
the first conductive plug penetrates through the interlayer dielectric layer on the first grid structure and covers the top surface of the first grid structure and part of the first dielectric layer on two sides of the first grid structure;
and the second conductive plug penetrates through the interlayer dielectric layers on two sides of the first grid structure, a first distance is formed between the second conductive plug and the first conductive plug, a second distance is formed between the second conductive plug and the first grid structure, the first distance is smaller than the second distance, the first distance refers to the minimum distance from the edge of the second conductive plug to the edge of the first conductive plug, and the second distance refers to the minimum distance from the edge of the second conductive plug to the edge of the first grid structure.
2. The antifuse structure circuit of claim 1, wherein the first distance is 20% to 80% of the second distance.
3. The antifuse structure circuit of claim 1, wherein the first and second conductive plugs are made of metal; the interlayer dielectric layer is made of silicon oxide or low-K dielectric material.
4. The antifuse structure circuit of claim 1, wherein the number of the first gate structures is one or more.
5. The anti-fuse structure circuit according to claim 4, wherein when the number of the first gate structures is one, the first gate structures have two first conductive plugs thereon, and the first conductive plugs are respectively located at two ends of the first gate structures along the extending direction of the first gate structures; when the number of the first gate structures is multiple, each first gate structure is provided with two first conductive plugs, and the first conductive plugs are respectively positioned at two ends of the first gate structure in the extending direction of the first gate structure.
6. The antifuse structure circuit of claim 4, wherein when the number of the first gate structures is one, the first gate structure has a first conductive plug thereon, and the first conductive plug is located at one end of the first gate structure in a direction along the extension direction of the first gate structure; when the number of the first gate structures is multiple, each first gate structure is provided with a first conductive plug, and the first conductive plug is positioned at one end of the first gate structure in the extending direction of the first gate structure.
7. The antifuse structure circuit of claim 1, wherein the first gate structure extends in a direction parallel to the second conductive plug, and a dimension of the first gate structure in the extending direction is greater than a dimension of the second conductive plug in the extending direction; the first grid structure comprises a connecting area which is suitable for being connected with the first conductive plug, and an interlayer dielectric layer on the connecting area and an interlayer dielectric layer between the second conductive plugs on two sides of the first grid structure are not provided with an overlapping area.
8. The antifuse structure circuit of claim 1, wherein the first conductive plugs are located between the second conductive plugs.
9. The antifuse structure circuit of claim 1, further comprising: and the first source-drain doped regions are respectively positioned in the substrates at two sides of the first grid structure and are electrically connected with the second conductive plug.
10. The antifuse structure circuit of claim 1, wherein the interlevel dielectric layer further comprises a second dielectric layer, the second dielectric layer overlying the first dielectric layer and the first gate structure; the first conductive plug only penetrates through the second dielectric layer; the second conductive plug penetrates through the first dielectric layer and the second dielectric layer.
11. The antifuse structure circuit of claim 1, wherein the set of control gate structures further comprises a second gate structure; the interlayer dielectric layer also covers the second grid structure; the antifuse structure circuit further includes: the second source-drain doped regions are respectively positioned in the substrates at two sides of the second grid structure; a third conductive plug penetrating through the interlayer dielectric layer on the second grid structure; and the fourth conductive plug penetrates through interlayer dielectric layers on two sides of the second grid structure, the fourth conductive plug is electrically connected with the second source drain doped region, a third distance is formed between the fourth conductive plug and the third conductive plug, a fourth distance is formed between the fourth conductive plug and the second grid structure, the third distance refers to the minimum distance from the edge of the fourth conductive plug to the edge of the third conductive plug, and the fourth distance refers to the minimum distance from the edge of the fourth conductive plug to the edge of the second grid structure.
12. The antifuse structure circuit of claim 11, wherein the second distance is less than or equal to a fourth distance, and the first distance is less than a third distance.
13. The antifuse structure circuit of claim 1, wherein the control region is plural in number; the substrate further comprises isolation regions located between adjacent control regions; the antifuse structure circuit further includes: an isolation gate structure on the substrate isolation region, the isolation gate structure adapted to not have a voltage applied thereto; and the third source-drain doped regions are respectively positioned in the substrates at two sides of the isolation gate structure.
14. A method for forming an anti-fuse structure circuit, comprising:
providing a substrate, wherein the substrate comprises a control area;
forming a control grid structure group and an antifuse on a substrate control area, wherein the control grid structure group comprises a first grid structure;
the method for forming the antifuse comprises the following steps:
forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the first grid structure and comprises a first dielectric layer, and the top surface of the first dielectric layer is flush with the top surface of the first grid structure;
forming a first conductive plug penetrating through the interlayer dielectric layer on the first grid structure, wherein the first conductive plug covers the top surface of the first grid structure and part of the first dielectric layer on two sides of the first grid structure;
and forming a second conductive plug penetrating through the interlayer dielectric layers on two sides of the first gate structure, wherein a first distance is formed between the second conductive plug and the first conductive plug, a second distance is formed between the second conductive plug and the first gate structure, the first distance is smaller than the second distance, the first distance refers to the minimum distance from the edge of the second conductive plug to the edge of the first conductive plug, and the second distance refers to the minimum distance from the edge of the second conductive plug to the edge of the first gate structure.
15. The method of claim 14, wherein the first distance is 20% to 80% of the second distance.
16. The method of claim 14, wherein the number of the first gate structures is one or more; when the number of the first gate structures is one, the first gate structure is provided with two first conductive plugs which are respectively positioned at two ends of the first gate structure along the extension direction of the first gate structure, or the first gate structure is provided with one first conductive plug which is positioned at one end of the first gate structure along the extension direction of the first gate structure; when the number of the first gate structures is multiple, each first gate structure is provided with two first conductive plugs, the first conductive plugs are respectively located at two ends of the first gate structure along the extending direction of the first gate structure, or each first gate structure is provided with one first conductive plug, and the first conductive plugs are located at one end of the first gate structure along the extending direction of the first gate structure.
17. The method of claim 14, wherein the extending direction of the first gate structure is parallel to the extending direction of the second conductive plug, and the dimension of the first gate structure in the extending direction is larger than the dimension of the second conductive plug in the extending direction; the first grid structure comprises a connecting area which is suitable for being connected with the first conductive plug, and an interlayer dielectric layer on the connecting area and an interlayer dielectric layer between the second conductive plugs on two sides of the first grid structure are not provided with an overlapping area.
18. The method of claim 14, wherein the first conductive plugs are located between the second conductive plugs.
19. The method of claim 14, wherein the set of control gate structures further comprises a second gate structure; the interlayer dielectric layer also covers the second grid structure; the method for forming the anti-fuse structure circuit further comprises the following steps: forming a second source-drain doped region in the process of forming the control grid structure group and the anti-fuse, wherein the second source-drain doped region is respectively positioned in the substrates at two sides of the second grid structure; forming a third conductive plug penetrating through the interlayer dielectric layer on the second grid structure; forming a fourth conductive plug penetrating through the interlayer dielectric layers on the two sides of the second grid structure, wherein the fourth conductive plug is electrically connected with the second source drain doped region, a third distance is formed between the fourth conductive plug and the third conductive plug, and a fourth distance is formed between the fourth conductive plug and the second grid structure; the second distance is less than or equal to a fourth distance, and the first distance is less than a third distance, the third distance refers to a minimum distance from an edge of the fourth conductive plug to an edge of the third conductive plug, and the fourth distance refers to a minimum distance from an edge of the fourth conductive plug to an edge of the second gate structure.
20. The method of claim 14, wherein the number of the control regions is plural; the substrate further comprises isolation regions located between adjacent control regions; the method for forming the anti-fuse structure circuit further comprises the following steps: and forming an isolation grid structure and a third source drain doped region, wherein the isolation grid structure is positioned on the substrate isolation region, the isolation grid structure is suitable for not applying voltage, and the third source drain doped region is respectively positioned in the substrate at two sides of the isolation grid structure.
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| CN116367542A (en) * | 2021-12-24 | 2023-06-30 | 长鑫存储技术有限公司 | Antifuse array structure and memory |
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