KR20160092923A - Vertical type cmos inverter device - Google Patents

Vertical type cmos inverter device Download PDF

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KR20160092923A
KR20160092923A KR1020160005678A KR20160005678A KR20160092923A KR 20160092923 A KR20160092923 A KR 20160092923A KR 1020160005678 A KR1020160005678 A KR 1020160005678A KR 20160005678 A KR20160005678 A KR 20160005678A KR 20160092923 A KR20160092923 A KR 20160092923A
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metal layer
layer
gate
polarity
terminal
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KR1020160005678A
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KR101743864B1 (en
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허천신
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허천신
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Abstract

Disclosed is a vertical complementary metal-oxide semiconductor (CMOS) inverter device. The vertical CMOS inverter device of the present invention includes: a first metal layer; a second metal layer formed on the first metal layer and on which an input terminal and an output terminal are patterned; a third metal layer formed on the second metal layer; a first gate ploy layer formed between the first and second metal layers and on which a first gate terminal is patterned; a first semi-conductive layer formed in a lateral surface of the first gate terminal and operated for the conduction between the output terminal of the second metal layer and the first metal layer according to a level of voltages applied to the input terminal of the second metal layer; a second gate poly layer formed between the second and third metal layers and on which a second gate terminal is pattered; and a second semi-conductive layer formed on a lateral surface of the second gate terminal between the second and third metal layers and operated for the conduction between the output terminal of the second metal layer and the third metal layer according to the level of the voltages applied to the input terminal of the second metal layer. The vertical CMOS inverter device of the present invention is formed by stacking up each component in a vertical direction. Accordingly, according to the vertical CMOS inverter device of the present invention, a required layout area is remarkably decreased. In addition, a delay due to connection is minimized by reducing a connection length of the components, thus high-speed operation is possible.

Description

{Vertical Type CMOS Inverter Device}

The present invention relates to a semiconductor circuit device, and more particularly, to a CMOS inverter device.

The semiconductor chip is formed to include various kinds of semiconductor circuit elements, among which a large number of CMOS inverter elements are formed. These CMOS inverter devices are generally formed across the surface of the semiconductor substrate in the horizontal direction.

However, the CMOS inverter device formed in the horizontal direction requires a large layout area, and the connection line of the signals becomes long, so that a delay occurs in the signal transmission. As a result, the size of the semiconductor chip becomes large and it becomes difficult to develop a high-speed circuit.

Therefore, it is required to develop a CMOS inverter device that reduces the required layout area and shortens the connection length between circuits as much as possible to enable high-speed operation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above needs, and an object of the present invention is to provide a vertical CMOS inverter device capable of reducing a required layout area and enabling high-speed operation.

According to an aspect of the present invention, there is provided a vertical CMOS inverter device. A vertical CMOS inverter device of the present invention includes: a first metal layer formed on a semiconductor substrate and supplying a first supply voltage; A second metal layer formed on the first metal layer and having an input terminal and an output terminal patterned; A third metal layer formed on the second metal layer and supplying a second supply voltage; A first gate poly layer formed between the first metal layer and the second metal layer and patterned with a first gate terminal, the first gate terminal electrically connected to the input terminal of the second metal layer, The first gate poly layer being electrically insulated from output terminals of the first metal layer and the second metal layer; The first metal layer is formed on a side of the first gate terminal between the first metal layer and the second metal layer. The first metal layer is formed on the first metal layer, The first semiconductor layer being driven to conduct the output terminal of the second metal layer; A second gate poly layer formed between the second metal layer and the third metal layer and having a second gate terminal patterned thereon, the second gate terminal electrically connected to the input terminal of the second metal layer The second gate poly layer being electrically insulated from the output terminal of the second metal layer and the third metal layer; And a second semiconductor layer formed on a side surface of the second gate terminal between the second metal layer and the third metal layer, wherein the second metal layer has a second metal layer, Layer and the second semiconductor layer driven to electrically conduct the third metal layer.

In the vertical CMOS inverter device of the present invention as described above, the respective components are vertically stacked. Thus, according to the vertical CMOS inverter device of the present invention, the required layout area is remarkably reduced. Also, since the connection length of the components is shortened, the delay due to the connection is minimized, and high-speed operation is enabled.

A brief description of each drawing used in the present invention is provided.
1 is a cross-sectional view illustrating a vertical CMOS inverter device according to an embodiment of the present invention.
Figs. 2A and 2B are diagrams showing an equivalent circuit of the vertical CMOS inverter device of Fig. 1. Fig.
3 is a flowchart for explaining a method of manufacturing the vertical CMOS inverter device of FIG.
FIGS. 4 to 10 are cross-sectional views showing cross sections at respective steps according to the manufacturing method of FIG.

For a better understanding of the present invention and its operational advantages, and the objects attained by the practice of the present invention, reference should be made to the accompanying drawings, which illustrate preferred embodiments of the invention, and the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are being provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

It should be noted that, in understanding each of the drawings, the same members are denoted by the same reference numerals whenever possible. Further, detailed descriptions of known functions and configurations that may be unnecessarily obscured by the gist of the present invention are omitted.

On the other hand, in order to clearly illustrate the layers (or films) and regions in the drawings, the thickness is enlarged. It is to be understood that when an element or layer is referred to as being "on" another part, it is understood that the term "layer", "film" . Conversely, when a part is referred to as being "directly on" another part, it means that there is no other part in the middle.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(Vertical type Seamos  Of the inverter device Example )

1 is a cross-sectional view illustrating a vertical CMOS inverter device according to an embodiment of the present invention. Referring to FIG. 1, the vertical CMOS inverter device of the present invention includes a first metal layer MET1, a second metal layer MET2, a third metal layer MET3, a first gate poly layer GPL1, (FCD1), a second gate poly layer (GPL2), and a second semiconductor layer (FCD2).

The first metal layer MET1 is formed on the semiconductor substrate SUB and supplies the first supply voltage VPW1.

The second metal layer MET2 is formed on the first metal layer MET1, and the input terminal NIN and the output terminal NUT are patterned.

The third metal layer MET3 is formed on the second metal layer MET2 and supplies the second supply voltage VPW2.

The first gate poly layer GPL1 is formed between the first metal layer MET1 and the second metal layer MET2 and the first gate terminal NGA1 is patterned. At this time, the first gate terminal NGA1 is electrically connected to the input terminal NIN of the second metal layer MET2, and the output of the first metal layer MET1 and the output of the second metal layer MET2 And is electrically insulated from the terminal (NUT).

The first semiconductor layer FCD1 is formed on a side surface of the first gate terminal NGA1 between the first metal layer MET1 and the second metal layer MET2. At this time, the first semiconductor layer FCD1 is electrically connected to the first metal layer MET1 and the second metal layer MET2 according to the level of a voltage applied to the input terminal NIN of the second metal layer MET2, And the output terminal NUT of the transistor Q2 is electrically connected.

Preferably, the first semiconductor layer FCD1 includes a first source layer LSC1, a first channel layer LCH1, and a first drain layer LDR1.

The first source layer LSC1 includes an impurity of a first polarity and is connected to the first metal layer MET1.

The first channel layer LCH1 includes an impurity of a second polarity and is formed directly on the first source layer LSC1. At this time, the second polarity is opposite to the first polarity.

The first drain layer LDR1 is formed directly on the first channel layer LCH1. The first drain layer LDR1 includes an impurity of the first polarity and is connected to the output terminal NUT of the second metal layer MET2.

The second gate poly layer GPL2 is formed between the second metal layer MET2 and the third metal layer MET3 and the second gate terminal NGA2 is patterned. At this time, the second gate terminal NGA2 is electrically connected to the input terminal NIN of the second metal layer MET2, and the output of the third metal layer MET3 and the output of the second metal layer MET2 And is electrically insulated from the terminal (NUT).

The second semiconductor layer FCD2 is formed on the side surface of the second gate terminal NGA2 between the second metal layer MET2 and the second metal layer MET3. At this time, the second semiconductor layer FCD2 is electrically connected to the third metal layer MET3 and the second metal layer MET2 according to the level of the voltage applied to the input terminal NIN of the second metal layer MET2. And the output terminal NUT of the transistor Q2 is electrically connected.

Preferably, the second semiconductor layer FCD2 includes a second drain layer LDR2, a second channel layer LCH2, and a second source layer LSC2.

The second drain layer LDR2 includes an impurity of a second polarity and is connected to the output terminal NUT of the second metal layer MET2.

The second channel layer LCH2 includes an impurity of the first polarity and is formed directly on the second drain layer LDR2.

The second source layer LSC2 is formed directly on the first channel layer LCH1. The second source layer LSC2 includes an impurity of the second polarity and is connected to the third metal layer MET3.

In the vertical CMOS inverter device of the preferred embodiment, the first supply voltage VPW1 is lower than the second supply voltage VPW2, the first polarity is n-type, and the second polarity is p-type .

In this case, a vertical CMOS inverter device having an equivalent circuit as shown in Fig. 2A is realized. In FIG. 2A, the first supply voltage VPW1 is a ground voltage VSS and the second supply voltage VPW2 is a power supply voltage VDD.

In a vertical CMOS inverter device of another preferred embodiment, the first supply voltage VPW1 is higher than the second supply voltage VPW2, the first polarity is a p-type, the second polarity is an n-type to be.

In this case, a vertical CMOS inverter device having an equivalent circuit as shown in Fig. 2B is implemented. 2B, the first supply voltage VPW1 is a power supply voltage VDD and the second supply voltage VPW2 is a ground voltage VSS.

In the vertical CMOS inverter device of the present invention as described above, the respective components are vertically stacked. Accordingly, in the vertical CMOS inverter according to the present invention, each component is vertically stacked. Thus, according to the vertical CMOS inverter device of the present invention, the required layout area is remarkably reduced. Also, since the connection length of the components is shortened, the delay due to the connection is minimized, and high-speed operation is enabled.

(Vertical type Seamos  Method of manufacturing inverter device)

Next, a method of manufacturing the vertical CMOS inverter device of the present invention is described.

3 is a flowchart for explaining a method of manufacturing the vertical CMOS inverter device of FIG.

Referring to FIG. 3, the vertical CMOS inverter device includes a first metal layer forming step S10, a first gate poly layer forming step S20, a first gate terminal / first semiconductor layer forming step S30 (S50), a second gate terminal / second semiconductor layer forming step (S60), and a third metal layer forming step (S70) .

In the first metal layer forming step (S10), as shown in FIG. 4, the first metal layer MET1 is formed on the prepared semiconductor substrate SUB. Specifically, a first insulating layer 100 is formed on the semiconductor substrate SUB, and the first metal layer MET1 is formed directly on the first insulating layer 100. Accordingly, the first metal layer MET1 is insulated from the semiconductor substrate SUB by the first insulating layer 100.

In the first gate poly layer forming step S20, as shown in FIG. 5, a first gate poly layer GPL1 is formed on the first metal layer MET1. Specifically, a second insulating layer 210 is formed on the first metal layer MET1, and the first gate poly layer GPL1 is formed directly on the second insulating layer 210. Referring to FIG. Accordingly, the first gate poly layer GPL1 is insulated from the first metal layer MET1 by the second insulating layer 210. [

The first gate poly layer GPL1 is patterned into a first gate region ARGAT1 and a third insulating layer 220 is formed on the first gate poly layer GPL1 patterned with the first gate region ARGAT1. .

In the first gate terminal / first semiconductor layer formation step (S30), a first gate terminal (NGA1) and a first semiconductor layer (FCD1) are formed as shown in FIG. More specifically, the third insulating layer 220, the first gate poly layer GPL1, and the second insulating layer (ARPL1) are formed in the first semiconductive region ARCD1 including at least a part of the first gate region ARGAT1 210 are etched. As a result, the first gate terminal NGA1 is formed.

A first gate oxide film 300 is formed on the sidewall of the first gate terminal NGA1. A first source layer LSC1, a first channel layer LCH1 and a first drain layer LDR1 are stacked on the sidewall of the first gate terminal NGA1 where the first gate oxide film 300 is formed, The first semiconductor layer FCD1 is formed.

At this time, the first source layer LSC1 is a semiconductor material (for example, silicon) including an impurity of a first polarity and is connected to the first metal layer MET1.

The first channel layer (LCH1) is a semiconductor material containing an impurity of a second polarity and is formed directly connected to the first source layer (LSC1).

The first drain layer LDR1 is a semiconductor material containing an impurity of the first polarity and is formed directly above the first channel layer LCH1.

In the second metal layer forming step S40, as shown in FIG. 7, a second metal layer MET2 is formed, and the input terminal NIN and the output terminal NUT are patterned. Specifically, the third insulating layer 220 of the first contact region ARCT1 is etched to open the first gate terminal NGA1.

The second metal layer MET2 is formed in a state where the first gate terminal NGA1 of the first contact region ARCT1 is open. The second metal layer MET2 is patterned to form the input terminal NIN and the output terminal NUT.

As a result, the input terminal NIN of the second metal layer MET2 is connected to the first gate terminal NGA1, and the output terminal NUT of the second metal layer MET2 is connected to the first And is connected to the first drain layer LDR1 of the semiconductor layer FCD1.

A fourth insulating layer 400 is formed on the second metal layer MET2 on which the input terminal NIN and the output terminal NUT are patterned.

In the second gate poly layer forming step (S50), the second gate poly layer (GPL2) is formed as shown in Fig. Specifically, the fourth insulating layer 400 of the second contact region ARCT2 is etched to open the input terminal NIN of the second metal layer MET2.

The second gate poly layer GPL2 is formed in a state where the input terminal NIN of the second metal layer MET2 is open. Then, the second gate poly layer GPL2 of the second gate region ARGAT2 is patterned.

 A fifth insulating layer 500 is formed on the second gate poly layer GPL2 on which the second gate region ARGAT2 is patterned.

In the second gate terminal / second semiconductor layer formation step (S60), a second gate terminal (NGA2) and a second semiconductor layer (FCD2) are formed as shown in Fig. Specifically, the fifth insulating layer 500, the second gate poly layer GPL2, and the fourth insulating layer (ARCL2) are formed in the second semiconductive region ARCD2 including at least a part of the second gate region ARGAT2 400 are etched. As a result, the second gate terminal NGA2 connected to the input terminal NIN of the second metal layer MET2 is formed.

A second gate oxide film 600 is formed on the sidewall of the second gate terminal NGA2. A second drain layer LDR2, a second channel layer LCH2 and a second source layer LSC2 are stacked on the sidewall of the second gate terminal NGA2 on which the second gate oxide film 600 is formed, The second semiconductor layer FCD2 connected to the output terminal NUT of the second metal layer MET2 is formed.

At this time, the second drain layer LDR2 is a semiconductor material (silicon) including an impurity of a second polarity and is connected to the output terminal NUT of the second metal layer MET2.

The second channel layer LCH2 is a semiconductor material containing an impurity of a first polarity and is formed directly above the second drain layer LDR2.

The second source layer (LSC2) is a semiconductor material containing an impurity of the second polarity, and is formed directly above the second channel layer (LCH2).

In the third metal layer forming step S70, as shown in FIG. 10, a third metal layer MET3 is formed on the fifth insulating layer 500 on which the second semiconductor layer FCD2 is formed.

Accordingly, the third metal layer MET3 is connected to the second source layer LSC2 of the second semiconductor layer FCD2, and is insulated from the second gate terminal NGA2.

According to the method of manufacturing the vertical CMOS inverter device of the present invention, the vertical CMOS inverter device of the present invention as shown in FIG. 1 is formed.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

For example, in the present specification, the first insulating layer 110 and the first metal layer 100 are shown and described as being formed directly on the semiconductor substrate SUB. However, since the first insulating layer 100 and the first metal layer MET1 are formed directly on the semiconductor substrate SUB as well as between the semiconductor substrate SUB and the first insulating layer 100, In embodiments where other materials or layers are present, the technical idea of the present invention is implemented.

Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (4)

In the vertical CMOS inverter device,
A first metal layer formed on the semiconductor substrate and supplying a first supply voltage;
A second metal layer formed on the first metal layer and having an input terminal and an output terminal patterned;
A third metal layer formed on the second metal layer and supplying a second supply voltage;
A first gate poly layer formed between the first metal layer and the second metal layer and patterned with a first gate terminal, the first gate terminal electrically connected to the input terminal of the second metal layer, The first gate poly layer being electrically insulated from output terminals of the first metal layer and the second metal layer;
The first metal layer is formed on a side of the first gate terminal between the first metal layer and the second metal layer. The first metal layer is formed on the first metal layer, The first semiconductor layer being driven to conduct the output terminal of the second metal layer;
A second gate poly layer formed between the second metal layer and the third metal layer and having a second gate terminal patterned thereon, the second gate terminal electrically connected to the input terminal of the second metal layer The second gate poly layer being electrically insulated from the output terminal of the second metal layer and the third metal layer; And
And a second semiconductor layer formed on a side surface of the second gate terminal between the second metal layer and the third metal layer, the second semiconductor layer being formed on the second metal layer in accordance with a level of a voltage applied to an input terminal of the second metal layer, And the second semi-conductor layer is electrically connected to the third metal layer through an output terminal of the third semiconductor layer.
The method according to claim 1,
The first semi-
A first source layer including an impurity of a first polarity, the first source layer being connected to the first metal layer;
A first channel layer including an impurity of a second polarity having a polarity opposite to the first polarity, the first channel layer being formed directly on the first source layer; And
And a first drain layer formed directly on the first channel layer, the first drain layer including an impurity of the first polarity, the first drain layer being connected to an output terminal of the second metal layer,
The second semiconductive layer
A second drain layer including an impurity of the second polarity and connected to an output terminal of the second metal layer;
A second channel layer including an impurity of the first polarity and formed directly on the second drain layer; And
And a second source layer formed directly on the second channel layer, the first source layer including an impurity of the second polarity and connected to the third metal layer, device.
3. The method of claim 2,
Wherein the first supply voltage has a level lower than the second supply voltage,
Wherein the first polarity is n-type,
And the second polarity is p-type
Vertical CMOS inverter device.
3. The method of claim 2,
The first supply voltage has a level higher than the second supply voltage,
Wherein the first polarity is p-type,
The second polarity is n-type
Vertical CMOS inverter device.

KR1020160005678A 2015-01-28 2016-01-17 Vertical type cmos inverter device KR101743864B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110970369A (en) * 2018-09-30 2020-04-07 中芯国际集成电路制造(上海)有限公司 CMOS inverter structure and forming method thereof
KR102324232B1 (en) * 2020-06-03 2021-11-08 연세대학교 산학협력단 Vertical Transistor Having Gate-All-Around Structure and Manufacturing Method Thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100625933B1 (en) 2005-09-29 2006-09-18 매그나칩 반도체 유한회사 Semiconductor device and method for fabrication of the same
JP5130596B2 (en) 2007-05-30 2013-01-30 国立大学法人東北大学 Semiconductor device
KR101351794B1 (en) 2012-10-31 2014-01-15 (주)피델릭스 Pilla type vertical channel transitor in semiconductor device and fabrication method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110970369A (en) * 2018-09-30 2020-04-07 中芯国际集成电路制造(上海)有限公司 CMOS inverter structure and forming method thereof
CN110970369B (en) * 2018-09-30 2022-08-02 中芯国际集成电路制造(上海)有限公司 CMOS inverter structure and forming method thereof
KR102324232B1 (en) * 2020-06-03 2021-11-08 연세대학교 산학협력단 Vertical Transistor Having Gate-All-Around Structure and Manufacturing Method Thereof

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