CN110970369B - CMOS inverter structure and forming method thereof - Google Patents

CMOS inverter structure and forming method thereof Download PDF

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CN110970369B
CN110970369B CN201811156601.6A CN201811156601A CN110970369B CN 110970369 B CN110970369 B CN 110970369B CN 201811156601 A CN201811156601 A CN 201811156601A CN 110970369 B CN110970369 B CN 110970369B
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semiconductor material
forming
source
drain epitaxial
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CN110970369A (en
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金吉松
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Abstract

The invention provides a CMOS inverter structure and a forming method thereof, wherein the CMOS inverter structure greatly reduces the space occupation of a device in the horizontal direction and improves the micro-shrinkage performance of a CMOS circuit by stacking a p-type horizontal surrounding grid field effect transistor and an n-type horizontal surrounding grid field effect transistor in the vertical direction. In addition, the forming method of the CMOS inverter structure successfully stacks the p-type horizontal surrounding grid field effect transistor and the n-type horizontal surrounding grid field effect transistor in the vertical direction through ingenious process flow design, simultaneously has relatively simple process flow, is easy to put into use, and can obtain great advantages of micro-shrinkage performance and other comprehensive performance after a 5nm node.

Description

CMOS inverter structure and forming method thereof
Technical Field
The invention relates to the field of semiconductor manufacturing processes, in particular to a CMOS inverter structure prepared by a horizontal surrounding gate field effect transistor process.
Background
A pair of N-channel and P-channel MOS transistors operate in a push-pull fashion to form a Complementary Metal-Oxide-Semiconductor (CMOS) device. The integrated circuit with certain logic function realized by the formed inverter basic circuit unit becomes a CMOS circuit.
In the process of continuously scaling down MOS devices, the moore's law is extended by the FinFET (Field Effect Transistor) due to its excellent performance and compatibility with the conventional CMOS process. At the 14nm node, since the width of the FinFET fin is only about 5nm, variations in channel width may cause undesirable variations in threshold voltage, drive current, and the like. The use of a Gate-All-Around Field Effect Transistor (GAAFET) device structure is a natural extension of a FinFET device.
The surrounding gate field effect transistor includes a horizontal type and a vertical type, wherein the vertical type surrounding gate, due to the channel extending in a direction perpendicular to the substrate, although convenient for scaling, requires a great change in process design at the same time; although the horizontal surrounding gate fet is relatively similar to the conventional FinFET process technology and is easy to use, the scaling is mainly performed by reducing the feature length, i.e., reducing the gate size and the channel size. Scaling by reducing feature lengths is increasingly difficult due to limitations in the degree of process development.
Disclosure of Invention
The technical problem to be solved by the invention is to improve the micro performance of a CMOS circuit formed by a horizontal surrounding grid field effect transistor through structural design.
In the process of creating the present invention, the inventor has noticed that, in the CMOS inverter structure in the prior art, the PMOS and the NMOS respectively occupy different active region positions, which causes a problem of an excessively large occupied area of a device cell, and by stacking the PMOS and the NMOS in a vertical direction, the occupied area of the cell can be greatly reduced. However, attempting to stack PMOS and NMOS in the vertical direction brings new problems that are difficult to solve. In previous semiconductor fabrication processes, such as FinFET structures, stacking PMOS and NMOS structures was particularly difficult due to the particularities of the structures. The invention provides a preparation method and a structure which can stack PMOS and NMOS in the vertical direction, and can obtain the advantages of great micro-shrinkage performance and other comprehensive performance after 5nm node.
Specifically, the present invention firstly provides a method for forming a CMOS inverter structure, which includes: forming a first channel layer and a second channel layer stacked in a vertical direction, the first channel layer being disposed above the second channel layer, the first channel layer and the second channel layer being channels having opposite carrier types; forming an interlayer dielectric layer which covers the side walls of the first channel layer and the second channel layer; etching the interlayer dielectric layer to expose the side wall of the first channel layer; forming an outer sidewall layer at least covering a sidewall of the first channel layer; continuously etching the interlayer dielectric layer to expose the side wall of the second channel layer; forming a second source-drain epitaxial layer along the side wall of the second channel layer; removing the outer side wall layer; and forming a first source-drain epitaxial layer along the side wall of the first channel layer.
Through the processes, the PMOS and the NMOS can be stacked along the vertical direction by the forming method provided by the invention, the space occupation of the active region of the CMOS inverter unit is greatly reduced, and the transistor density which can be achieved by the CMOS circuit is greatly improved. The method for etching the interlayer dielectric layer step by step and using the outer side wall layer to protect the upper channel is adopted, so that the preparation of the multilayer stacking structure can be simply and effectively completed.
In the present invention, the "vertical direction" refers to a direction perpendicular to the plane of the wafer substrate, the "horizontal direction" refers to a direction parallel to the plane of the wafer substrate, and the spatial relationship terms such as "under", "below", "under", "above", "over", and the like are spatial positions described in the case where the wafer is disposed upward in the gravity direction.
Further, the above-mentioned "the first channel layer and the second channel layer are channels having opposite carrier types" includes both the case where "the first channel layer is a p-type channel, the case where the second channel layer is an n-type channel" and "the first channel layer is an n-type channel, the case where the second channel layer is a p-type channel".
In a preferred embodiment of the present invention, the step of forming the first channel layer and the second channel layer stacked in the vertical direction specifically includes: providing a substrate; epitaxially growing a superlattice structure formed by alternately arranging first semiconductor material layers and second semiconductor material layers on the substrate, wherein the superlattice structure comprises a first part far away from the substrate and a second part close to the substrate, the first part at least comprises two first semiconductor material layers and a second semiconductor material layer which is sandwiched between the two first semiconductor material layers and is used as a first channel layer, and the second part at least comprises two second semiconductor material layers and a first semiconductor material layer which is sandwiched between the two second semiconductor material layers and is used as a second channel layer. The channel of the horizontal surrounding grid field effect transistor can be simply, conveniently and effectively prepared by utilizing the superlattice structure.
In a preferred embodiment of the present invention, after the etching the interlayer dielectric layer to expose the sidewall of the first channel layer, and before forming the outer sidewall layer, the method further includes: the side walls of the two layers of first semiconductor material layers in the first part are transversely etched to form a first transverse groove, and a first inner side wall layer is formed in the first transverse groove in a deposition mode; and/or after the interlayer dielectric layer is continuously etched and the side wall of the second channel layer is exposed, before a second source-drain epitaxial layer is formed along the side wall of the second channel layer, the method further comprises the following steps: and laterally etching the side walls of the two layers of second semiconductor material layers in the second part to form a second lateral groove, and depositing in the second lateral groove to form a second inner side wall layer. And the inner side wall is transversely etched and formed, so that the selectivity of epitaxial growth can be improved, and the parasitic capacitance can be effectively reduced.
In a preferred embodiment of the present invention, a layer spacing between the second semiconductor material layer as the first channel layer and the first semiconductor material layer as the second channel layer in the superlattice structure is greater than a sum of thicknesses of the second semiconductor material layer and the first semiconductor material layer. By reserving a larger interlayer spacing, for example, by growing a larger number of interlayers or controlling the epitaxial growth time to increase the layer thickness, the problem that the etching thickness is difficult to control when the interlayer dielectric layer is etched can be solved.
In a preferred technical scheme of the present invention, the first source drain epitaxial layer and the second source drain epitaxial layer are formed by an in-situ doped source drain epitaxial process.
Furthermore, the first source drain epitaxial layer is doped in situ in an n-type mode, and the second source drain epitaxial layer is doped in situ in a p-type mode. The larger the volume of the p-type epitaxy is, the higher the compressive stress is generated, and the smaller the volume of the n-type epitaxy is, the better tensile stress effect can be obtained. Therefore, the lower part is configured to be the p-type epitaxy with larger volume, and the upper part is configured to be the n-type epitaxy with smaller volume, so that the consideration of stress effect and circuit layout can be considered, the direct wiring above each epitaxial structure in the later stage step is allowed, and the stress effect of the epitaxial structure is ensured.
In a preferred embodiment of the present invention, before forming the interlayer dielectric layer, the method further includes: forming a first pseudo gate oxide layer covering the surface of the superlattice structure; forming a dummy gate across the superlattice structure; etching the superlattice structure which does not cover the pseudo grid until the substrate is exposed; after the first source-drain epitaxial layer is formed, the method further comprises the following steps: etching part of the pseudo gate and the first pseudo gate oxide layer to expose the two first semiconductor material layers of the first part; etching to remove the two first semiconductor material layers of the first part; forming a second pseudo gate oxide layer covering the second semiconductor material layer as the first channel layer; and removing the first pseudo gate oxide layer and the pseudo gate to expose the second part. By the method of etching the pseudo Gate oxide layer and the pseudo Gate in steps, the HKMG (High-k Metal Gate) Gate structure can be effectively replaced on the basis of the original superlattice structure.
The invention also provides a CMOS phase inverter structure which comprises a p-type horizontal surrounding grid field effect transistor and an n-type horizontal surrounding grid field effect transistor, wherein the p-type horizontal surrounding grid field effect transistor and the n-type horizontal surrounding grid field effect transistor are stacked in the vertical direction. The p-type horizontal surrounding grid field effect transistor and the n-type horizontal surrounding grid field effect transistor are stacked, so that the space occupation of the phase inverter structure can be greatly reduced, and the miniaturization of a CMOS circuit formed by the horizontal surrounding grid field effect transistors is facilitated.
The invention also provides a CMOS phase inverter structure which comprises a p-type horizontal surrounding grid field effect transistor and an n-type horizontal surrounding grid field effect transistor, wherein the p-type horizontal surrounding grid field effect transistor and the n-type horizontal surrounding grid field effect transistor are stacked in the vertical direction. The PMOS and the NMOS in the inverter structure are stacked in the vertical direction, so that the space occupation of the active area of the CMOS inverter unit is greatly reduced, and the transistor density which can be achieved by the CMOS circuit is greatly improved.
In a preferred technical scheme of the invention, the source drain epitaxial layer and the channel layer of the p-type horizontal surrounding gate field effect transistor and the n-type horizontal surrounding gate field effect transistor are stacked along the vertical direction, and the p-type horizontal surrounding gate field effect transistor and the n-type horizontal surrounding gate field effect transistor share a gate structure. By the method of sharing the metal gate, the metal gates in the same CMOS inverter unit can be formed into an integral structure without preparing an interconnection structure of PMOS and NMOS gates, and meanwhile, the parasitic resistance is reduced and the device performance is improved.
Further, in a preferred technical scheme of the present invention, the p-type horizontal surrounding gate field effect transistor includes a first source drain epitaxial layer, the n-type horizontal surrounding gate field effect transistor includes a second source drain epitaxial layer, the n-type horizontal surrounding gate field effect transistor is stacked above the p-type horizontal surrounding gate field effect transistor, and a volume of the first source drain epitaxial layer is smaller than a volume of the second source drain epitaxial layer. The technical scheme considers the stress effect of different source-drain epitaxy, the stability of the stacking structure and the difficulty of wiring design brought by the structure.
Furthermore, in a preferred technical scheme of the present invention, an isolation layer covers the second source-drain epitaxial layer, the first source-drain epitaxial layer covers a portion of the surface of the isolation layer, and an interconnection structure is disposed at a portion of the isolation layer not covering the first source-drain epitaxial layer, and the interconnection structure is electrically connected to at least the top of the second source-drain epitaxial layer. According to the technical scheme, the wires are respectively arranged at different horizontal positions of the device, the wire arrangement structure is simple and convenient, and the limitation of middle-section wire arrangement on the process shrinkage is overcome. In addition, the interconnection structure can be electrically connected with the side wall of the second source drain epitaxial layer, so that contact resistance is reduced, and the operation rate of the device is improved.
The invention also provides a semiconductor structure which can be a device, a unit, a component, a device or a system comprising the CMOS inverter structure provided by the invention.
Drawings
Fig. 1-18 are schematic structural diagrams of a CMOS inverter structure in different steps of a forming process according to an embodiment of the present invention.
Detailed Description
Hereinafter, preferred embodiments of the present invention will be described in general with reference to the accompanying drawings. The embodiments of the present invention are not limited to the following embodiments, and various embodiments within the technical concept of the present invention can be adopted.
One of the problems to be solved by the present invention is to stack the p-type horizontal surrounding gate fet and the n-type horizontal surrounding gate fet in the vertical direction, which brings many technological innovations and problems, and one of the problems is how to design the process, on one hand, the complexity of the process flow is reduced as much as possible, and the productivity is improved; on the other hand, it is necessary to prevent the subsequent process steps from damaging the previous structure and affecting the device performance. If the layer-by-layer preparation is carried out, the preparation process is extremely complicated; however, if the traditional layer-by-layer preparation method is abandoned, the process flow design of the three-dimensional structure is very challenging.
In order to solve the above problems, in the technical solution provided in this embodiment, first, the first interlayer dielectric layer 8 is used to protect the second portion 2-2 of the superlattice structure 2, and a sidewall and a channel structure of the first portion 2-1 are fabricated; protecting a first part 2-1 of the superlattice structure 2 by using the outer side wall layer 10, continuously etching the first interlayer dielectric layer 8 to expose the originally protected second part 2-2, and manufacturing a field effect tube structure of the second part 2-2; then, the outer sidewall layer 10 is removed, and the fet structure of the first portion 2-1 is re-fabricated. The technical scheme simplifies the process flow, prevents the influence of subsequent process steps on the existing structure, and can efficiently obtain the semiconductor structure with stacked p-type field effect transistors and n-type field effect transistors at low cost.
First, referring to fig. 1, a substrate 1 is provided, and a superlattice structure 2 stacked in a vertical direction is epitaxially grown along a surface of the substrate 1. In this embodiment, the superlattice structure 2 is composed of first semiconductor material layers 201 and second semiconductor material layers 202 alternately arranged in this order. Specifically, the first semiconductor material layer 201 is a silicon germanium material layer, and the second semiconductor material layer 202 is a silicon material layer.
In some embodiments of the present invention, substrate 1 may comprise a single crystal semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In the present embodiment, the substrate 1 is made of silicon.
The substrate 1 may comprise one or more buffer layers (not shown) in its surface area. The buffer layer may be used to gradually change the lattice constant from that of the substrate to that of the source/drain regions. The buffer layer may be formed from an epitaxially grown single crystal semiconductor material such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP.
In the present embodiment, the first semiconductor material layer 201 and the second semiconductor material layer 202 are made of materials having different lattice constants and may include one or more layers such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP.
In some embodiments of the present invention, the first semiconductor material layer 201 and the second semiconductor material layer 202 are made of Si, a Si compound, SiGe, Ge, or a Ge compound. In one embodiment, the first semiconductor material layer 201 is Si 1-x Ge x (where x is greater than 0.3) or Ge (x ═ 1) and the second semiconductor material layer 202 is Si or Si 1-y Ge y Wherein y is less than about 0.4 and x<y. In this embodiment, the first semiconductor material layer 201 is Si with 30% of germanium atom concentration 0.7 Ge 0.3 。
Referring to fig. 2, a patterned mask layer 3 is formed on the superlattice structure 2, and the superlattice structure 2 and the substrate 1 are etched by anisotropic dry etching using the mask layer 3 as a mask until the substrate 1 is etched to a certain thickness and a plurality of discrete fin-shaped superlattice structures 2 are formed.
And filling shallow trench isolation structures 4 between the formed discrete fin-shaped superlattice structures 2, wherein the shallow trench isolation structures 4 cover part of the side walls of the substrate 1 below the superlattice structures 2.
In this way, the top of the substrate 1 may be used as a continuation of the superlattice structure 2, which may be of the same material as the second semiconductor material layer 202 of the superlattice structure 2, and constitutes a first layer structure of a subsequently formed second portion 2-2 of the superlattice structure 2. The above method reduces the number of layers of the superlattice structure 2 to be grown, and maximally improves the yield.
Referring to fig. 3, the mask layer 3 is removed, and a first dummy gate oxide layer 5 is formed on the top and the sidewall of the formed superlattice structure 2, where the first dummy gate oxide layer 5 is used to protect the superlattice structure 2 from being affected by an etching process in a subsequent dummy gate 6 etching process. In this embodiment, the material of the first dummy gate oxide layer 5 is silicon dioxide.
And forming a dummy gate 6, wherein the dummy gate 6 crosses the fin part formed by the superlattice structure 2. In this embodiment, the dummy gate is polysilicon, and the forming of the dummy gate specifically includes the following steps: and depositing a polysilicon film, forming a patterned hard mask 7 on the surface of the polysilicon film, and etching the polysilicon film by taking the hard mask 7 as a mask to form a dummy gate 6.
Referring to fig. 4, the superlattice structure 2 not covered by the dummy gate 6 is etched, the sidewall of the superlattice structure 2 located right below the dummy gate 6 is exposed, and the etching step etches not only the superlattice structure 2 but also the substrate 1 located below the superlattice structure 2 until the height of the substrate 1 is lower than that of the shallow trench isolation structures 4, so as to form a groove sandwiched between the shallow trench isolation structures.
With continued reference to fig. 5-18, fig. 5-18 are cross-sectional views of the device taken along the a-a direction in fig. 4 during fabrication.
As shown in fig. 5, after the superlattice structure 2 is etched, the superlattice structure 2 on the top of the substrate 1 includes three first semiconductor material layers 201 and three second semiconductor material layers 202, where the first semiconductor material layer 201 is a germanium-silicon material layer, and the second semiconductor material layer 202 is a silicon material layer. In this embodiment, the lowest layer of the second semiconductor material layer 202 is formed by the silicon material layer on top of the substrate 1, but of course, in other embodiments of the present invention, the constituent parts of the superlattice structure 2 of the lowest layer can also be obtained by performing deposition growth separately.
In order to form stacked p-type and n-type fets in subsequent steps, the upper half (i.e., the first portion 2-1) and the lower half (i.e., the second portion 2-2) of the superlattice structure 2 require different types of channels to be constructed to accommodate different types of fets. Therefore, in the present embodiment, the superlattice structures 2 of the first portion 2-1 and the second portion 2-2 respectively form different types of sandwich structures to obtain different channel types. Specifically, the first portion 2-1 is a sandwich structure of two first semiconductor material layers 201 sandwiching a second semiconductor material layer 202, wherein the sandwiched second semiconductor material layer 202 is used as a conductive channel; the second portion 2-2 is a sandwich structure of two second semiconductor material layers 202 sandwiching a first semiconductor material layer 201, and the first semiconductor material layer 201 is used as a conductive channel.
With continued reference to fig. 6, a first interlayer dielectric layer 8 is deposited, the first interlayer dielectric layer 8 filling the recess sandwiched between the shallow trench isolation structures 4 and covering the sidewalls of the superlattice structure 2 of the second portion 2-2.
Specifically, the first interlayer dielectric layer 8 is formed by the following steps: firstly, depositing a silicon oxide dielectric film, grinding the silicon oxide dielectric film to be in the same plane with the hard mask 7 by adopting a chemical mechanical planarization method, then back etching the silicon oxide dielectric film, reducing the height of the silicon oxide dielectric film until the superlattice structure 2 of the first part 2-1 is completely exposed, stopping the etching step, and forming a first interlayer dielectric layer 8. The formed first interlayer dielectric layer 8 still covers the side wall surfaces of the two sides of the superlattice structure 2 of the second part 2-2, so that the superlattice structure 2 of the second part 2-2 below is not affected when the superlattice structure 2 of the first part 2-1 is subjected to process treatment.
The first interlayer dielectric layer 8 and the second interlayer dielectric layer 14, which will be described later, may be formed by a Fluid Chemical Vapor Deposition (FCVD) process, a High Density Plasma Deposition (HDP) process, a Plasma enhanced Deposition process, and the like, and the material of the interlayer dielectric layer 109 is silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride, a low-k dielectric material (having a dielectric constant greater than or equal to 2.5 and less than 3.9, such as porous silicon oxide or porous silicon nitride), or an ultra-low-k dielectric material (having a dielectric constant less than 2.5, such as porous SiCOH). In this embodiment, a Flow Chemical Vapor Deposition (FCVD) method is used to deposit a silicon dioxide material as an interlayer dielectric layer.
In the step of etching back the silicon oxide dielectric film, the etching thickness needs to be controlled, so that the top plane of the first interlayer dielectric layer 8 formed after etching is basically located at the interface of the first part 2-1 and the second part 2-2, which puts a very high requirement on the control of the etching thickness. In other embodiments of the present invention, the requirement for the etching thickness in the etching back step can be reduced by adjusting the morphology of the superlattice structure 2 during the growth of the superlattice structure 2, so that the layer distance between the second semiconductor material layer 202 sandwiched between the two first semiconductor material layers 201 in the first portion 2-1 and the first semiconductor material layer 201 sandwiched between the two second semiconductor material layers 202 in the second portion 2-2 is greater than the sum of the thicknesses of the two layers. Specifically, the thickness of the first semiconductor material layer 201 at the bottom of the first portion 2-1 or the second semiconductor material layer 202 at the top of the second portion 2-2 may be increased, or the number of stacked layers of the first semiconductor material layer 201 and the second semiconductor material layer 202 may be increased.
Referring to fig. 7, a portion of the superlattice structure 2 of the first portion 2-1, which is subsequently used as a replaced gate structure, that is, the first semiconductor material layer 201 on the periphery of the sandwich structure is laterally etched to form a first lateral groove (not shown in the figure), and a first inner sidewall layer 9 is deposited in the first lateral groove, where on one hand, the first inner sidewall layer 9 is used as a protection structure in a subsequent source-drain selective epitaxy process to ensure that an epitaxial structure grows along a channel sidewall; on the other hand, the first inner sidewall layer 9 can also isolate the gate structure and the source-drain epitaxial structure in the horizontal direction, so as to prevent short circuit or breakdown caused by too close distance between the gate structure and the source-drain epitaxial structure, and reduce the parasitic capacitance of the device. The lateral etching step uses an etching method with high isotropy, such as Selectra atomic layer etching, which has a high selectivity ratio for the first semiconductor material layer 201, i.e., a germanium-silicon material.
After forming the first inner sidewall layer 9 covering the sidewalls of the two first semiconductor material layers 201, forming the outer sidewall layer 10 outside the first inner sidewall layer 9, where the outer sidewall layer 10 covers the hard mask layer 7 and the sidewall surface of the first portion 2-1, so as to protect the structure of the first portion 2-1.
Referring to fig. 8, after the first portion 2-1 is protected by the outer sidewall layer 10, the first interlayer dielectric layer 8 is etched until the sidewall of the second portion 2-2 is exposed. In the subsequent procedure, an inner side wall etching and an epitaxial process are carried out on the surface of the side wall of the second part 2-2 to obtain a source drain structure of the bottom field effect transistor.
Referring to fig. 9, a second interior side wall layer 9' is prepared by the same or similar preparation method as that for the first interior side wall layer 9. In this embodiment, the preparation method of the second inner side wall layer 9' includes the following steps: a certain thickness of the second portion 2-2 is laterally etched, and subsequently the portion for forming the replacement gate structure, i.e. the second semiconductor material layer 202, is formed into a second lateral groove (not shown), and a second inner sidewall layer 9' is deposited in the second lateral groove.
Similarly, the lateral etching step of the second inner sidewall layer 9' is performed by an etching method having high selectivity and isotropy for the second semiconductor material layer 202, i.e., silicon material.
Referring to fig. 10, a second source-drain epitaxial layer 11 is formed, the second source-drain epitaxial layer 11 is obtained by epitaxial growth from the sidewall of the first semiconductor material layer 201 for forming a channel in the second portion 2-2, and the second source-drain epitaxial layer 11 covers the top surface of the first interlayer dielectric layer 8 and the sidewall surface of the second inner sidewall layer 9'.
In this embodiment, the second source-drain epitaxial layer 11 is grown by an in-situ doped source-drain epitaxial process, specifically, by a CVD, ALD or Molecular Beam Epitaxy (MBE) method, and the doped ions are p-type ions, for example, the second source-drain epitaxial layer 11 may be a germanium-silicon material doped with boron.
The larger the volume of the p-type epitaxy is, the higher the compressive stress is generated, and the smaller the volume of the n-type epitaxy is, the better tensile stress effect can be obtained. The lower part is configured into the p-type epitaxy with larger volume, and the upper part is configured into the n-type epitaxy with smaller volume, so that the stability of the stacked three-dimensional structure can be ensured, and meanwhile, the stress effect and the circuit layout can be considered.
Referring to fig. 11, an isolation layer 12 is formed, where the isolation layer 12 covers the second source/drain epitaxial layer 11 and abuts against the outer sidewall layer 10. In this embodiment, the outer sidewall layer 10 and the first inner sidewall layer 9 are made of different materials, and after the isolation layer 12 is manufactured, the outer sidewall layer 10 is removed by an etching method with high selectivity to the outer sidewall layer 10, and the first inner sidewall layer 9 is retained.
Referring to fig. 12, a first source-drain epitaxial layer 13 is continuously formed, where the first source-drain epitaxial layer 13 is obtained by epitaxial growth from a sidewall of the second semiconductor material layer 202 used for forming the channel region in the first portion 2-1, and the first source-drain epitaxial layer 13 covers a portion of the surface of the isolation layer 12.
In this embodiment, the first source-drain epitaxial layer 13 is also manufactured by an in-situ doped source-drain epitaxial process, and may be formed by a CVD, ALD or Molecular Beam Epitaxy (MBE) method, where the doped ions are n-type ions, such as silicon materials doped with phosphorus atoms.
Referring to fig. 13, a second interlayer dielectric layer 14 is formed, where the second interlayer dielectric layer 14 covers the surface of the formed device structure, and includes the surfaces of the second source/drain epitaxial layer 11, the isolation layer 12, the first source/drain epitaxial layer 13, and the hard mask layer 7. In this embodiment, the second interlayer dielectric layer 14 is formed by a fluid chemical vapor deposition method, and is made of silicon dioxide.
Referring to fig. 14, the hard mask layer 7 and the second interlayer dielectric layer 14 are polished by a chemical mechanical planarization method until the first dummy gate oxide layer 5 shown in fig. 3 and 4 is exposed. And etching part of the dummy gate 6 and the first dummy gate oxide layer 5 to expose the first semiconductor material layer 201 and the first inner sidewall layer 9 of the first part 2-1 at the top of the superlattice structure 2.
As shown in fig. 15, the first semiconductor material layer 201 of the first portion 2-1 is etched by using a selective etching method, and after the first semiconductor material layer 201 is removed, the second semiconductor material layer 202 serving as a channel is exposed; covering a second pseudo gate oxide layer 15 on the surface of the second semiconductor material layer 202 for temporarily protecting the second semiconductor material layer 202 used as the channel of the upper field effect transistor.
With continued reference to fig. 16, after the second dummy gate oxide layer 15 is formed, the remaining portions of the dummy gate 6 and the first dummy gate oxide layer 5 are removed by etching, so as to expose the superlattice structure 2 of the second portion 2-2. The second layer of semiconductor material 202, i.e., the layer of silicon material, in the superlattice structure 2 of the second portion 2-2 is removed to expose the layer of first semiconductor material 201 in the second portion 2-2, which serves as a channel.
And then, removing the second pseudo gate oxide layer 15 for temporarily protecting the channel structure of the upper field effect transistor, and simultaneously exposing the second semiconductor material layer 202 of the first channel layer 19-1 serving as the first part 2-1 and the first semiconductor material layer 201 of the second channel layer 19-2 serving as the second part 2-2, and forming a gate oxide layer 16 surrounding the channel on the surfaces of the first channel layer 19-1 and the second channel layer 19-2, wherein in the embodiment, the gate oxide layer 16 is made of a high-k dielectric material and can be, for example, hafnium oxide.
Referring to fig. 17, a metal gate 17 is deposited, where the metal gate 17 at least fills the first semiconductor material layer 201 of the first portion 2-1 and the second semiconductor material layer 202 of the second portion 2-2, and in this embodiment, the material of the metal gate 17 is tungsten. In other embodiments, structures such as a work function adjusting layer and a diffusion barrier layer may be further included.
Referring to fig. 18, in a subsequent process, an interconnection structure of the formed inverter unit is fabricated, where the interconnection structure includes a first power line 18-1 electrically connected to the second source-drain epitaxial layer 11, a second power line 18-2 electrically connected to the first source-drain epitaxial layer 13, a gate input (not shown in the figure) electrically connected to the metal gate 17, and an intra-device interconnection structure 18-3 electrically connecting source-drain electrodes of the two field effect transistors.
Because the volume of the second source-drain epitaxial structure 11 and the projection area occupied along the vertical direction are both larger than the first source-drain epitaxial structure 13, the contact structure electrically connected with the second source-drain epitaxial structure 11 can be manufactured by slotting on the isolation layer 12 which does not cover the first source-drain epitaxial structure 13. Therefore, as shown in fig. 18, the stacked structure can conveniently arrange the contact structures from different horizontal positions and lead out wires, and meanwhile, the gate input is distributed at the bottom of the device, so that middle-stage (MOL) wiring is facilitated, and parasitic resistance is reduced.
In addition, in the preparation process of the method, the grid metals 17 of different field effect transistors of the phase inverter can be directly formed into an integral structure and are electrically connected with each other, the interconnection structure of PMOS and NMOS grids is not required to be prepared, and the production process is simplified.
The present embodiment further provides a CMOS inverter structure, as shown in fig. 18, the CMOS inverter structure includes a p-type horizontal surrounding gate fet and an n-type horizontal surrounding gate fet, and the two fets are stacked in a vertical direction, so that the space occupation of the CMOS inverter structure is greatly reduced.
In addition, the p-type horizontal surrounding gate fet and the n-type horizontal surrounding gate fet share a metal gate 17. By the method of sharing the metal gate 17, the metal gates in the same CMOS inverter unit can be formed into an integral structure without preparing an interconnection structure of PMOS and NMOS gates, and meanwhile, the parasitic resistance is reduced, and the device performance is improved.
So far, the technical solutions of the present invention have been described with reference to the accompanying drawings, but it is obvious to those skilled in the art that the scope of the present invention is not limited to these specific embodiments. Equivalent changes or substitutions of related technical features can be made by those skilled in the art without departing from the principle of the invention, and the technical scheme after the changes or substitutions can fall into the protection scope of the invention.

Claims (12)

1. A method of forming a CMOS inverter structure, the method comprising:
forming a first channel layer and a second channel layer stacked in a vertical direction, the first channel layer being disposed above the second channel layer, the first channel layer and the second channel layer being channels having opposite carrier types;
forming an interlayer dielectric layer which covers the side walls of the first channel layer and the second channel layer;
etching the interlayer dielectric layer to expose the side wall of the first channel layer;
forming an outer sidewall layer at least covering a sidewall of the first channel layer;
continuously etching the interlayer dielectric layer to expose the side wall of the second channel layer;
forming a second source-drain epitaxial layer along the side wall of the second channel layer;
removing the outer side wall layer;
and forming a first source-drain epitaxial layer along the side wall of the first channel layer.
2. The method of forming a CMOS inverter structure according to claim 1, wherein the step of forming the first channel layer and the second channel layer stacked in the vertical direction further comprises:
providing a substrate;
epitaxially growing a superlattice structure formed by alternately arranging first semiconductor material layers and second semiconductor material layers on the substrate, wherein the superlattice structure comprises a first part far away from the substrate and a second part close to the substrate, the first part at least comprises two first semiconductor material layers and a second semiconductor material layer which is sandwiched between the two first semiconductor material layers and is used as a first channel layer, and the second part at least comprises two second semiconductor material layers and a first semiconductor material layer which is sandwiched between the two second semiconductor material layers and is used as a second channel layer.
3. The method of forming a CMOS inverter structure of claim 2,
after the etching the interlayer dielectric layer to expose the side wall of the first channel layer and before forming the outer side wall layer, the method further comprises the following steps: the side walls of the two layers of first semiconductor material layers in the first part are transversely etched to form a first transverse groove, and a first inner side wall layer is formed in the first transverse groove in a deposition mode;
and/or
After the interlayer dielectric layer is continuously etched and the side wall of the second channel layer is exposed, and before a second source-drain epitaxial layer is formed along the side wall of the second channel layer, the method further comprises the following steps: and laterally etching the side walls of the two layers of second semiconductor material layers in the second part to form a second lateral groove, and depositing in the second lateral groove to form a second inner side wall layer.
4. The method for forming a CMOS inverter structure according to claim 2 or 3, wherein a layer spacing between the second semiconductor material layer as the first channel layer and the first semiconductor material layer as the second channel layer in the superlattice structure is larger than a sum of thicknesses of the two layers.
5. The method for forming the CMOS inverter structure according to claim 1 or 2, wherein the first source-drain epitaxial layer and the second source-drain epitaxial layer are formed by an in-situ doped source-drain epitaxial process.
6. The method for forming the CMOS inverter structure of claim 5, wherein the first source drain epitaxial layer is doped n-type and the second source drain epitaxial layer is doped p-type.
7. The method of forming a CMOS inverter structure of claim 2, further comprising, prior to forming the interlevel dielectric layer:
forming a first pseudo gate oxide layer covering the surface of the superlattice structure;
forming a dummy gate across the superlattice structure;
etching the superlattice structure which does not cover the pseudo grid until the substrate is exposed;
after the first source-drain epitaxial layer is formed, the method further comprises the following steps:
etching part of the pseudo gate and the first pseudo gate oxide layer to expose the two first semiconductor material layers of the first part;
etching to remove the two first semiconductor material layers of the first part;
forming a second pseudo gate oxide layer covering the second semiconductor material layer as the first channel layer;
and removing the first pseudo gate oxide layer and the pseudo gate to expose the second part.
8. A CMOS inverter structure comprising a p-type horizontal surrounding gate field effect transistor and an n-type horizontal surrounding gate field effect transistor, wherein the CMOS inverter structure is formed according to the method for forming a CMOS inverter structure as claimed in any one of claims 1 to 7, and the p-type horizontal surrounding gate field effect transistor and the n-type horizontal surrounding gate field effect transistor are stacked in a vertical direction.
9. The CMOS inverter structure of claim 8, wherein the source drain epitaxial layer and the channel layer of the p-type and n-type horizontal surrounding gate fets are stacked in a vertical direction and share a gate structure.
10. The CMOS inverter structure of claim 9, wherein the n-type horizontally surrounding gate fet comprises a first source drain epitaxial layer, the p-type horizontally surrounding gate fet comprises a second source drain epitaxial layer, the n-type horizontally surrounding gate fet is stacked above the p-type horizontally surrounding gate fet, and the volume of the first source drain epitaxial layer is less than the volume of the second source drain epitaxial layer.
11. The CMOS inverter structure of claim 10, wherein an isolation layer covers the second source-drain epitaxial layer, the first source-drain epitaxial layer covers a portion of the surface of the isolation layer, an interconnection structure is disposed at a portion of the isolation layer not covering the first source-drain epitaxial layer, and the interconnection structure is electrically connected to at least the top of the second source-drain epitaxial layer.
12. A semiconductor structure characterized in that it has a CMOS inverter structure according to any one of claims 8 to 11.
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