CN115295548B - Inverter and preparation method thereof - Google Patents
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- CN115295548B CN115295548B CN202211220031.9A CN202211220031A CN115295548B CN 115295548 B CN115295548 B CN 115295548B CN 202211220031 A CN202211220031 A CN 202211220031A CN 115295548 B CN115295548 B CN 115295548B
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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Abstract
The application relates to a phase inverter and a preparation method thereof, wherein the structure comprises: a substrate; a first doped structure including a first drain, a first channel and a first source sequentially stacked on a first surface of the substrate; a second doped structure including a second drain, a second channel and a second source sequentially stacked on the first surface of the substrate; the grid structure is arranged on the first surface of the substrate and is positioned between the first doping structure and the second doping structure; wherein the second drain is of opposite doping type to the first drain, the second channel is of opposite doping type to the first channel, and the second source is of opposite doping type to the first source. By adopting the structure, the area of the wafer can be saved, and the space utilization rate of the device is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor wafer fabrication technologies, and in particular, to an inverter and a fabrication method thereof.
Background
The Complementary Metal Oxide Semiconductor (CMOS) inverter is a Complementary Metal Oxide Semiconductor (CMOS) device formed by a N-type Metal-Oxide-Semiconductor (NMOS) transistor and a P-type Metal-Oxide-Semiconductor (PMOS) transistor operating in a push-pull manner. A CMOS inverter is a device often used in a circuit, and receives an input signal and outputs an output signal logically inverted from the input signal.
The current CMOS inverter is generally of a planar structure, i.e., the gate, drain and source of the MOS transistor are arranged in a direction parallel to the wafer surface. However, such planar CMOS inverters tend to waste wafer area.
Disclosure of Invention
In view of the above, it is desirable to provide an inverter and a method for fabricating the same, which can save the wafer area.
In one aspect, the present invention provides an inverter comprising: a substrate; a first doped structure including a first drain, a first channel and a first source sequentially stacked on a first surface of a substrate; the second doping structure comprises a second drain electrode, a second channel and a second source electrode which are sequentially stacked on the first surface of the substrate; the grid structure is arranged on the first surface of the substrate and is positioned between the first doping structure and the second doping structure; the second drain electrode is opposite to the first drain electrode in doping type, the second channel is opposite to the first channel in doping type, and the second source electrode is opposite to the first source electrode in doping type.
In some embodiments, the gate structure comprises: a polysilicon layer; and the gate oxide layer is positioned between the polycrystalline silicon layer and the first doping structure, between the polycrystalline silicon layer and the second doping structure and between the polycrystalline silicon layer and the substrate.
In some embodiments, the inverter further comprises: the first level connection end is arranged on the first doping structure and is electrically connected with the first source electrode and the first channel; the second level connection end is arranged on the second doping structure and is electrically connected with the second source electrode and the second channel; the input end is arranged on the grid structure and is electrically connected with the polycrystalline silicon layer; and the output end is arranged on the second surface of the substrate and is electrically connected with the first drain electrode and the second drain electrode, and the second surface of the substrate is opposite to the first surface of the substrate.
In some embodiments, the inverter further comprises: the dielectric layers are positioned between the first level connecting end and the first doping structure, between the second level connecting end and the second doping structure and between the input end and the grid structure; the first contact structure penetrates through the dielectric layer and the first source electrode and extends into the first channel; the second contact structure penetrates through the dielectric layer and the second source electrode and extends into the second channel; and the third contact structure penetrates through the dielectric layer and extends into the polycrystalline silicon layer.
In some embodiments, the first contact structure includes a first doped end located within the first channel, the first doped end being of the same doping type as the first channel; the second contact structure comprises a second doping end positioned in the second channel, and the doping type of the second doping end is the same as that of the second channel; the third contact structure comprises a third doping end positioned in the polysilicon layer, the phase inverter comprises two third contact structures, the third doping end of one third contact structure is opposite to the first doping end and has the same doping type, and the third doping end of the other third contact structure is opposite to the second doping end and has the same doping type.
In some embodiments, the substrate includes a first doped silicon layer and a second doped silicon layer stacked in sequence, the second doped silicon layer is doped with the same type as the first doped silicon layer, and the doping concentration of the second doped silicon layer is less than that of the first doped silicon layer.
On the other hand, the invention also provides a preparation method of the inverter, which comprises the following steps: providing a substrate; forming a groove extending into the substrate on the first surface of the substrate; forming a grid structure in the groove; forming a first doped structure on a first side of the gate structure, wherein the first doped structure comprises a first source electrode, a first channel and a first drain electrode which are sequentially stacked along a direction far away from the first surface of the substrate; and forming a second doped structure on the second side of the gate structure, wherein the gate structure is positioned between the first doped structure and the second doped structure, and the second doped structure comprises a second source, a second channel and a second drain which are sequentially stacked along the direction far away from the first surface of the substrate.
In some embodiments, forming a first doped structure on a first side of a gate structure includes: forming a barrier layer on the first surface of the substrate and the gate structure; performing ion implantation on the substrate in the first depth interval at the first side of the grid structure to form a first drain electrode; performing ion implantation on the substrate of a second depth interval on the first side of the gate structure to form a first channel, wherein the maximum depth in the second depth interval is equal to the minimum depth in the first depth interval; and performing ion implantation on the substrate of a third depth interval on the first side of the gate structure to form a first source electrode, wherein the maximum depth in the third depth interval is equal to the minimum depth in the second depth interval.
In some embodiments, forming a second doped structure on a second side of the gate structure includes: performing ion implantation on the substrate in the first depth interval at the second side of the grid structure to form a second drain electrode; performing ion implantation on the substrate in the second depth interval at the second side of the grid structure to form a second channel; performing ion implantation on the substrate in the third depth interval at the second side of the grid structure to form a second source electrode; and removing the barrier layer.
In some embodiments, further comprising the steps of: forming a metal layer on the first doping structure, the second doping structure and the grid structure; patterning the metal layer to form a first level connection end positioned on the first doping structure, a second level connection end positioned on the second doping structure and an input end positioned on the grid structure; the output terminal is formed on a second surface of the substrate, which is opposite to the first surface of the substrate.
According to the phase inverter and the preparation method thereof, the NMOS tube and the PMOS tube share one grid and are positioned on two sides of the shared grid. The source electrode, the channel region and the drain electrode of the NMOS tube and the PMOS tube are respectively and sequentially stacked in a vertical mode. The vertical CMOS inverter improves the utilization density of devices and saves the plane area of a wafer.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Description of reference numerals:
FIG. 1 is a schematic diagram of an inverter according to one embodiment;
FIG. 2 is a schematic diagram of an inverter according to one embodiment;
FIG. 3 is a schematic diagram of an inverter according to one embodiment;
FIG. 4 is a schematic diagram of an inverter according to one embodiment;
FIG. 5 is a schematic diagram of an inverter according to one embodiment;
FIG. 6 is a flow chart of a method of fabricating an inverter according to one embodiment;
FIG. 7 is a schematic sectional view showing a structure obtained in step S601 in the manufacturing method of an inverter according to an embodiment;
FIG. 8 is a schematic sectional view illustrating a structure obtained in step S602 in the method for manufacturing an inverter according to an embodiment;
FIG. 9 is a schematic sectional view illustrating a structure obtained in step S602 in the method for manufacturing an inverter according to an embodiment;
FIG. 10 is a schematic sectional view illustrating a structure obtained in step S602 in the method for manufacturing an inverter according to an embodiment;
FIG. 11 is a schematic sectional view showing a structure obtained in step S603 in the manufacturing method of an inverter according to one embodiment;
FIG. 12 is a schematic sectional view showing a structure obtained in step S603 in the manufacturing method of an inverter according to one embodiment;
FIG. 13 is a schematic sectional view showing the structure obtained in step S604 in the method for manufacturing an inverter according to one embodiment;
FIG. 14 is a schematic sectional view illustrating the structure obtained in step S605 of the method for manufacturing an inverter according to an embodiment;
FIG. 15 is a flowchart of step S604 of a method for manufacturing an inverter according to an embodiment;
fig. 16 is a schematic cross-sectional view of the structure obtained in step S1501 in the method for manufacturing an inverter according to an embodiment;
fig. 17 is a schematic cross-sectional view illustrating a structure obtained in step S1502 in a method for manufacturing an inverter according to an embodiment;
fig. 18 is a schematic cross-sectional view illustrating the structure obtained in step S1503 in the method for manufacturing an inverter according to an embodiment;
FIG. 19 is a schematic sectional view showing a structure obtained in step S1504 in the method for manufacturing an inverter according to an embodiment;
FIG. 20 is a flowchart of step S605 of a method for manufacturing an inverter according to an embodiment;
FIG. 21 is a schematic sectional view showing a structure obtained in step S2001 in a manufacturing method of an inverter in one embodiment;
FIG. 22 is a schematic sectional view showing a structure obtained in step S2002 in the manufacturing method of an inverter according to one embodiment;
FIG. 23 is a schematic sectional view showing a structure obtained in step S2003 in the manufacturing method of an inverter according to one embodiment;
FIG. 24 is a schematic sectional view showing a structure obtained in step S2004 in the manufacturing method of an inverter according to an embodiment;
FIG. 25 is a flow chart of a method of fabricating an inverter according to one embodiment;
fig. 26 is a schematic cross-sectional view of a structure obtained in steps S2501, S2502, and S2503 in the method for manufacturing an inverter according to an embodiment;
FIG. 27 is a flow chart of a method of fabricating an inverter according to one embodiment;
FIG. 28 is a schematic sectional view illustrating the structure obtained in step S2701 of the method for manufacturing an inverter according to one embodiment;
fig. 29 is a schematic cross-sectional view illustrating a structure obtained in step S2702 in the manufacturing method of an inverter according to an embodiment;
FIG. 30 is a schematic sectional view illustrating the structure obtained in step S2702 of the method for manufacturing an inverter according to an embodiment;
fig. 31 is a schematic cross-sectional view of the structure obtained in step S2703 in the method for manufacturing an inverter according to an embodiment.
Description of reference numerals:
110. a substrate, 111, a first surface of the substrate, 112, a second surface of the substrate;
120. a first doping structure 121, a first drain electrode 122, a first channel 123, a first source electrode;
130. a second doping structure 131, a second drain, 132, a second channel, 133, a second source;
140. a grid structure 141, a grid oxide layer 142 and a polycrystalline silicon layer;
310. a first level connection end 320, a second level connection end 330, an input end 340 and an output end;
410. a dielectric layer, 420, a first contact structure, 430, a second contact structure, 440, a third contact structure, 441, a third contact structure, 442, a third contact structure;
510. a first doped silicon layer, 520, a second doped silicon layer;
810. a hard mask layer;
1010. a trench;
1110. a first silicon oxide layer;
1610. a second silicon oxide layer;
2810. a first metal layer;
3010. and (4) a protective layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In the present invention, the "vertical direction" refers to a direction perpendicular to the plane of the wafer substrate, the "horizontal direction" refers to a direction parallel to the plane of the wafer substrate, and the spatial relationship terms such as "under", "below", "under", "above", "over", and the like are spatial positions described in the case where the wafer is disposed upward in the gravity direction.
As described in the background, the current planar CMOS inverter occupies a large planar area of the wafer.
For the above reasons, in one embodiment, as shown in fig. 1, an inverter is provided, comprising a substrate 110, a first doped structure 120, a second doped structure 130, and a gate structure 140. The first doping structure 120 includes a first drain 121, a first channel 122 and a first source 123 sequentially stacked on the first surface 111 of the substrate. The second doping structure 130 includes a second drain 131, a second channel 132, and a second source 133 sequentially stacked on the first surface 111 of the substrate 110. The gate structure 140 is disposed on the first surface 111 of the substrate and between the first doped structure 120 and the second doped structure 130. The second drain 131 is doped opposite to the first drain 121, the second channel 132 is doped opposite to the first channel 122, and the second source 133 is doped opposite to the first source 123.
Specifically, the substrate 110 includes a single crystal silicon layer. The single crystal silicon layer is doped with an N-type dopant or a P-type dopant.
Illustratively, the substrate is an N-type doped single crystal silicon layer. The first doped structure 120 is a PMOS transistor, i.e. the first channel 122 is a P-type doped layer, the first drain 121 is an N-type doped layer, and the first source 123 is an N-type doped layer. The second doped structure 130 is an NMOS transistor, i.e., the second channel 132 is an N-type doped layer, the second drain 131 is a P-type doped layer, and the second source 133 is a P-type doped layer.
In the above embodiment, the first doping structure 120 and the second doping structure 130 are respectively configured on two sides of the gate structure 140, so that the utilization rate of the vertical space of the device is improved, and the consumption of the wafer plane area is reduced.
In one embodiment, as shown in fig. 2, the gate structure includes a polysilicon layer 142 and a gate oxide layer 141. The gate oxide layer 141 is positioned between the polysilicon layer 142 and the first doped structure 120, between the polysilicon layer 142 and the second doped structure 130, and between the polysilicon layer 142 and the substrate 110.
Specifically, the gate oxide layer 141 is a silicon oxide layer, the thickness of the gate oxide layer 141 is 0.001 to 0.1 μm, and the width of the gate oxide layer 141 is 0.5 to 5 μm. The width of the gate oxide layer 141 refers to the length occupied by the gate oxide layer in the substrate horizontal direction. The width of the polysilicon layer 142 is the same as the width of the gate oxide layer 141. The width of the polysilicon layer 142 refers to a length occupied by the polysilicon layer 142 in the substrate horizontal direction. The thickness of the polysilicon layer 142 is 1 to 10 μm.
Illustratively, the gate oxide layer 141 is 0.001 μm thick and 0.5 μm wide. The polysilicon layer 142 has a height of 1 μm and a width of 0.5 μm.
Illustratively, the gate oxide layer 141 is 0.01 μm thick and 1.5 μm wide. The polysilicon layer 142 has a height of 3 μm and a width of 1.5 μm.
Illustratively, the gate oxide layer 141 is 0.05 μm thick and 3 μm wide. The polysilicon layer 142 has a height of 5 μm and a width of 3 μm.
Illustratively, the gate oxide layer 141 is 0.1 μm thick and 5 μm wide. The polysilicon layer 142 has a height of 10 μm and a width of 5 μm.
In one embodiment, as shown in fig. 3, the inverter further comprises a first level connection 310, a second level connection 320, an input terminal 330 and an output terminal 340. The first level connection terminal 310 is disposed on the first doped structure 120 and electrically connected to the first source 123 and the first channel 122. And a second level connection terminal 320 disposed on the second doping structure 130 and electrically connected to the second source 133 and the second channel 132. The input end 330 is disposed on the gate structure 140 and electrically connected to the polysilicon layer 142. And an output terminal 340 disposed on the second surface 300 of the substrate 110 and electrically connected to the first drain electrode 121 and the second drain electrode 131. The second surface 112 of the substrate 110 is opposite to the first surface 111 of the substrate 110.
Specifically, the first level connection end 310, the second level connection end 320 and the input end 330 each include at least two metal layers, such as an aluminum (Al) layer and a copper (Cu) layer, which are sequentially stacked, and the thicknesses of the first level connection end 310, the second level connection end 320 and the input end 330 are all 0.8 to 5 μm. The output end 340 comprises at least two metal layers which are sequentially stacked, such as at least two layers of a titanium (Ti) layer, a nickel (Ni) layer and a silver (Ag) layer, and the thickness of the output end 340 is 1 to 10 micrometers.
Illustratively, the first level connection terminal 310, the second level connection terminal 320 and the input terminal 330 each include an Al layer and a Cu layer stacked in this order, and the first level connection terminal 310, the second level connection terminal 320 and the input terminal 330 each have a thickness of 0.8 μm. The output terminal 340 includes a Ti layer and a Ni layer sequentially stacked, and the thickness of the output terminal 340 is 1 μm.
Illustratively, each of the first level connection terminal 310, the second level connection terminal 320, and the input terminal 330 includes an Al layer and a Cu layer stacked in sequence, and the thickness of each of the first level connection terminal 310, the second level connection terminal 320, and the input terminal 330 is 3 μm. The output terminal 340 includes a Ti layer and an Ag layer sequentially stacked, and the thickness of the output terminal 340 is 5 μm.
Illustratively, each of the first level connection terminal 310, the second level connection terminal 320 and the input terminal 330 includes an Al layer and a Cu layer which are sequentially stacked, and the thickness of each of the first level connection terminal 310, the second level connection terminal 320 and the input terminal 330 is 5 μm. The output terminal 340 includes a Ni layer and an Ag layer sequentially stacked, and the thickness of the output terminal 340 is 10 μm.
In one embodiment, as shown in fig. 4, the inverter further includes a dielectric layer 410, a first contact structure 420, a second contact structure 430, and a third contact structure 440. Dielectric layers 410 are located between the first level connection 310 and the first doped structure 120, between the second level connection 320 and the second doped structure 130, and between the input terminal 330 and the gate structure 140. The first contact structure 420 extends through the dielectric layer 410 and the first source 123 and into the first channel 122. And a second contact structure 430 extending through the dielectric layer 410 and the second source 133 and into the second channel 132. Third contact structure 440 extends through dielectric layer 410 and into polysilicon layer 142.
Specifically, the dielectric layer 410 is composed of multiple components, and the dielectric layer 410 is a key layer for connecting the front-end device and the back-end metal connection line. The first contact structure 420, the second contact structure 430, and the third contact structure 440 include at least one of a Ti layer, a TiN layer, and a W layer. The first level connection terminal 310 is connected to the first contact structure 420. The second level connection terminal 320 is connected to the second contact structure 430. The input end 330 is connected to a third contact structure 440.
Illustratively, the first contact structure 420, the second contact structure 430, and the third contact structure 440 include a Ti layer and a TiN layer, which are sequentially stacked.
Illustratively, the first contact structure 420, the second contact structure 430, and the third contact structure 440 include a Ti layer and a W layer stacked in sequence.
In one embodiment, as shown in fig. 4, the first contact structure 420 includes a first doped end located within the first channel 122, the first doped end being of the same doping type as the first channel 122. The second contact structure 430 includes a second doped end located within the second channel 132, the second doped end being of the same doping type as the second channel. The third contact structure 440 includes a third doped terminal located within the polysilicon layer. The inverter includes two third contact structures, a third doped end of the third contact structure 441 is opposite to the first doped end and has the same doping type, and a third doped end of the third contact structure 442 is opposite to the second doped end and has the same doping type.
Specifically, the first doped end in the first trench 122 is located at the contact end of the first contact structure 420 and the first trench 122, and the doped particles at the first doped end are particles having the same doping type As the first trench 122 and larger mass number, such As boron (B), phosphorus (P), arsenic (As), boron difluoride (BF) 2 ) Or indium (In). A second doped end in the second channel 132 is located at a contact end of the second contact structure 430 and the second channel 132, and the doped particles at the second doped end are particles having the same doping type As the second channel 122 and larger mass number, such As B, P, as, BF 2 Or In, etc. Third connectionContact structure 440 includes at least one pair of third contact structure 441 and third contact structure 442 that are symmetric about a centerline of polysilicon layer 142. Third contact structure 441 is adjacent to first contact structure 420 and third contact structure 442 is adjacent to second contact structure 430. The third doped end of the third contact structure 441 is located at the contact end of the third contact structure 441 and the polysilicon layer 142, and the doping type of the third doped end of the third contact structure 441 is the same as that of the first doped end. The third doped end of the third contact structure 442 is located at the contact end of the third contact structure 442 and the polysilicon layer 142, and the doping type of the third doped end of the third contact structure 442 is the same as the doping type of the second doped end.
Illustratively, the first channel 122 is doped P-type and the second channel 132 is doped N-type. The first doping end is doped In a P type, and In is selected as a doping impurity. The second doping end is doped in an N type, and As is selected As a doping impurity. The third doped end of the third contact structure 441 is P-type doped, and In is selected as a doping impurity. The third doped end of the third contact structure 442 is doped N-type, and As is selected As the doping impurity.
In the above embodiment, the first doping end of the first contact structure 420, the second doping end of the second contact structure 430, and the third doping end of the third contact structure 440 are doped with impurities, so that the contact resistance in the electrical connection process can be reduced, and an effective ohmic contact can be formed.
In one embodiment, as shown in fig. 5, the substrate 110 includes a first doped silicon layer 510 and a second doped silicon layer 520 stacked in sequence, the second doped silicon layer 520 has the same doping type as the first doped silicon layer 510, and the doping concentration of the second doped silicon layer 520 is less than that of the first doped silicon layer 510.
Specifically, the first doped silicon layer 510 is a single crystal silicon layer doped with N-type or P-type dopant, and the second doped silicon layer 520 is a single crystal silicon layer doped with the same dopant type as the first doped silicon layer 510. According to the actual process requirements, when the CMOS inverter requires higher voltage endurance, the second doped silicon layer 520 with N-type light doping can be grown on the first doped silicon layer 510 with N-type heavy doping. The resistivity of the first doped silicon layer 510 is 0.0001 to 0.1 Ω · cm, the thickness of the first doped silicon layer 510 is 500 to 1000 μm, and the diameter of the first doped silicon layer 510 may be 100mm, 150mm, 200mm, 300mm. The resistivity of the second doped silicon layer 520 is 0.01 to 1 Ω · cm, the thickness of the second doped silicon layer 520 is 1 to 30 μm, and the diameter of the second doped silicon layer 520 is consistent with the diameter of the first doped silicon layer 510, and may be 100mm, 150mm, 200mm, or 300mm.
Illustratively, the resistivity of the first doped silicon layer 510 is 0.0001 Ω · cm, the thickness of the first doped silicon layer 510 is 500 μm, and the diameter of the first doped silicon layer 510 is 100mm. The resistivity of the second doped silicon layer 520 is 0.01 Ω · cm, the thickness of the second doped silicon layer 520 is 1 μm, and the diameter of the second doped silicon layer 520 is 100mm.
Illustratively, the resistivity of the first doped silicon layer 510 is 0.001 Ω · cm, the thickness of the first doped silicon layer 510 is 700 μm, and the diameter of the first doped silicon layer 510 is 200mm. The resistivity of the second doped silicon layer 520 is 0.5 Ω · cm, the thickness of the second doped silicon layer 520 is 15 μm, and the diameter of the second doped silicon layer 520 is 200mm.
Illustratively, the resistivity of the first doped silicon layer 510 is 0.1 Ω · cm, the thickness of the first doped silicon layer 510 is 1000 μm, and the diameter of the first doped silicon layer 510 is 300mm. The resistivity of the second doped silicon layer 520 is 1 Ω · cm, the thickness of the second doped silicon layer 520 is 30 μm, and the diameter of the second doped silicon layer 520 is 300mm.
In the above embodiment, when the first doped structure 120 is a PMOS transistor, a high level is inputted to the first level connection terminal 310. In this case, the second doping structure 130 is an NMOS transistor, and a low level is input at the second level connection terminal 320, and an inversion is formed between the input terminal 330 and the output terminal 340. Specifically, when the input of the CMOS inverter is high, that is, when a high is input at the input terminal 330, the output terminal 340 outputs a low. When the input of the CMOS inverter is low, that is, when the input 330 is low, the output 340 outputs high. In addition, a diode may be formed between the substrate 110 and a drain region having a doping type opposite to that of the substrate 110 due to the difference in doping of the base. In practical applications, as long as the high level applied at the input end 330 exceeds the threshold voltage of the diode, the diode is in the forward conducting state, and the operation of the main body CMOS inverter is not affected, so that the operating region of the CMOS inverter is selective.
Based on the same inventive concept, the embodiment of the application also provides a preparation method for realizing the structure. Specific embodiments of the production method of the above structure are given below. The listed parameters are only for reference and should be adjusted during actual operation according to the actual conditions of the equipment to obtain the best results.
In one embodiment, a method for manufacturing an inverter, as shown in fig. 6, includes the steps of:
s601, providing a substrate.
As shown in fig. 7, the substrate 110 includes a first doped silicon layer 510 doped N-type and a second doped silicon layer 520 doped N-type grown by an epitaxial process. The doping concentration of the first doped silicon layer 510 is higher than the doping concentration of the second doped silicon layer 520.
S602, forming a trench extending into the substrate on the first surface of the substrate.
Specifically, step S602 includes: a hard mask layer 810 is grown on the second doped silicon layer 520 by Chemical Vapor Deposition (CVD) or furnace process, as shown in fig. 8; performing a photolithography process, i.e., coating a photoresist, exposing and developing, to expose a specific region of the hard mask layer 810; selecting a specific area of the hard mask layer 810 by a dry etching process, and remaining the hard mask layer 810 at other parts, as shown in fig. 9; etching a trench 1010 in the second doped silicon layer 520 by a dry etching process; all of the hard mask layer 810 is removed by a wet etch process, as shown in fig. 10. The specific region on the hard mask layer 810 refers to a region corresponding to the trench 1010. The depth of the groove 1010 is 1 to 10um, and the width is 0.5 to 5um.
And S603, forming a gate structure in the groove.
Specifically, step S603 includes: a first silicon oxide layer 1110 is grown on the first surface 111 of the substrate and the surface of the trench 1010 by a furnace process. The polysilicon layer 142 is grown in the trench 1010 by a furnace process, and the polysilicon layer 142 can completely fill the trench 1010 and has a certain margin on the upper plane of the trench 1010. As shown in fig. 11, the surface-surplus polysilicon layer 142 is removed through a chemical mechanical polishing or polysilicon etch-back process, which is stopped at the first silicon oxide layer 1110 on the first surface 111 of the substrate. The first silicon oxide layer 1110 and the polysilicon layer 142 on the first surface 111 of the substrate, which are damaged by the chemical mechanical polishing or the polysilicon etch-back process, are removed through a wet etching process, as shown in fig. 12. The silicon oxide layer on the surface of the trench 1010 serves as a gate oxide layer 141, and the gate oxide layer 141 and the polysilicon layer 142 together form a gate structure.
S604, a first doped structure is formed on the first side of the gate structure, and the first doped structure includes a first source, a first channel, and a first drain sequentially stacked along a direction away from the first surface of the substrate.
As shown in fig. 13, the first doped structure 120 sequentially stacks the first drain 121 doped with N type, the first channel 122 doped with P type, and the first source 123 doped with N type.
S605, forming a second doped structure on the second side of the gate structure, where the gate structure is located between the first doped structure and the second doped structure, and the second doped structure includes a second source, a second channel, and a second drain sequentially stacked along a direction away from the first surface of the substrate.
As shown in fig. 14, the second doping structure 130 is sequentially stacked with a P-type doped second drain 131, an N-type doped second channel 132 and a P-type doped second source 133.
In one embodiment, as shown in fig. 15, forming a first doped structure on a first side of a gate structure includes:
s1501, a barrier layer is formed on the first surface of the substrate and the gate structure.
As shown in fig. 16, a second silicon oxide layer 1610 is grown on the first surface 111 of the substrate by a CVD process or a furnace process, and the silicon oxide layer 1610 can serve as an oxide layer at the top corner of the trench 1010 and a barrier layer for subsequent ion implantation. The thickness range of the barrier layer is 0.005 to 0.5 mu m.
S1502, performing ion implantation on the substrate in the first depth interval on the first side of the gate structure to form a first drain.
As shown in fig. 17, an N-type impurity is implanted into the first depth region of the first side of the gate structure 140 by photolithography and ion implantation using a mask to complete N-type doping, thereby forming the first drain 121.
And S1503, performing ion implantation on the substrate of a second depth interval on the first side of the gate structure to form a first channel, wherein the maximum depth in the second depth interval is equal to the minimum depth in the first depth interval.
As shown in fig. 18, a first trench 122 is formed by implanting P-type impurities into the second depth region of the first side of the gate structure through photolithography and ion implantation processes using the same photomask to complete P-type doping. The maximum depth of the second depth interval is equal to the minimum depth of the first depth interval.
S1504, performing ion implantation on the substrate of a third depth interval on the first side of the gate structure to form a first source electrode, wherein the maximum depth in the third depth interval is equal to the minimum depth in the second depth interval.
As shown in fig. 19, an N-type impurity is implanted into the third depth interval of the first side of the gate structure 140 by photolithography and ion implantation processes using the same photomask to complete N-type doping, thereby forming the first source 123. The range of the implantation region in the photomask is adjusted according to the electrical requirements, and all or half of the polysilicon layer can be selectively included in the implantation region. The doping concentration of the first doping structure is adjusted according to the electrical requirements of the device.
In one embodiment, as shown in fig. 20, forming a second doped structure on the second side of the gate structure comprises the steps of:
s2001, ion implantation is performed on the substrate of the first depth section on the second side of the gate structure to form a second drain.
As shown in fig. 21, another photo mask is used to implant P-type impurities into the first depth region on the second side of the gate structure 140 through photolithography and ion implantation processes, so as to complete P-type doping, thereby forming the second drain 131.
S2002, performing ion implantation on the substrate in the second depth interval on the second side of the gate structure to form a second channel.
As shown in fig. 22, using the same mask, through photolithography and ion implantation processes, N-type impurities are implanted into the second depth region of the first side of the gate structure to complete N-type doping, so as to form a second trench 132. The maximum depth of the second depth interval is equal to the minimum depth of the first depth interval.
And S2003, performing ion implantation on the substrate in the third depth interval on the second side of the gate structure to form a second source electrode.
As shown in fig. 23, a P-type impurity is implanted into the third depth interval of the first side of the gate structure by photolithography and ion implantation processes using the same photomask to complete P-type doping, thereby forming a second source 133. The range of the implantation region in the photomask is adjusted according to the electrical requirements, and all or half of the polysilicon layer can be selectively included in the implantation region. The doping concentration of the second doping structure is adjusted according to the electrical requirement of the device.
And S2004, removing the barrier layer.
As shown in fig. 24, the barrier layer, i.e., the second silicon oxide layer 1610, which is lost by the ion implantation step is completely removed by a wet etching process. Wet etching is the removal of a portion of a wafer not covered by photoresist by first decomposing the wafer using a suitable chemical reagent and then converting the wafer into a soluble compound.
In one embodiment, as shown in fig. 25, the method further comprises the steps of:
s2501, growing a dielectric layer on the first surface of the substrate through a CVD process.
The dielectric layer 410 is a multi-step, multi-component composition.
S2502, forming a first contact hole in the dielectric layer and the first doping structure, forming a second contact hole in the dielectric layer and the second doping structure, and forming a third contact hole in the dielectric layer and the grid structure through photoetching and etching processes.
S2503, a first contact structure is formed in the first contact hole, a second contact structure is formed in the second contact hole, and a third contact structure is formed in the third contact hole.
As shown in fig. 26, doping impurities of corresponding types are implanted into the first doping terminal of the first contact structure 420, the second doping terminal of the second contact structure 430 and the third doping terminal of the third contact structure 440. Under special circumstances, the whole doping process can be directly performed without selectively shielding the dielectric layer 410 to expose the implantation region, and at this time, the doping amount needs to be strictly controlled to avoid affecting the dielectric property of the dielectric layer 410.
Specifically, ti, titanium nitride (TiN), or tungsten (W) is filled into the first contact hole, the second contact hole, and the third contact hole through a CVD or ion implantation process, and the Ti, tiN, or W on the upper surface of the dielectric layer 410 is removed through a chemical mechanical polishing or etching back process to form a first contact structure, a second contact structure, and a third contact structure.
In one embodiment, as shown in fig. 27, the method further comprises the steps of:
s2701, a metal layer is formed on the first doping structure, the second doping structure and the gate structure.
As shown in fig. 28, a first metal layer 2810 is sputtered on the upper surface of the dielectric layer 410 by a physical vapor deposition process. The first metal layer 2810 may include an Al layer or a Cu layer stacked in sequence, and has a thickness of 0.8 to 5 μm.
S2702, the metal layer is patterned to form a first level connection end on the first doped structure, a second level connection end on the second doped structure, and an input end on the gate structure.
As shown in fig. 29, a patterning process is performed on the surface of the first metal layer 2810 through a photolithography and etching process, that is, the metal layers in the regions corresponding to the first level connection terminal 310, the second level connection terminal 320 and the input terminal 330 are retained, and the other portions of the first metal layer 2810 are removed. The first level connection 310 is connected to the first contact structure 420, the second level connection 320 is connected to the second contact structure 430, and the input terminal 330 is connected to the third contact structure 440.
Further, as shown in fig. 30, a passivation layer 3010 is grown on the surface of the dielectric layer 410 by a CVD process, and the thickness of the passivation layer 3010 is greater than that of the first metal layer 2810. Through the photolithography and etching processes, regions related to the subsequent packaging process and the like are removed on the surface of the protective layer 3010, and a portion of the protective layer 3010 on the surfaces of the first level connection terminal 310, the second level connection terminal 320 and the input terminal 330 is exposed.
S2703, forming an output terminal on a second surface of the substrate, the second surface of the substrate being opposite to the first surface of the substrate.
As shown in fig. 31, the second surface 112 of the substrate is subjected to a back process by grinding and wet etching processes, so as to thin the substrate to a desired thickness, wherein the thickness is in a range of 30 to 300 μm. A second metal layer is sputtered on the second surface 112 of the substrate by a physical vapor deposition process, and the second metal layer can be used as an output 340 of the device. The metal layer can be Ti, ni or Ag, and the thickness can be 1 to 10 mu m.
It should be understood that, although the steps in the flowcharts related to the embodiments as described above are sequentially displayed as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims (8)
1. An inverter, characterized in that the inverter comprises:
a substrate;
a first doped structure including a first drain, a first channel and a first source sequentially stacked on a first surface of the substrate;
a second doped structure including a second drain, a second channel and a second source sequentially stacked on the first surface of the substrate;
the grid structure is arranged on the first surface of the substrate and is positioned between the first doping structure and the second doping structure; the gate structure includes: a polysilicon layer; a gate oxide layer between the polysilicon layer and the first doped structure, between the polysilicon layer and the second doped structure, and between the polysilicon layer and the substrate;
wherein the second drain is of opposite doping type to the first drain, the second channel is of opposite doping type to the first channel, and the second source is of opposite doping type to the first source,
a first level connection terminal disposed on the first doped structure and electrically connected to the first source and the first channel;
a second level connection terminal disposed on the second doped structure and electrically connected to the second source and the second channel;
the input end is arranged on the grid structure and is electrically connected with the polycrystalline silicon layer;
and the output end is arranged on the second surface of the substrate and is electrically connected with the first drain electrode and the second drain electrode, and the second surface of the substrate is opposite to the first surface of the substrate.
2. The inverter of claim 1, further comprising:
dielectric layers located between the first level connection end and the first doped structure, between the second level connection end and the second doped structure, and between the input end and the gate structure;
the first contact structure penetrates through the dielectric layer and the first source electrode and extends into the first channel;
the second contact structure penetrates through the dielectric layer and the second source electrode and extends into the second channel;
and the third contact structure penetrates through the dielectric layer and extends into the polycrystalline silicon layer.
3. The inverter of claim 2, wherein the first contact structure comprises a first doped terminal located within the first channel, the first doped terminal being of the same doping type as the first channel;
the second contact structure comprises a second doped end positioned in the second channel, and the second doped end is the same as the second channel doping type;
the third contact structure comprises a third doping end positioned in the polysilicon layer, the phase inverter comprises two third contact structures, the third doping end of one third contact structure is opposite to the first doping end and has the same doping type, and the third doping end of the other third contact structure is opposite to the second doping end and has the same doping type.
4. The inverter according to any one of claims 1 to 3, wherein the substrate comprises a first doped silicon layer and a second doped silicon layer stacked in this order, the second doped silicon layer is doped with the same type as the first doped silicon layer, and the doping concentration of the second doped silicon layer is smaller than that of the first doped silicon layer.
5. A method for manufacturing an inverter, the method comprising:
providing a substrate;
forming a groove extending into the substrate on the first surface of the substrate;
forming a grid structure in the groove;
forming a first doped structure on a first side of the gate structure, wherein the first doped structure comprises a first source electrode, a first channel and a first drain electrode which are sequentially stacked along a direction far away from the first surface of the substrate;
and forming a second doped structure on the second side of the gate structure, wherein the gate structure is positioned between the first doped structure and the second doped structure, and the second doped structure comprises a second source electrode, a second channel and a second drain electrode which are sequentially stacked along the direction far away from the first surface of the substrate.
6. The method of claim 5, wherein forming a first doped structure on a first side of the gate structure comprises:
forming a barrier layer on the first surface of the substrate and the gate structure;
performing ion implantation on the substrate in the first depth interval at the first side of the gate structure to form the first drain electrode;
performing ion implantation on the substrate of a second depth interval on the first side of the gate structure to form the first channel, wherein the maximum depth in the second depth interval is equal to the minimum depth in the first depth interval;
and performing ion implantation on the substrate of a third depth interval on the first side of the gate structure to form the first source electrode, wherein the maximum depth in the third depth interval is equal to the minimum depth in the second depth interval.
7. The method of claim 6, wherein forming a second doped structure on a second side of the gate structure comprises:
performing ion implantation on the substrate of the first depth interval at the second side of the gate structure to form the second drain electrode;
performing ion implantation on the substrate of the second depth interval at the second side of the gate structure to form the second channel;
performing ion implantation on the substrate of the third depth interval at the second side of the gate structure to form the second source electrode;
and removing the barrier layer.
8. The method of any one of claims 5-7, further comprising:
forming a metal layer on the first doped structure, the second doped structure and the gate structure;
patterning the metal layer to form a first level connection end positioned on the first doping structure, a second level connection end positioned on the second doping structure and an input end positioned on the grid structure;
forming an output on a second surface of the substrate, the second surface of the substrate being opposite the first surface of the substrate.
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