CN101958328A - CMOS (Complementary Metal Oxide Semiconductor) device and manufacturing method thereof - Google Patents
CMOS (Complementary Metal Oxide Semiconductor) device and manufacturing method thereof Download PDFInfo
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- CN101958328A CN101958328A CN200910054961XA CN200910054961A CN101958328A CN 101958328 A CN101958328 A CN 101958328A CN 200910054961X A CN200910054961X A CN 200910054961XA CN 200910054961 A CN200910054961 A CN 200910054961A CN 101958328 A CN101958328 A CN 101958328A
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Abstract
The invention relates to a CMOS (Complementary Metal Oxide Semiconductor) device and a manufacturing method thereof. The CMOS device comprises a silicon substrate, as well as a first buried oxide layer, first top layer silicon, a second buried oxide layer and second top layer silicon which are arranged on the silicon substrate in sequence, wherein the first top layer silicon and the second top layer silicon are different in 3.3 crystallographic orientation; a first field effect transistor is formed on the first top layer silicon used as a substrate, a second field effect transistor is formed on the second top layer silicon used as a substrate and is aligned to the first field effect transistor, and the conduction types of the first field effect transistor and the second field effect transistor are different. In the provided CMOS device, the crystallographic orientations of substrates of conducting channels formed by NMOS (N-Channel Metal Oxide Semiconductor) transistors and PMOS (P-Channel Metal Oxide Semiconductor) transistors are respectively (100) and (110), so that the mobility of respective current carrier is increased, and the response speed of the CMOS device is increased. The problem of current leakage of the substrates is solved by insulating the substrate of each transistor through stacking the transistors and using multiple buried oxide layers.
Description
Technical field
The present invention relates to semiconductor CMOS technology, relate in particular to a kind of cmos device and manufacture method thereof.
Background technology
CMOS (Complementary Metal Oxide Semiconductor) (CMOS:Complementary Metal Oxide Semiconductor) device is the basis of modern semiconductors integrated circuit technique, forms the elementary cell of digital integrated circuit.Cmos device is the transistorized a kind of organic assembling of nmos pass transistor and PMOS, constitutes logical device, when its advantage is only logic state transition to be arranged, just can produce big electric current, and under stable logic state, have only minimum electric current to pass through, therefore can significantly reduce the power consumption of logical circuit.
As shown in Figure 1, be the structure of existing a kind of typical C MOS device (inverter), comprise the nmos pass transistor M1 and the PMOS transistor M2 of series connection, an end ground connection, another termination power Vdd.Nmos pass transistor M1 links to each other as input Vin with the grid of M2 in the PMOS transistor, the source is leaked and is linked to each other as output end vo ut, described nmos pass transistor M1 has opposite threshold voltage with PMOS transistor M2, when input Vin input low level, PMOS transistor M2 conducting, nmos pass transistor M1 ends, and output voltage V out is considered as exporting high level near Vdd; When input Vin input high level, nmos pass transistor M1 conducting, PMOS transistor M2 ends, and output voltage V out is 0V with approaching, is considered as output low level.
As everyone knows, at room temperature in the silicon carrier mobility difference of hole and electronics bigger.Therefore use the hole always will be far below nmos pass transistor as the speed of carrier mobility in the PMOS transistor of main charge carrier, the PMOS transistor becomes the greatest factor that influences the cmos device response speed, and the carrier mobility that how to improve in the cmos device becomes urgent problem.
IBM has proposed a kind of method that adopts mixed substrates to improve the cmos device response speed international semiconductor electronic device seminar (International Electron Devices Meeting) in 2003, as shown in Figure 2, nmos pass transistor M1 is formed on the top layer silicon 3 of silicon-on-insulator 10 in cmos device, wherein top layer silicon 3 is＜100〉crystal orientation, PMOS transistor M2 then directly is formed at＜110〉crystal orientation bottom silicon 1 on, be formed with isolating oxide layer 4 between nmos pass transistor M1 and the PMOS transistor M2.＜100〉in the silicon materials in crystal orientation, the carrier mobility maximum of electronics, and＜110〉in the silicon materials in crystal orientation, the carrier mobility maximum in hole.Therefore adopt the substrate that mixes, make that nmos pass transistor M1 and PMOS transistor M2 form conducting channel respectively in the substrate silicon of different crystal orientations in the cmos device, increase mobility of charge carrier rate separately, can improve the performance of cmos device effectively.Yet there are the following problems for this technology: the bottom of nmos pass transistor is formed with oxygen buried layer 2, can effectively eliminate substrate leakage current, and PMOS is owing to directly be formed at bottom silicon 1 surface, and its bottom leakage current will be very serious, and influence the performance of CMOS.
Summary of the invention
The problem that the present invention solves provides a kind of cmos device and manufacture method thereof, and is compatible mutually with existing C MOS technology, has higher carrier mobility, thereby obtains response speed faster.
For addressing the above problem, the invention provides a kind of cmos device, comprising:
Silicon base is positioned at first oxygen buried layer, first top layer silicon and second oxygen buried layer, second top layer silicon on the silicon base successively;
The crystal orientation of described first top layer silicon and second top layer silicon is inequality;
With first top layer silicon is first field-effect transistor that substrate forms;
With second top layer silicon is second field-effect transistor that substrate forms and aims at first field-effect transistor; Described first field-effect transistor is different with the conduction type of second field-effect transistor, and series connection mutually.
As possibility, described first field-effect transistor comprises first source electrode, first drain electrode that is positioned at first top layer silicon and isolates mutually, and first channel body that connects first source electrode, first drain electrode, the described first channel body surface is formed with first grid dielectric layer, and first grid dielectric layer surface is formed with gate electrode; Second field-effect transistor comprises second source electrode, second drain electrode that is positioned at second top layer silicon and isolates mutually, and second channel body that connects second source electrode, second drain electrode, the described second channel body surface is formed with second gate dielectric layer, and the second gate dielectric layer surface is formed with gate electrode; Wherein first channel body and second channel body are cylindrical.
As possibility, described first field-effect transistor and second field-effect transistor be gate electrode altogether, and gate electrode forms and coat the surface of the first grid dielectric layer and second gate dielectric layer; The side of gate electrode also is formed with insulative sidewall.
As possibility, described first top layer silicon is＜100〉crystal orientation, and first field-effect transistor is a nmos pass transistor; Described second top layer silicon is＜110〉crystal orientation, and second field-effect transistor is the PMOS transistor.As another possibility, described first top layer silicon is＜110〉crystal orientation, and first field-effect transistor is the PMOS transistor; Described second top layer silicon is＜100〉crystal orientation, and second field-effect transistor is a nmos pass transistor.
The present invention also provides a kind of manufacture method of cmos device, comprising:
Silicon base is provided, on silicon base, forms first oxygen buried layer, first top layer silicon and second oxygen buried layer, second top layer silicon successively;
Described first top layer silicon is different with the crystal orientation of second top layer silicon, and doping type is opposite;
With first top layer silicon is substrate, forms first field-effect transistor, is substrate with second top layer silicon, forms second field-effect transistor;
Described second field-effect transistor is aimed at first field-effect transistor, and the conduction type difference;
Carry out rear end silication insulating process, lead to the interconnection line in source region.
As possibility, wherein said formation first field-effect transistor and second field-effect transistor specifically comprise:
Second top layer silicon, second oxygen buried layer and first top layer silicon, first oxygen buried layer beyond the etching presumptive area successively is until first oxygen buried layer that exposes first top layer silicon bottom on the presumptive area from the side;
First oxygen buried layer on the described presumptive area of side direction etching and second oxygen buried layer make on the win top layer silicon and second top layer silicon and form the first unsettled channel body and second channel body respectively, and described first channel body are aimed at second channel body;
With described first channel body and the second channel body cylinderization;
Form first grid dielectric layer, second gate dielectric layer respectively in first channel body and the second channel body surface;
Surface at first grid dielectric layer, second gate dielectric layer forms gate electrode;
In first top layer silicon of the first channel body both sides, form first source electrode and first drain electrode, in second top layer silicon of the second channel body both sides, form second source electrode and second drain electrode.
As possibility, described first top layer silicon is＜100〉crystal orientation, and doping type is the P type, and second top layer silicon is＜110〉crystal orientation, and doping type is the N type; As another possibility, described first top layer silicon is＜110〉crystal orientation, and doping type is the N type, and second top layer silicon is＜100〉crystal orientation, and doping type is the P type.
As possibility, described with first channel body and the second channel body cylinderization, specifically comprise:
First channel body and second channel body are carried out high-temperature thermal oxidation;
First channel body and second channel body are carried out short annealing.
As preferred version, the temperature of described high-temperature thermal oxidation is 900～1200 degrees centigrade, and the time is 30～120 minutes.
As possibility, the described first grid dielectric layer and second gate dielectric layer can be silica or high dielectric constant material, adopt thermal oxidation, chemical vapour deposition (CVD) CVD or atomic deposition ALD to form; Described gate electrode is polysilicon or metal gate electrode, adopts chemical vapour deposition (CVD) CVD or atomic deposition ALD to form.
As possibility, described formation first source electrode, first drains and forms second source electrode, second drain electrode, specifically comprises:
In first top layer silicon of the first channel body both sides and in second top layer silicon of the second channel body both sides, carry out reverse ion respectively and inject the shallow doping of formation injection region;
Side at gate electrode forms insulative sidewall;
In the shallow doping injection region of the shallow doping injection region of the first channel body both sides and the second channel body both sides, mix deeply respectively, form described first source electrode, first drain electrode and second source electrode, second drain electrode.
As possibility, before leading to the interconnection line in source region, described second source electrode of etching, second drain electrode and second oxygen buried layer expose first source electrode and first top that drains.
In the cmos device provided by the present invention, the substrate crystal orientation that nmos pass transistor and PMOS transistor form conducting channel is respectively＜and 100〉and＜110, help improving mobility of charge carrier rate separately, further improve the response speed of cmos device, and, solve the substrate leakage flow problem by transistor stack being aided with the multilayer oxygen buried layer to each transistor substrate insulation.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose of the present invention, feature and advantage will be more clear.Parts same as the prior art have used identical Reference numeral in the accompanying drawing.Accompanying drawing and not drawn on scale focus on illustrating purport of the present invention.In the accompanying drawings for clarity sake, amplified the size in layer and zone.
Fig. 1 is the circuit diagram of existing C MOS device (inverter);
Fig. 2 is the sectional structure chart of existing a kind of compound substrate cmos device;
Fig. 3 is the sectional structure chart of cmos device of the present invention;
Fig. 4 is the generalized section of cmos device of the present invention along A-A ' cross section among Fig. 3;
Fig. 5 is the schematic equivalent circuit of cmos device of the present invention;
Fig. 6 a and Fig. 6 b are the manufacture method flow chart of cmos device of the present invention;
Fig. 7 to Figure 20 is the generalized section of cmos device manufacture method specific embodiment of the present invention.
Fig. 9 a, Figure 10 a, Figure 11 a, Figure 12 a, Figure 13 a, Figure 14 a and Figure 15 a are respectively among Fig. 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14 and Figure 15 the generalized section along B-B ' shown in Figure 9 cross section.
Embodiment
Existing compound substrate cmos device, owing to always have a transistor directly to be formed on the silicon base, and be easy to generate the leakage current of substrate, cmos device of the present invention is by piling up transistor on silicon-on-insulator, and the top layer silicon conduct substrate of transistor formation conducting channel separately of using different crystal orientations and level, be aided with the multilayer oxygen buried layer substrate is insulated, solve above-mentioned leakage problem.
As shown in Figure 3, be the sectional structure chart of cmos device of the present invention, Fig. 4 is the generalized section along A-A ' cross section among Fig. 3, and in conjunction with Fig. 3 and Fig. 4, cmos device of the present invention specifically comprises:
Wherein, the crystal orientation of first top layer silicon 102 and second top layer silicon 202 is inequality, can select according to concrete needs, selects for use usually＜100〉crystal orientation be beneficial to the migration of electronics or select for use＜110〉crystal orientation be beneficial to the migration in hole;
Be formed at the first field-effect transistor N1 on first top layer silicon 102; Be formed on second top layer silicon 202 and the second field-effect transistor N2 that aims at the first field-effect transistor N1;
Wherein, the first field-effect transistor N1 connects mutually with the second field-effect transistor N2, and according to the crystal orientation of first top layer silicon 102 and second top layer silicon 202, the first field-effect transistor N1 is corresponding with it to improve corresponding mobility of charge carrier rate with the conduction type of the second field-effect transistor N2; When top layer silicon was＜100〉crystal orientation, the field-effect transistor on this top layer silicon was NMOS, and when top layer silicon was＜110〉crystal orientation, then the field-effect transistor on this top layer silicon was PMOS.
The described first field-effect transistor N1 comprises that being positioned at first top layer silicon, 102 mutual first source electrodes 11, first of isolating drains 12, and first channel body 13 that connects first source electrode 11, first drain electrode 12; The second field-effect transistor N2 comprises that being positioned at second top layer silicon, 202 mutual second source electrodes 21, second of isolating drains 22, and second channel body 23 that connects second source electrode 21, second drain electrode 22; Described first channel body 13 and second channel body 23 are cylindrical.
Be formed with first grid dielectric layer 14, second gate dielectric layer 24 respectively on the surface of first channel body 13 and second channel body 23; The described first field-effect transistor N1 and the second field-effect transistor N2 common gate electrode 5.With reference to shown in Figure 4, described gate electrode 5 forms and coats the surface of the first grid dielectric layer 14 and second gate dielectric layer 24; The side of gate electrode 5 also is formed with insulative sidewall 6, owing to the section angle limitations, the part of insulative sidewall 6 only is shown among Fig. 3, and described insulative sidewall 6 also should be formed at the whole lateral surface of gate electrode 5.
Operation principle to cmos device of the present invention is described further below.
For ease of explanation, suppose among Fig. 3 and Fig. 4 that described first top layer silicon 102 is＜100〉crystal orientation, the first field-effect transistor N1 is a nmos pass transistor; Described second top layer silicon 202 is＜110〉crystal orientation, and the second field-effect transistor N2 is the PMOS transistor; Two field-effect transistors have opposite threshold voltage.
Now with first source electrode, 11 ground connection, second source electrode 21 meets forward voltage Vdd, and first drain electrode 12 is connected as output end vo ut with second drain electrode 22, and gate electrode 5 connects input Vin, and then the equivalent circuit diagram of cmos device of the present invention as shown in Figure 5.
As input Vin during to gate electrode 5 input low levels (described low level negative sense surpasses the threshold voltage of the second field-effect transistor N2), the second field-effect transistor N2 conducting, the first field-effect transistor N1 ends, and output voltage V out equals forward voltage Vdd, is considered as exporting high level; As input Vin during to gate electrode 5 input high levels (described high level forward surpasses the threshold voltage of the first field-effect transistor N1)), the first field-effect transistor N1 conducting, the second field-effect transistor N2 ends, and output voltage V out is 0V with equaling, is considered as output low level.
From above-mentioned analysis as can be known, cmos device of the present invention can be realized the logic function of existing C MOS inverter equally; First top layer silicon 102 and second top layer silicon 202 are used different crystal orientations, and the conduction type of corresponding respective fields effect transistor improves transistorized carrier mobility speed; Be formed with first oxygen buried layer 101 and second oxygen buried layer 201 on the other hand in the bottom of first top layer silicon 102 and second top layer silicon 202 respectively,, avoided leakage problem as the dielectric base of respective fields effect transistor; Further with the first field-effect transistor N1 and the second field-effect transistor N2 common gate electrode 5, and coat channel body separately, simplify stacked structure, be easy to produce and realize.
Based on above-mentioned cmos device structure, the present invention also provides a kind of manufacture method of cmos device, and shown in Fig. 6 a, described manufacture method basic procedure comprises:
S1, provide silicon base, form first oxygen buried layer, first top layer silicon and second oxygen buried layer, second top layer silicon successively on silicon base, described first top layer silicon is different with the crystal orientation of second top layer silicon, and doping type is opposite;
As possibility, described first top layer silicon is＜100〉crystal orientation, and doping type is the P type, and second top layer silicon is＜110〉crystal orientation, and doping type is the N type; As another possibility, described first top layer silicon is＜110〉crystal orientation, and doping type is the N type, and second top layer silicon is＜100〉crystal orientation, and doping type is the P type.
S2, being substrate with first top layer silicon, forming first field-effect transistor, is substrate with second top layer silicon, forms second field-effect transistor; Described second field-effect transistor is aimed at first field-effect transistor, and the conduction type difference.
S3, carry out rear end silication insulating process, lead to the interconnection line in source region.
Shown in Fig. 6 b, form first field-effect transistor and second field-effect transistor described in the S2 step, specifically comprise:
S21, second top layer silicon, second oxygen buried layer and first top layer silicon, first oxygen buried layer beyond the etching presumptive area successively are until first oxygen buried layer that exposes first top layer silicon bottom on the presumptive area from the side.
First oxygen buried layer and second oxygen buried layer on S22, the described presumptive area of side direction etching make on the win top layer silicon and second top layer silicon and form the first unsettled channel body and second channel body respectively, and described first channel body are aimed at second channel body.
As possibility; described side direction etching can be blocked other zones of protection with mask; adopt selectivity wet etching part first oxygen buried layer and second oxygen buried layer; because first oxygen buried layer and the second oxygen buried layer thickness of side direction are the thinnest; so can form two perforation of aiming at up and down quickly in side direction; described perforation top is by the first unsettled top layer silicon and the second top layer silicon part, respectively as first channel body and second channel body.Preferably, second oxygen buried layer between first channel body and second channel body is by etching removal fully.
S23, with described first channel body and the second channel body cylinderization; Specifically comprise:
First channel body and second channel body are carried out high-temperature thermal oxidation;
First channel body and second channel body are carried out short annealing.
S24, form first grid dielectric layer, second gate dielectric layer respectively in first channel body and the second channel body surface;
S25, form gate electrode on the surface of first grid dielectric layer, second gate dielectric layer;
As preferred version, when described gate electrode is also filled aforementioned side direction etching, the remaining space of the perforation that between first channel body, second channel body and first oxygen buried layer, forms.
S26, formation first source electrode and first drain electrode in first top layer silicon of the first channel body both sides form second source electrode and second drain electrode in second top layer silicon of the second channel body both sides; Specifically comprise:
In first top layer silicon of the first channel body both sides and in second top layer silicon of the second channel body both sides, carry out reverse ion respectively and inject the shallow doping of formation injection region;
Side at gate electrode forms insulative sidewall;
In the shallow doping injection region of the shallow doping injection region of the first channel body both sides and the second channel body both sides, mix deeply respectively, form described first source electrode, first drain electrode and second source electrode, second drain electrode.
Before leading to the interconnection line in source region in this external described S3 step, can drain and second oxygen buried layer by described second source electrode of first etching, second, expose the top of first source electrode and first drain electrode,, make interconnection line so that form vertical contact hole.
Below in conjunction with the generalized section of Fig. 7 to Figure 21, a specific embodiment of cmos device manufacture method of the present invention is described.
At first as shown in Figure 7, provide silicon base 100, on silicon base 100, form first oxygen buried layer 101 and first top layer silicon 102 successively.The material of described first oxygen buried layer 101 can be silica, forms by chemical vapour deposition (CVD) CVD, and thickness range is 10～200nm; The material of described first top layer silicon 102 can be monocrystalline silicon, and the crystal orientation can be＜100〉or＜110, can form by chemical vapour deposition (CVD) CVD, thickness range is 10-100nm; Then first top layer silicon 102 is carried out plasma doping, doping type is selected according to the crystal orientation, if first top layer silicon, 102 crystal orientation are for＜100〉then doping type be the P type, if the crystal orientation is＜110〉then doping type be the N type.In the present embodiment, the crystal orientation of described first top layer silicon 102 is＜100 〉, doping type is the P type.
As shown in Figure 8, form second oxygen buried layer 201 and second top layer silicon 202 successively on the surface of first top layer silicon 102.The material of described second oxygen buried layer 201 can be silica, forms by chemical vapour deposition (CVD) CVD, and thickness range is 10～200nm; The material of described second top layer silicon 202 can be monocrystalline silicon, and the crystal orientation can be＜100〉or＜110, but inequality with first top layer silicon 102, can form by chemical vapour deposition (CVD) CVD, thickness range is 10-100nm; Then second top layer silicon 202 is carried out plasma doping, doping type is opposite with first top layer silicon 102.In the present embodiment, the crystal orientation of described second top layer silicon 202 is＜110 〉, doping type is the N type.
Shown in Fig. 9 and Fig. 9 a, pre-determine the zone that forms cmos device, second top layer silicon 202, second oxygen buried layer 201 and first top layer silicon 102, first oxygen buried layer 101 beyond the etching presumptive area successively is until first oxygen buried layer 101 that exposes first top layer silicon, 102 bottoms on the presumptive area from the side.
Wherein Fig. 9 a is the generalized section along B-B ' cross section among Fig. 9, and to have the accompanying drawing of a suffix be generalized section, explanation hereby with this cross section all to label in the aftermentioned content.
Shown in Figure 10 and Figure 10 a, described first oxygen buried layer 101 of side direction etching and second oxygen buried layer 201, make on the win top layer silicon 102 and second top layer silicon 202 and all form unsettled part, respectively as first channel body 13 and second channel body 23, and described first channel body 13 is aimed at second channel body 23.
Described side direction etching adopts the selectivity wet etching; can block other zones of protection with mask; from Fig. 9 a as can be known; described first oxygen buried layer 101 and second oxygen buried layer 201 are the thinnest at the thickness of side direction; so can form perforation quickly, and the oxygen buried layer of other parts can't be subjected to very big influence.In the present embodiment, first oxygen buried layer 101 and second oxygen buried layer, 201 materials are silica, so adopt hydrofluoric acid to carry out etching.Described perforation top is by first unsettled top layer silicon 102 and second top layer silicon, 202 parts, respectively as first channel body 13 and second channel body 23.Wherein second oxygen buried layer 201 between first channel body 13 and second channel body 23 is by etching removal fully.
Shown in Figure 11 and Figure 11 a, earlier first channel body 13 and second channel body 23 are carried out high-temperature thermal oxidation; Then first channel body 13 and second channel body 23 are carried out short annealing, in the present embodiment, the temperature of described high-temperature thermal oxidation is 900～1200 degrees centigrade, and the time is 30～120 minutes.After annealing finishes, first channel body 13 and second channel body 23 will become cylindrical, and the surface is with layer oxide film (unmarked among the figure).
Shown in Figure 12 and Figure 12 a, remove the oxide-film on first channel body 13 and second channel body, 23 surfaces, can adopt hydrofluoric acid solution to clean and remove.Cleaning solution concentration and time can decide according to the oxidated layer thickness of first channel body 13 and second channel body, 23 surface attachment, should carry out 5-15 minute cleaning with the hydrofluoric acid of dilution generally speaking.
Shown in Figure 13 and Figure 13 a, form the first grid dielectric layer 14 and second gate dielectric layer 24 respectively on the surface of first channel body 13 and second channel body 23, described first, second gate dielectric layer can be silica or high dielectric constant material (High-K material), can adopt chemical vapour deposition (CVD) CVD or atomic deposition ALD to form, can also directly thermal oxidation formation on first, second channel body of monocrystalline silicon material during material selective oxidation silicon.In the present embodiment, adopt the surface deposition high dielectric constant material of atomic deposition ALD technology, form the first grid dielectric layer 14 and second gate dielectric layer 24 respectively in first channel body 13 and second channel body 23.
In addition as possibility, if described first grid dielectric layer 23, when second gate dielectric layer, 24 materials are silica, can omit the step that the oxide film to first channel body 13 and second channel body, 23 surfaces shown in Figure 12 and Figure 12 a cleans removal.
Shown in Figure 14 and Figure 14 a, at the surface deposition gate electrode 5 of first grid dielectric layer 23, second gate dielectric layer 24, described gate electrode 5 can also can be metal gate electrode for polysilicon, can adopt chemical vapour deposition (CVD) CVD or atomic deposition ALD to form.In the present embodiment, described gate electrode 5 is a metal gate electrode, adopt chemical vapour deposition (CVD) CVD to form, and when filling aforementioned side direction etching, the remaining space of the perforation that between first channel body 13, second channel body 23 and first oxygen buried layer 101, forms, therefore gate electrode 5 scopes that form are bigger, need subsequent step to carry out etching.
Shown in Figure 15 and Figure 15 a, the position of definition gate electrode 5, and carry out etching, and the described gate electrode 5 of patterning, gate electrode described in the present embodiment 5 is square, forms fin-shaped on oxygen buried layer 101 surfaces.The size range of described gate electrode 5: long L:10～50nm, wide W:10-80nm, high H:10-300nm.
As shown in figure 16, in first top layer silicon 202 of gate electrode 5 both sides, second top layer silicon 102, substep carries out reverse ion and injects and form shallow doping injection region; Wherein in first top layer silicon 102 of first channel body, 13 both sides, form N type light dope injection region NLDD, in second top layer silicon 202 of second channel body, 23 both sides, form P type light dope injection region PLDD.
As shown in figure 17, form insulative sidewall 6 in the side of gate electrode 5, described insulative sidewall 6 can also can be silica for silicon nitride.In the present embodiment, because the restriction at section visual angle, insulative sidewall 6 not only is confined to part shown in second top layer silicon, 202 tops, and should be formed at the vertical outer (as shown in phantom in FIG.) of described fin-shaped gate electrode 5.
As shown in figure 18, in described N type shallow doping injection region NLDD and the shallow doping of P type injection region PLDD, mix deeply again, form first source electrode 11 and first drain electrode 12 in the both sides of first channel body 13, form second source electrode 21 and second drain electrode 22 in the both sides of second channel body 23.
As shown in figure 19, described second source electrode 21 of etching, second drain electrode, 22 and second oxygen buried layer 201 expose the top of first source electrode 11 and first drain electrode 12.
As shown in figure 20, carry out rear end silication insulating process, draw the interconnection line of each active area.
In the present embodiment, formed nmos pass transistor on first top layer silicon 102, formed the PMOS transistor on second top layer silicon 202, two transistor forms stacked structure, the active area bottom is formed with first oxygen buried layer 101 and second oxygen buried layer 201 respectively, avoids the generation of leakage current.Can change the transistorized level up and down of nmos pass transistor and PMOS in addition, it is similar that it forms technology, only need change the crystal orientation and the doping type of the top layer silicon of different levels, those skilled in the art should push away according to aforementioned disclosed technical scheme, repeat no more.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (17)
1. a cmos device is characterized in that, comprising:
Silicon base is positioned at first oxygen buried layer, first top layer silicon and second oxygen buried layer, second top layer silicon on the silicon base successively;
The crystal orientation of described first top layer silicon and second top layer silicon is inequality;
With first top layer silicon is first field-effect transistor that substrate forms;
With second top layer silicon is second field-effect transistor that substrate forms and aims at first field-effect transistor; Described first field-effect transistor is different with the conduction type of second field-effect transistor.
2. cmos device as claimed in claim 1 is characterized in that, described first field-effect transistor is connected with second field-effect transistor.
3. cmos device as claimed in claim 1, it is characterized in that, described first field-effect transistor comprises first source electrode, first drain electrode that is positioned at first top layer silicon and isolates mutually, and first channel body that connects first source electrode, first drain electrode, the described first channel body surface is formed with first grid dielectric layer, and first grid dielectric layer surface is formed with gate electrode; Second field-effect transistor comprises second source electrode, second drain electrode that is positioned at second top layer silicon and isolates mutually, and second channel body that connects second source electrode, second drain electrode, the described second channel body surface is formed with second gate dielectric layer, and the second gate dielectric layer surface is formed with gate electrode; Wherein first channel body and second channel body are cylindrical.
4. cmos device as claimed in claim 3 is characterized in that, described first field-effect transistor and second field-effect transistor be gate electrode altogether, and described gate electrode forms and coat the surface of the first grid dielectric layer and second gate dielectric layer.
5. cmos device as claimed in claim 4 is characterized in that the side of described gate electrode is formed with insulative sidewall.
6. cmos device as claimed in claim 1 is characterized in that, described first top layer silicon is＜100〉crystal orientation, and first field-effect transistor is a nmos pass transistor; Described second top layer silicon is＜110〉crystal orientation, and second field-effect transistor is the PMOS transistor.
7. cmos device as claimed in claim 1 is characterized in that, described first top layer silicon is＜110〉crystal orientation, and first field-effect transistor is the PMOS transistor; Described second top layer silicon is＜100〉crystal orientation, and second field-effect transistor is a nmos pass transistor.
8. the manufacture method of a cmos device is characterized in that, comprising:
Silicon base is provided, on silicon base, forms first oxygen buried layer, first top layer silicon and second oxygen buried layer, second top layer silicon successively;
Described first top layer silicon is different with the crystal orientation of second top layer silicon, and doping type is opposite;
With first top layer silicon is substrate, forms first field-effect transistor, is substrate with second top layer silicon, forms second field-effect transistor;
Described second field-effect transistor is aimed at first field-effect transistor, and the conduction type difference;
Carry out rear end silication insulating process, lead to the interconnection line in source region.
9. the manufacture method of a kind of cmos device as claimed in claim 8 is characterized in that, described formation
First field-effect transistor and second field-effect transistor specifically comprise:
Second top layer silicon, second oxygen buried layer and first top layer silicon, first oxygen buried layer beyond the etching presumptive area successively is until first oxygen buried layer that exposes first top layer silicon bottom on the presumptive area from the side;
First oxygen buried layer on the described presumptive area of side direction etching and second oxygen buried layer make on the win top layer silicon and second top layer silicon and form the first unsettled channel body and second channel body respectively, and described first channel body are aimed at second channel body;
With described first channel body and the second channel body cylinderization;
Form first grid dielectric layer, second gate dielectric layer respectively in first channel body and the second channel body surface;
Surface at first grid dielectric layer, second gate dielectric layer forms gate electrode;
In first top layer silicon of the first channel body both sides, form first source electrode and first drain electrode, in second top layer silicon of the second channel body both sides, form second source electrode and second drain electrode.
10. the manufacture method of cmos device as claimed in claim 9 is characterized in that, described first top layer silicon is＜100〉crystal orientation, and doping type is the P type, and second top layer silicon is＜110〉crystal orientation, and doping type is the N type.
11. the manufacture method of cmos device as claimed in claim 9 is characterized in that, described first top layer silicon is＜110〉crystal orientation, and doping type is the N type, and second top layer silicon is＜100〉crystal orientation, and doping type is the P type.
12. the manufacture method of cmos device as claimed in claim 9 is characterized in that, and is described with first channel body and the second channel body cylinderization, specifically comprises:
First channel body and second channel body are carried out high-temperature thermal oxidation;
First channel body and second channel body are carried out short annealing.
13. the manufacture method of cmos device as claimed in claim 12 is characterized in that, the temperature of described high-temperature thermal oxidation is 900～1200 degrees centigrade, and the time is 30～120 minutes.
14. the manufacture method of cmos device as claimed in claim 11 is characterized in that, the described first grid dielectric layer and second gate dielectric layer are silica or high dielectric constant material, adopt thermal oxidation, chemical vapour deposition (CVD) or atomic deposition ALD to form.
15. the manufacture method of cmos device as claimed in claim 11 is characterized in that, described gate electrode is polysilicon or metal gate electrode, adopts atomic deposition ALD to form.
16. the manufacture method of cmos device as claimed in claim 11 is characterized in that, described formation first source electrode, first drains and forms second source electrode, second drain electrode, specifically comprises:
In first top layer silicon of the first channel body both sides and in second top layer silicon of the second channel body both sides, carry out reverse ion respectively and inject the shallow doping of formation injection region;
Side at gate electrode forms insulative sidewall;
In the shallow doping injection region of the shallow doping injection region of the first channel body both sides and the second channel body both sides, mix deeply respectively, form described first source electrode, first drain electrode and second source electrode, second drain electrode.
17. the manufacture method of cmos device as claimed in claim 9 is characterized in that, before the described interconnection line that leads to the source region, also comprises: described second source electrode of etching, second drain electrode and second oxygen buried layer, expose the top of first source electrode and first drain electrode.
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| CN102709252A (en) * | 2012-05-22 | 2012-10-03 | 上海华力微电子有限公司 | Method for improving read-out redundancy of static random access memory |
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| CN103178060A (en) * | 2011-12-23 | 2013-06-26 | 上海中科联和显示技术有限公司 | Field effect transistor complementary inverter and production method thereof |
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| CN105723501B (en) * | 2013-12-18 | 2020-02-21 | 英特尔公司 | Heterogeneous layer device |
| CN103812501A (en) * | 2014-02-13 | 2014-05-21 | 清华大学 | Phase inverter |
| CN103812501B (en) * | 2014-02-13 | 2017-02-15 | 清华大学 | Phase inverter |
| CN110970369A (en) * | 2018-09-30 | 2020-04-07 | 中芯国际集成电路制造(上海)有限公司 | CMOS inverter structure and forming method thereof |
| CN110970369B (en) * | 2018-09-30 | 2022-08-02 | 中芯国际集成电路制造(上海)有限公司 | CMOS inverter structure and forming method thereof |
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