CN101969061A - Fin-type tunneling transistor integrated circuit and manufacturing method thereof - Google Patents
Fin-type tunneling transistor integrated circuit and manufacturing method thereof Download PDFInfo
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- CN101969061A CN101969061A CN 201010293306 CN201010293306A CN101969061A CN 101969061 A CN101969061 A CN 101969061A CN 201010293306 CN201010293306 CN 201010293306 CN 201010293306 A CN201010293306 A CN 201010293306A CN 101969061 A CN101969061 A CN 101969061A
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Abstract
The invention belongs to the technical field of manufacturing of semiconductor integrated circuits, and in particular relates to a fin-type tunneling transistor integrated circuit and a manufacturing method thereof. On the basis of a silicon-on-insulator substrate, a tunneling transistor has a fin-type grid structure, a high-k dielectric is used as a grid dielectric and a low-k dielectric is used as a side wall material. The drive current of the fin-type tunneling transistor integrated circuit is improved, the switching speed of the integrated circuit is increased and the power consumption of a chip is reduced. Further, the invention also discloses the method for manufacturing the fin-type tunneling transistor integrated circuit.
Description
Technical field
The invention belongs to the following semiconductor integrated circuit manufacturing technology field of 30 nanometers, be specifically related to a kind of semiconductor integrated circuit and manufacture method thereof, particularly a kind of fin type tunneling transistor (Fin-TFET) integrated circuit and manufacture method thereof.
Background technology
Metal-oxide-silicon field-effect transistor (MOSFET) is widely used among the various electronic products.Along with the development of integrated circuit technique, the size of MOSFET is more and more littler, and the transistor density that unit matrix lists is also more and more higher.Thing followed short-channel effect is also obvious further.How to reduce the power consumption of portable equipment, become a research focus of technical field of semiconductors.Integrated circuit (IC)-components technology node of today has been in about 50 nanometers, and the leakage current between the MOSFET source-drain electrode rises rapidly along with dwindling of channel length.Particularly drop to 30 nanometers when following when channel length, be necessary to use novel device obtaining less leakage current, thereby reduce chip power-consumption.Such as, adopt tunneling field-effect transistor, can reduce the leakage current between source-drain electrode.
One of solution of the above problems is exactly to adopt tunneling field-effect transistor (TFET) structure.Compare with traditional MOSFET, tunneling field-effect transistor can further dwindle the size of circuit, has excellent specific properties such as low-leakage current, the low subthreshold value amplitude of oscillation, low-power consumption.Fig. 1 is the structure chart of the tunneling field-effect transistor on plane.On silicon substrate 100, shown in 101 current channels when opening for device, 102 is the source region of device, 103 is the drain region of device, 104 is the grid of device, 105 is grid curb wall, 106 is gate oxide.For the tunnelling type field-effect transistor of N type, mix for the P type in the source region, mixes for the N type in the drain region, and when grid added positive voltage respectively with drain electrode, transistor was opened.At this moment, the positive voltage of drain electrode makes drain region and source region form a back-biased diode, thereby has reduced leakage current.And the grid positive voltage makes the decline of being with of substrate intrinsic region, and then the energy belt profile between substrate and the source region become more precipitous, distance between conduction band and the valence band is dwindled, thereby the valence band electronics in source region is tunneling to the conduction band of raceway groove inversion regime easily, has finally formed channel current.For the tunnelling type field-effect transistor of P type, its operation principle is similar to the N type, and when adding negative voltage respectively, transistor is in running order for different is its grid and drain electrode (P type doped region).
Although the leakage current of plane tunneling field-effect transistor is lower than traditional metal-oxide-semiconductor, can reduce the power consumption of chip greatly, but its drive current is compared metal-oxide-semiconductor also a young waiter in a wineshop or an inn, three orders of magnitude, has limited the performance of device, therefore is necessary to use novel device to obtain bigger drive current.
Summary of the invention
In view of this, the objective of the invention is to tunneling field-effect transistor that proposes a kind of new structure and preparation method thereof, to obtain bigger drive current.
For reaching above-mentioned purpose of the present invention, the present invention proposes a kind of integrated circuit that adopts the new structure tunneling transistor, on the basis of using the SOI substrate, this new device adopts fin type grid structure, and adopt high K medium as gate medium, adopt low k dielectric as the abutment wall material.
The invention allows for the manufacture method of above-mentioned fin type tunneling transistor integrated circuit, concrete steps comprise:
Silicon substrate on the insulator is provided;
Oxidation forms one deck silicon oxide film;
Form the ground floor photoresist;
Mask, exposure, etching form the figure that needs doping;
In described substrate, form doped region with first kind of doping type;
Divest the ground floor photoresist;
Form second layer photoresist;
Mask, exposure, etching form the figure that needs doping;
In described substrate, form doped region with second kind of doping type;
Divest described second layer photoresist;
Silicon layer on mask, exposure, the etching insulator forms fin type structure;
Form the ground floor insulation film;
Form the ground floor conductive film;
Mask, exposure, the described ground floor conductive film of etching form the grid of device;
Form second layer insulation film;
The described second layer insulation film of autoregistration etching forms grid curb wall;
The described ground floor insulation film of etching;
Form three-layer insulated film;
Mask, exposure, the described three-layer insulated film of etching form contact hole;
Form Metal Contact.
Further, described ground floor insulation film is Ta
2O
5, Pr
2O
3, TiO
2, HfO
2, ZrO
2Deng high dielectric constant.Described second layer insulation film is silica, silicon nitride or is medium with low dielectric constant such as organic insulator.Described three-layer insulated film is silica, silicon nitride or the insulating material for mixing mutually between them.Described ground floor conductive film is metal, alloy or the polysilicon for mixing.
Further, described first kind of doping type is the n type; Second kind of doping type p type; Perhaps, described first kind of doping type is the p type; Second kind of doping type n type.
Tunneling transistor integrated circuit proposed by the invention can be accelerated the switching speed of integrated circuit when improving the integrated circuit drive current, reduce chip power-consumption.Tunneling transistor integrated circuit proposed by the invention is highly suitable for the manufacturing of integrated circuit (IC) chip, particularly the manufacturing of low-power consumption chip.
Description of drawings
Fig. 1 is the sectional view of tunneling transistor of a kind of planar structure of prior art.
Fig. 2 to Fig. 8 is the process chart of an embodiment of tunneling transistor integrated circuit provided by the invention.
Embodiment
Below with reference to accompanying drawings illustrative embodiments of the present invention is elaborated.In the drawings, for convenience of description, amplified the thickness in layer and zone, shown in size do not represent actual size.Reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of etching has crooked or mellow and full characteristics usually, but in embodiments of the present invention, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.Simultaneously in the following description, employed term substrate can be understood as and comprises the just Semiconductor substrate in processes, may comprise other prepared thin layer thereon.
At first, form the silicon substrate structure of insulator, shown in Fig. 2 a, 200a shown in it is thick layer-of-substrate silicon, shown in 200b be thin silicon dioxide intermediate layer, shown in 200c be thin monocrystalline silicon top layer.Fig. 2 b is the sectional view of Fig. 2 a along the xy face.
Next, oxidation forms one deck silicon oxide film, deposit one deck photoresist again, and mask, exposure, etching form then needs the figure that mixes, then carries out n type ion and injects and form doped region 201, removes photoresist.And then the new photoresist of deposit one deck, and mask, exposure, etching form and need the figure that mixes, carries out p type ion then and inject and form doped region 202, divests behind photoresist and the silicon oxide film shown in Fig. 3 a.Fig. 3 a along the sectional view of xy face shown in Fig. 3 b.
Next, the photoresist that deposit one deck is new, then, mask, exposure and etching silicon layer 200c form fin type structure, divest behind the photoresist as shown in Figure 4.
After fin type structure formed, deposit one deck high K medium 203 was shown in Fig. 5 a.High K medium is such as being HfO
2Fig. 5 a along the sectional view of xy face shown in Fig. 5 b.
Next, deposit one deck polysilicon, etch polysilicon forms the grid 204 of device then, shown in Fig. 6 a, Fig. 6 a along the sectional view of xy face shown in Fig. 6 b.
Next, deposit one deck low k dielectric, the etching low k dielectric forms grid curb wall 205 then, shown in Fig. 7 a, Fig. 7 a along the sectional view of xy face shown in Fig. 7 b.
At last, etched portions high dielectric constant 203, deposit one deck insulation film 206 then, insulation film 206 is such as being silicon dioxide or silicon nitride, etching insulation film 206 forms contact hole then, and deposit layer of metal again 207 is such as being titanium nitride, etching forms Metal Contact then, as shown in Figure 8.
As mentioned above, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in the specification.
Claims (8)
1. fin type tunneling transistor integrated circuit, it is characterized in that this tunneling transistor integrated circuit adopts fin type grid structure based on the silicon substrate on the insulator in described tunneling transistor, and adopt high K medium as gate medium, adopt low k dielectric as the abutment wall material.
2. the manufacture method of a fin type tunneling transistor integrated circuit as claimed in claim 1 is characterized in that concrete steps comprise:
Silicon substrate on the insulator is provided;
In described substrate, form doped region with first kind of doping type;
In described substrate, form doped region with second kind of doping type;
Silicon layer on the etching insulator forms fin type structure;
Form the ground floor insulation film;
Form the ground floor conductive film;
The described ground floor conductive film of etching forms the grid of device;
Form second layer insulation film;
The described second layer insulation film of etching forms grid curb wall;
The described ground floor insulation film of etching;
Form three-layer insulated film;
The described three-layer insulated film of etching forms contact hole;
Form Metal Contact.
3. manufacture method according to claim 2 is characterized in that, described ground floor insulating film material is Ta
2O
5, Pr
2O
3, TiO
2, HfO
2Or ZrO
2High dielectric constant.
4. manufacture method according to claim 2 is characterized in that, described second layer insulating film material is silica, silicon nitride or is the organic insulator medium with low dielectric constant.
5. manufacture method according to claim 2 is characterized in that, described three-layer insulated thin-film material is silica, silicon nitride or the insulating material for mixing mutually between them.
6. manufacture method according to claim 2 is characterized in that, described ground floor conductive film is metal, alloy or the polysilicon for mixing.
7. manufacture method according to claim 2 is characterized in that, described first kind of doping type is the n type; Second kind of doping type p type.
8. manufacture method according to claim 2 is characterized in that, described first kind of doping type is the p type; Second kind of doping type n type.
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| CN 201010293306 CN101969061A (en) | 2010-09-27 | 2010-09-27 | Fin-type tunneling transistor integrated circuit and manufacturing method thereof |
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| CN 201010293306 CN101969061A (en) | 2010-09-27 | 2010-09-27 | Fin-type tunneling transistor integrated circuit and manufacturing method thereof |
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Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102306660A (en) * | 2011-09-08 | 2012-01-04 | 上海华力微电子有限公司 | MOS (metal oxide semiconductor) device structure and manufacturing method thereof |
| CN102403234A (en) * | 2011-12-13 | 2012-04-04 | 复旦大学 | Method for manufacturing fin field effect transistor with high-K metal gate by using self alignment technology |
| CN103021857A (en) * | 2011-09-28 | 2013-04-03 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of multi-grid field effect transistor |
| CN103035577A (en) * | 2011-10-09 | 2013-04-10 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN103117306A (en) * | 2011-11-16 | 2013-05-22 | 台湾积体电路制造股份有限公司 | Tunnel FET and methods for forming the same |
| CN103151390A (en) * | 2013-03-15 | 2013-06-12 | 南通大学 | Tunneling field effect transistor |
| CN104183487A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | FinTFET semiconductor device and manufacturing method thereof |
| CN104347704A (en) * | 2013-07-25 | 2015-02-11 | 中国科学院微电子研究所 | Tunneling field effect transistor and manufacturing method thereof |
| WO2015032296A1 (en) * | 2013-09-06 | 2015-03-12 | 北京大学深圳研究生院 | Tunnelling field effect transistor |
| CN104425593A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Tunneling field effect transistor and forming method thereof |
| CN105026309A (en) * | 2013-03-28 | 2015-11-04 | 英特尔公司 | Multigate resonant channel transistor |
| US20150340489A1 (en) * | 2014-05-26 | 2015-11-26 | Semiconductor Manufacturing International (Shanghai) Corporation | Fin tunneling field effect transistor and manufacturing method thereof |
| CN105990409A (en) * | 2015-02-11 | 2016-10-05 | 中国科学院微电子研究所 | Preparation method of multilayer tunneling junction three-dimensional tunneling field effect transistor |
| CN107068562A (en) * | 2015-09-18 | 2017-08-18 | 格罗方德半导体公司 | Three-dimensional fin tunneling field-effect transistor |
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| US20050272192A1 (en) * | 2004-06-04 | 2005-12-08 | Chang-Woo Oh | Methods of forming fin field effect transistors using oxidation barrier layers and related devices |
| US20070045741A1 (en) * | 2005-09-01 | 2007-03-01 | Leonard Forbes | DRAM tunneling access transistor |
| CN1988177A (en) * | 2005-12-24 | 2007-06-27 | 三星电子株式会社 | Fin-fet having gaa structure and methods of fabricating the same |
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Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102306660A (en) * | 2011-09-08 | 2012-01-04 | 上海华力微电子有限公司 | MOS (metal oxide semiconductor) device structure and manufacturing method thereof |
| CN103021857B (en) * | 2011-09-28 | 2015-12-16 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of multiple gate field effect transistor |
| CN103021857A (en) * | 2011-09-28 | 2013-04-03 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of multi-grid field effect transistor |
| CN103035577A (en) * | 2011-10-09 | 2013-04-10 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN103117306A (en) * | 2011-11-16 | 2013-05-22 | 台湾积体电路制造股份有限公司 | Tunnel FET and methods for forming the same |
| CN103117306B (en) * | 2011-11-16 | 2015-11-18 | 台湾积体电路制造股份有限公司 | tunnel FET and forming method thereof |
| CN102403234B (en) * | 2011-12-13 | 2014-08-06 | 复旦大学 | Method for manufacturing fin field effect transistor with high-K metal gate by using self alignment technology |
| CN102403234A (en) * | 2011-12-13 | 2012-04-04 | 复旦大学 | Method for manufacturing fin field effect transistor with high-K metal gate by using self alignment technology |
| CN103151390A (en) * | 2013-03-15 | 2013-06-12 | 南通大学 | Tunneling field effect transistor |
| CN105026309B (en) * | 2013-03-28 | 2017-04-12 | 英特尔公司 | Multigate resonant channel transistor |
| CN105026309A (en) * | 2013-03-28 | 2015-11-04 | 英特尔公司 | Multigate resonant channel transistor |
| CN104183487A (en) * | 2013-05-21 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | FinTFET semiconductor device and manufacturing method thereof |
| CN104347704A (en) * | 2013-07-25 | 2015-02-11 | 中国科学院微电子研究所 | Tunneling field effect transistor and manufacturing method thereof |
| CN104347704B (en) * | 2013-07-25 | 2018-01-30 | 中国科学院微电子研究所 | tunneling field effect transistor and manufacturing method thereof |
| CN104425593A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Tunneling field effect transistor and forming method thereof |
| US9793351B2 (en) | 2013-09-06 | 2017-10-17 | Peking University Shenzhen Graduate School | Tunnelling field effect transistor |
| WO2015032296A1 (en) * | 2013-09-06 | 2015-03-12 | 北京大学深圳研究生院 | Tunnelling field effect transistor |
| CN105336772A (en) * | 2014-05-26 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Fin type tfet and manufacturing method thereof |
| US20150340489A1 (en) * | 2014-05-26 | 2015-11-26 | Semiconductor Manufacturing International (Shanghai) Corporation | Fin tunneling field effect transistor and manufacturing method thereof |
| US10615081B2 (en) | 2014-05-26 | 2020-04-07 | Semiconductor Manufacturing International (Shanghai) Corporation | Fin tunneling field effect transistor and manufacturing method thereof |
| CN105336772B (en) * | 2014-05-26 | 2021-11-30 | 中芯国际集成电路制造(上海)有限公司 | Fin type TFET (thin film transistor) and manufacturing method thereof |
| CN105990409A (en) * | 2015-02-11 | 2016-10-05 | 中国科学院微电子研究所 | Preparation method of multilayer tunneling junction three-dimensional tunneling field effect transistor |
| CN105990409B (en) * | 2015-02-11 | 2019-01-08 | 中国科学院微电子研究所 | Preparation method of multilayer tunneling junction three-dimensional tunneling field effect transistor |
| CN107068562A (en) * | 2015-09-18 | 2017-08-18 | 格罗方德半导体公司 | Three-dimensional fin tunneling field-effect transistor |
| CN107068562B (en) * | 2015-09-18 | 2020-09-18 | 格罗方德半导体公司 | Three-dimensional fin tunneling field effect transistor |
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Application publication date: 20110209 |