CN104347704A - Tunneling field effect transistor and manufacturing method thereof - Google Patents

Tunneling field effect transistor and manufacturing method thereof Download PDF

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Publication number
CN104347704A
CN104347704A CN201310315051.9A CN201310315051A CN104347704A CN 104347704 A CN104347704 A CN 104347704A CN 201310315051 A CN201310315051 A CN 201310315051A CN 104347704 A CN104347704 A CN 104347704A
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grid
dielectric layer
fin
doped region
substrate
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CN104347704B (en
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朱正勇
朱慧珑
许淼
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Thin Film Transistor (AREA)

Abstract

The invention provides a tunneling field effect transistor, which comprises a substrate, wherein a fin is arranged on the substrate, and the fin is provided with a first side surface and a second side surface which are opposite, and a third side surface and a fourth side surface which are opposite; a first gate dielectric layer and a second gate dielectric layer respectively formed on the first side surface and the second side surface; the first grid electrode and the second grid electrode are formed on the substrate and are respectively connected with the first grid dielectric layer and the second grid dielectric layer; and the first doped region and the second doped region are formed on the substrate and respectively connected with the third side surface and the fourth side surface, and the first doped region and the second doped region have different doping types. The width of the tunneling junction is controlled by the width of the fin channel region, and the tunneling junction has a larger effective tunneling area, so that the conduction current can be increased. Meanwhile, in the transistor structure, the tunneling occurs in the semiconductor layer, namely in the channel, and the tunneling layer is undoped or low-doped, so that the leakage current can be reduced, and the sub-threshold characteristic of the device can be improved. In addition, due to the adoption of double-gate control, the bipolar conduction characteristic can be better controlled, and the device is turned off.

Description

Then field-effect transistor and manufacture method thereof is worn
Technical field
The present invention relates to field of semiconductor devices, particularly one wears field-effect transistor and manufacture method thereof then.
Background technology
Along with constantly reducing of device size, the device count on unit are chip gets more and more, and how to reduce power consumption and becomes the problem become increasingly conspicuous.
The conventional structure of then wearing field-effect transistor (Normal-TFET) mainly comprises the source/drain region of substrate (raceway groove), gate dielectric layer, grid and grid both sides, mainly based on the work of quantum tunneling effect, then field-effect transistor is worn for P type, grid applies negative voltage, the electromotive force of channel region raises, there is quantum to channel region and then wear in source region, electronics and the hole of then wearing generation are flowed out from source region and drain region.
Then wear field-effect transistor for routine, its subthreshold swing (SS) can be less than 60meV/dec, provides a kind of approach for reducing power consumption.But in order to reduce subthreshold swing and improve On current, need then to wear knot more narrow better, but existing structure then wear field-effect transistor, to inject and heat treatment process federation causes the diffusion profile of impurity, be difficult to realize narrow then wear knot.
In addition, then wear in field-effect transistor in routine, source-drain area is all highly doped, and doping will certainly introduce defect, and the leakage current relevant to these defects can destroy the reduction of subthreshold swing.And conventional field-effect transistor of then wearing has the dipole characteristic can opened under positive negative gate voltage, and device can be caused to be difficult to turn off completely.
Summary of the invention
Object of the present invention is intended to solve above-mentioned technological deficiency, provides one then to wear field-effect transistor and manufacture method thereof.
The invention provides one and then wear field-effect transistor, comprising:
Substrate, substrate has fin, and described fin has the first relative side, the second side and the 3rd relative side, the 4th side;
Be formed at the first grid dielectric layer on the first side and the second side and second gate dielectric layer respectively;
Be formed at the first grid and second grid that connect with first grid dielectric layer and second gate dielectric layer on substrate, respectively;
Be formed at the first doped region and the second doped region that connect with the 3rd side, the 4th side on substrate, respectively, described first doped region and the second doped region have different doping types.
Preferably, the width of fin raceway groove is not more than 10nm.
Preferably, described first doped region and the second doped region are formed by epitaxial growth.
Preferably, described first grid dielectric layer is also formed between first grid and substrate, and described second gate dielectric layer is also formed between second grid and substrate.
Preferably, on the 3rd side of fin and the 4th end, place, side, be also formed with the first side wall and the second side wall respectively, to make first grid, the two ends of second grid do not cover fin.
In addition, present invention also offers a kind of manufacture method of then wearing field-effect transistor, comprise step:
There is provided substrate, described substrate is formed with fin, described fin has the first relative side, the second side and the 3rd relative side, the 4th side;
Described first side and the second side are formed first grid dielectric layer and second gate dielectric layer respectively;
Form the first grid and second grid that connect with first grid dielectric layer and second gate dielectric layer respectively over the substrate; And
Form the first doped region and the second doped region that connect with the 3rd side, the 4th side respectively over the substrate, described first doped region and the second doped region have different doping types.
The formation method of described fin and first grid dielectric layer and second gate dielectric layer specifically comprises:
SOI substrate is provided;
Described SOI substrate is formed the first mask layer of patterning;
The second mask layer is formed at the sidewall of the first mask layer;
With the first mask layer and the second mask layer for sheltering, the top layer silicon of patterned SOI substrate;
The sidewall of top layer silicon after patterning forms first grid dielectric layer;
Remove the first mask layer and under top layer silicon, to form fin;
The sidewall that described fin exposes forms second gate dielectric layer.
Preferably, the width of described fin is not more than 10nm.
Preferably, being formed between first grid dielectric layer and the step forming fin, also step is comprised: carry out filling to form the first dummy grid;
After formation second gate dielectric layer, also comprise step: carry out filling to form the second dummy grid;
After formation first doped region and the second doped region, also comprise step: remove described first dummy grid and the second dummy grid, again form first grid and second grid.
Preferably, between formation first grid, second grid and formation first doped region, the second doped region, also step is comprised:
On the 3rd side of fin and the 4th end, place, side, form the first side wall and the second side wall respectively, to make first grid, the two ends of second grid do not cover fin.
Preferably, the step of described manufacture method specifically comprises:
Substrate is provided, forms fin ray over the substrate;
First side, the second side of described fin ray form first grid dielectric layer and second gate dielectric layer successively, and forms the first grid and second grid that connect with first grid dielectric layer and second gate dielectric layer respectively respectively over the substrate;
Form the 4th mask layer, and form the 5th mask layer at the sidewall of the 4th mask layer, the 4th mask layer is across the first grid of the second doped region and both sides thereof and second grid, and the 5th mask layer is across the first grid of channel region and both sides thereof and second grid;
Under the sheltering of the 4th mask layer and the 5th mask layer, remove first grid, first grid dielectric layer, second grid and second gate dielectric layer, and expose fin ray;
The first grid exposed and the sidewall of second grid and the fin ray of exposure form the first side wall;
The first doped region is formed in the fin ray part exposed;
Cover the first doped region and form the first interlayer dielectric layer;
Under the sheltering of the 5th mask layer, the first side wall and the first interlayer dielectric layer, remove the 4th mask layer and under first grid, first grid dielectric layer, second grid and second gate dielectric layer, and expose fin ray;
The first grid exposed and the sidewall of second grid and the fin ray of exposure form the second side wall;
The second doped region is formed in the fin ray part exposed;
Cover the second doped region and form the second interlayer dielectric layer.
What the embodiment of the present invention provided wears field-effect transistor then, in formation source area, both sides and the drain region of fin, the two sides of fin forms grid, result in formation of double-gated devices, fin is channel region, and the field-effect transistor of then wearing of this structure is do not inject the narrow of diffusion-restricted by impurity then to wear knot, and its thin and thick by channel region controls then to wear knot, and have and larger effectively then wear area, therefore can improve On current.Meanwhile, transistor arrangement of the present invention, it is then worn and betides in semiconductor layer, namely in raceway groove, because tunnel layer is undoped or low-doped, therefore can reduce the leakage current relevant to defect, thus improve the Sub-Threshold Characteristic of device.In addition, owing to adopting double grid to control, therefore can better control bipolar-conduction characteristic, realize device and turn off.
Accompanying drawing explanation
The present invention above-mentioned and/or additional aspect and advantage will become obvious and easy understand from the following description of the accompanying drawings of embodiments, wherein:
Fig. 1-Figure 42 shows the schematic diagram then wearing each formation stages of field-effect transistor according to the embodiment of the present invention, comprising vertical view, AA ', BB ' and LL ' to cross sectional view.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
The present invention be intended to propose a kind of newly then wear field-effect transistor structure, be difficult to realize narrow then wear knot to overcome existing field-effect transistor structure of then wearing, be vertical view with reference to figure 40-42(Figure 40, LL ', AA ' that Figure 41,42 is respectively Figure 40 to view) shown in, described field-effect transistor of then wearing comprises:
Substrate 100-1,100-2, substrate has fin 140, and described fin 140 has the first relative side, the second side and the 3rd relative side, the 4th side;
Be formed at the first grid dielectric layer 120 on the first side and the second side and second gate dielectric layer 122 respectively;
Be formed at the first grid 134 and second grid 152 that connect with first grid dielectric layer 120 and second gate dielectric layer 122 on substrate, respectively;
Be formed at the first doped region 170 and the second doped region 180 connected with the 3rd side, the 4th side on substrate, respectively, described first doped region 170 and the second doped region 180 have different doping types.
Then field-effect transistor of wearing of the present invention is fin transistor, then wear in field-effect transistor structure of the present invention, two sides of fin form source area and drain region, another two sides of fin form grid, and result in formation of double-gated devices, fin is channel region, both sides grid applies different voltage, raceway groove two sides are in different electromotive forces, when this electrical potential difference is greater than the energy gap of channel material, quantum occurs between conduction band and valence band and then wears.Then the charge carrier (electronics and hole) wearing generation is flowed out by source and drain, thus forms conducting loop.Then the field-effect transistor of wearing of this structure is do not inject the narrow of diffusion-restricted by impurity then to wear knot, its width by fin controls the width then wearing knot, and have and larger effectively then wear area (being long-pendingly directly proportional to fin height x length is), therefore can improve On current.In addition, the channel region due to transistor of the present invention can undope or only low-doped, thus significantly reduces the electric current relevant to defect, can realize lower subthreshold swing.
In embodiments of the present invention, the width of fin 140 can control at about 10nm or thinner, to realize narrow then wearing knot.
Described fin 140 is preferably the little material of band gap, can be such as monocrystalline silicon, polysilicon, amorphous silicon, germanium, SiGe, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or other compound semiconductors.In the present embodiment, described fin is by SOI(silicon-on-insulator) top layer silicon of substrate formed.
Described first grid dielectric layer 120 or second gate dielectric layer 122 can be silica, silicon oxynitride or high K medium material etc., high K medium material such as hafnium base oxide, HfO 2, HfSiO, HfSiON, HfTaO, HfTiO etc., and other high-g value, such as La 2o 3, TiO 2deng.Described first grid 134 or second grid 152 can be one or more layers structure, and gate electrode can comprise metal gate electrode or polysilicon etc., such as, can comprise: Ti, TiAl x, TiN, TaN x, HfN, TiC x, TaC x, HfC x, Ru, TaN x, TiAlN, WCN, MoAlN, RuO x, polysilicon or other suitable materials, or their combination.
First doped region 170 and the second doped region 180 are source area or drain region, and for N-type device, drain region is N-type heavy doping, and source area is the heavy doping of P type; To P type device, drain region is the heavy doping of P type, and source area is N-type heavy doping.In the present embodiment, the first doped region 170 and the second doped region 180 are formed by epitaxial growth.
In the present embodiment, described first grid dielectric layer 120 is also formed between first grid 134 and substrate 100-2, and described second gate dielectric layer 122 is also formed between second grid 152 and substrate 100-2.
Be described structure of then wearing field-effect transistor of the present invention above, in addition, present invention also offers the manufacture method of above-mentioned transistor, described method comprises:
There is provided substrate, described substrate is formed with fin, described fin has the first relative side, the second side and the 3rd relative side, the 4th side;
Described first side and the second side are formed first grid dielectric layer and second gate dielectric layer respectively;
Form the first grid and second grid that connect with first grid dielectric layer and second gate dielectric layer respectively over the substrate; And
Form the first doped region and the second doped region that connect with the 3rd side, the 4th side respectively over the substrate, described first doped region and the second doped region have different doping types.
For a better understanding of the present invention, below in conjunction with accompanying drawing 1-42, the embodiment of the manufacture method of this structure is described in detail.
First, provide SOI substrate 100, shown in figure 1.
SOI substrate 100 is by bottom silicon 100-1, oxygen buried layer 100-2 and top layer silicon 100-3, and fin is formed by top layer silicon 100-3.
Then, fin 140 is formed.
In the present invention, control by the width of fin the width then wearing knot, certainly, then wear knot more narrow better, the method that the present embodiment proposes is particularly useful for the formation of narrow fin, and such as width is at the fin of about 10nm or less.
In the particular embodiment, first, cap rock and the first mask layer 106 on it is formed on the substrate 100, in the present embodiment, as shown in Figure 1, cap rock comprises the first oxide skin(coating) 102 of being formed successively and amorphous silicon layer 104, first mask layer 106 is such as the first nitride layer.In the present embodiment, subsequent technique Etch selectivity is considered in the selection of the material of cap rock and each mask layer, can form mask layer, be only example herein according to the concrete material needing selection suitable.
Then, carry out patterning, as shown in Figure 2, first on the first mask layer 106, form photosensitive etching agent 108, as shown in Figure 3, and with photosensitive etching agent 108 for the first mask layer 106 and amorphous silicon layer 104 described in mask etching, as shown in Figure 4, after realizing the patterning of the first mask layer 106 and amorphous silicon layer 104, the second mask layer 110 is formed at the sidewall of this first mask layer 106 and amorphous silicon layer 104, in the present embodiment, this second mask layer 110 is nitride, and its width determines the width of follow-up formation fin.Then, as shown in Figure 5, under the sheltering of the first mask layer 106 and the second mask layer 110, etching first oxide skin(coating) 102 and top layer silicon 100-3 is continued.
Then, as shown in Figure 6, the inwall of the opening formed after etching is formed first grid dielectric layer 120, namely, the sidewall of cap rock 102,110 and the surface of exposed substrate 100-2 of fin 140 and fin form first grid dielectric layer 120, and fill this opening formation first grid 130, according to the needs of subsequent technique, if follow-up source-drain area is formed or other techniques affect to some extent on grid, this first grid 130 can be dummy grid, that is, after the complete source-drain area of follow-up formation, removed, and again formed first grid.Certainly, if do not have technologic impact or selection to have suitable electric conducting material as grid, this first grid also can be formed at this moment in the lump, with simple flow, the integrated level improving technique.In the present embodiment, this first grid 130 is dummy grid, adopts polycrystalline silicon material to be formed.
Then, then, with the second mask layer 110 and the 3rd mask layer 132 for sheltering, continue removal first mask layer 106 and under amorphous silicon layer 104, first oxide skin(coating) 102 and top layer silicon 100-3, thus define fin 140, remaining first oxide skin(coating) 102 and the second mask layer 110 are the cap rock of fin 140, as Fig. 9.Particularly, in the present embodiment, first first grid is removed part, and to fill formation the 3rd mask layer the 132, three mask layer be nitride, as shown in Figure 7.Then, carry out cmp and remove the first mask layer 106, until expose amorphous silicon layer 104, as shown in Figure 8.Then, etch, remove amorphous silicon layer 104 and the first lower oxide skin(coating) 102 and top layer silicon 100-3 thereof, as shown in Figure 9, thus form fin 140, in the present embodiment, the fin herein formed is fin ray, with reference to (AA ' direction view of Figure 12) Figure 13 shown.
Then, the inwall of the opening formed after etching is formed second gate dielectric layer 122, namely on another sidewall of cap rock 102,110 and the surface of exposed substrate 100-2 of fin 140 and fin, form second gate dielectric layer 122, and fill this opening and form second grid 150, as shown in Figure 10.Same first grid, this second grid can be that dummy grid also can for real grid, and in this embodiment, second grid is also dummy grid, can be formed by polysilicon.
After formation fin and grid, continue formation first doped region and the second doped region, i.e. source area and drain region.
In the present embodiment, first form the 4th mask layer, as shown in figure 11, the 4th mask layer comprises the second oxide skin(coating) 160, second nitride layer 162 and the trioxide layer 164 formed successively, and described 4th mask layer covers the part of the second doped region; Then, form the 5th mask layer 166 at the sidewall of the 4th mask layer, consider Etch selectivity, in this embodiment, the 5th mask layer 166 is formed by SiGe, being used for covering fin channel part, is vertical view with reference to figure 12-14(Figure 12, and Figure 13, Figure 14 are respectively AA ' and the BB ' direction view of Figure 12).
Then, etch, until expose fin 140, in etching process, due to the Etch selectivity that trioxide layer 164 is different from nitride, under it is sheltered, first etching removes the 3rd not masked mask layer 132, second mask layer 110(is nitride), then, continue etching removal first oxide skin(coating) 102, in etching, the trioxide layer 164 of the 4th mask layer is also removed, then etching removal first and second grid 130 is continued, 150, first and second gate dielectric layers 120, 122, (Figure 15 is vertical view as seen in figs. 15-17, Figure 16, Figure 17 is respectively AA ' and the BB ' direction view of Figure 15) in erosion process at the moment, by the Etch selectivity of different materials, select different etching ions or etching agent, divide and etched several times.
Then, carry out deposit and form the first side wall 168, side wall at least covers the sidewall of the first and second exposed sides of grid, in the present embodiment, first side wall 168 be formed in the 5th mask layer 166 and under other layer of side exposed sidewall on, with reference to figure 18(vertical view) shown in.
Then, form the first doped region 170 in the part of the fin exposed, it has the first doping type, as shown in Figure 19 (vertical view).In the present embodiment, the mode of selective epitaxial (epi) is adopted to form this first doped region 170, i.e. the silicon doping district of N-type doping.Certainly, in other embodiments, the first doped region and the secondth district also can select the material different from channel layer to be formed.
Then, cover the first doped region 170, form the first interlayer dielectric layer 172, in the present embodiment, the first interlayer dielectric layer 172 is oxide, after deposit first interlayer dielectric layer 172, carry out cmp (CMP), to realize planarization, if Figure 20-22(Figure 20 is vertical view, Figure 21,22 is respectively AA ', the BB ' direction view of Figure 20).
Then, proceed etching, remove successively the second nitride layer 162, second oxide skin(coating) 160 and under the second mask layer 110, first oxide skin(coating) 102, the 3rd mask layer 132, first and second grid 130,150, first and second gate medium 120,122, expose the fin under the 4th mask layer and oxygen buried layer 100-2, as shown in figure 23 (vertical view).
Then, carry out deposit and form the second side wall 174, side wall at least covers the sidewall of the exposed opposite side of the first and second grids, in the present embodiment, second side wall 174 be formed in the 5th mask layer 166 and under the exposed sidewall of other layer of opposite side on, with reference to (vertical view) shown in Figure 24.
Then, form the second doped region 180 in the part of the fin exposed, it has the second doping type, as shown in Figure 25 (vertical view).In the present embodiment, the mode of selective epitaxial (epi) is adopted to form this second doped region 180, i.e. the silicon doping district of P type doping.
Then, cover the second doped region 180, form the second interlayer dielectric layer 182, in the present embodiment, the second interlayer dielectric layer 182 is oxide, after deposit second interlayer dielectric layer 182, carry out cmp (CMP), to realize planarization, if Figure 26-29(Figure 26 is vertical view, Figure 27,28,29 is respectively AA ', BB ', the LL ' direction view of Figure 26).
So far, the first doped region and second doped region of the present embodiment is defined.In the preferred embodiment, form the first doped region and the second doped region by different mask layers and side wall autoregistration, process integration is high.
Then, as required, whether again first grid and second grid can be formed.
Particularly, in the present embodiment, first, cmp (CMP) is carried out, until expose second grid 150, if Figure 30,31(Figure 30 is vertical view, the LL ' direction view that Figure 31 is Figure 30) shown in.
Then, remove the second grid 150 of dummy grid, and again form second grid 152, if Figure 32,33(Figure 32 is vertical view, the LL ' direction view that Figure 33 is Figure 32) shown in.
Then, remove the second grid 152 of part, and form dielectric layer 184 between third layer thereon, in the present embodiment, between third layer, dielectric layer 184 is oxide, if Figure 34,35(Figure 34 is vertical view, and the LL ' direction view that Figure 35 is Figure 34) shown in.
Then, carry out cmp (CMP), until expose first grid 130, if Figure 36,37(Figure 36 is vertical view, the LL ' direction view that Figure 37 is Figure 36) shown in.
Then, remove the first grid 130 of dummy grid, and again form first grid 134, if Figure 38,39(Figure 38 is vertical view, the LL ' direction view that Figure 39 is Figure 38) shown in.
So far, first grid 134 and second grid 152 is again defined.
Then, forming the 4th interlayer dielectric layer 186 covering whole device, such as, is oxide, and meanwhile, form source and drain contact 190,192 and gate contact 194, if Figure 40-42(Figure 40 is vertical view, Figure 41,42 is respectively LL ', the AA ' direction view of Figure 40)
So far, the fin defining the embodiment of the present invention wears field-effect transistor then.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.

Claims (11)

1. then wear a field-effect transistor, it is characterized in that, comprising:
Substrate, substrate has fin, and described fin has the first relative side, the second side and the 3rd relative side, the 4th side;
Be formed at the first grid dielectric layer on the first side and the second side and second gate dielectric layer respectively;
Be formed at the first grid and second grid that connect with first grid dielectric layer and second gate dielectric layer on substrate, respectively;
Be formed at the first doped region and the second doped region that connect with the 3rd side, the 4th side on substrate, respectively, described first doped region and the second doped region have different doping types.
2. according to claim 1ly then wear field-effect transistor, it is characterized in that, the width of fin raceway groove is not more than 10nm.
3. according to claim 1ly then wear field-effect transistor, it is characterized in that, described first doped region and the second doped region are formed by epitaxial growth.
4. according to claim 1ly then wear field-effect transistor, it is characterized in that, described first grid dielectric layer is also formed between first grid and substrate, and described second gate dielectric layer is also formed between second grid and substrate.
5. according to claim 1ly then wear field-effect transistor, it is characterized in that, on the 3rd side of fin and the 4th end, place, side, be also formed with the first side wall and the second side wall respectively, to make first grid, the two ends of second grid do not cover fin.
6. then wear a manufacture method for field-effect transistor, it is characterized in that, comprise step:
There is provided substrate, described substrate is formed with fin, described fin has the first relative side, the second side and the 3rd relative side, the 4th side;
Described first side and the second side are formed first grid dielectric layer and second gate dielectric layer respectively;
Form the first grid and second grid that connect with first grid dielectric layer and second gate dielectric layer respectively over the substrate; And
Form the first doped region and the second doped region that connect with the 3rd side, the 4th side respectively over the substrate, described first doped region and the second doped region have different doping types.
7. manufacture method according to claim 6, is characterized in that, the formation method of described fin and first grid dielectric layer and second gate dielectric layer specifically comprises:
SOI substrate is provided;
Described SOI substrate is formed the first mask layer of patterning;
The second mask layer is formed at the sidewall of the first mask layer;
With the first mask layer and the second mask layer for sheltering, the top layer silicon of patterned SOI substrate;
The sidewall of top layer silicon after patterning forms first grid dielectric layer;
Remove the first mask layer and under top layer silicon, to form fin;
The sidewall that described fin exposes forms second gate dielectric layer.
8. manufacture method according to claim 7, is characterized in that, the width of described fin is not more than 10nm.
9. manufacture method according to claim 7, is characterized in that, being formed between first grid dielectric layer and the step forming fin, also comprises step: carry out filling to form the first dummy grid;
After formation second gate dielectric layer, also comprise step: carry out filling to form the second dummy grid;
After formation first doped region and the second doped region, also comprise step: remove described first dummy grid and the second dummy grid, again form first grid and second grid.
10. manufacture method according to claim 6, is characterized in that, between formation first grid, second grid and formation first doped region, the second doped region, also comprises step:
On the 3rd side of fin and the 4th end, place, side, form the first side wall and the second side wall respectively, to make first grid, the two ends of second grid do not cover fin.
11. 1 kinds of manufacture methods of then wearing field-effect transistor, it is characterized in that, the step of described manufacture method specifically comprises:
Substrate is provided, forms fin ray over the substrate;
First side, the second side of described fin ray form first grid dielectric layer and second gate dielectric layer successively, and forms the first grid and second grid that connect with first grid dielectric layer and second gate dielectric layer respectively respectively over the substrate;
Form the 4th mask layer, and form the 5th mask layer at the sidewall of the 4th mask layer, the 4th mask layer is across the first grid of the second doped region and both sides thereof and second grid, and the 5th mask layer is across the first grid of channel region and both sides thereof and second grid;
Under the sheltering of the 4th mask layer and the 5th mask layer, remove first grid, first grid dielectric layer, second grid and second gate dielectric layer, and expose fin ray;
The first grid exposed and the sidewall of second grid and the fin ray of exposure form the first side wall;
The first doped region is formed in the fin ray part exposed;
Cover the first doped region and form the first interlayer dielectric layer;
Under the sheltering of the 5th mask layer, the first side wall and the first interlayer dielectric layer, remove the 4th mask layer and under first grid, first grid dielectric layer, second grid and second gate dielectric layer, and expose fin ray;
The first grid exposed and the sidewall of second grid and the fin ray of exposure form the second side wall;
The second doped region is formed in the fin ray part exposed;
Cover the second doped region and form the second interlayer dielectric layer.
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