CN102569405B - Tunneling transistor with quasi-coaxial cable structure and forming method of tunneling transistor - Google Patents
Tunneling transistor with quasi-coaxial cable structure and forming method of tunneling transistor Download PDFInfo
- Publication number
- CN102569405B CN102569405B CN201210015260.7A CN201210015260A CN102569405B CN 102569405 B CN102569405 B CN 102569405B CN 201210015260 A CN201210015260 A CN 201210015260A CN 102569405 B CN102569405 B CN 102569405B
- Authority
- CN
- China
- Prior art keywords
- channel region
- semiconductor substrate
- layer
- described semiconductor
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Thin Film Transistor (AREA)
Abstract
The invention provides a tunneling transistor with a quasi-coaxial cable structure and a forming method of the tunneling transistor. The tunneling transistor comprises a semiconductor substrate with a first doping type, a vertical semiconductor column, a channel region and a grid structure, wherein the semiconductor substrate is of a source region or a drain region; the vertical semiconductor column with a second doping type is formed on the semiconductor substrate, wherein the semiconductor column is of a source region or drain region; the channel region is formed on the semiconductor substrate and surrounds the lateral wall of the semiconductor column; and the grid structure is formed on the semiconductor substrate and surrounds the lateral wall of the channel region. According to the tunneling transistor provided by the embodiment of the invention, the integration level of a TFET (Tunneling Field Effect Transistor) device can be increased, and the driving capability of the TFET device is improved.
Description
Technical field
The present invention relates to semiconductor design and manufacturing technology field, particularly a kind of tunneling transistor with accurate coaxial cable structure and forming method thereof.
Background technology
For a long time, in order to obtain higher chip density, operating rate and lower power consumption faster.It is constantly scaled that the characteristic size of metal-oxide semiconductor fieldeffect transistor (MOSFET) is being followed so-called Moore's Law (Moore ' slaw) always, and its operating rate is more and more faster.The current scope that has entered into nanoscale.Yet, serious challenge of the thing followed is to have occurred short-channel effect, such as subthreshold voltage drop (Vtroll-off), drain electrode, cause that potential barrier reduces the phenomenons such as (DIBL), Punchthrough (punch through), the off-state leakage current of device is enlarged markedly, thereby cause performance to worsen.
Current, to bring in order to reduce short-channel effect negative effect, people have proposed various corrective measures, and wherein that particularly outstanding is tunneling field-effect transistor (tunneling field effect transistor, TFET).While being in subthreshold value state due to MOSFET device, device is weak transoid, and now thermionic emission is main conductive mechanism, and therefore, at room temperature the sub-threshold slope of MOSFET is limited to 60mV/dec.For traditional MOSFET, on the one hand, because the active area of tunneling field-effect transistor device is essentially tunnel junctions, therefore, tunneling field-effect transistor has the more weak short-channel effect that even do not have; Simultaneously, the main Current mechanism of tunneling field-effect transistor is bandtoband (band-to-band tunneling), in sub-threshold region and saturation region drain current and additional gate source voltage be exponential relationship, therefore tunneling field-effect transistor has lower sub-threshold slope, and electric current is subject to the impact of temperature hardly.
The preparation technology of tunneling field-effect transistor is compatible mutually with traditional complementary type metal-oxide semiconductor fieldeffect transistor (CMOSFET) technique.The transistorized structure of TFET is the p-i-n diode based on Metal-oxide-semicondutor grid-control, as shown in Figure 1, is a typical N-shaped raceway groove TFET in prior art.Particularly, source region 1000 ' and a N-type impure drain region 2000 ' that N-type raceway groove TFET comprises a P type doping, between source region and drain region, by a channel region 3000 ', kept apart, grid stacking 4000 ' comprise the gate dielectric layer and the gate electrode that are positioned at top, channel region.
Closed condition at TFET device; while not applying grid voltage; what between source region 1000 ' and drain region 2000 ', form becomes back-biased diode; and the potential barrier of being set up by reversed biased diodes is greater than the potential barrier that common complementary type MOSFET sets up; therefore, even sub-threshold leakage current and the Direct Tunneling of TFET device reduce greatly when this has just caused channel length very short.When the grid to TFET applies voltage, under the effect of being on the scene effect, the channel region 3000 ' of device produces the passage of an electronics, once the electron concentration generation degeneracy in raceway groove, between source region 1000 ' and channel region 3000 ', will form so a tunnel junctions, the tunnelling current that tunnelling produces is by this tunnel junctions.From the angle that can be with, this tunneling field-effect transistor based on grid-control P-I-N diode structure is by control gate pole tension, to regulate the length of tunnel of formed PN junction between source region 1000 ' and channel region 3000 '.
The shortcoming of existing TFET device is: along with dwindling of the characteristic size of TFET device, between source region and channel region, the sectional area of horizontal tunnelling reduces, and causes TFET device performance to reduce; In addition, the TFET device of existing horizontal structure has restricted the further raising of its integrated level.
Summary of the invention
Object of the present invention is intended at least solve one of above-mentioned technological deficiency, particularly solves or avoid to occur the above-mentioned shortcoming of TFET device.
For achieving the above object, one aspect of the present invention proposes a kind of tunneling transistor with accurate coaxial cable structure, it is characterized in that, comprising: have the Semiconductor substrate of the first doping type, described Semiconductor substrate is source region or drain region; Be formed on the vertical semiconductor post with the second doping type in described Semiconductor substrate, described semiconductor column is drain region or source region; Be formed in described Semiconductor substrate, around the channel region of described semiconductor column sidewall; Be formed in described Semiconductor substrate, around the grid structure of described channel region sidewall.
In one embodiment of the invention, the material of described semiconductor column comprises: a kind of in Ge, SiGe or III-V family material, these semi-conducting materials not only can form heterojunction, and energy gap is little, are conducive to increase the tunnelling probability of TFET.
In one embodiment of the invention, described channel region is that extension forms, and the thickness of described channel region is less than 10nm, thereby can effectively reduce the tunnelling path of TFET.
In one embodiment of the invention, the top of described channel region is lower than the top of described semiconductor column, the top of described grid structure lower than or flush in the top of described channel region, by the source region of TFET and top portions of gates are arranged on to different horizontal planes, to avoid being positioned at the through hole (being that source region contacts and gate contact) of source region and top portions of gates, interconnect, be conducive to reduce the technology difficulty of manufacturing source region contact and gate contact.
In one embodiment of the invention, if using described semiconductor column as source region, take described Semiconductor substrate as drain region: when described semiconductor column is the heavy doping of P type, described channel region is P type weak doping, N-type weak doping or intrinsic, when described Semiconductor substrate is N-type heavy doping, form N-type tunneling field-effect transistor; When described semiconductor column is N-type heavy doping, described channel region is N-type weak doping, P type weak doping or intrinsic, when described Semiconductor substrate is the heavy doping of P type, forms P type tunneling field-effect transistor.If using described semiconductor column as drain region, take described Semiconductor substrate as source region, and, when described semiconductor column is the heavy doping of P type, described channel region is P type weak doping, N-type weak doping or intrinsic, when described Semiconductor substrate is N-type heavy doping, form P type tunneling field-effect transistor; When described semiconductor column is N-type heavy doping, described channel region is N-type weak doping, P type weak doping or intrinsic, when described Semiconductor substrate is the heavy doping of P type, forms N-type tunneling field-effect transistor.
The present invention also proposes a kind of formation method with the tunneling transistor of accurate coaxial cable structure on the other hand, comprises the following steps: Semiconductor substrate is provided, described Semiconductor substrate is carried out to first kind doping to form source region or drain region; In described Semiconductor substrate, form vertical semiconductor post, described semiconductor column is carried out to Second Type doping with the pillared drain region of shape or source region; Sidewall around described semiconductor column forms channel region; Sidewall around described channel region forms grid structure.
In one embodiment of the invention, form described vertical semiconductor post and comprise: growing semiconductor nano wire or nanobelt in described Semiconductor substrate, to form described vertical semiconductor post.The semiconductor column forming by grow nanowire or nanobelt can further form double grid or ring grid (gate-all-around) structure thereon, is conducive to increase the control ability of grid to channel region, improves effective electric field, increases tunnelling probability.
In one embodiment of the invention, the material of described semiconductor column comprises: a kind of in Ge, SiGe or III-V family material, these semi-conducting materials not only can form heterojunction, and energy gap is little, are conducive to increase the tunnelling probability of TFET.
In one embodiment of the invention, forming described source region, drain region and channel region comprises: described Semiconductor substrate is carried out to N-type heavy doping to form described source region or drain region, described semiconductor column is carried out to the heavy doping of P type to form drain region or the source region of described column, and P type weak doping, N-type weak doping or intrinsic are carried out to form described channel region in described channel region; Or, described Semiconductor substrate is carried out to the heavy doping of P type to form described source region or drain region, described semiconductor column is carried out to N-type heavy doping to form drain region or the source region of described column, and P type weak doping, N-type weak doping or intrinsic are carried out to form described channel region in described channel region.If using described semiconductor column as source region, take described Semiconductor substrate as drain region, the first doping situation forms N-type tunneling field-effect transistor, and the second doping situation forms P type tunneling field-effect transistor; If using described semiconductor column as drain region, take described Semiconductor substrate as source region, the first doping situation forms P type tunneling field-effect transistor, and the second doping situation forms N-type tunneling field-effect transistor.
In one embodiment of the invention, forming described channel region comprises the following steps: in described Semiconductor substrate and described semiconductor column surface, form described channel layer; On described channel layer, form the first mask layer, the top of described the first mask layer is lower than the top of described semiconductor column, to expose the part channel layer that is formed on described semiconductor column top; The described part channel layer that etching exposes; Remove described the first mask layer; Be formed on the described channel layer in described Semiconductor substrate with removal, so that be looped around the described channel layer of described semiconductor column sidewall, form channel region, the top of described channel region is lower than the top of described semiconductor column.In a preferred embodiment of the present invention, at described Semiconductor substrate and described semiconductor column surface epitaxial growth channel layer, the thickness of the channel layer forming by epitaxial growth can be less than 10nm, thereby can effectively reduce the tunnelling path of TFET.
In one embodiment of the invention, forming described grid structure comprises the following steps: on described Semiconductor substrate, described channel region, described semiconductor column surface, form gate dielectric layer; On described gate dielectric layer, form the second mask layer, the top of described the second mask layer lower than or flush in the top of described channel region, to expose the part gate dielectric layer that is formed on described semiconductor column top and top, described channel region; The described part gate dielectric layer that etching exposes; Remove described the second mask layer, so that remaining described gate dielectric layer forms gate medium; On described Semiconductor substrate, described gate medium, described channel region, described semiconductor column surface, form grid layer; On described grid layer, form the 3rd mask layer, the top of described the 3rd mask layer flushes in the top of described gate medium substantially, to expose the described grid layer of part that is formed on described semiconductor column top, top, described channel region and described gate medium top; The described part of grid pole layer that etching exposes; Remove described the 3rd mask layer; Be formed on the described grid layer in described Semiconductor substrate with removal, so that be looped around the described grid layer of described channel region sidewall, form grid.
In one embodiment of the invention, by deposit high density plasma oxide to form described the first mask layer, the second mask layer and the 3rd mask layer.
The invention provides a kind of tunneling transistor with accurate coaxial cable structure and forming method thereof, one side is by forming source region or drain region, channel region, grid structure to form the TFET of vertical configuration stereochemical structure on drain region or source region, thus the integrated level of raising TFET device; On the other hand by source region or drain region, channel region, grid structure in the horizontal direction structure be arranged to coaxial cable structure, ring-type tunnelling cross section from source region to channel region is with respect to common plane tunnelling cross section, tunnelling sectional area increases greatly, grid significantly strengthen the control ability of channel region, thereby improve the driving force of TFET device.
The aspect that the present invention is additional and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or the additional aspect of the present invention and advantage will become from the following description of the accompanying drawings of embodiments and obviously and easily understand, wherein:
Fig. 1 is a typical N-shaped tunneling field-effect transistor structure chart in prior art;
Fig. 2 is the stereogram of the TFET structure with accurate coaxial cable structure of the embodiment of the present invention;
Fig. 3 is the profile of the TFET structure with accurate coaxial cable structure shown in Fig. 2;
The section of structure of each step of formation method of the TFET structure with accurate coaxial cable structure that Fig. 4-12 are the embodiment of the present invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Below by the embodiment being described with reference to the drawings, be exemplary, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific technique the invention provides and the example of material, but those of ordinary skills can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are for the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
Fig. 2 and Fig. 3 are respectively stereogram and the profile of the TFET structure with accurate coaxial cable structure of the embodiment of the present invention.As shown in Figures 2 and 3, according to the TFET with accurate coaxial cable structure of the embodiment of the present invention, comprise: have the Semiconductor substrate 100 of the first doping type, Semiconductor substrate 100 is source region or the drain region of TFET; Be formed on the vertical semiconductor post 200 with the second doping type in Semiconductor substrate 100, semiconductor column 200 is drain region or the source region of TFET; Be formed in Semiconductor substrate 100, around the channel region 300 of semiconductor column 200 sidewalls; And be formed in Semiconductor substrate 100, and around the grid structure 400 of channel region 300 sidewalls.It should be noted that; in various embodiments of the present invention; using Semiconductor substrate 100 as drain region, using semiconductor column 200 as source region (for simplicity's sake; in Fig. 2 and Fig. 3, drain region is labeled as to 100; source region is labeled as 200) as example; for source-drain area being exchanged to the tunneling transistor arrangement with accurate coaxial cable structure obtaining, within being included in protection scope of the present invention equally.That is to say, according to the TFET of the embodiment of the present invention, from horizontal direction, comprise three layers of coaxial cable structure, internal layer is that 200， intermediate layer, source region is channel region 300, and skin is grid structure 400; From vertical direction, channel region, 200, intermediate layer, internal layer source region 300 and the accurate coaxial cable structure of drain region 100 formation that is positioned at the two bottom, wherein drain region 100 is equivalent to the skin of this accurate coaxial cable structure.In addition, because channel region 300 is central column, sidewall around semiconductor column 200, the tunnelling cross section from 200Dao channel region, internal layer source region 300 of this TFET structure is ring-type tunnelling cross section, plane tunnelling cross section with respect to general T FET, tunnelling sectional area increases greatly, and grid significantly strengthen the control ability of channel region, thereby improves the driving force of TFET device.
In embodiments of the present invention, the material of semiconductor column 200 can comprise a kind of in Ge, SiGe or III-V family material, and these semi-conducting materials not only can form heterojunction, and energy gap is little, are conducive to increase the tunnelling probability of TFET.
The material of Semiconductor substrate 100 can comprise the semi-conducting materials such as silicon, germanium, diamond, carborundum, GaAs, indium arsenide or indium phosphide.In addition, substrate 100 can comprise epitaxial loayer alternatively, can be by stress changes to strengthen its performance, and also can comprise silicon-on-insulator (SOI) structure.In the present embodiment, take silicon as substrate, the material in drain region 100 is silicon; Channel region 300 can be the material that is suitable as channel region known in those skilled in the art, for example silicon; The material of grid structure 400 can be polysilicon or metal.
In embodiments of the present invention, channel region 300 can form by extension, and the thickness of channel region can be less than 10nm.Due to the 200Dao channel region, Wei Cong source region, tunnelling path 300 of TFET, therefore less channel region thickness can reduce the tunnelling path of TFET effectively.
In embodiments of the present invention, preferably, the top of channel region 300 is lower than the top of semiconductor column 200, the top of grid structure 400 lower than or flush in the top of channel region 300, by the source region of TFET and top portions of gates are arranged on to different horizontal planes, to avoid being positioned at the through hole (being that source region contacts and gate contact) of source region and top portions of gates, interconnect, be conducive to reduce the technology difficulty of manufacturing source region contact and gate contact.
In embodiments of the present invention, for N-type TFET, source region 200 (semiconductor column 200) is the heavy doping of P type, and channel region 300 is P type weak doping, N-type weak doping or intrinsic, and drain region 100 (Semiconductor substrate 100) is N-type heavy doping; For P type TFET, source region 200 (semiconductor column 200) is N-type heavy doping, and channel region 300 is N-type weak doping, P type weak doping or intrinsic, and drain region 100 (Semiconductor substrate 100) is the heavy doping of P type.
The section of structure of each step of formation method of the TFET structure with accurate coaxial cable structure that Fig. 4-12 are the embodiment of the present invention.It should be noted that, the embodiment of the present invention be take and formed N-type TFET and describe this formation method as example, and the formation method of P type TFET can, with reference to following step, not repeat them here.According to the formation method of the embodiment of the present invention, comprise the following steps.
Step S101: Semiconductor substrate 100 is provided, Semiconductor substrate 100 is carried out to first kind doping to form source region or drain region.The material of Semiconductor substrate 100 can comprise the semi-conducting materials such as silicon, germanium, diamond, carborundum, GaAs, indium arsenide or indium phosphide.In addition, substrate 100 can comprise epitaxial loayer alternatively, can be by stress changes to strengthen its performance, and also can comprise silicon-on-insulator (SOI) structure.In the present embodiment, take silicon as substrate, and silicon substrate 100 is carried out to N-type heavy doping to form drain region 100.
Step S102: form vertical semiconductor post 200 in Semiconductor substrate 100, semiconductor column 200 is carried out to Second Type doping with the pillared drain region of shape or source region, as shown in Figure 4.The material of semiconductor column 200 can comprise a kind of in Ge, SiGe or III-V family material, and these semi-conducting materials not only can form heterojunction, and energy gap is little, are conducive to increase the tunnelling probability of TFET.In the present embodiment, the material of semiconductor column 200 is Ge.Semiconductor column 200 can form by photoetching process, in the preferred embodiment of the invention, on can Semiconductor substrate 100, growing semiconductor nano wire or nanobelt (for example Ge nano wire or nanobelt), to form vertical semiconductor post 200, then carry out the heavy doping of P type to form source region 200 to semiconductor column 200.The semiconductor column 200 forming by grow nanowire or nanobelt can further form double grid or ring grid (gate-all-around) structure thereon, is conducive to increase the control ability of grid to channel region, improves effective electric field, increases tunnelling probability.
Step S103: the sidewall around semiconductor column 200 forms channel region 300.Can comprise the following steps particularly:
(3-1) in Semiconductor substrate 100 and semiconductor column 200 surfaces, form channel layer 302, as shown in Figure 5.In the preferred embodiment of the invention, at Semiconductor substrate 100 and the surperficial epitaxial growth channel layer 302 of semiconductor column 200, the channel layer thickness forming by extension can be less than 10nm, and less channel region thickness can reduce the tunnelling path of TFET effectively.In the present embodiment, the material of channel layer 302 can be silicon; Channel layer 302 can be P type weak doping, N-type weak doping or intrinsic.
(3-2) on channel layer 302, form the top of the first mask layer 304, the first mask layers 304 lower than the top of semiconductor column 200, to expose the part channel layer 302 that is formed on semiconductor column 200 tops, as shown in Figure 6.Particularly, can be by deposit high-density plasma (HDP) oxide to form the first mask layer 304.Because the thickness of the first mask layer 304 has determined the height of the channel region 300 of final formation, in the present embodiment, preferably, the top of the first mask layer 304 is lower than the top of semiconductor column 200, thereby makes the top of the channel region 300 that forms lower than the top in source region 200.
(3-3) the part channel layer 302 that etching exposes, for example, material silicon that can selective etch channel layer 302.
(3-4) remove the first mask layer 304.
(3-5) remove and be formed on the channel layer 302 in Semiconductor substrate 100, so that be looped around the channel layer 302 of semiconductor column 200 sidewalls, form the top of 300， channel region, channel region lower than the top of semiconductor column 200, as shown in Figure 7.In the present embodiment, can adopt isotropic dry etch, for example adopt reactive plasma etching, the channel layer 302 that is positioned in Semiconductor substrate 100 and be looped around semiconductor column 200 sidewalls is removed to identical thickness simultaneously, and this thickness equals the thickness of the channel layer 302 on semiconductor step 306.Be pointed out that, when removal is positioned at the channel layer 302 in Semiconductor substrate 100, the height that is looped around the channel layer 302 of semiconductor column 200 sidewalls also can be therefore impaired, but because the height being etched away is only for being less than 10nm, be far smaller than the height of channel region 300, therefore this loss is negligible.
Step S104: the sidewall around channel region 300 forms grid structure 400.In this example, grid structure 400 can comprise gate medium 402 and grid 404.Forming gate medium 402 and grid 404 specifically can comprise the following steps:
(4-1) on Semiconductor substrate 100, channel region 300, semiconductor column 200 surfaces, form gate dielectric layer 401, as shown in Figure 8.The material of gate dielectric layer 401 can be high K medium material, for example comprise hafnium sill, as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), nitrogen hafnium silicon oxide (HfSiON), hafnium oxide tantalum (HfTaO), hafnium oxide titanium (HfTiO), hafnium oxide zirconium (HfZrO), its combination and/or other suitable material.The deposit of gate dielectric layer 401 can adopt conventional depositing technics to form, for example chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma enhanced atomic layer deposit (PEALD) or additive method.
(4-2) on gate dielectric layer, form the second mask layer, the top of the second mask layer is lower than the top of channel region 300, to expose the part gate dielectric layer 401 that is formed on semiconductor column 200 tops and 300 tops, channel region.Can form the second mask layer with reference to the formation method of the first mask layer 304.In like manner, because the thickness of the second mask layer has determined the height of the grid structure 400 of final formation, in the present embodiment, preferably, the top of the second mask layer lower than or flush in the top of channel region 300, thereby make the top of the grid structure 400 that forms lower than the top of channel region 300.
(4-3) the part gate dielectric layer 401 that etching exposes, for example, high K medium material that can selective etch gate dielectric layer 401.
(4-4) remove the second mask layer, so that remaining gate dielectric layer 401 forms gate medium 402, as shown in Figure 9.
(4-5) on Semiconductor substrate 100, gate medium 402, channel region 300, semiconductor column 200 surfaces, form grid layer 403, as shown in figure 10.The material of grid layer 403 can be polysilicon, the deposit of grid layer 403 can adopt conventional depositing technics to form, for example chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma enhanced atomic layer deposit (PEALD) or additive method.
(4-6) on grid layer 403, form the 3rd mask layer, the top of the 3rd mask layer flushes in the top of gate medium 402 substantially, to expose the part of grid pole layer 403 that is formed on semiconductor column 200 tops, 300 tops, channel region and gate medium 402 tops.Can form the 3rd mask layer with reference to the formation method of the first mask layer 304.
(4-7) the part of grid pole layer 403 that etching exposes, for example, material polysilicon that can selective etch grid layer 403.
(4-8) remove the 3rd mask layer.
(4-9) remove and be formed on the grid layer 403 in Semiconductor substrate 100, so that be looped around the grid layer 403 of channel region 300 sidewalls, form grid 404, as shown in figure 11.In the present embodiment, can adopt isotropic dry etch, for example, adopt reactive plasma etching, remove and be formed on the grid layer 403 in Semiconductor substrate 100.
In embodiments of the present invention, after step S104, be also included in grid 404 and source region 200 tops formation through holes and fill metal, usining and contact 407 as gate contact 405 with source region, as shown in figure 12.Because the embodiment of the present invention is arranged on different horizontal planes by the source region of TFET and top portions of gates, therefore can avoid causing being positioned at because of fabrication error the interconnective problem of through hole (being that source region contacts and gate contact) of source region and top portions of gates, be conducive to reduce the technology difficulty of manufacturing source region contact and gate contact.
The embodiment of the present invention provides a kind of tunneling transistor with accurate coaxial cable structure and forming method thereof, one side is by forming source region or drain region, channel region, grid structure to form the TFET of vertical configuration stereochemical structure on drain region or source region, thus the integrated level of raising TFET device; On the other hand by source region or drain region, channel region, grid structure in the horizontal direction structure be arranged to coaxial cable structure, ring-type tunnelling cross section from source region to channel region is with respect to common plane tunnelling cross section, tunnelling sectional area increases greatly, thereby improves the performance of TFET device.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And the specific features of description, structure, material or feature can be with suitable mode combinations in any one or more embodiment or example.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification to these embodiment, scope of the present invention is by claims and be equal to and limit.
Claims (11)
1. a tunneling transistor with accurate coaxial cable structure, is characterized in that, comprising:
The Semiconductor substrate with the first doping type, described Semiconductor substrate is source region or drain region;
Be formed on the vertical semiconductor post with the second doping type in described Semiconductor substrate, described semiconductor column is drain region or source region;
Be formed in described Semiconductor substrate, around the channel region of described semiconductor column sidewall; With
Be formed in described Semiconductor substrate, around the grid structure of described channel region sidewall, wherein, the top of described channel region is lower than the top of described semiconductor column, the top of described grid structure lower than or flush in the top of described channel region.
2. the tunneling transistor with accurate coaxial cable structure as claimed in claim 1, is characterized in that, the material of described semiconductor column comprises: Ge, SiGe or III-V family material.
3. the tunneling transistor with accurate coaxial cable structure as claimed in claim 1, is characterized in that, described channel region is that extension forms, and the thickness of described channel region is less than 10nm.
4. the tunneling transistor with accurate coaxial cable structure as claimed in claim 1, is characterized in that:
Described semiconductor column is the heavy doping of P type, and described channel region is P type weak doping, N-type weak doping or intrinsic, and described Semiconductor substrate is N-type heavy doping; Or
Described semiconductor column is N-type heavy doping, and described channel region is N-type weak doping, P type weak doping or intrinsic, and described Semiconductor substrate is the heavy doping of P type.
5. a formation method with the tunneling transistor of accurate coaxial cable structure, is characterized in that, comprises the following steps:
Semiconductor substrate is provided, described Semiconductor substrate is carried out to first kind doping to form source region or drain region;
In described Semiconductor substrate, form vertical semiconductor post, described semiconductor column is carried out to Second Type doping with the pillared drain region of shape or source region;
Sidewall around described semiconductor column forms channel region;
Sidewall around described channel region forms grid structure, wherein,
Forming described channel region comprises:
In described Semiconductor substrate and described semiconductor column surface, form channel layer;
On described channel layer, form the first mask layer, the top of described the first mask layer is lower than the top of described semiconductor column, to expose the part channel layer that is formed on described semiconductor column top;
The described part channel layer that etching exposes;
Remove described the first mask layer; With
Removal is formed on the described channel layer in described Semiconductor substrate, so that be looped around the described channel layer of described semiconductor column sidewall, forms channel region, and the top of described channel region is lower than the top of described semiconductor column.
6. the formation method with the tunneling transistor of accurate coaxial cable structure as claimed in claim 5, it is characterized in that, forming described vertical semiconductor post comprises: growing semiconductor nano wire or nanobelt in described Semiconductor substrate, and to form described vertical semiconductor post.
7. the formation method with the tunneling transistor of accurate coaxial cable structure as claimed in claim 5, is characterized in that, the material of described semiconductor column comprises: Ge, SiGe or III-V family material.
8. the formation method with the tunneling transistor of accurate coaxial cable structure as claimed in claim 5, is characterized in that, forms described source region, drain region and channel region and comprises:
Described Semiconductor substrate is carried out to N-type heavy doping to form described source region or drain region, described semiconductor column is carried out to the heavy doping of P type to form drain region or the source region of described column, and P type weak doping, N-type weak doping or intrinsic are carried out to form described channel region in described channel region; Or
Described Semiconductor substrate is carried out to the heavy doping of P type to form described source region or drain region, described semiconductor column is carried out to N-type heavy doping to form drain region or the source region of described column, and P type weak doping, N-type weak doping or intrinsic are carried out to form described channel region in described channel region.
9. the formation method with the tunneling transistor of accurate coaxial cable structure as claimed in claim 5, is characterized in that, in described Semiconductor substrate and described semiconductor column surface extension, forms described channel layer, and the thickness of described channel layer is less than 10nm.
10. the formation method with the tunneling transistor of accurate coaxial cable structure as claimed in claim 5, is characterized in that, forms described grid structure and comprises:
On described Semiconductor substrate, described channel region, described semiconductor column surface, form gate dielectric layer;
On described gate dielectric layer, form the second mask layer, the top of described the second mask layer lower than or flush in the top of described channel region, to expose the part gate dielectric layer that is formed on described semiconductor column top and top, described channel region;
The described part gate dielectric layer that etching exposes;
Remove described the second mask layer, so that remaining described gate dielectric layer forms gate medium;
On described Semiconductor substrate, described gate medium, described channel region, described semiconductor column surface, form grid layer;
On described grid layer, form the 3rd mask layer, the top of described the 3rd mask layer flushes in the top of described gate medium substantially, to expose the described grid layer of part that is formed on described semiconductor column top, top, described channel region and described gate medium top;
The described part of grid pole layer that etching exposes;
Remove described the 3rd mask layer; With
Removal is formed on the described grid layer in described Semiconductor substrate, so that be looped around the described grid layer of described channel region sidewall, forms grid.
The formation method of 11. tunneling transistors with accurate coaxial cable structure as described in claim 5 or 10, is characterized in that, by deposit high density plasma oxide to form described the first mask layer, the second mask layer and the 3rd mask layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210015260.7A CN102569405B (en) | 2012-01-17 | 2012-01-17 | Tunneling transistor with quasi-coaxial cable structure and forming method of tunneling transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210015260.7A CN102569405B (en) | 2012-01-17 | 2012-01-17 | Tunneling transistor with quasi-coaxial cable structure and forming method of tunneling transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102569405A CN102569405A (en) | 2012-07-11 |
| CN102569405B true CN102569405B (en) | 2014-02-19 |
Family
ID=46414364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210015260.7A Active CN102569405B (en) | 2012-01-17 | 2012-01-17 | Tunneling transistor with quasi-coaxial cable structure and forming method of tunneling transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102569405B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579324B (en) * | 2013-11-18 | 2016-04-06 | 北京大学 | A kind of three source tunneling field-effect transistors and preparation method thereof |
| CN108807660A (en) * | 2017-05-02 | 2018-11-13 | 上海磁宇信息科技有限公司 | Use the ultra high density random access memory framework of vertical-type circulating type field-effect transistor |
| CN110729360B (en) * | 2019-10-25 | 2022-12-09 | 中国科学院微电子研究所 | Nanotube device and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101410963A (en) * | 2006-04-04 | 2009-04-15 | 美光科技公司 | Nanowire transistor with surrounding gate |
| CN101635309A (en) * | 2008-07-25 | 2010-01-27 | 海力士半导体有限公司 | All around gate type semiconductor device and method of manufacturing the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7888721B2 (en) * | 2005-07-06 | 2011-02-15 | Micron Technology, Inc. | Surround gate access transistors with grown ultra-thin bodies |
| JP5460950B2 (en) * | 2007-06-06 | 2014-04-02 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device and manufacturing method thereof |
-
2012
- 2012-01-17 CN CN201210015260.7A patent/CN102569405B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101410963A (en) * | 2006-04-04 | 2009-04-15 | 美光科技公司 | Nanowire transistor with surrounding gate |
| CN101635309A (en) * | 2008-07-25 | 2010-01-27 | 海力士半导体有限公司 | All around gate type semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102569405A (en) | 2012-07-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7834345B2 (en) | Tunnel field-effect transistors with superlattice channels | |
| US8697510B2 (en) | Tunnel field-effect transistor with narrow band-gap channel and strong gate coupling | |
| US8629420B1 (en) | Drain extended MOS device for bulk FinFET technology | |
| CN102184955B (en) | Complementary tunneling field effect transistor and forming method thereof | |
| KR20150005584A (en) | A Method of Fabricating Tunnel Transistors with Abrupt Junctions | |
| US8614468B2 (en) | Mask-less and implant free formation of complementary tunnel field effect transistors | |
| TWI613830B (en) | Tunneling field effect transistor and methods of making such a transistor | |
| CN104465657A (en) | Complementary tfet and manufacturing method thereof | |
| US20120223390A1 (en) | Tunneling field effect transistor and method for forming the same | |
| CN104517847B (en) | Nodeless mesh body pipe and forming method thereof | |
| US10896974B2 (en) | Method of fabricating semiconductor device | |
| CN102169901A (en) | Tunneling field effect transistor having heterogeneous grid work function and formation method thereof | |
| WO2015066971A1 (en) | Junction modulation-type tunnelling field effect transistor and preparation method therefor | |
| CN105633147A (en) | Tunneling field effect transistor and manufacturing method thereof | |
| KR20140088658A (en) | Independent and Different Work Fuction Double Gated electron-hole Bilayer Tunnel Field Effect Transistor and its Fabrication Method | |
| CN102569405B (en) | Tunneling transistor with quasi-coaxial cable structure and forming method of tunneling transistor | |
| US20110284934A1 (en) | Semiconductor device and method of fabricating the same | |
| CN105118858A (en) | A vertical tunneling field effect transistor | |
| CN104576721A (en) | Tunneling field effect transistor with electric field concentration effect to enhance on state current | |
| KR101682420B1 (en) | Self-aligned heterojunction tunnel field-effect transistor using selective germanium condensation and sidewall processes | |
| WO2016029711A1 (en) | Tunnel field effect transistor and manufacturing method thereof | |
| KR101367989B1 (en) | A fabrication method of ultra-thin finfet and the ultra-thin finfet fabricated by this method. | |
| CN102544105B (en) | Tunnel transistor with quasi-coaxial cable structure and forming method thereof | |
| US11201246B2 (en) | Field-effect transistor structure and fabrication method | |
| CN103123899A (en) | FinFET (field effect transistor) device manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |