CN102569405A - Tunneling transistor with quasi-coaxial cable structure and forming method of tunneling transistor - Google Patents
Tunneling transistor with quasi-coaxial cable structure and forming method of tunneling transistor Download PDFInfo
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Abstract
The invention provides a tunneling transistor with a quasi-coaxial cable structure and a forming method of the tunneling transistor. The tunneling transistor comprises a semiconductor substrate with a first doping type, a vertical semiconductor column, a channel region and a grid structure, wherein the semiconductor substrate is of a source region or a drain region; the vertical semiconductor column with a second doping type is formed on the semiconductor substrate, wherein the semiconductor column is of a source region or drain region; the channel region is formed on the semiconductor substrate and surrounds the lateral wall of the semiconductor column; and the grid structure is formed on the semiconductor substrate and surrounds the lateral wall of the channel region. According to the tunneling transistor provided by the embodiment of the invention, the integration level of a TFET (Tunneling Field Effect Transistor) device can be increased, and the driving capability of the TFET device is improved.
Description
Technical field
The present invention relates to semiconductor design and manufacturing technology field, particularly a kind of tunneling transistor and forming method thereof with accurate coaxial cable structure.
Background technology
For a long time, in order to obtain higher chip density, operating rate and lower power consumption faster.It is constantly scaled that the characteristic size of metal-oxide semiconductor fieldeffect transistor (MOSFET) is being followed so-called Moore's Law (Moore ' slaw) always, and its operating rate is more and more faster.The current scope that has entered into nanoscale.Yet; Serious challenge of the thing followed is short-channel effect to have occurred; For example subthreshold voltage drop (Vtroll-off), drain electrode cause that potential barrier reduces (DIBL), break-through phenomenons such as (punch through) is leaked in the source; Make the off-state leakage current of device enlarge markedly, thereby cause performance to worsen.
Current, in order to reduce the negative effect that short-channel effect brings, people have proposed various corrective measures, and wherein particularly outstanding is tunneling field-effect transistor (tunneling field effect transistor, TFET).Because when the MOSFET device was in the subthreshold value state, device was weak transoid, this moment, thermionic emission was main conductive mechanism, and therefore, at room temperature the sub-threshold slope of MOSFET is subject to 60mV/dec.For traditional MOSFET, on the one hand, because the active area of tunneling field-effect transistor device is essentially tunnel junctions, therefore, tunneling field-effect transistor has more weak even does not have short-channel effect; Simultaneously; The main current machine of tunneling field-effect transistor is made as band-band tunnelling (band-to-band tunneling); Be exponential relationship in sub-threshold region and saturation region drain current with the gate source voltage that adds; Therefore tunneling field-effect transistor has lower sub-threshold slope, and electric current receives Influence of Temperature hardly.
The preparation technology of tunneling field-effect transistor is compatible mutually with traditional complementary type metal-oxide semiconductor fieldeffect transistor (CMOSFET) technology.The transistorized structure of TFET is based on the p-i-n diode of Metal-oxide-semicondutor grid-control, and is as shown in Figure 1, is typical n type raceway groove TFET in the prior art.Particularly; N type raceway groove TFET comprises source region 1000 ' and N type impure drain region 2000 ' that a P type mixes; Kept apart by a channel region 3000 ' between source region and the drain region, grid pile up 4000 ' and comprise a gate dielectric layer and a gate electrode that is positioned at the channel region top.
Closed condition at the TFET device; When promptly not applying grid voltage; What form between source region 1000 ' and the drain region 2000 ' becomes back-biased diode; And the potential barrier that the potential barrier of being set up by reversed biased diodes is set up greater than complementary type MOSFET usually, therefore, even the sub-threshold leakage current and the direct Tunneling electric current of this TFET device when just having caused channel length very short reduce greatly.When the grid to TFET applies voltage; The channel region 3000 ' of device produces the passage of an electronics under the effect of field effect; In case the electron concentration generation degeneracy in the raceway groove; Between source region 1000 ' and channel region 3000 ', will form a tunnel junctions so, the tunnelling current that tunnelling produces is through this tunnel junctions.From the angle that can be with, this tunneling field-effect transistor based on grid-control P-I-N diode structure is a length of tunnel of regulating formed PN junction between source region 1000 ' and the channel region 3000 ' through the control gate pole tension.
The shortcoming of existing TFET device is: along with dwindling of the characteristic size of TFET device, the sectional area of horizontal tunnelling reduces between source region and the channel region, causes the TFET device performance to reduce; In addition, the TFET device of existing horizontal structure has restricted the further raising of its integrated level.
Summary of the invention
The object of the invention is intended to solve at least one of above-mentioned technological deficiency, particularly solves or avoid to occur the above-mentioned shortcoming of TFET device.
For achieving the above object, one aspect of the present invention proposes a kind of tunneling transistor with accurate coaxial cable structure, it is characterized in that comprise: have the Semiconductor substrate of first doping type, said Semiconductor substrate is source region or drain region; Be formed on the vertical semiconductor post with second doping type on the said Semiconductor substrate, said semiconductor column is drain region or source region; Be formed on the said Semiconductor substrate, around the channel region of said semiconductor column sidewall; Be formed on the said Semiconductor substrate, around the grid structure of said channel region sidewall.
In one embodiment of the invention, the material of said semiconductor column comprises: a kind of in Ge, SiGe or the III-V family material, these semi-conducting materials not only can form heterojunction, and energy gap is little, help increasing the tunnelling probability of TFET.
In one embodiment of the invention, said channel region is that extension forms, and the thickness of said channel region is less than 10nm, thereby can reduce the tunnelling path of TFET effectively.
In one embodiment of the invention; The top of said channel region is lower than the top of said semiconductor column; The top of said grid structure is lower than or flushes in the top of said channel region; Source region and top portions of gates through with TFET are arranged on the different horizontal face, interconnect with the through hole of avoiding being positioned at source region and top portions of gates (be source region contact with grid contact), help reducing making the technology difficulty that the source region contact contacts with grid.
In one embodiment of the invention; If with said semiconductor column as the source region; With said Semiconductor substrate is the drain region: then working as said semiconductor column is the heavy doping of P type; Said channel region is P type weak doping, N type weak doping or intrinsic, when said Semiconductor substrate is the heavy doping of N type, constitutes N type tunneling field-effect transistor; When said semiconductor column is the heavy doping of N type, said channel region is N type weak doping, P type weak doping or intrinsic, when said Semiconductor substrate is the heavy doping of P type, constitutes P type tunneling field-effect transistor.If with said semiconductor column as the drain region; With said Semiconductor substrate is the source region, and then working as said semiconductor column is the heavy doping of P type, and said channel region is P type weak doping, N type weak doping or intrinsic; When said Semiconductor substrate is the heavy doping of N type, constitute P type tunneling field-effect transistor; When said semiconductor column is the heavy doping of N type, said channel region is N type weak doping, P type weak doping or intrinsic, when said Semiconductor substrate is the heavy doping of P type, constitutes N type tunneling field-effect transistor.
The present invention also proposes a kind of formation method with tunneling transistor of accurate coaxial cable structure on the other hand, may further comprise the steps: Semiconductor substrate is provided, said Semiconductor substrate is carried out the first kind mix to form source region or drain region; On said Semiconductor substrate, form the vertical semiconductor post, said semiconductor column is carried out second type mix to form the drain region or the source region of column; Sidewall around said semiconductor column forms channel region; Sidewall around said channel region forms the grid structure.
In one embodiment of the invention, form said vertical semiconductor post and comprise: growing semiconductor nano wire or nano belt on said Semiconductor substrate, to form said vertical semiconductor post.The semiconductor column that forms through grow nanowire or nano belt can further form double grid or ring grid (gate-all-around) structure above that, helps increasing the control ability of grid to channel region, improves effective electric field, increases the tunnelling probability.
In one embodiment of the invention, the material of said semiconductor column comprises: a kind of in Ge, SiGe or the III-V family material, these semi-conducting materials not only can form heterojunction, and energy gap is little, help increasing the tunnelling probability of TFET.
In one embodiment of the invention; Forming said source region, drain region and channel region comprises: said Semiconductor substrate is carried out the heavy doping of N type to form said source region or drain region; Said semiconductor column is carried out drain region or the source region of P type heavy doping to form said column, and said channel region is carried out P type weak doping, N type weak doping or intrinsic to form said channel region; Perhaps; Said Semiconductor substrate is carried out the heavy doping of P type to form said source region or drain region; Said semiconductor column is carried out drain region or the source region of N type heavy doping to form said column, and said channel region is carried out P type weak doping, N type weak doping or intrinsic to form said channel region.If as the source region, is drain region with said Semiconductor substrate with said semiconductor column, then first kind of doping situation constitutes N type tunneling field-effect transistor, and second kind of doping situation constitutes P type tunneling field-effect transistor; If as the drain region, is source region with said Semiconductor substrate with said semiconductor column, then first kind of doping situation constitutes P type tunneling field-effect transistor, and second kind of doping situation constitutes N type tunneling field-effect transistor.
In one embodiment of the invention, forming said channel region may further comprise the steps: form said channel layer in said Semiconductor substrate and said semiconductor column surface; On said channel layer, form first mask layer, the top of said first mask layer is lower than the top of said semiconductor column, is formed on the part channel layer at said semiconductor column top with exposure; The said part channel layer that etching exposes; Remove said first mask layer; Be formed on the said channel layer on the said Semiconductor substrate with removal, form channel region so that be looped around the said channel layer of said semiconductor column sidewall, the top of said channel region is lower than the top of said semiconductor column.In a preferred embodiment of the present invention, at said Semiconductor substrate and said semiconductor column surface epitaxial growth channel layer, the thickness of the channel layer that forms through epitaxial growth can be less than 10nm, thereby can reduce the tunnelling path of TFET effectively.
In one embodiment of the invention, forming said grid structure may further comprise the steps: form gate dielectric layer on said Semiconductor substrate, said channel region, said semiconductor column surface; On said gate dielectric layer, form second mask layer, the top of said second mask layer is lower than or flushes in the top of said channel region, is formed on the part gate dielectric layer at said semiconductor column top and said channel region top with exposure; The said part gate dielectric layer that etching exposes; Remove said second mask layer, so that remaining said gate dielectric layer forms gate medium; Form grid layer on said Semiconductor substrate, said gate medium, said channel region, said semiconductor column surface; On said grid layer, form the 3rd mask layer, the top of said the 3rd mask layer flushes in the top of said gate medium basically, is formed on the said grid layer of part at said semiconductor column top, said channel region top and said gate medium top with exposure; The said part of grid pole layer that etching exposes; Remove said the 3rd mask layer; Be formed on the said grid layer on the said Semiconductor substrate with removal, form grid so that be looped around the said grid layer of said channel region sidewall.
In one embodiment of the invention, through the deposit high density plasma oxide to form said first mask layer, second mask layer and the 3rd mask layer.
The present invention provides a kind of tunneling transistor with accurate coaxial cable structure and forming method thereof; On the one hand through on drain region or source region, forming source region or drain region, channel region, grid structure constituting the TFET of vertical configuration stereochemical structure, thereby improve the integrated level of TFET device; On the other hand with source region or drain region, channel region, grid structure in the horizontal direction structure be arranged to coaxial cable structure; Ring-type tunnelling cross section from the source region to the channel region is with respect to common planar tunnelling cross section; The tunnelling sectional area increases greatly; Grid significantly strengthen the control ability of channel region, thereby improve the driving force of TFET device.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize through practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is typical n type tunneling field-effect transistor structure chart in the prior art;
Fig. 2 is the stereogram of the TFET structure with accurate coaxial cable structure of the embodiment of the invention;
Fig. 3 is the profile of the TFET structure with accurate coaxial cable structure shown in Figure 2;
Fig. 4-12 is the section of structure of each step of formation method of the TFET structure with accurate coaxial cable structure of the embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing of hereinafter provides many various embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition; First characteristic of below describing second characteristic it " on " structure can comprise that first and second characteristics form the embodiment of direct contact; Can comprise that also additional features is formed on the embodiment between first and second characteristics, such first and second characteristics possibly not be direct contacts.
Fig. 2 and Fig. 3 are respectively the stereogram and the profile of the TFET structure with accurate coaxial cable structure of the embodiment of the invention.As shown in Figures 2 and 3, the TFET with accurate coaxial cable structure according to the embodiment of the invention comprises: have the Semiconductor substrate 100 of first doping type, Semiconductor substrate 100 is source region or the drain region of TFET; Be formed on the vertical semiconductor post 200 with second doping type on the Semiconductor substrate 100, semiconductor column 200 is drain region or the source region of TFET; Be formed on the Semiconductor substrate 100, around the channel region 300 of semiconductor column 200 sidewalls; And be formed on the Semiconductor substrate 100, and around the grid structure 400 of channel region 300 sidewalls.What need explanation is; In various embodiments of the present invention; With Semiconductor substrate 100 as the drain region, with semiconductor column 200 as an example as source region (for for simplicity, among Fig. 2 and Fig. 3 the drain region is labeled as 100, the source region is labeled as 200); For source-drain area is exchanged the tunneling transistor arrangement with accurate coaxial cable structure that obtains, be included within protection scope of the present invention equally.That is to say that the TFET according to the embodiment of the invention sees from horizontal direction, comprise three layers of coaxial cable structure, internal layer is source region 200, and the intermediate layer is a channel region 300, and skin is a grid structure 400; See from vertical direction, internal layer source region 200, intermediate layer channel region 300 and the accurate coaxial cable structure of drain region 100 formations that is positioned at the two bottom, wherein drain region 100 is equivalent to the skin of this accurate coaxial cable structure.In addition; Because channel region 300 is central column, around the sidewall of semiconductor column 200,300 the tunnelling cross section from internal layer source region 200 to channel region of this TFET structure is ring-type tunnelling cross section; Tunnelling cross section, plane with respect to general T FET; The tunnelling sectional area increases greatly, and grid significantly strengthen the control ability of channel region, thereby improves the driving force of TFET device.
In embodiments of the present invention, the material of semiconductor column 200 can comprise a kind of in Ge, SiGe or the III-V family material, and these semi-conducting materials not only can form heterojunction, and energy gap is little, help increasing the tunnelling probability of TFET.
The material of Semiconductor substrate 100 can comprise semi-conducting materials such as silicon, germanium, diamond, carborundum, GaAs, indium arsenide or indium phosphide.In addition, substrate 100 can comprise epitaxial loayer alternatively, can be by stress changes strengthening its performance, and also can comprise silicon-on-insulator (SOI) structure.In the present embodiment, be substrate with silicon, promptly the material in drain region 100 is a silicon; Channel region 300 can be the material that is suitable as channel region known in those skilled in the art, for example silicon; The material of grid structure 400 can be polysilicon or metal.
In embodiments of the present invention, channel region 300 can form through extension, and the thickness of channel region can be less than 10nm.Because the tunnelling path of TFET is 200 to channel region 300, so less channel region thickness can reduce the tunnelling path of TFET effectively from the source region.
In embodiments of the present invention; Preferably; The top of channel region 300 is lower than the top of semiconductor column 200, and the top of grid structure 400 is lower than or flushes in the top of channel region 300, is arranged on the different horizontal face through source region and top portions of gates with TFET; Interconnect with the through hole of avoiding being positioned at source region and top portions of gates (be source region contact contact), help reducing and make the technology difficulty that the source region contact contacts with grid with grid.
In embodiments of the present invention, for N type TFET, source region 200 (semiconductor column 200) is the heavy doping of P type, and channel region 300 is P type weak doping, N type weak doping or intrinsic, and drain region 100 (Semiconductor substrate 100) is the heavy doping of N type; For P type TFET, source region 200 (semiconductor column 200) is the heavy doping of N type, and channel region 300 is N type weak doping, P type weak doping or intrinsic, and drain region 100 (Semiconductor substrate 100) is the heavy doping of P type.
Fig. 4-12 is the section of structure of each step of formation method of the TFET structure with accurate coaxial cable structure of the embodiment of the invention.What need explanation is, the embodiment of the invention is that example describes should the formation method to form N type TFET, and the formation method of P type TFET can repeat no more at this with reference to following step.Formation method according to the embodiment of the invention may further comprise the steps.
Step S101: Semiconductor substrate 100 is provided, Semiconductor substrate 100 is carried out the first kind mix to form source region or drain region.The material of Semiconductor substrate 100 can comprise semi-conducting materials such as silicon, germanium, diamond, carborundum, GaAs, indium arsenide or indium phosphide.In addition, substrate 100 can comprise epitaxial loayer alternatively, can be by stress changes strengthening its performance, and also can comprise silicon-on-insulator (SOI) structure.In the present embodiment, be substrate with silicon, and silicon substrate 100 is carried out the heavy doping of N type to form drain region 100.
Step S102: on Semiconductor substrate 100, form vertical semiconductor post 200, semiconductor column 200 is carried out second type mix to form the drain region or the source region of column, as shown in Figure 4.The material of semiconductor column 200 can comprise a kind of in Ge, SiGe or the III-V family material, and these semi-conducting materials not only can form heterojunction, and energy gap is little, help increasing the tunnelling probability of TFET.In the present embodiment, the material of semiconductor column 200 is Ge.Semiconductor column 200 can form through photoetching process; In the preferred embodiment of the invention; Growing semiconductor nano wire or nano belt (for example Ge nano wire or nano belt) are carried out the heavy doping of P type to form source region 200 to semiconductor column 200 then to form vertical semiconductor post 200 on can Semiconductor substrate 100.The semiconductor column 200 that forms through grow nanowire or nano belt can further form double grid or ring grid (gate-all-around) structure above that, helps increasing the control ability of grid to channel region, improves effective electric field, increases the tunnelling probability.
Step S103: the sidewall around semiconductor column 200 forms channel region 300.Can may further comprise the steps particularly:
(3-1) form channel layer 302 on Semiconductor substrate 100 and semiconductor column 200 surfaces, as shown in Figure 5.In the preferred embodiment of the invention; At Semiconductor substrate 100 and semiconductor column 200 surperficial epitaxial growth channel layers 302; The channel layer thickness that forms through extension can be less than 10nm, and less channel region thickness can reduce the tunnelling path of TFET effectively.In the present embodiment, the material of channel layer 302 can be a silicon; Channel layer 302 can be P type weak doping, N type weak doping or intrinsic.
The top that (3-2) on channel layer 302, forms first mask layer, 304, the first mask layers 304 is lower than the top of semiconductor column 200, is formed on the part channel layer 302 at semiconductor column 200 tops with exposure, and is as shown in Figure 6.Particularly, can be through deposit high-density plasma (HDP) oxide to form first mask layer 304.Because the thickness of first mask layer 304 has determined the height of the channel region 300 of final formation; In the present embodiment; Preferably, the top of first mask layer 304 is lower than the top of semiconductor column 200, thereby makes the top of the channel region 300 of formation be lower than the top in source region 200.
(3-3) etching exposed portions channel layer 302, for example, material silicon that can selective etch channel layer 302.
(3-4) remove first mask layer 304.
(3-5) removal is formed on the channel layer 302 on the Semiconductor substrate 100, forms channel region 300 so that be looped around the channel layer 302 of semiconductor column 200 sidewalls, and the top of channel region is lower than the top of semiconductor column 200, and is as shown in Figure 7.In the present embodiment; Can adopt isotropic dry etch; For example adopt the reactive plasma etching; The channel layer 302 that will be positioned on the Semiconductor substrate 100 and be looped around semiconductor column 200 sidewalls is removed identical thickness simultaneously, and this thickness equals the thickness of the channel layer 302 on the semiconductor step 306.Be pointed out that; When removal is positioned at the channel layer 302 on the Semiconductor substrate 100; The height that is looped around the channel layer 302 of semiconductor column 200 sidewalls also can be therefore impaired; But, be far smaller than the height of channel region 300, so this loss can be ignored because the height that is etched away is merely less than 10nm.
Step S104: the sidewall around channel region 300 forms grid structure 400.In this example, grid structure 400 can comprise gate medium 402 and grid 404.Forming gate medium 402 specifically can may further comprise the steps with grid 404:
(4-1) form gate dielectric layer 401 on Semiconductor substrate 100, channel region 300, semiconductor column 200 surfaces, as shown in Figure 8.The material of gate dielectric layer 401 can be the high K medium material, for example comprises the hafnium sill, like hafnium oxide (HfO2); Hafnium silicon oxide (HfSiO), nitrogen hafnium silicon oxide (HfSiON), hafnium oxide tantalum (HfTaO); Hafnium oxide titanium (HfTiO), hafnium oxide zirconium (HfZrO), its combination and/or other suitable material.The deposit of gate dielectric layer 401 can adopt conventional depositing technics to form, for example chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma enhanced atomic layer deposit (PEALD) or additive method.
(4-2) on gate dielectric layer, form second mask layer, the top of second mask layer is lower than the top of channel region 300, is formed on the part gate dielectric layer 401 at semiconductor column 200 tops and channel region 300 tops with exposure.Can form second mask layer with reference to the formation method of first mask layer 304.In like manner; Because the thickness of second mask layer has determined the height of the grid structure 400 of final formation, in the present embodiment, preferably; The top of second mask layer is lower than or flushes in the top of channel region 300, thereby makes the top of the grid structure 400 of formation be lower than the top of channel region 300.
(4-3) etching exposed portions gate dielectric layer 401, for example, high K medium material that can selective etch gate dielectric layer 401.
(4-4) remove second mask layer, so that it is remaining gate dielectric layer 401 forms gate medium 402, as shown in Figure 9.
(4-5) form grid layer 403 on Semiconductor substrate 100, gate medium 402, channel region 300, semiconductor column 200 surfaces, shown in figure 10.The material of grid layer 403 can be a polysilicon; The deposit of grid layer 403 can adopt conventional depositing technics to form, for example chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma enhanced atomic layer deposit (PEALD) or additive method.
(4-6) on grid layer 403, form the 3rd mask layer, the top of the 3rd mask layer flushes in the top of gate medium 402 basically, is formed on the part of grid pole layer 403 at semiconductor column 200 tops, channel region 300 tops and gate medium 402 tops with exposure.Can form the 3rd mask layer with reference to the formation method of first mask layer 304.
(4-7) etching exposed portions grid layer 403, for example, material polysilicon that can selective etch grid layer 403.
(4-8) remove the 3rd mask layer.
(4-9) removal is formed on the grid layer 403 on the Semiconductor substrate 100, forms grid 404 so that be looped around the grid layer 403 of channel region 300 sidewalls, and is shown in figure 11.In the present embodiment, can adopt isotropic dry etch, for example adopt the reactive plasma etching, remove and be formed on the grid layer 403 on the Semiconductor substrate 100.
In embodiments of the present invention, after step S104, also be included in grid 404 and form through hole and fill metal with 200 tops, source region, to contact 407 with the source region, shown in figure 12 as grid contact 405.Because the embodiment of the invention is arranged on the different horizontal face with source region and the top portions of gates of TFET; So can avoid causing being positioned at the interconnective problem of through hole (be source region contact contact) of source region and top portions of gates, help reducing the manufacturing source region and contact the technology difficulty that contacts with grid with grid because of fabrication error.
The embodiment of the invention provides a kind of tunneling transistor with accurate coaxial cable structure and forming method thereof; On the one hand through on drain region or source region, forming source region or drain region, channel region, grid structure constituting the TFET of vertical configuration stereochemical structure, thereby improve the integrated level of TFET device; On the other hand with source region or drain region, channel region, grid structure in the horizontal direction structure be arranged to coaxial cable structure; Ring-type tunnelling cross section from the source region to the channel region is with respect to common planar tunnelling cross section; The tunnelling sectional area increases greatly, thereby improves the performance of TFET device.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means the concrete characteristic, structure, material or the characteristics that combine this embodiment or example to describe and is contained at least one embodiment of the present invention or the example.In this manual, the schematic statement to above-mentioned term not necessarily refers to identical embodiment or example.And concrete characteristic, structure, material or the characteristics of description can combine with suitable manner in any one or more embodiment or example.
Although illustrated and described embodiments of the invention; For those of ordinary skill in the art; Be appreciated that under the situation that does not break away from principle of the present invention and spirit and can carry out multiple variation, modification, replacement and modification that scope of the present invention is accompanying claims and be equal to and limit to these embodiment.
Claims (13)
1. the tunneling transistor with accurate coaxial cable structure is characterized in that, comprising:
Semiconductor substrate with first doping type, said Semiconductor substrate are source region or drain region;
Be formed on the vertical semiconductor post with second doping type on the said Semiconductor substrate, said semiconductor column is drain region or source region;
Be formed on the said Semiconductor substrate, around the channel region of said semiconductor column sidewall; With
Be formed on the said Semiconductor substrate, around the grid structure of said channel region sidewall.
2. the tunneling transistor with accurate coaxial cable structure as claimed in claim 1 is characterized in that, the material of said semiconductor column comprises: Ge, SiGe or III-V family material.
3. the tunneling transistor with accurate coaxial cable structure as claimed in claim 1 is characterized in that, said channel region is that extension forms, and the thickness of said channel region is less than 10nm.
4. the tunneling transistor with accurate coaxial cable structure as claimed in claim 1 is characterized in that, the top of said channel region is lower than the top of said semiconductor column, and the top of said grid structure is lower than or flushes in the top of said channel region.
5. the tunneling transistor with accurate coaxial cable structure as claimed in claim 1 is characterized in that:
Said semiconductor column is the heavy doping of P type, and said channel region is P type weak doping, N type weak doping or intrinsic, and said Semiconductor substrate is the heavy doping of N type; Perhaps
Said semiconductor column is the heavy doping of N type, and said channel region is N type weak doping, P type weak doping or intrinsic, and said Semiconductor substrate is the heavy doping of P type.
6. the formation method with tunneling transistor of accurate coaxial cable structure is characterized in that, may further comprise the steps:
Semiconductor substrate is provided, said Semiconductor substrate is carried out the first kind mix to form source region or drain region;
On said Semiconductor substrate, form the vertical semiconductor post, said semiconductor column is carried out second type mix to form the drain region or the source region of column;
Sidewall around said semiconductor column forms channel region;
Sidewall around said channel region forms the grid structure.
7. the formation method with tunneling transistor of accurate coaxial cable structure as claimed in claim 6; It is characterized in that; Forming said vertical semiconductor post comprises: growing semiconductor nano wire or nano belt on said Semiconductor substrate, and to form said vertical semiconductor post.
8. the formation method with tunneling transistor of accurate coaxial cable structure as claimed in claim 6 is characterized in that the material of said semiconductor column comprises: Ge, SiGe or III-V family material.
9. the formation method with tunneling transistor of accurate coaxial cable structure as claimed in claim 6 is characterized in that, forms said source region, drain region and channel region and comprises:
Said Semiconductor substrate is carried out the heavy doping of N type to form said source region or drain region; Said semiconductor column is carried out drain region or the source region of P type heavy doping to form said column, and said channel region is carried out P type weak doping, N type weak doping or intrinsic to form said channel region; Perhaps
Said Semiconductor substrate is carried out the heavy doping of P type to form said source region or drain region; Said semiconductor column is carried out drain region or the source region of N type heavy doping to form said column, and said channel region is carried out P type weak doping, N type weak doping or intrinsic to form said channel region.
10. the formation method with tunneling transistor of accurate coaxial cable structure as claimed in claim 6 is characterized in that, forms said channel region and comprises:
Form channel layer in said Semiconductor substrate and said semiconductor column surface;
On said channel layer, form first mask layer, the top of said first mask layer is lower than the top of said semiconductor column, is formed on the part channel layer at said semiconductor column top with exposure;
The said part channel layer that etching exposes;
Remove said first mask layer; With
Removal is formed on the said channel layer on the said Semiconductor substrate, forms channel region so that be looped around the said channel layer of said semiconductor column sidewall, and the top of said channel region is lower than the top of said semiconductor column.
11. the formation method with tunneling transistor of accurate coaxial cable structure as claimed in claim 10 is characterized in that, forms said channel layer in said Semiconductor substrate and said semiconductor column surface extension, the thickness of said channel layer is less than 10nm.
12. the formation method with tunneling transistor of accurate coaxial cable structure as claimed in claim 6 is characterized in that, forms said grid structure and comprises:
Form gate dielectric layer on said Semiconductor substrate, said channel region, said semiconductor column surface;
On said gate dielectric layer, form second mask layer, the top of said second mask layer is lower than or flushes in the top of said channel region, is formed on the part gate dielectric layer at said semiconductor column top and said channel region top with exposure;
The said part gate dielectric layer that etching exposes;
Remove said second mask layer, so that remaining said gate dielectric layer forms gate medium;
Form grid layer on said Semiconductor substrate, said gate medium, said channel region, said semiconductor column surface;
On said grid layer, form the 3rd mask layer, the top of said the 3rd mask layer flushes in the top of said gate medium basically, is formed on the said grid layer of part at said semiconductor column top, said channel region top and said gate medium top with exposure;
The said part of grid pole layer that etching exposes;
Remove said the 3rd mask layer; With
Removal is formed on the said grid layer on the said Semiconductor substrate, forms grid so that be looped around the said grid layer of said channel region sidewall.
13. like claim 10 or 12 described formation methods, it is characterized in that with tunneling transistor of accurate coaxial cable structure, through the deposit high density plasma oxide to form said first mask layer, second mask layer and the 3rd mask layer.
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