CN108321197A - Tunneling field effect transistor and manufacturing method thereof - Google Patents
Tunneling field effect transistor and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 230000005641 tunneling Effects 0.000 title abstract description 7
- 238000002353 field-effect transistor method Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 230000005669 field effect Effects 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims description 22
- 230000005621 ferroelectricity Effects 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 6
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- 230000000694 effects Effects 0.000 abstract description 3
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a tunneling field effect transistor and a manufacturing method thereof.A formed source region is positioned under a part of a gate structure and in a substrate on the side surface of the gate structure, namely the gate structure is overlapped to cover a part of the source region, so that the potential control capability of gate voltage on a source region/a channel region of a device can be improved, further, the area of the source region is larger than that of the drain region, the doping concentration of the source region is higher than that of the drain region, the carrier concentration of the source region is generally higher than that of the drain region, and a finally formed gate with a ferroelectric gate layer has a negative capacitance effect, can amplify the surface potential of the gate, can increase the tunneling probability of the device and integrally improve the on-state current of the device.
Description
Technical field
The present invention relates to semiconductor devices and its manufacturing field, more particularly to a kind of tunnel field-effect transistor and its manufacture
Method.
Background technology
With the continuous development of integrated circuit technique, device size constantly reduces, cause device short-channel effect and
The problems such as Leakage Current, is more and more prominent, and the power consumption of circuit is caused to be continuously increased.It is brilliant for traditional metal oxide field effect
Body pipe (MOSFET) device, is limited to the flooding mechanism of carrier, at normal temperatures subthreshold swing (SS) nothing of MOSFET element
Method breaks through 60mV/dec, this has seriously affected the switching rate under corresponding gate voltage, has caused leakage current with supply voltage
Reduction be exponentially increased.
Tunneling field-effect transistor (TFET, Tunneling Field Effect Transistor), operation principle is
Band-to-band-tunneling mechanism, it is sub- since firing current and the temperature of TFET do not have index dependence from operation principle
Threshold current is not limited by carrier heat distribution, and SS may be implemented to be less than 60meV/dec, to reduce power consumption, reducing device
Cut-off current provides a kind of approach.However, being limited by tunnelling probability, traditional TFET tunnelling currents are smaller, it is difficult to which satisfaction is answered
Use demand.
Invention content
In view of this, the purpose of the present invention is to provide a kind of tunnel field-effect transistor and its manufacturing method, device is improved
The tunnel probability and tunnel electric current of part.
To achieve the above object, the present invention has following technical solution：
A kind of tunnel field-effect transistor, including：
Substrate；
Grid structure on substrate, the grid structure include gate dielectric layer and grid thereon；
Drain region in the substrate of the grid structure side；
Source region under the grid structure of part and in the substrate of the grid structure other side, the source region and institute
Stating drain region has different doping types.
Optionally, the area of the source region is more than the area in the drain region.
Optionally, the doping concentration of the source region is higher than the doping concentration in the drain region.
Optionally, the high an order of magnitude of doping concentration in at least more described drain region of the doping concentration of the source region.
Optionally, further include：There is the heterogeneous channel layer of different materials, the heterogeneous channel layer to be located at institute with the substrate
It states in the substrate under grid structure and is covered by the grid structure, the heterogeneous channel layer is close to one end of the source region embedded in described
In source region.
Optionally, the substrate is silicon substrate, and the heterogeneous channel layer includes：InAs、GaAs、InGaAs、InP、GeSi、
It is one or more in GeSn, SiC.
Optionally, the grid includes ferroelectricity grid layer.
A kind of manufacturing method of tunnel field-effect transistor, including：
Substrate is provided；
Source region is formed in the substrate；
Grid structure is formed, the grid structure is located at the substrate by the part source region and the source region, the grid knot
Structure includes gate dielectric layer and grid thereon；
Drain region, the source region and drain region tool are formed in the substrate of the grid structure side opposite with the source region
There is different doping types.
Optionally, the area of the source region is more than the area in the drain region.
Optionally, after forming source region, before formation grid structure, further include：
Opening is formed in the substrate of the source region and source region side, and is formed in the opening with the substrate with not
With the heterogeneous channel layer of material；Then,
The formation grid structure, including：
Grid structure is formed on the heterogeneous channel layer, the grid structure covers the heterogeneous channel layer.
The source region of tunnel field-effect transistor provided in an embodiment of the present invention and its manufacturing method, formation is located at part grid knot
Under structure and in the substrate of grid structure side, that is to say, that the source region of grid structure overlapped coverage part, in this way, grid can be improved
Pole tension is to the potential control ability of device source region/channel region, and further, the area of source region is more than the area in drain region, makes source
Area's carrier concentration is generally higher than drain region carrier concentration, to increase the tunnel probability of device, the whole ON state for improving device
Electric current.
Further, the heterogeneous raceway groove with substrate channel different materials is also formed between source region and drain region in the substrate
Layer, the heterogeneous channel layer reduce band gap, further improve the tunnel probability of carrier, increase the tunnel electricity of device
Stream improves transistor driving ability.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 shows the flow chart of the manufacturing method of tunnel field-effect transistor according to the ... of the embodiment of the present invention；
Fig. 2-9 shows the knot during manufacturing method formation tunnel field-effect transistor according to the ... of the embodiment of the present invention
Structure schematic diagram.
Specific implementation mode
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention
Specific implementation mode be described in detail.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still the present invention can be with
Implemented different from other manner described here using other, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
Secondly, combination schematic diagram of the present invention is described in detail, when describing the embodiments of the present invention, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the scope of protection of the invention.In addition, three-dimensional space that should be comprising length, width and depth in actual fabrication.
The present invention is intended to provide a kind of tunnel field-effect transistor and its manufacturing method, to improve the tunnel probability of device,
Increase the tunnel electric current of device so that tunnel field-effect transistor disclosure satisfy that application demand.Described in reference diagram 9, the application carries
A kind of tunnel field-effect transistor has been supplied, including：
Substrate 100；
Grid structure 130 on substrate 100, grid of the grid structure 130 including gate dielectric layer 1301 and thereon；
Drain region 140 in the substrate of 130 side of the grid structure；
Source region 110 under the part grid structure 130 and in the substrate 100 of 130 other side of the grid structure,
The source region 110 and the drain region 140 have different doping types.
In the present invention, the source region of formation is located under the grid structure of part and in the substrate of grid structure side, that is to say, that
The source region of grid structure overlapped coverage part, in this way, potential control ability of the gate voltage to device source region/channel region can be improved,
Increase the tunnel electric current of device, and then increases the ON state current of device.
In embodiments of the present invention, substrate 100 is semiconductor substrate, such as can be Si substrates, Ge substrates, SiGe linings
Bottom, SOI (silicon-on-insulator, Silicon On Insulator) or GOI (germanium on insulator, Germanium On
Insulator) etc..Substrate 100 can also be the substrate for including other elements semiconductor or compound semiconductor, such as GaAs,
InP or SiC etc. can also be laminated construction, such as Si/SiGe etc. can be with other epitaxial structures, such as SGOI (insulators
Upper germanium silicon) etc..The substrate 100 can have the substrate of doping, for example, boron doped P type substrate, doping concentration for example may be used
Think 1.56x1016cm-3.Be also formed with isolated area 102 in substrate 100, the isolated area 102 may include silica or its
He can separate the material of the active area of device, and isolated area 102 for example can be shallow trench isolation.
The material of grid of the grid structure 130 including gate dielectric layer 1301 and thereon, gate dielectric layer 1301 can be oxidation
Silicon or high K medium material or other suitable dielectric materials, high K medium material are compared with silica, have high-k
Material, high K medium material such as hafnium base oxide, HfO2, HfSiO, HfSiON, HfTaO, HfTiO etc..
Grid can be single layer or laminated construction, it is preferable that the grid is the laminated construction for including metal gate, more preferably
Ground further includes ferroelectricity grid layer in grid, in some embodiments, as shown in figure 9, grid includes stacked gradually from bottom to up
One metal gate 1302, ferroelectricity grid layer 1303, the second metal gate 1304 and gate electrode layer 1305.Wherein, the first metal gate 1301
Material with the second metal gate 1302 can be one kind or more in elemental metals, alloy, the metal nitrides such as Ti, Ta, Hf etc.
Kind, such as can be Ti, TiAlx、TiN、TaNx、HfN、TiCx、TaCxEtc..The material of ferroelectricity grid layer 1303 for example can be
Doped with the elements such as aluminium (Al), strontium (Sr), barium (Ba), pick (Zr), niobium (Nb), chromium (Cr), lanthanum (La) or bismuth (Bi) hafnium oxide,
Manganese oxide, titanium oxide, oxidation load or iron oxide etc..Gate electrode layer 1305 can be metal electrode material, such as can be gold
(Au), silver-colored (Ag) etc..The finally formed grid with ferroelectricity grid layer can amplify gate surface electricity with negative capacitance effect
Gesture, to promote the further promotion of transistor ON state current.
Source region 110 from the substrate 100 that the region under part grid structure 130 extends to 130 side of grid structure, that is,
It says, source region 110 has part overlapping region with grid structure 130, and drain region 140 is formed in the grid structure 130 opposite with source region 110 separately
In the substrate 100 of side, the region between source region 110 and drain region 140 is channel region.Due to grid structure part overlapped coverage source
Area can improve potential control ability of the gate voltage to device source region/channel region, increase the tunnel electric current of device, and then increase
The ON state current of device.
Source region 110 and drain region 140 are different doping types, and for n-type device, source region is P-doped zone, drain region N
Type doped region；For p-type device, source region is N-doped zone, and drain region is P-doped zone, and the doped chemical of n-type doping for example may be used
Think P, As, Sb etc., the doped chemical of p-type doping is such as can be B, Al, Ga.
In more preferably embodiment, source region 110 has the area of bigger compared with drain region 140, can be along channel direction, source region
110 have broader doping length compared with drain region 140, and/or, along grid direction, source region 110 has longer mix compared with drain region 140
Miscellaneous length.The area of source region is more than the area in drain region, and source region carrier concentration is made generally to be higher than drain region carrier concentration, to increase
The tunnel probability of big device, the whole ON state current for improving device
Further, the doping concentration of source region 110 can be higher than the doping concentration in drain region 140, the doping concentration of source region 110
At least compared with the high an order of magnitude of doping concentration in drain region 140, so that device has while capable of further increasing ON state current
There is lower reverse leakage current.In specific application, the doping concentration order of magnitude of source region 110 can be 1020, drain region 140
The doping concentration order of magnitude can be 1017-1019。
In addition, heterogeneous channel layer 122 can also be formed further in substrate 100, the heterogeneous channel layer 122 refer to
There is the channel layer of different materials, the heterogeneous channel layer 122 to be formed in the substrate under grid structure 130 as the substrate of raceway groove
In, it is covered by grid structure 130, one end is embedded in source region 110, and other end side is drain region 140 so that source region 110 is located at grid knot
Subregion under structure 130 is sunk area, heterogeneous channel layer 122 is filled in sunk area, in this way, heterogeneous channel layer is in
Between source region 110 and drain region 140, a part for the channel region as transistor device.The raceway groove of the heterogeneous channel layer and substrate
With different materials, and heterojunction structure is formd between source region/channel region, reduces band gap, further increase
The tunnel probability of carrier, increases the ON state current of device, improves transistor driving ability.
In specific application, the thickness that heterogeneous channel layer 122 can be arranged according to the performance of specific device can be
10-100nm, when substrate is silicon substrate, heterogeneous channel layer can be InAs, GaAs, InGaAs, InP, GeSi, GeSn, SiC
In it is one or more.
In addition, above-mentioned transistor device can also include other necessary structures, such as including 130 side wall of grid structure
On side wall 150 and exposure 140 surface of source region 110 and drain region on metal silicide layer 160 etc..
The tunneling field-effect transistor structure of the present invention is described above, in order to better understand the present invention, with
Under specific embodiment and forming method will be described in detail in conjunction with flow chart.
Refering to what is shown in Fig. 1, in step S01, substrate 100 is provided, as shown in Figure 2.
In the present embodiment, it for example can be body silicon substrate, SOI (silicon-on-insulator) that substrate, which uses silicon substrate, silicon substrate,
Substrate or other laminated substrates.In other embodiments, it can also be other substrates, which, which plays, supports and be used to form crystalline substance
Body tube device.
In the present embodiment, which is with boron doped p-type doped substrate, a concentration of 1.56x10 of doping16cm-3。
Isolation structure 102 is formed in substrate 100, which is shallow trench isolation, specifically, can be
Mask pattern is formed on substrate 100, then, is formed shallow trench in the substrate using lithographic technique, later, is formed in shallow trench
The dielectric material of silica, to form the isolated area 102 of shallow trench isolation, the region between isolated area 102 is used to form crystalline substance
Body pipe then removes mask pattern, as shown in Figure 3.
In step S02, source region 110 is formed in the substrate 100, with reference to shown in figure 4.
In the present embodiment, source region 110 is adulterated using p-type, specifically, the mask figure of source region can be initially formed on substrate
Case then carries out the ion implanting of p-type doping, and the element of p-type doping for example can be B, BF2, Al, Ga etc., implantation dosage is
1012~1015cm-2, Implantation Energy is 40~300kev, and implant angle is 7 degree, can be led in this step or in subsequent step
Annealing activation doping is crossed, to form source region 110, as shown in Figure 4.
In step S03, grid structure 130 is formed, the grid structure 130 is located at the part source region 110 and the source region 110
On other substrate 100, grid of the grid structure 130 including gate dielectric layer 1301 and thereon, with reference to shown in figure 8.
In the embodiment, grid structure 130 is laminated construction, as shown in fig. 7, specifically, it is possible, firstly, to using deposition or outside
Prolong technique and form gate dielectric layer 1301, gate dielectric layer 1301 for example can be HfO2；Then, deposition or epitaxy technique may be used
The first metal gate 1302 is formed on gate dielectric layer 1301, the first metal gate 1302 for example can be TiN；Then, it may be used
Sol-gel technology forms ferroelectricity grid layer 1303 on first metal gate 1302, and ferroelectricity grid layer 1303 for example can be to mix
The miscellaneous hafnium sill for having pick (Zr) or lanthanum (La) or aluminium (Al)；Then, atom layer deposition process may be used and form the second metal
Grid 1304, the second metal gate 1304 can have material identical with the first metal gate 1302；Then, magnetron sputtering may be used
Technology forms gate electrode layer 1305 on the second metal gate 1304；Finally, Patternized technique is carried out, above-mentioned lamination is carved
Erosion, to form grid structure 130, as shown in figure 8, the grid structure 130 includes gate dielectric layer 1301, the first gold medal successively from bottom to top
Belong to grid 1302, ferroelectricity grid layer 1303, the second metal gate 1304 and gate electrode layer 1305, along channel direction, the part grid structure
130 is overlapping with the source region 110 of part.
In step S04, drain region is formed in the substrate 100 of the side opposite with the source region 110 of the grid structure 130
140, the source region 110 and the drain region 140 have different doping types, with reference to shown in figure 9.
In the present embodiment, drain region 140 uses n-type doping, specifically, the mask figure in drain region can be initially formed on substrate
Case then carries out the ion implanting of n-type doping, and the element of n-type doping is such as can be P, As, Sb, implantation dosage 1012~
1015cm-2, Implantation Energy is 20~300kev, and implant angle is 7 degree, with reference to shown in figure 9.In the present embodiment, by adjusting
Implantation dosage and Implantation Energy in the doping of source region 110 and 140 doping process of drain region, can make the doping of source region 110 dense
Degree more preferably passes through control technique higher than the doping concentration in drain region 140 so that the doping concentration of source region 110 is at least compared with drain region
140 high an order of magnitude of doping concentration.
Then, annealing process can be carried out, annealing process includes first time annealing process, which is conventional anneal
The temperature range of technique, annealing can be 650-950 DEG C, and the time of annealing can be 1s~2min；Then, it is moved back for the second time
The temperature range of ignition technique, annealing can be 950-1350 DEG C, which can be that fast peak is annealed, and the time of annealing can
Think 5ms~10s, by twice annealing technique, the impurity activation that source region 110 and drain region 140 can be injected, meanwhile, improve
The characteristic of grid structure 130 realizes its ferroelectricity negative capacitance characteristic.
Then, other components of tunnel transistor device can be completed, such as side is formed on the side wall of grid structure 130
Wall 150 forms metal silicide layer 160 on the surface that source region 110 and drain region 140 expose, and is subsequently formed interlayer medium
Layer and source, leakage, the contact of grid etc., these techniques can be completed using the processing technology of existing cmos device,
Details are not described herein again.
In another embodiment, with unlike above-described embodiment, in the substrate under grid structure, it is also formed with heterogeneous ditch
Emphasis, is described part unlike the embodiments above by channel layer below, and same section will not be described in great detail.
In step S201, substrate 100 is provided, as shown in Figure 2.
In step S202, source region 110 is formed in the substrate 100, with reference to shown in figure 4.
Step S201 is the same as the step S01 of above-described embodiment, step S02s of the step S202 with above-described embodiment.
In step S203, opening 120 is formed in the substrate 100 of 110 side of the source region 110 and source region, and opening
The heterogeneous channel layer 122 that there are different materials with the substrate 100 is formed in mouth 120, with reference to shown in figure 5 and Fig. 6.
In the present embodiment, substrate 100 is silicon substrate, and the material of heterogeneous channel layer 122 can be：InAs、GaAs、
It is one or more in InGaAs, InP, GeSi, GeSn, SiC.Specifically, heterogeneous channel layer can be formed on substrate 100
Mask pattern, along channel direction, which exposes the source region 110 of part and the substrate 100 of its side, then utilizes
Lithographic technique removes the substrate material of segment thickness, and the thickness etched away can be 10-100nm, to, opening 120 is formed,
As shown in Figure 5.Then, the channel material different from substrate can be filled in the opening by deposition or epitaxy technique, such as
InAs, so that heterogeneous channel layer 122 is formd, as shown in fig. 6, source region of the heterogeneous channel layer 122 instead of part so that
Heterogeneous channel layer 122 is partly embedded in by source area side in source region 110.
In step S204, grid structure 130 is formed on the heterogeneous channel layer 122, the grid structure 130 covers described different
Matter channel layer 122, with reference to shown in figure 8.
In the embodiment, grid structure 130 is laminated construction, as shown in fig. 7, specifically, it is possible, firstly, to using deposition or outside
Prolong technique and form gate dielectric layer 1301, gate dielectric layer 1301 for example can be HfO2；Then, deposition or epitaxy technique may be used
The first metal gate 1302 is formed on gate dielectric layer 1301, the first metal gate 1302 for example can be TiN；Then, it may be used
Sol-gel technology forms ferroelectricity grid layer 1303 on first metal gate 1302, and ferroelectricity grid layer 1303 for example can be to mix
The miscellaneous hafnium sill for having pick (Zr) or lanthanum (La) or aluminium (Al)；Then, atom layer deposition process may be used and form the second metal
Grid 1304, the second metal gate 1304 can have material identical with the first metal gate 1302；Then, magnetron sputtering may be used
Technology forms gate electrode layer 1305 on the second metal gate 1304；Finally, Patternized technique is carried out, above-mentioned lamination is carved
Erosion forms grid structure 130 on heterogeneous channel layer 122, as shown in figure 8, the grid structure 130 includes gate medium successively from bottom to top
The 1301, first metal gate 1302 of layer, ferroelectricity grid layer 1303, the second metal gate 1304 and gate electrode layer 1305.More preferably, as schemed
Shown in 8, heterogeneous channel layer 122 is completely covered by the side of source area 110 in the grid structure 130 after channel direction, patterning
End, the other side are flushed with the end of heterogeneous channel layer 122, thereby enhance control ability of the gate voltage to source region/channel region
While reduce its control ability to drain region/channel region, bring higher positive tunnelling and contained reverse tunnel, therefore
Make device that there is the performance of higher ON state current and lower reverse leakage current.
In step S205, drain region is formed in the substrate 100 of the side opposite with the source region 110 of the grid structure 130
140, the source region 110 and the drain region 140 have different doping types, with reference to shown in figure 9.
With the step S04 in above-described embodiment.
So far, the tunneling field-effect transistor of the embodiment of the present invention is formd.Then, can be as needed, form device
Other structures, such as side wall, metal silicide layer, source, drain contact, gate contact.
The above is only a preferred embodiment of the present invention, although the present invention has been disclosed in the preferred embodiments as above, so
And it is not limited to the present invention.Any technical person familiar with the field is not departing from technical solution of the present invention ambit
Under, many possible changes and modifications all are made to technical solution of the present invention using the methods and technical content of the disclosure above,
Or it is revised as the equivalent embodiment of equivalent variations.Therefore, every content without departing from technical solution of the present invention, according to the present invention
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within the technology of the present invention side
In the range of case protection.
Claims (10)
1. a kind of tunnel field-effect transistor, which is characterized in that including：
Substrate；
Grid structure on substrate, the grid structure include gate dielectric layer and grid thereon；
Drain region in the substrate of the grid structure side；
Source region under the grid structure of part and in the substrate of the grid structure other side, the source region and the leakage
Area has different doping types.
2. transistor according to claim 1, which is characterized in that the area of the source region is more than the area in the drain region.
3. transistor according to claim 1, which is characterized in that the doping concentration of the source region is mixed higher than the drain region
Miscellaneous concentration.
4. transistor according to claim 3, which is characterized in that at least more described drain region of the doping concentration of the source region
The high an order of magnitude of doping concentration.
5. according to the transistor described in any one of claim 1-4, which is characterized in that further include：Have not with the substrate
With the heterogeneous channel layer of material, covered in the substrate that the heterogeneous channel layer is located under the grid structure and by the grid structure,
The heterogeneous channel layer is close to one end of the source region in the source region.
6. transistor according to claim 5, which is characterized in that the substrate is silicon substrate, the heterogeneous channel layer packet
It includes：It is one or more in InAs, GaAs, InGaAs, InP, GeSi, GeSn, SiC.
7. transistor according to claim 1, which is characterized in that the grid includes ferroelectricity grid layer.
8. a kind of manufacturing method of tunnel field-effect transistor, which is characterized in that including：
Substrate is provided；
Source region is formed in the substrate；
Grid structure is formed, the grid structure is located at the substrate by the part source region and the source region, the grid structure packet
Include gate dielectric layer and grid thereon；
Drain region is formed in the substrate of the grid structure side opposite with the source region, the source region and the drain region have not
Same doping type.
9. manufacturing method according to claim 8, which is characterized in that the area of the source region is more than the face in the drain region
Product.
10. manufacturing method according to claim 8 or claim 9, which is characterized in that after forming source region, formed grid structure it
Before, further include：
Opening is formed in the substrate of the source region and source region side, and is formed in the opening from the substrate with different materials
The heterogeneous channel layer of material；Then,
The formation grid structure, including：
Grid structure is formed on the heterogeneous channel layer, the grid structure covers the heterogeneous channel layer.
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| CN110828312A (en) * | 2019-10-14 | 2020-02-21 | 西安电子科技大学 | Planar tunneling field effect transistor based on transfer printing technology and preparation method thereof |
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